Variable component sub-line compilation optimization method and related device

Abstract

The invention discloses a variable component sub-line compilation optimization method and a related device, and belongs to the technical field of quantum computing, and the method comprises the following steps: if a variable component sub-line is not compiled for the first time and a mapping relation is unchanged, calling quantum hardware resources to execute the compiled variable component sub-line so as to update logic gate parameters in the variable component sub-line, the mapping relation is used for representing the corresponding relation between the logic bits in the variable component sub-lines and the physical bits in the quantum hardware resources. According to the method, the mapping relation result is stored during the first compiling, and a mechanism for judging whether the compiling is the first compiling is introduced into the compiling process, so that the tedious remapping operation is avoided, the time and computing resources required by the compiling process are remarkably reduced, the parameter updating can be quickly responded, and the execution efficiency of the variable component sub-line is improved.

Description

Technical Field

[0001] This invention belongs to the field of quantum computing technology, specifically a variable quantum circuit compilation optimization method and related apparatus. Background Technology

[0002] In the current compilation process of variable quantum circuits, the commonly used compilation strategy requires cumbersome remapping operations each time. This undoubtedly puts a heavy load on the processor and exposes many shortcomings in execution efficiency, which has a significant negative impact on the overall compilation efficiency.

[0003] Therefore, the urgent technical problem to be solved is to propose a new variable quantum circuit compilation method, so as to improve the efficiency of the overall compilation process. Summary of the Invention

[0004] The purpose of this invention is to provide a variable quantum circuit compilation optimization method and related apparatus, which aims to improve the efficiency of the overall compilation process of variable quantum circuits.

[0005] One embodiment of the present invention provides a variable quantum circuit compilation optimization method, the method comprising:

[0006] If the variable quantum circuit is not being compiled for the first time and the mapping relationship remains unchanged, then the quantum hardware resources are invoked to execute the compiled variable quantum circuit to update the logic gate parameters in the variable quantum circuit. The mapping relationship is used to characterize the correspondence between the logic bits in the variable quantum circuit and the physical bits in the quantum hardware resources.

[0007] Optionally, the method further includes:

[0008] If the variable quantum circuit is not being compiled for the first time and the mapping relationship has changed, then the correspondence between the logical bits in the variable quantum circuit and the physical bits in the quantum hardware resources is updated to obtain the new compiled variable quantum circuit; and the step of calling the quantum hardware resources to execute the compiled variable quantum circuit is performed to update the logic gate parameters in the variable quantum circuit.

[0009] Optionally, the method further includes:

[0010] If the variable sub-circuit is being compiled for the first time, a mapping operation is performed on the variable sub-circuit and the mapping relationship is recorded, and the compiled variable sub-circuit is determined based on the mapping relationship;

[0011] The execution step involves calling quantum hardware resources to execute the compiled variable quantum circuit to update the logic gate parameters in the variable quantum circuit.

[0012] Optionally, the method further includes:

[0013] Determine whether the variable quantum circuit is being compiled for the first time;

[0014] Before determining whether the variable quantum circuit is being compiled for the first time, the method further includes:

[0015] The input original variable quantum circuit is subjected to gate optimization processing to obtain the optimized variable quantum circuit; the gate optimization processing includes at least one of gate decomposition operation, gate merging operation and gate replacement operation.

[0016] Optionally, the mapping relationship is established during the first mapping operation and is released when at least one of the following conditions is met: the last iteration is completed, the computation task corresponding to the variable quantum circuit ends, the compilation of the variable quantum circuit fails, or the execution of the variable quantum circuit fails.

[0017] Optionally, the quantum hardware resources include quantum processors and / or quantum virtual machines.

[0018] Another embodiment of the present invention provides a variable quantum circuit compilation optimization apparatus, the apparatus comprising:

[0019] The compilation processing unit is used to determine whether the variable quantum circuit is not being compiled for the first time and whether the mapping relationship remains unchanged. If so, it calls the quantum hardware resources to execute the compiled variable quantum circuit to update the logic gate parameters in the variable quantum circuit. The mapping relationship is used to characterize the correspondence between the logic bits in the variable quantum circuit and the physical bits in the quantum hardware resources.

[0020] Another embodiment of the present invention provides an electronic device, wherein the computer-readable storage medium stores a computer program, the computer program including program instructions, which, when executed by a processor, perform the methods described in any of the above embodiments.

[0021] Another embodiment of the present invention provides a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor, perform the methods described in any of the above embodiments.

[0022] Another embodiment of the present invention provides a quantum computer operating system, wherein the quantum computer operating system implements variable quantum circuit compilation optimization according to the method described in any of the above embodiments.

[0023] Compared with the prior art, the present invention first determines that if the variable quantum circuit is not being compiled for the first time and the mapping relationship remains unchanged, then it calls quantum hardware resources to execute the compiled variable quantum circuit to update the logic gate parameters in the variable quantum circuit. The mapping relationship is used to characterize the correspondence between the logic bits in the variable quantum circuit and the physical bits in the quantum hardware resources.

[0024] This invention first assumes that the variable quantum circuit is not being compiled for the first time and considers that when the mapping relationship remains unchanged, it executes the compiled variable quantum circuit by calling quantum hardware resources to update the logic gate parameters in the variable quantum circuit. By introducing a mechanism to determine whether it is the first compilation in the compilation process, the cumbersome remapping operation is avoided every time, significantly reducing the time and computing resources required for compilation, thereby enabling a fast response to parameter updates and improving the execution efficiency of the variable quantum circuit. Since this invention no longer needs to re-execute the entire compilation process, it reduces the need for reconfiguration and initialization of quantum hardware resources, which helps to optimize the utilization of hardware resources and reduce the consumption of hardware resources. Attached Figure Description

[0025] Figure 1 This is a network block diagram of a variable quantum circuit compilation optimization system provided in an embodiment of the present invention.

[0026] Figure 2 A flowchart of a variable quantum circuit compilation optimization method provided in an embodiment of the present invention.

[0027] Figure 3 A flowchart of another variable quantum circuit compilation optimization method provided in an embodiment of the present invention.

[0028] Figure 4 A flowchart of another variable quantum circuit compilation optimization method provided in an embodiment of the present invention.

[0029] Figure 5 The following is a flowchart illustrating a variable quantum circuit compilation optimization method provided in an embodiment of the present invention.

[0030] Figure 6 This is a structural diagram of a variable quantum circuit compilation optimization device provided in an embodiment of the present invention.

[0031] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0032] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0033] Figure 1 This is a network block diagram of a variable quantum circuit compilation optimization system provided in an embodiment of the present invention. The variable quantum circuit compilation optimization system may include a network 110, a server 120, a wireless device 130, a client 140, storage 150, a classical computing unit 160, a quantum computing unit 170, and may also include additional memory, a classical processor, a quantum processor, and other devices not shown.

[0034] Network 110 is a medium used to provide communication links between various devices and computers connected together within a variable quantum circuit compilation and optimization system, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks and combinations thereof, and the connection method can be wired, wireless communication links or fiber optic cables, etc.

[0035] Server 120, wireless device 130, and client 140 are conventional data processing systems that may contain data and application programs or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0036] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 163 (application program 173). The application program 163 (application program 173) may be used to implement a quantum algorithm compiled by a variable quantum circuit compilation optimization method provided in an embodiment of the present invention.

[0037] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0038] It should be noted that a true quantum computer has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical computing unit 160, which is responsible for performing classical calculations and control; and the quantum computing unit 170, which is responsible for running quantum programs to achieve quantum computing.

[0039] The aforementioned classical computing unit 160 and quantum computing unit 170 can be integrated into a single device or distributed across two different devices. For example, a first device including the classical computing unit 160 runs a classical computer operating system, providing quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum programs using the quantum application development tools and services on the second device, and send these quantum programs to a second device including the quantum computing unit 170 via the network services. The second device runs a quantum computer operating system, which parses and compiles the quantum program's code into instructions that the quantum processor 170 can recognize and execute. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0040] The computing units of the classic processor 161 within the classic computing unit 160 are based on CMOS transistors on a silicon chip. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of such computing units in a silicon chip is sufficient; currently, a single classic processor 161 contains tens of thousands of computing units. Given this sufficient number and the fixed selectable computing logic of the CMOS transistors (e.g., AND logic), computational performance is achieved by combining a large number of CMOS transistors with a limited set of logic functions during operation.

[0041] In the quantum computing unit 170, the basic computing unit of the quantum processor 171 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logical functions. Given the limited number of qubits and the diverse logical functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse logical function combinations to achieve computational effects.

[0042] Based on these differences, the design of classical logic functions applied to CMOS transistors and the design of quantum logic functions applied to qubits are significantly and fundamentally different. The design of classical logic functions applied to CMOS transistors does not need to consider the individuality of CMOS transistors. For example, the representation of a CMOS transistor in a silicon chip is its individual identifier, location, and usable time of each CMOS transistor. Therefore, classical algorithms composed of classical logic functions only express the operational relationship of the algorithm, not the algorithm's dependence on individual CMOS transistors.

[0043] Quantum logic functions applied to qubits need to consider the individuality of each qubit, such as its position within the quantum chip, its relationship with surrounding qubits, and the duration of its usable time. Therefore, quantum algorithms composed of quantum logic functions not only express the computational relationships within the algorithm but also its dependence on the individual qubits.

[0044] A quantum chip can include qubits and channels for controlling them. Quantum logic gates are implemented using analog signals. Different combinations of analog signals are applied to the qubits through these channels, thereby creating quantum circuits with different functions to process data. Therefore, the design of quantum logic functions in the qubits (including the design of whether qubits are used and the design of the efficiency of each qubit) is crucial for improving the computational performance of quantum computers and requires special design. This is the unique characteristic of quantum algorithms based on quantum logic functions, and it is fundamentally and significantly different from classical algorithms based on classical logic functions. The aforementioned design considerations for qubits are technical problems that ordinary computing devices do not need to consider or address.

[0045] In the field of quantum computing, the compilation strategy commonly used in the current compilation process of quantum circuits requires tedious remapping operations each time. This undoubtedly puts a heavy load on the processor and has a significant negative impact on the overall compilation efficiency.

[0046] Therefore, a more efficient variable quantum circuit compilation method is needed to improve the overall compilation process efficiency.

[0047] See Figure 2 , Figure 2 A variable quantum circuit compilation method provided by an embodiment of the present invention includes the following steps:

[0048] Step S201: If the variable quantum circuit is not being compiled for the first time and the mapping relationship remains unchanged, then the quantum hardware resources are called to execute the compiled variable quantum circuit to update the logic gate parameters in the variable quantum circuit. The mapping relationship is used to characterize the correspondence between the logic bits in the variable quantum circuit and the physical bits in the quantum hardware resources.

[0049] The mapping relationship refers to the one-to-one correspondence between the logical bits in the variable quantum circuit and the physical bits in the quantum hardware resources; in this application, quantum hardware resources refer to quantum processors and / or quantum virtual machines.

[0050] Specifically, by considering two preconditions—first, the variable quantum circuit is not being compiled for the first time, and second, the mapping relationship between logical bits and physical bits remains unchanged during the compilation process—when both conditions are met, the system will call upon actual quantum hardware resources to execute the compiled variable quantum circuit. The purpose of this execution is to update the logic gate parameters in the variable quantum circuit.

[0051] For example, suppose a quantum computing research team is developing a variable quantum circuit called "QMatSim" for materials science research. They perform the first compilation of this variable quantum circuit, determining the mapping between logical bits and physical bits in quantum hardware resources (such as a superconducting quantum processor). For instance, the first logical bit in the variable quantum circuit is mapped to the first physical bit of the quantum processor, the second logical bit to the second physical bit, and so on. After the initial compilation and execution, some preliminary predictions of material properties were obtained. However, these results did not fully meet expectations. To improve the accuracy of the predictions, it was decided to adjust the logic gate parameters in the "QMatSim" variable quantum circuit. Before adjusting the parameters, two preconditions were established: first, the "QMatSim" variable quantum circuit had not been compiled for the first time (because it had been compiled once before); second, the mapping relationship between logic bits and physical bits remained unchanged during the compilation process. This was because the configuration of the quantum processor was not changed, nor was the mapping relationship between logic bits and physical bits modified. Since both conditions were met simultaneously, the recompilation process was skipped, and the quantum hardware resources (i.e., the previously used superconducting quantum processor) were directly invoked to execute the already compiled "QMatSim" variable quantum circuit. During execution, the logic gate parameters in the variable quantum circuit were updated according to the preset parameter adjustment strategy. These updated parameters were used to simulate the electronic structure of the material and generate new prediction results.

[0052] This invention first assumes that the variable quantum circuit is not being compiled for the first time and considers that the mapping relationship remains unchanged. Then, it calls quantum hardware resources to execute the compiled variable quantum circuit to update the logic gate parameters in the variable quantum circuit. By introducing a mechanism to determine whether it is the first compilation in the compilation process, the cumbersome remapping operation is avoided every time, which significantly reduces the time and computing resources required for compilation. This enables a fast response to parameter updates and improves the execution efficiency of the variable quantum circuit. Since this invention no longer needs to re-execute the entire compilation process, it reduces the need for reconfiguration and initialization of quantum hardware resources, which helps to optimize the utilization of hardware resources and reduce the consumption of hardware resources.

[0053] See Figure 3 , Figure 3 A flowchart of another variable quantum circuit compilation optimization method provided by an embodiment of the present invention, the method comprising the following steps:

[0054] Step S301: If the variable quantum circuit is not being compiled for the first time and the mapping relationship has changed, then update the correspondence between the logical bits in the variable quantum circuit and the physical bits in the quantum hardware resources to obtain the newly compiled variable quantum circuit; and execute the step of calling the quantum hardware resources to execute the compiled variable quantum circuit to update the logic gate parameters in the variable quantum circuit.

[0055] Specifically, by considering two preconditions—first, the variable quantum circuit is not being compiled for the first time, and second, the mapping relationship between logical bits and physical bits changes during the compilation process—when both conditions are met, the correspondence between logical bits in the variable quantum circuit and physical bits in the quantum hardware resources is updated to obtain a new compiled variable quantum circuit. Then, subsequent steps are executed, and the compiled variable quantum circuit is executed by calling the quantum hardware resources to update the logic gate parameters in the variable quantum circuit.

[0056] For example, suppose a quantum algorithm for optimizing drug molecule structures is being developed. This algorithm relies on a complex variable quantum circuit to simulate the interaction between the drug molecule and the target protein. This variable quantum circuit consists of multiple logical bits (representing different properties or states of the drug molecule) and quantum logic gates (simulating intermolecular interactions). The variable quantum circuit is designed and compiled, and then executed on quantum hardware (such as a superconducting quantum processor) to test its initial performance. During the initial compilation, the logical bits (e.g., L1, L2, L3) in the variable quantum circuit are mapped to the physical bits (e.g., P1, P2, P3) of the original quantum hardware resources, and compilation is successful. Subsequently, new quantum hardware resources are introduced, with a physical bit layout of P1', P2', P3', P4' (here, an additional physical bit P4' is added, and the characteristics of the original physical bits are also different). The variable quantum circuit is recompiled and optimized on the new hardware to improve the algorithm's execution efficiency and accuracy. Since this is not the first compilation of the variable quantum circuit (because it has already been compiled once on the old hardware), and because the physical bit layout and characteristics of the new hardware are different from those of the old hardware, the mapping relationship between logical bits and physical bits needs to be changed. Based on the physical bit layout and characteristics of the new hardware, the correspondence between logical bits (L1, L2, L3) and physical bits (P1', P2', P3') in the variable quantum circuit is updated (here it is assumed that P4' is not used temporarily because the variable quantum circuit only requires three logical bits). The compiled variable quantum circuit is reconfigured to adapt to the characteristics of the new hardware. Next, the compiled variable quantum circuit is executed by calling the new quantum hardware resources to update the logic gate parameters in the variable quantum circuit. During execution, due to the characteristics of the qubits and logic gates of the new hardware, the logic gate parameters (such as rotation angle, phase, etc.) in the variable quantum circuit may be fine-tuned or optimized based on experimental results to improve the accuracy and efficiency of the algorithm.

[0057] In summary, this step extends the approach to cases where the variable quantum circuit is not being compiled for the first time and changes in mapping relationships are considered. By adding a new step, the applicability and functionality of the original method are expanded, improving its flexibility and practicality in real-world applications. Considering changes in mapping relationships, the method can cope with real-world situations such as updates or configuration changes in quantum hardware resources, ensuring the algorithm runs effectively in different hardware environments. When mapping relationships change, the correspondence between logical bits and physical bits is updated promptly, and the variable quantum circuit is recompiled, ensuring the algorithm executes correctly in new hardware environments and avoiding execution failures or result deviations due to mapping errors.

[0058] See Figure 4 , Figure 4A flowchart of another variable quantum circuit compilation optimization method provided in an embodiment of the present invention, the method comprising the following steps:

[0059] Step S401: If the variable quantum circuit is being compiled for the first time, then perform a mapping operation on the variable quantum circuit and record the mapping relationship, and determine the compiled variable quantum circuit based on the mapping relationship.

[0060] Specifically, assuming the variable quantum circuit is being compiled for the first time, a mapping operation is performed on the variable quantum circuit. This operation maps the logical bits (i.e., the qubits defined in the algorithm) in the quantum circuit to the physical bits in the quantum hardware resources. The mapping relationship between the logical bits and the physical bits is then recorded. After the mapping relationship is determined, a compiled quantum circuit suitable for the current quantum hardware is generated to ensure that the compiled quantum circuit can be executed correctly on the given quantum hardware. The compiled quantum circuit is executed by calling the quantum hardware resources, and the logic gate parameters in the quantum circuit are updated according to the execution results. This update is usually based on some optimization objective (such as minimizing energy, maximizing success rate, etc.). By iterating this process, the optimal solution to the problem is gradually approached.

[0061] Step S402: Execute the step described above by calling quantum hardware resources to compile the variable quantum circuit to update the logic gate parameters in the variable quantum circuit.

[0062] Specifically, the mapping operation is first performed based on the premise of the initial compilation of the variable quantum circuit. After the mapping operation is completed, the compiled quantum circuit is executed by calling quantum hardware resources, and its logic gate parameters are updated through actual operation.

[0063] For example, suppose researchers design a variable quantum circuit based on the quantized representation of the Hamiltonian of the hydrogen molecule. This circuit contains multiple parameterized quantum gates (such as rotation gates) to simulate the quantum states of the hydrogen molecule. When this variable quantum circuit is ready for its first compilation, it is not yet associated with any specific quantum hardware resource and only contains an abstract representation of logical bits. During the first compilation, the system performs a mapping operation on this variable quantum circuit. The purpose of this step is to map the logical bits (such as q0, q1, etc.) in the circuit to the physical bits on quantum hardware (such as IBM Quantum, Google Quantum, etc.). When performing the mapping operation, the physical characteristics of the quantum hardware are taken into account, such as the connectivity between qubits (which qubits can interact directly) and the noise level of the qubits. After the mapping is completed, the system records the mapping relationship between logical bits and physical bits (e.g., q0->physical bit 3, q1->physical bit 5, etc.). Based on the recorded mapping relationship, the system generates a compiled quantum circuit suitable for the current quantum hardware. This compiled quantum circuit converts quantum logic gates and measurement operations into specific physical operations, ensuring that they can be correctly executed on the quantum hardware. By calling quantum hardware resources to execute the compiled quantum circuit, the system updates the logic gate parameters (e.g., rotation angle) in the variable quantum circuit according to the execution result (e.g., the expected value of the measured energy). This update is based on minimizing the expected value of the Hamiltonian of the hydrogen molecule as the optimization objective. By continuously repeating the process of compilation, execution, feedback, and optimization, the optimal solution of the ground state energy of the hydrogen molecule can be gradually approached.

[0064] In summary, by clarifying the key steps during the initial compilation—namely, performing the mapping operation and recording the mapping relationship—this step provides the foundational data for subsequent logic gate parameter updates and possible recompilation, ensuring the correct execution of the quantum circuit on quantum hardware. Generating the compiled quantum circuit based on the mapping relationship ensures its physical executability. This step serves as a crucial bridge between quantum computing theory and practice. Updating the logic gate parameters by running the compiled quantum circuit optimizes its performance and provides more accurate initial conditions for subsequent computational tasks.

[0065] See Figure 5 , Figure 5 The following is a flowchart illustrating a variable quantum circuit compilation optimization method provided in an embodiment of the present invention.

[0066] Step S501: Perform gate optimization processing on the input original variable quantum circuit to obtain the optimized variable quantum circuit; the gate optimization processing includes at least one of gate decomposition operation, gate merging operation and gate replacement operation.

[0067] Among them, gate optimization refers to the techniques used in the compilation of quantum circuits to reduce the number of quantum logic gates, improve the execution efficiency of quantum circuits, or adapt to the requirements of specific quantum hardware by rearranging, merging, replacing, or decomposing quantum gates; gate decomposition is the process of breaking down a complex quantum gate into a series of more basic and simpler quantum gate sequences; gate merging is the process of identifying and merging adjacent sequences in a quantum circuit that can be combined into more efficient quantum gates; and gate substitution is the process of replacing existing quantum gates in a quantum circuit with equivalent but more efficient or more suitable quantum gates for current quantum hardware.

[0068] Specifically, the input original variable quantum circuit is subjected to gate optimization processing, which mainly includes gate decomposition operation, gate merging operation, and gate replacement operation. The gate optimization processing mentioned here may include at least one of the following: gate decomposition operation (decomposing a complex quantum gate into a series of simple quantum gates), gate merging operation (merging adjacent identical or mergeable quantum gates into a single quantum gate to reduce the number of quantum gates), and gate replacement operation (replacing the original quantum gate with a more efficient or more suitable quantum gate).

[0069] In summary, gate optimization is a key step in preprocessing the original variable quantum circuit. It is a commonly used technique in quantum circuit compilation, aiming to reduce the resource consumption of quantum circuits (such as the number of qubits and quantum gates) or improve the execution efficiency of quantum circuits by optimizing the use of quantum gates.

[0070] Step S502: Determine whether the variable quantum circuit is being compiled for the first time;

[0071] Specifically, after the gate optimization process is completed, it is necessary to determine whether the current variable quantum circuit is being compiled for the first time.

[0072] In summary, by introducing a mechanism to determine whether it is the first compilation in the compilation process, the tedious remapping operation is avoided every time, significantly reducing the time and computing resources required for compilation.

[0073] For example, suppose you are designing quantum computing software for quantum chemistry simulations for a quantum computing company. The core of this software is a module that can compile and optimize quantum circuits to run complex quantum chemistry algorithms on a specific superconducting quantum processor. These algorithms involve a large number of quantum gate operations, so optimizing these operations is crucial to reducing runtime and improving algorithm efficiency. Suppose you have a primitive variable quantum circuit containing multiple complex quantum gates (such as Toffoli gates and Fredkin gates) that are directly used for specific steps in the quantum chemistry algorithm, such as simulating intermolecular interactions.

[0074] First, a gate decomposition operation is used to identify all Tofoli and Fredkin gates, which are then decomposed into a series of CNOT gates and single-qubit gates (such as Hadamard and T gates). This is because superconducting quantum processors typically directly support CNOT gates and some basic single-qubit gates, but not complex multi-qubit gates. Next, a gate merging operation is used to traverse the optimized quantum circuit, searching for merging sequences of adjacent quantum gates. For example, consecutive Hadamard and T gates can be merged into a more efficient equivalent gate in some cases, or multiple adjacent CNOT gates can be merged to reduce the total number of gates. Finally, a gate substitution operation is used to check if there are any quantum gates that can be replaced by more efficient or more suitable quantum gates for the current superconducting quantum hardware. For example, if a single-qubit rotation gate is inefficient to implement in hardware, it might be replaced by a series of CNOT gates and more efficient single-qubit gates. Through this gate optimization process, an optimized variable quantum circuit is obtained, which contains fewer quantum gates and is more suitable for operation on the target superconducting quantum processor.

[0075] After gate optimization, it is necessary to determine whether the current variable quantum circuit is being compiled for the first time. This is achieved by checking an internal status flag (such as the Boolean variable isFirstCompile). This flag is set to true each time a new compilation task begins and changed to false after the first compilation is completed. If it is the first compilation (isFirstCompile == true), the subsequent compilation process continues, which may include steps such as qubit mapping and quantum circuit remapping to ensure that the quantum circuit can be adapted to the physical connection of the target quantum processor. If it is not the first compilation (isFirstCompile == false), these potentially time-consuming remapping steps are skipped, and the mapping relationships recorded and saved during the previous compilation process are used directly, thereby saving compilation time and computational resources.

[0076] In one embodiment of this application, the mapping relationship is established when the mapping operation is executed for the first time and is released when at least one of the following conditions is met: the last iteration is completed, the computation task corresponding to the variable quantum circuit ends, the compilation of the variable quantum circuit fails, or the execution of the variable quantum circuit fails.

[0077] Specifically, during the first compilation of a variable quantum circuit, or when recompilation is required and the mapping relationship changes, the system performs a mapping operation to establish the correspondence between logical bits and physical bits. Once established, the mapping relationship is not fixed; however, it remains unchanged until each successful compilation and execution of the quantum circuit without triggering the release condition. In this application, the conditions for releasing the mapping relationship are: first, the completion of the last iteration; when all iterations of the quantum computing task have been completed and no further optimization or testing is needed, the mapping relationship will be released, marking the end of the current quantum computing task; second, the end of the computation task, regardless of whether it has been completed. The mapping relationship will be released once the quantum computing task reaches its preset goal or is terminated prematurely for any reason, according to all predetermined iterations. Thirdly, if compilation fails, and insurmountable obstacles such as insufficient resources or mapping conflicts are encountered during compilation, the mapping relationship will be released immediately, and it may be necessary to re-evaluate the feasibility of the entire quantum computing task or adjust its design. Fourthly, if execution fails, even if compilation is successful, if errors or failures occur when executing variable quantum circuits on quantum hardware (such as qubit errors, gate operation errors, etc.), the mapping relationship also needs to be released in order to troubleshoot, recompile, or select other quantum hardware resources.

[0078] In summary, by establishing and dynamically managing mapping relationships, unnecessary repetitive mapping operations are reduced, thus accelerating computation. Simultaneously, by setting explicit release conditions, timely responses can be made to situations such as task completion, compilation or execution failures, ensuring effective resource release and supporting troubleshooting and flexible task adjustments. This mechanism enables quantum computing tasks to execute more efficiently and reliably, improving their flexibility and reliability.

[0079] In one embodiment of this application, the quantum hardware resources include a quantum processor and / or a quantum virtual machine.

[0080] See Figure 6 , Figure 6 A variable quantum circuit compilation optimization apparatus provided in this embodiment of the invention may include:

[0081] The compilation processing unit 601 is used to determine whether the variable quantum circuit is not being compiled for the first time and whether the mapping relationship remains unchanged. If so, it calls the quantum hardware resources to execute the compiled variable quantum circuit to update the logic gate parameters in the variable quantum circuit. The mapping relationship is used to characterize the correspondence between the logic bits in the variable quantum circuit and the physical bits in the quantum hardware resources.

[0082] The mapping relationship refers to the one-to-one correspondence between the logical bits in the variable quantum circuit and the physical bits in the quantum hardware resources; in this application, quantum hardware resources refer to quantum processors and / or quantum virtual machines.

[0083] Specifically, if the variable quantum circuit is not being compiled for the first time and the mapping relationship has changed, then the correspondence between the logical bits in the variable quantum circuit and the physical bits in the quantum hardware resources is updated to obtain the newly compiled variable quantum circuit; and the step of calling the quantum hardware resources to execute the compiled variable quantum circuit is performed to update the logic gate parameters in the variable quantum circuit.

[0084] Specifically, if the variable sub-circuit is being compiled for the first time, a mapping operation is performed on the variable sub-circuit and the mapping relationship is recorded, and the compiled variable sub-circuit is determined based on the mapping relationship;

[0085] The execution step involves calling quantum hardware resources to execute the compiled variable quantum circuit to update the logic gate parameters in the variable quantum circuit.

[0086] Specifically, determine whether the variable quantum circuit is being compiled for the first time;

[0087] Before determining whether the variable quantum circuit is being compiled for the first time, the method further includes:

[0088] The input original variable quantum circuit is subjected to gate optimization processing to obtain the optimized variable quantum circuit; the gate optimization processing includes at least one of gate decomposition operation, gate merging operation and gate replacement operation.

[0089] Specifically, the mapping relationship is established during the first mapping operation and is released when at least one of the following conditions is met: the last iteration is completed, the computation task corresponding to the variable quantum circuit ends, the compilation of the variable quantum circuit fails, or the execution of the variable quantum circuit fails.

[0090] Specifically, the quantum hardware resources include quantum processors and / or quantum virtual machines.

[0091] The specific functions and effects of the variable quantum circuit compilation and optimization device described above can be explained by referring to other embodiments in this specification, and will not be repeated here. Each module in the variable quantum circuit compilation device can be implemented entirely or partially through software, hardware, or a combination thereof. Each module can be embedded in or independent of the processor in a computer device in hardware form, or it can be stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0092] Please see Figure 7 This specification also provides an electronic device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement a variable quantum circuit compilation optimization method according to any of the above embodiments. Please refer to [link to documentation]. Figure 7 The computer device can be a classical computer or a quantum computer.

[0093] This specification also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform a variable quantum circuit compilation optimization method according to any of the above embodiments.

[0094] This invention also provides a quantum computer operating system, which implements the variable quantum circuit compilation optimization method according to any of the above-described method embodiments provided in this invention.

[0095] It is understood that the specific examples in this specification are only intended to help those skilled in the art better understand the implementation methods described herein, and are not intended to limit the scope of the invention.

[0096] It is understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this specification in any way.

[0097] It is understood that the various implementation methods described in this specification can be implemented individually or in combination, and the implementation methods in this specification are not limited in this respect.

[0098] Unless otherwise stated, all technical and scientific terms used in the embodiments of this specification have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0099] It is understood that the processor in the embodiments of this specification can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this specification. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this specification can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0100] It is understood that the memory in the embodiments of this specification may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0101] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0102] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0103] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0104] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0105] In addition, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0106] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this specification, in essence, or the parts that contribute to the prior art, or parts of the technical solutions, can be embodied in the form of software products. These computer software products are stored in a storage medium and include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0107] The above description is merely a specific embodiment of this specification, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this specification should be included within the scope of protection of this specification. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A variable quantum circuit compilation optimization method, characterized in that, The method includes: If the variable quantum circuit is not being compiled for the first time and the mapping relationship remains unchanged, then the quantum hardware resources are invoked to execute the compiled variable quantum circuit to update the logic gate parameters in the variable quantum circuit. The mapping relationship is used to characterize the correspondence between the logic bits in the variable quantum circuit and the physical bits in the quantum hardware resources.

2. The method according to claim 1, characterized in that, The method further includes: If the variable quantum circuit is not being compiled for the first time and the mapping relationship has changed, then the correspondence between the logical bits in the variable quantum circuit and the physical bits in the quantum hardware resources is updated to obtain the new compiled variable quantum circuit; and the step of calling the quantum hardware resources to execute the compiled variable quantum circuit is performed to update the logic gate parameters in the variable quantum circuit.

3. The method according to claim 1, characterized in that, The method further includes: If the variable sub-circuit is being compiled for the first time, a mapping operation is performed on the variable sub-circuit and the mapping relationship is recorded, and the compiled variable sub-circuit is determined based on the mapping relationship; The execution step involves calling quantum hardware resources to execute the compiled variable quantum circuit to update the logic gate parameters in the variable quantum circuit.

4. The method according to claim 1, characterized in that, The method further includes: Determine whether the variable quantum circuit is being compiled for the first time; Before determining whether the variable quantum circuit is being compiled for the first time, the method further includes: The input original variable quantum circuit is subjected to gate optimization processing to obtain the optimized variable quantum circuit; the gate optimization processing includes at least one of gate decomposition operation, gate merging operation and gate replacement operation.

5. The method according to any one of claims 1-4, characterized in that, The mapping relationship is established during the first mapping operation and is released when at least one of the following conditions is met: the last iteration is completed, the computation task corresponding to the variable quantum circuit ends, the compilation of the variable quantum circuit fails, or the execution of the variable quantum circuit fails.

6. The method according to claim 1, characterized in that, The quantum hardware resources include quantum processors and / or quantum virtual machines.

7. A variable quantum circuit compilation optimization device, characterized in that, The device includes: The compilation processing unit is used to determine whether the variable quantum circuit is not being compiled for the first time and whether the mapping relationship remains unchanged. If so, it calls the quantum hardware resources to execute the compiled variable quantum circuit to update the logic gate parameters in the variable quantum circuit. The mapping relationship is used to characterize the correspondence between the logic bits in the variable quantum circuit and the physical bits in the quantum hardware resources.

8. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to execute the method as described in claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in claims 1-6.

10. A quantum computer operating system, characterized in that, The quantum computer operating system implements variable quantum circuit compilation optimization according to any one of claims 1-6.

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