Systemverilog and C language mutual conversion method

Abstract

The invention discloses a system verilog and C language mutual conversion method, which relates to the field of digital chips and comprises the following steps: acquiring an original file, and respectively extracting common keywords, keyword categories and keyword detailed description information of a system verilog programming language and a C language; a SystemVerilog and C language keyword corresponding table is constructed, and the keyword corresponding table is used for establishing a mapping relation between keywords of the two languages and providing a keyword matching basis for code conversion; storing the content of the keyword corresponding table in the form of a dictionary data structure by using a script language, wherein the dictionary uses key value pairs to store keywords of SystemVerilog and c language which are matched with each other; storing paths or names of all original files needing to be converted in a list data structure by using a script language; and traversing each original file in the list to perform language conversion. According to the method, rapid and efficient conversion between the SystemVerilog and the C language is realized by utilizing the script file.

Description

Technical Field

[0001] This invention relates to the field of digital chips, and specifically to a method for mutual conversion between SystemVerilog and C language. Background Technology

[0002] The most commonly used programming languages ​​in the digital chip field are SystemVerilog and C. In the verification field, SystemVerilog is often used to write code, and C is also frequently used. Moreover, in project practice, it is common to encounter situations where a certain function needs to be implemented using both SystemVerilog and C. In such cases, it is necessary to use two languages ​​to write code to achieve the same function. If a tool could be developed that can convert SystemVerilog code into C code, or vice versa, it would avoid the repeated development of the same function, reduce errors introduced by human coding, and most importantly, reduce manpower input, which could shorten the project cycle to a certain extent. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for mutual conversion between SystemVerilog and C language, so as to achieve accurate and efficient conversion between SystemVerilog and C language.

[0004] The objective of this invention is achieved through the following technical solution: A method for converting between SystemVerilog and C languages ​​includes the following steps: Obtain the original files and extract commonly used keywords, keyword categories, and detailed descriptions of keywords for both the SystemVerilog and C programming languages. Construct a keyword mapping table between SystemVerilog and C language. The keyword mapping table is used to establish the mapping relationship between keywords in the two languages ​​and provide a keyword matching basis for code conversion. The contents of the keyword mapping table are stored in a dictionary data structure using a scripting language. The dictionary uses key-value pairs to store mutually matching SystemVerilog and C language keywords. A first dictionary data is generated, in which the key stores the SystemVerilog language keyword and the value stores the matching C language keyword. The key and value values ​​in the first dictionary data are swapped to generate a second dictionary data. Use a scripting language to store the paths or names of all the original files that need to be converted in a list data structure; The process involves iterating through each original file in the list and performing language conversion. The specific steps include: Identify the file extension of the original file. If the original file is in SystemVerilog, call the first dictionary data; if the original file is in C, call the second dictionary data. Filter out useless information in the original file code that does not affect the code logic, including comments, blank lines, newline characters, and compiler instructions; Based on the first or second dictionary data called, filter out statements or code in the original file that do not have corresponding keywords between SystemVerilog and C language; Process each line of code in the remaining original file, performing corresponding keyword replacement based on the first or second dictionary data being called; Based on the characteristics of the target language, special keywords or syntax are adaptively post-processed and corrected, and finally the language-converted file is output.

[0005] Furthermore, the construction of the SystemVerilog and C language keyword mapping table includes: The extracted commonly used keywords are categorized into eight major categories: data type keywords, storage and scope keywords, flow control keywords, concurrency and event keywords, hardware modeling keywords, object-oriented and verification keywords, compiler instruction keywords, and others. The category information of keywords in each major category is identified, and keywords with the same category information in SystemVerilog and C language are extracted and placed in the same row of the keyword mapping table.

[0006] Furthermore, the adaptive post-processing and correction of special keywords or syntax based on the characteristics of the target language specifically includes: querying the keyword mapping table, and adapting the keywords according to the found grammatical keywords.

[0007] The beneficial effects of this invention are: This invention enables rapid and efficient conversion between SystemVerilog and C languages ​​using script files. It saves a significant amount of manpower, improves efficiency, avoids human-introduced errors and repetitive development work by using script tools, and can be reused across different projects. One-time script development provides lifelong benefits. Attached Figure Description

[0008] Figure 1 A flowchart illustrating a method for mutual conversion between SystemVerilog and C language provided by this invention; Figure 2 This is a flowchart illustrating the language conversion steps of traversing each original file in the list in this invention. Figure 3This invention extracts a keyword information table for the SystemVerilog programming language. Figure 4 This is a table mapping SystemVerilog and C language keywords constructed in this invention. Detailed Implementation

[0009] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0010] See Figures 1-4 The present invention provides a technical solution: A method for converting between SystemVerilog and C languages, such as... Figure 1 The steps shown are as follows: S1. Obtain the original file and extract commonly used keywords, keyword categories, and detailed descriptions of keywords for both SystemVerilog and C programming languages. See details in [link to documentation]. Figure 3 System Verilog conforms to the IEEE 1800 standard and is an extension of Verilog HDL. It adds many new features, making it more suitable for hardware verification and design.

[0011] S2. Construct a keyword mapping table between SystemVerilog and C language. The keyword mapping table is used to establish the mapping relationship between keywords in the two languages ​​and provide a keyword matching basis for code conversion. The construction of the SystemVerilog and C language keyword mapping table includes: S201. The extracted commonly used keywords are classified into eight major categories: data type keywords, storage and scope keywords, flow control keywords, concurrency and event keywords, hardware modeling keywords, object-oriented and verification keywords, compiler instruction keywords, and other categories. S202. Identify the category information of keywords in each major category, extract keywords with the same category information in SystemVerilog and C language, and place them in the same row of the keyword mapping table. See [link to keyword mapping table] for details. Figure 4 The table only shows a portion of the corresponding data type keywords; the corresponding tables for the other seven categories are similar.

[0012] S3. Using a scripting language, store the contents of the keyword mapping table in a dictionary data structure. The dictionary uses key-value pairs to store mutually matching SystemVerilog and C language keywords. Generate first dictionary data. In the first dictionary data, the key stores the SystemVerilog language keyword, and the value stores the matching C language keyword. Swap the key and value values ​​in the first dictionary data to generate second dictionary data. S4. Use a scripting language to store the paths or names of all the original files that need to be converted in a list data structure. S5. Iterate through each original file in the list and perform language conversion, as shown below. Figure 2 As shown, the specific steps include: S501. Identify the file extension of the original file. If the original file is in SystemVerilog, call the first dictionary data. If the original file is in C, call the second dictionary data. S502. Filter out useless information in the original file code that does not affect the code logic, including comments, blank lines, newline characters, and compiler instructions; S503. Based on the first or second dictionary data being called, filter out statements or code in the original file that do not have corresponding keywords between SystemVerilog and C language; S504. Process each line of code in the remaining original file, and perform corresponding keyword replacement processing based on the first or second dictionary data called; S505. Based on the characteristics of the target language, perform adaptive post-processing and correction on special keywords or syntax, and finally output the language-converted file.

[0013] In one specific embodiment, the adaptive post-processing and correction of special keywords or syntax based on the characteristics of the target language includes: querying a keyword mapping table, and adapting the keywords according to the found grammatical keywords.

[0014] Alternatively, you can search for syntax keywords and then adapt the keywords accordingly; or adapt the keywords sequentially.

[0015] This invention enables rapid and efficient conversion between SystemVerilog and C languages ​​using script files. It saves a significant amount of manpower, improves efficiency, avoids human-introduced errors and repetitive development work by using script tools, and can be reused across different projects. One-time script development provides lifelong benefits.

[0016] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A method for converting between systemverilog and C, comprising: The method comprises the following steps: ​ Obtaining original files, extracting common keywords, keyword categories and detailed keyword information of SystemVerilog programming language and C language respectively; Building a keyword correspondence table of SystemVerilog and C language, which is used to establish a mapping relationship between the keywords of the two languages and provide a keyword matching basis for code conversion; Storing the content of the keyword correspondence table in a dictionary data structure using a script language, and storing the keywords of SystemVerilog and C language that match each other using key-value pairs in the dictionary; Generating first dictionary data, in which the key saves the keywords of SystemVerilog language and the value saves the keywords of C language that match the keywords of SystemVerilog language, and generating second dictionary data by swapping the key and value in the first dictionary data; Storing the paths or names of all original files that need to be converted in a list data structure using a script language; Iterating through each original file in the list to perform language conversion, which comprises the following steps: Identifying the suffix of the original file, if the original file is in SystemVerilog language, calling the first dictionary data, if the original file is in C language, calling the second dictionary data; Filtering useless information in the original file code that does not affect the code logic, including comments, blank lines, line breaks and compiler instructions; According to the called first or second dictionary data, filtering the statements or codes in the original file that have no corresponding keywords between SystemVerilog and C language; Processing each line of code of the remaining original file, and performing corresponding keyword replacement processing according to the called first or second dictionary data; According to the characteristics of the target language, adaptive post-processing and correction are performed on special keywords or syntax, and finally the language converted file is outputted.

2. The method of claim 1, wherein: The building of the keyword correspondence table of SystemVerilog and C language comprises: Classifying the extracted common keywords, which are classified into eight categories, including data type category keywords, storage and scope category keywords, flow control category keywords, concurrency and event category keywords, hardware modeling category keywords, object-oriented and verification category, compiler instruction category and other categories; Identifying the category information of the keywords in each category, and extracting the keywords with the same category information in SystemVerilog and C language into the same row in the keyword correspondence table.

3. The method of claim 1, wherein the systemverilog and C language are converted to each other. The adaptive post-processing and correction of special keywords or syntax according to the characteristics of the target language specifically comprises: querying the keyword correspondence table, and adapting the keywords according to the found syntax keywords.

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