Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device.The display panel comprises a pixel circuit and a light-emitting device which are electrically connected, the pixel circuit comprises a driving transistor, a data writing module and a bias adjusting module, the input end of the data writing module is electrically connected with a data signal line, and the output end of the data writing module is electrically connected with the driving transistor; the input end of the bias adjusting module is electrically connected with an adjusting voltage signal line, and the output end is electrically connected with the driving transistor; wherein in the nth-level pixel circuit, the control end of the data writing module is electrically connected with the nth-level first scanning line, the control end of the bias adjusting module is electrically connected with the (n + m) th-level or (n-m) th-level first scanning line, and m is a positive integer. According to the display panel, the data writing module and the bias adjusting module in the same pixel circuit can share the same group of peripheral driving circuits, the number of groups of the peripheral driving circuits in the display panel can be reduced, the frame width of the display panel can be reduced, and the narrow frame of the display panel can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] In the field of display, a peripheral driving circuit is usually arranged in a display panel to drive a pixel circuit to work. The peripheral driving circuit is usually arranged in a frame area of the display panel.

[0003] In the prior art, in order to drive the pixel circuit to work normally, the number of groups of the peripheral driving circuit needs to be set to be relatively large, which is not conducive to the realization of narrow frame of the display panel. Therefore, there is an urgent need for a solution. SUMMARY

[0004] Therefore, the embodiments of the present application provide a display panel and a display device to solve the above problems.

[0005] In a first aspect, the embodiments of the present application provide a display panel, comprising a pixel circuit and a light emitting device electrically connected, the pixel circuit comprising: a driving transistor for generating a light emitting driving current; a data writing module, an input end of the data writing module being electrically connected with a data signal line and an output end of the data writing module being electrically connected with the driving transistor; a bias adjusting module, an input end of the bias adjusting module being electrically connected with an adjusting voltage signal line and an output end of the bias adjusting module being electrically connected with the driving transistor; In the nth stage pixel circuit, a control end of the data writing module is electrically connected with an nth stage first scan line, a control end of the bias adjusting module is electrically connected with an nth+m stage or an nth-m stage first scan line, and m is a positive integer.

[0006] In a second aspect, the embodiments of the present application further provide a display panel, comprising a pixel circuit and a light emitting device electrically connected, the pixel circuit comprising: a driving transistor for generating a light emitting driving current; a data writing transistor, a first pole of the data writing transistor being electrically connected with a data signal line and a second pole of the data writing transistor being electrically connected with a first pole of the driving transistor; a bias adjusting transistor, a first pole of the bias adjusting transistor being electrically connected with an adjusting voltage signal line and a second pole of the bias adjusting transistor being electrically connected with the first pole or the second pole of the driving transistor; a threshold value compensating transistor, a first pole of the threshold value compensating transistor being electrically connected with a second pole of the driving transistor and a second pole of the threshold value compensating transistor being electrically connected with a gate of the driving transistor; The gate reset transistor has a first pole electrically connected with the first reset voltage signal line, a second pole electrically connected with the second pole of the driving transistor, and a gate electrically connected with the first reset voltage signal line. In the nth pixel circuit, the gate of the bias adjustment transistor is electrically connected with the nth second scan line, and the gate of the gate reset transistor is electrically connected with the nth-m second scan line, where m is a positive integer.

[0007] In a third aspect, based on the same inventive concept, the embodiments of the present application provide a display device, which comprises the display panel provided in the first aspect and the second aspect.

[0008] In the embodiments of the present application, the data writing module in the nth pixel circuit is electrically connected with the nth first scan line, and the bias adjustment module is electrically connected with the nth+m first scan line or the nth-m first scan line. Therefore, the data writing module and the bias adjustment module can share the same set of peripheral driving circuits, which is conducive to reducing the number of sets of peripheral driving circuits in the display panel, thereby being conducive to reducing the frame width of the display panel and realizing narrow frame of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0010] Figure 1 A schematic diagram of a display panel provided in the embodiments of the present application; Figure 2 A schematic diagram of a pixel circuit provided in the embodiments of the present application; Figure 1 A schematic diagram of a pixel circuit provided in the embodiments of the present application; Figure 3 A schematic diagram of another display panel provided in the embodiments of the present application; Figure 4 A schematic diagram of another pixel circuit provided in the embodiments of the present application; Figure 1 A schematic diagram of another pixel circuit provided in the embodiments of the present application; Figure 5 A schematic diagram of another pixel circuit provided in the embodiments of the present application; Figure 1 A schematic diagram of another pixel circuit provided in the embodiments of the present application; Figure 6 Figure 1 A schematic diagram of another pixel circuit provided in the embodiments of the present application; Figure 7 A schematic diagram of another pixel circuit provided in the embodiments of the present application; Figure 1 A schematic diagram of another pixel circuit provided in the embodiments of the present application; Figure 8 A schematic diagram of another display panel provided in the embodiments of the present application; ​Figure 9 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application; Figure 10 for Figure 7 The image shows a timing diagram of a pixel circuit. Figure 11 for Figure 1 Another schematic diagram of a mid-pixel circuit; Figure 12 for Figure 1 Another schematic diagram of a mid-pixel circuit; Figure 13 for Figure 1 Another schematic diagram of a mid-pixel circuit; Figure 14 for Figure 1 Another schematic diagram of a mid-pixel circuit; Figure 15 for Figure 1 Another schematic diagram of a mid-pixel circuit; Figure 16 for Figure 15 The image shows a timing diagram of a pixel circuit. Figure 17 for Figure 1 Another schematic diagram of a mid-pixel circuit; Figure 18 for Figure 1 Another schematic diagram of a mid-pixel circuit; Figure 19 for Figure 18 The image shows a timing diagram of a pixel circuit. Figure 20 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0011] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0012] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0013] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0014] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this article generally indicates that the related objects before and after it have an "or" relationship.

[0015] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0016] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application. Figure 2 for Figure 1 A schematic diagram of a mid-pixel circuit.

[0017] This application embodiment provides a display panel 01, such as Figure 1 As shown, the display panel 01 includes a pixel circuit 10 and a light-emitting device 20 electrically connected. The pixel circuit 10 drives the light-emitting device 20 to emit light. For example, the pixel circuit 10 is arranged in an array in the display panel 01 along a first direction X and a second direction Y. The first direction X can be the row direction of the display panel 01, and the second direction Y can be the column direction of the display panel 01.

[0018] Combination Figure 2 As shown, the pixel circuit 10 includes a driving transistor Td, a data writing module 11, and a bias adjustment module 12. The driving transistor Td is used to generate a light-emitting driving current.

[0019] The input terminal of the data writing module 11 is electrically connected to the data signal line DL1, and the output terminal is electrically connected to the driving transistor Td. The data signal line DL1 is used to transmit the data voltage Vdata. The input terminal of the bias adjustment module 12 is electrically connected to the adjustment voltage signal line DL2, and the output terminal is electrically connected to the driving transistor Td. The adjustment voltage signal line DL2 is used to transmit the bias adjustment voltage DVH.

[0020] For example, such as Figure 2 As shown, the output terminal of the data writing module 11 is electrically connected to the first terminal of the driving transistor Td. The data writing module 11 is used to transmit the data voltage Vdata to the first terminal of the driving transistor Td so that the data voltage Vdata can be written into the gate of the driving transistor Td.

[0021] The output terminal of the bias adjustment module 12 is electrically connected to the first terminal of the driving transistor Td. The bias adjustment module 12 is used to transmit the bias adjustment voltage DVH to the driving transistor Td to improve the bias state of the driving transistor Td.

[0022] In the nth pixel circuit 10, the control terminal of the data writing module 11 is electrically connected to the first scan line S1 of the nth level, and the control terminal of the bias adjustment module 12 is electrically connected to the first scan line S1 of the (n+m)th or (nm)th level, where m is a positive integer. Figure 2 The diagram only illustrates the situation where the control terminal of the bias adjustment module 12 is electrically connected to the first scan line S1 of the (n+m)th stage.

[0023] For example, such as Figure 3 As shown, Figure 3 This is a schematic diagram of another display panel provided in an embodiment of this application. The display panel 01 includes a display area AA and a border area NA surrounding the display area AA, a pixel circuit 10 and a light-emitting device 20. Figure 3 (Not shown in the image) Located in the display area AA, the border area NA includes multiple sets of peripheral driving circuits 30. The peripheral driving circuits 30 are electrically connected to the pixel circuit 10 and are used to provide scanning signals to the pixel circuit 10 to drive the pixel circuit 10 to work.

[0024] The same set of peripheral driving circuits 30 includes multiple cascaded shift register units 301, and each shift register unit 301 is electrically connected to at least one row of pixel circuits 10. In the display area AA, multiple pixel circuits 10 arranged along the first direction X (row direction) can be called a row of pixel circuits. Multiple pixel circuits 10 in a row of pixel circuits 10 are pixel circuits of the same level 10. The nth level pixel circuit 10 can refer to the nth row of pixel circuits. The first scan line S1 electrically connected to the data writing module 11 in the nth row of pixel circuits can be called the nth level first scan line S1, where n is a positive integer. The (n+m)th or (nm)th level first scan line S1 can refer to the first scan line S1 electrically connected to the data writing module 11 in the (n+m)th row of pixel circuits or the first scan line S1 electrically connected to the data writing module 11 in the (nm)th row of pixel circuits.

[0025] It should be noted that, since both n and m are positive integers, when nm ≤ 0, the first scan line S1 of the nm-th level can refer to the first scan line S1 additionally set on the side of the first row of pixel circuits near the edge of the display panel. These first scan lines S1 may not be electrically connected to the data writing module 11. When n+m is greater than the total number of rows of pixel circuits, the first scan line S1 of the n+m-th level can refer to the first scan line S1 additionally set on the side of the last row of pixel circuits near the edge of the display panel. These first scan lines S1 may not be electrically connected to the data writing module 11. Figure 3 The example shown is m=1.

[0026] For example, such as Figure 3 As shown, the multiple sets of peripheral driving circuits 30 include a first set of peripheral driving circuits 31. The shift register unit 301 in the first set of peripheral driving circuits 31 is electrically connected to the pixel circuit 10 through the first scan line S1. In the first set of peripheral driving circuits 31, multiple shift register units 301 are electrically connected to multiple levels of the first scan line S1, and the multiple shift register units 301 sequentially transmit scan signals to the first scan line S1.

[0027] In this embodiment, the data writing module 11 in the nth-level pixel circuit 10 is electrically connected to the first scan line S1 of the nth level, and the bias adjustment module 12 is electrically connected to the first scan line S1 of the (n+m)th or (nm)th level. Therefore, the data writing module 11 and the bias adjustment module 12 can share the same set of peripheral driving circuits, for example... Figure 3 The first set of peripheral driving circuits 31 shown eliminates the need for an additional set of peripheral driving circuits for the bias adjustment module 12, which helps reduce the number of sets of peripheral driving circuits in the display panel 01, thereby helping to reduce the bezel width of the display panel 01 and achieve a narrow bezel for the display panel 01.

[0028] In one embodiment of this application, such as Figure 2 As shown, the data writing module 11 includes a data writing transistor T1. The first terminal of the data writing transistor T1 is electrically connected to the data signal line DL1, the second terminal is electrically connected to the first terminal of the driving transistor Td, and the gate is electrically connected to the control terminal of the data writing module 11. The data writing module 11 may include only one data writing transistor T1.

[0029] The bias adjustment module 12 includes a bias adjustment transistor T2. The first terminal of the bias adjustment transistor T2 is electrically connected to the adjustment voltage signal line DL2, the second terminal is electrically connected to the first terminal of the drive transistor Td, and the gate is electrically connected to the control terminal of the bias adjustment module 12. The bias adjustment module 12 may include only one bias adjustment transistor T2.

[0030] The channel type of the data writing transistor T1 is the same as that of the bias adjustment transistor T2.

[0031] In this embodiment, the channel type of the data writing transistor T1 is the same as that of the bias adjustment transistor T2. Therefore, when both the gate of the data writing transistor T1 and the gate of the bias adjustment transistor T2 receive a high-level signal or both receive a low-level signal, their switching states can be the same. That is, within the same pixel circuit 10, the level of the enable signal required to turn on the data writing transistor T1 and the bias adjustment transistor T2 can be the same.

[0032] Since the gate of the data writing transistor T1 is electrically connected to the first scan line S1, the enable signal for controlling the data writing transistor T1 to turn on, transmitted by the first scan line S1, can also be used as the enable signal for controlling the bias adjustment transistor T2 to turn on. This makes it possible for the data writing transistor T1 and the bias adjustment transistor T2 to be connected to different levels of the first scan line S1 in the same pixel circuit 10, as long as the time periods for transmitting the enable signals of the first scan line S1 connected to the data writing transistor T1 and the first scan line S1 connected to the bias adjustment transistor T2 are staggered. This is beneficial to realize that the data writing transistor T1 and the bias adjustment transistor T2 in the same pixel circuit 10 can both be electrically connected to the first group of peripheral driving circuits 31, reducing the number of groups of peripheral driving circuits.

[0033] In the same pixel circuit 10, since the data writing transistor T1 and the bias adjustment transistor T2 are electrically connected to the first scan line S1 of different levels, and the first scan line S1 of different levels transmits the enable signal at different times, the data writing transistor T1 and the bias adjustment transistor T2 in the same pixel circuit 10 can be turned on at different times to meet the normal operation requirements of the pixel circuit 10.

[0034] Optional, such as Figure 2 As shown, both the data writing transistor T1 and the bias adjustment transistor T2 are P-type transistors. Both the data writing transistor T1 and the bias adjustment transistor T2 can be made of low-temperature polycrystalline silicon.

[0035] Furthermore, such as Figure 4 As shown, Figure 4 for Figure 1 Another schematic diagram of the mid-pixel circuit shows that the data writing transistor T1 and the bias adjustment transistor T2 can be a top-bottom dual-gate structure. Since gate voltages can be applied to both the top and bottom gates simultaneously, the gate control capability of the data writing transistor T1 and the bias adjustment transistor T2 can be enhanced. This significantly reduces leakage current in the off state while maintaining high on-current, thereby increasing the switching ratio of the data writing transistor T1 and the bias adjustment transistor T2.

[0036] Meanwhile, since the top and bottom gates can surround the channel of the transistor from both sides, a more symmetrical and uniform electric field distribution can be formed, which helps to improve the mobility of charge carriers. Therefore, making the data writing transistor T1 and the bias adjustment transistor T2 into a top and bottom dual-gate structure can also improve the mobility of charge carriers of both, thereby improving the device performance of the data writing transistor T1 and the bias adjustment transistor T2.

[0037] Optional, such as Figure 4As shown, in the data writing transistor T1 and the bias adjustment transistor T2, the top gate is electrically connected to the first scan line S1, and the bottom gate receives a fixed potential signal, such as the power supply voltage PVDD.

[0038] By having the bottom gate receive a fixed potential signal, the bottom gate can provide a stable electric field environment. The top gate only needs to be finely adjusted to achieve precise threshold voltage control, reducing threshold voltage fluctuations during use. This helps to reduce threshold voltage fluctuations in the data writing transistor T1 and the bias adjustment transistor T2, thereby improving the device uniformity of the data writing transistor T1 and the bias adjustment transistor T2 in the display panel 01.

[0039] In addition, such as Figure 4 As shown, the driving transistor Td can also be a P-type transistor and has a top-bottom dual-gate structure, with its bottom gate receiving the power supply voltage PVDD.

[0040] Optional, such as Figure 5 As shown, Figure 5 for Figure 1 Another schematic diagram of the mid-pixel circuit shows that both the data writing transistor T1 and the bias adjustment transistor T2 are N-type transistors, and the active layers of both the data writing transistor T1 and the bias adjustment transistor T2 include metal oxide.

[0041] For example, the active layers of both the data write transistor T1 and the bias adjustment transistor T2 consist of indium gallium zinc oxide (IGZO). Metal-oxide-semiconductor materials typically have wide band gaps, making it difficult for electrons to transition from the valence band to the conduction band without external excitation. Therefore, in the off-state, the number of electrons in the channel is extremely small, resulting in very low off-state leakage current.

[0042] Moreover, metal oxide materials are highly insulating in their natural state and only form conductive channels when an appropriate gate voltage is applied. This characteristic means that there are almost no free carriers in the off state, thus significantly reducing the off-state leakage current.

[0043] Therefore, by making the active layers of both the data writing transistor T1 and the bias adjustment transistor T2 include metal oxide, the material properties of metal oxide can be used to reduce the off-state leakage current of the data writing transistor T1 and the bias adjustment transistor T2. This is beneficial to reducing the power consumption of the pixel circuit 10 and improving the operational reliability of the pixel circuit 10.

[0044] Furthermore, such as Figure 6 As shown, Figure 6 for Figure 1Another schematic diagram of the mid-pixel circuit shows that both the data writing transistor T1 and the bias adjustment transistor T2 are top-bottom dual-gate structures, with the top gate and bottom gate connected together, and both electrically connected to the first scan line S1.

[0045] By connecting the top gate and the bottom gate together, they can work together in the channel region of the transistor to provide a more uniform and powerful electric field. This makes it more effective to control the carrier concentration and mobility in the channel, thereby improving the driving capability of the data writing transistor T1 and the bias adjustment transistor T2.

[0046] Furthermore, by connecting the top gate and the bottom gate together, the voltages of the bottom gate and the top gate can be the same, which helps to reduce parasitic capacitance and resistance caused by gate voltage differences, thereby improving the reliability and consistency of the data writing transistor T1 and the bias adjustment transistor T2.

[0047] Please continue to refer to this. Figure 2 , Figure 4- Figure 6 In one embodiment of this application, the pixel circuit 10 further includes a threshold compensation module 13 and a gate reset module 14. The input terminal of the threshold compensation module 13 is electrically connected to the second pole of the driving transistor Td, and the output terminal is electrically connected to the gate of the driving transistor Td.

[0048] The input terminal of the gate reset module 14 is electrically connected to the first reset voltage signal line XL1, and the output terminal is electrically connected to the driving transistor Td. The gate reset module 14 is used to transmit the first reset voltage Vref1 on the first reset voltage signal line XL1 to the gate of the driving transistor Td so as to reset the gate of the driving transistor Td.

[0049] Both the threshold compensation module 13 and the gate reset module 14 include metal-oxide transistors.

[0050] For example, such as Figure 2 , Figure 4- Figure 6 As shown, the threshold compensation module 13 includes a threshold compensation transistor T3. The first terminal of the threshold compensation transistor T3 is electrically connected to the second terminal of the driving transistor Td, and the second terminal of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor Td. The threshold compensation transistor T3 is used to compensate the threshold voltage of the driving transistor Td to the gate of the driving transistor Td.

[0051] The gate reset module 14 includes a gate reset transistor T4. The first terminal of the gate reset transistor T4 is electrically connected to the first reset voltage signal line XL1, and the second terminal of the gate reset transistor T4 is electrically connected to the gate of the driving transistor Td. The gate reset transistor T4 is used to transmit the first reset voltage Vref1 to the gate of the driving transistor Td.

[0052] The active layers of both the threshold compensation transistor T3 and the gate reset transistor T4 consist of metal oxide.

[0053] For example, the active layers of both the threshold compensation transistor T3 and the gate reset transistor T4 include indium gallium zinc oxide (IGZO).

[0054] In this embodiment, both the threshold compensation module 13 and the gate reset module 14 include metal oxide transistors. This allows the low leakage current characteristic of metal oxide transistors to be utilized to reduce the leakage current of the gate potential of the driving transistor Td through the threshold compensation module 13 and the gate reset module 14. This is beneficial to improving the stability of the gate potential of the driving transistor Td, thereby improving the stability of the driving current provided by the pixel circuit 10 to the light-emitting device 20.

[0055] Optional, such as Figure 4 and Figure 6 As shown, both the threshold compensation transistor T3 and the gate reset transistor T4 are top-bottom dual-gate structures, with the top gate connected to the bottom gate. Connecting the top and bottom gates allows them to work together in the transistor's channel region, providing a more uniform and powerful electric field. This makes the control of carrier concentration and mobility in the channel more effective, thereby improving the driving capability of both the threshold compensation transistor T3 and the gate reset transistor T4.

[0056] Furthermore, by connecting the top gate and the bottom gate together, the voltages of the bottom gate and the top gate can be the same, which helps to reduce parasitic capacitance and resistance caused by gate voltage differences, thereby improving the reliability and consistency of the threshold compensation transistor T3 and the gate reset transistor T4.

[0057] Optional, such as Figure 2 , Figure 4- Figure 6 As shown, the gate of the gate reset transistor T4 is electrically connected to the gate reset scan line S1N, and the gate of the threshold compensation transistor T3 is electrically connected to the threshold compensation scan line S2N. The gate reset scan line S1N and the threshold compensation scan line S2N can be connected to different peripheral driving circuits 30 along with the first scan line S1.

[0058] For example, in combination Figure 3As shown, the multiple sets of peripheral driving circuits 30 also include a second set of peripheral driving circuits 32 and a third set of peripheral driving circuits 33. The shift register unit 301 in the second set of peripheral driving circuits 32 is electrically connected to the pixel circuit 10 through the gate reset scan line S1N. In the second set of peripheral driving circuits 32, multiple shift register units 301 sequentially transmit scan signals to the multi-level gate reset scan lines S1N. Among them, the gate reset scan line S1N connected to the gate reset transistor T4 in the nth level pixel circuit can be called the nth level gate reset scan line S1N. One shift register unit 301 in the second set of peripheral driving circuits 32 can be electrically connected to one or two levels of gate reset scan lines S1N. Figure 3 This only illustrates the electrical connection between a shift register unit 301 in the second set of peripheral drive circuits 32 and the corresponding two-stage gate reset reset scan line S1N.

[0059] The shift register unit 301 in the third set of peripheral driving circuits 33 is electrically connected to the pixel circuit 10 through the threshold compensation scan line S2N. In the third set of peripheral driving circuits 33, multiple shift register units 301 sequentially transmit scanning signals to the multi-level threshold compensation scan lines S2N. Among them, the threshold compensation scan line S2N connected to the threshold compensation transistor T3 in the nth level pixel circuit can be called the nth level threshold compensation scan line S2N. One shift register unit 301 in the third set of peripheral driving circuits 33 can be electrically connected to one or two levels of threshold compensation scan lines S2N. Figure 3 This only illustrates the situation where a shift register unit 301 in the third set of peripheral drive circuits 33 is electrically connected to the corresponding two-stage threshold compensation scan line S2N.

[0060] For example, such as Figure 3 As shown, the first set of peripheral driving circuits 31 can drive the pixel circuit 10 on both sides, while the second set of peripheral driving circuits 32 and the third set of peripheral driving circuits 33 can drive the pixel circuit 10 on one side. The second set of peripheral driving circuits 32 and the third set of peripheral driving circuits 33 can be located on opposite sides of the display area AA.

[0061] In this embodiment, the gate reset scan line S1N, the threshold compensation scan line S2N, and the first scan line S1 are connected to different peripheral driving circuits 30. Then, the gate reset transistor T4 and the threshold compensation transistor T3 can be controlled by independent control timing, which is beneficial to improving the driving flexibility of the pixel circuit 10.

[0062] Optional, such as Figure 7 As shown, Figure 7 for Figure 1Another schematic diagram of the pixel circuit shows that in the nth-level pixel circuit 10, the gate of the threshold compensation transistor T3 is electrically connected to the first scan line S1 of the nth level. The gate of the gate reset transistor T4 is electrically connected to the first scan line S1 of the npth level, where p is a positive integer.

[0063] That is, in the nth level pixel circuit 10, the gate of the threshold compensation transistor T3 and the gate of the data writing transistor T1 are both electrically connected to the first scan line S1 (the first scan line of the nth level) of the same level, and the gate of the gate reset transistor T4 is electrically connected to the first scan line S1 of the npth level connected to the data writing transistor T1 in the npth level pixel circuit.

[0064] For example, such as Figure 8 As shown, Figure 8 This is a schematic diagram of another display panel provided in an embodiment of this application. The plurality of peripheral driving circuits 30 include a first peripheral driving circuit 31. The shift register unit 301 in the first peripheral driving circuit 31 is electrically connected to the pixel circuit 10 via a first scan line S1. In the first peripheral driving circuit 31, the shift register unit 301 is electrically connected to the first scan line S1 in a one-to-one correspondence, and the shift register unit 301 sequentially transmits scan signals to the first scan line S1. Specifically, the nth level first scan line S1 is electrically connected to the nth level shift register unit 301 of the first peripheral driving circuit 31, and the npth level first scan line S1 is electrically connected to the npth level shift register unit 301 of the first peripheral driving circuit 31.

[0065] It should be noted that when np≤0, the first scan line S1 of the npth level can refer to the first scan line S1 additionally set on the side of the first row pixel circuit near the edge of the display panel. These first scan lines S1 may not be electrically connected to the data writing module 11. Figure 8 The example shown is p=1.

[0066] Based on this configuration, in the same pixel circuit 10, the data writing transistor T1, bias adjustment transistor T2, threshold compensation transistor T3, and gate reset transistor T4 can share the same set of peripheral driving circuits, such as... Figure 8 The first set of peripheral driving circuits 31 shown is beneficial to further reduce the number of peripheral driving circuits in the display panel 01, thereby helping to further achieve a narrow bezel in the display panel 01.

[0067] In the nth-level pixel circuit 10, the data writing transistor T1 and the threshold compensation transistor T3 are electrically connected to the nth-level first scan line S1. During the period when the first scan line transmits the enable signal, the data writing transistor T1 and the threshold compensation transistor T3 are turned on, and the data voltage Vdata can be transmitted to the gate of the driving transistor Td through the data writing transistor T1, the driving transistor Td, and the threshold compensation transistor T3.

[0068] When the gate reset transistor T4 is electrically connected to the first scan line S1 of the np-th stage, before the data voltage Vdata is written to the driving transistor Td, the first scan line S1 of the np-th stage can transmit an enable signal to control the gate reset transistor T4 to turn on. The first reset voltage Vref1 is transmitted to the gate of the driving transistor Td through the gate reset transistor T4 to complete the reset of the gate potential of the driving transistor Td.

[0069] Optional, np < 10.

[0070] When the bias adjustment transistor T2 is electrically connected to the first scan line S1 of the (n+m)th stage, after the data voltage Vdata is written to the driving transistor Td, the first scan line S1 of the (n+m)th stage can transmit an enable signal to control the bias adjustment transistor T2 to turn on. The adjustment voltage DVH is transmitted to the driving transistor Td through the bias adjustment transistor T2 to adjust the bias state of the driving transistor Td.

[0071] When the bias adjustment transistor T2 is electrically connected to the first scan line S1 of the nm-th stage, before the data voltage Vdata is written to the driving transistor Td, the first scan line S1 of the nm-th stage can transmit an enable signal to control the bias adjustment transistor T2 to turn on. The adjustment voltage DVH is transmitted to the driving transistor Td through the bias adjustment transistor T2 to adjust the bias state of the driving transistor Td. At this time, m≠p can be set so that the bias adjustment transistor T2 and the gate reset transistor T4 can be turned on at different times, which helps to avoid the gate reset process and the bias adjustment process of the driving transistor Td from interfering with each other.

[0072] Please continue to refer to this. Figure 2 , Figure 4- Figure 7 The pixel circuit 10 also includes a power supply voltage writing transistor T5, a light emission control transistor T6, and an anode reset transistor T7. The first terminal of the power supply voltage writing transistor T5 is electrically connected to the first power supply voltage signal line DL3, and the second terminal of the power supply voltage writing transistor T5 is electrically connected to the first terminal of the driving transistor Td. The first power supply voltage signal line DL3 is used to transmit the power supply voltage PVDD.

[0073] The first terminal of the light-emitting control transistor T6 is electrically connected to the second terminal of the driving transistor Td. The second terminal of the light-emitting control transistor T6 is electrically connected to the first terminal of the light-emitting device 20, which can be an organic light-emitting diode (OLED). The first terminal of the light-emitting device 20 can be its anode. The second terminal of the light-emitting device 20 receives the power supply voltage PVEE. The first terminal of the anode reset transistor T7 is electrically connected to the second reset voltage signal line XL2. The second terminal of the anode reset transistor T7 is electrically connected to the first terminal of the light-emitting device 20. The second reset voltage signal line XL2 is used to transmit the second reset voltage Vref2. The anode reset transistor T7 can transmit the second reset voltage Vref2 to the first terminal of the light-emitting device 20, completing the reset of the first terminal of the light-emitting device 20.

[0074] For example, such as Figure 9 As shown, Figure 9 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. The display panel 01 includes a substrate PI, an array layer AR, and a light-emitting device 20. The pixel circuit 10 is located in the array layer AR, and the light-emitting device 20 is located on the side of the array layer AR away from the substrate PI.

[0075] The light-emitting device 20 includes a first electrode 21, a second electrode 22, and a light-emitting layer 23 located between the first electrode 21 and the second electrode 22. The first electrode 21 is located on the side of the light-emitting layer 23 close to the substrate PI. The pixel circuit 10 is electrically connected to the first electrode 21. The first electrode 21 can be the anode of the light-emitting device 20, and the second electrode 22 can be the cathode of the light-emitting device 20.

[0076] It should be noted that, Figure 9 The image only shows one transistor in the pixel circuit 10 connected to the light-emitting device 20. This transistor can be a light-emitting control transistor T6 or an anode reset transistor T7.

[0077] The channel type of the power supply voltage writing transistor T5 is the same as that of the light-emitting control transistor T6.

[0078] For example, such as Figure 2 , Figure 4- Figure 7 As shown, both the power supply voltage writing transistor T5 and the light-emitting control transistor T6 are P-type transistors.

[0079] Furthermore, such as Figure 4 , Figure 6 and Figure 7 As shown, both the power supply voltage writing transistor T5 and the light-emitting control transistor T6 are top-bottom dual-gate structures. The top gate is electrically connected to the control signal line, while the bottom gate receives a fixed potential signal, such as the power supply voltage PVDD.

[0080] By having the bottom gate receive a fixed potential signal, the bottom gate can provide a stable electric field environment. The top gate only needs to be finely adjusted to achieve precise threshold voltage control, reducing threshold voltage fluctuations during use. This helps to reduce threshold voltage fluctuations in the power supply voltage writing transistor T5 and the light-emitting control transistor T6, thereby improving the device uniformity of the power supply voltage writing transistor T5 and the light-emitting control transistor T6 in the display panel 01.

[0081] Optional, such as Figure 7 As shown, the gate of the power supply voltage writing transistor T5 and the gate of the light-emitting control transistor T6 are both electrically connected to the light-emitting control signal line EM, and the gate of the anode reset transistor T7 is electrically connected to the second scan line S2.

[0082] For example, such as Figure 7 As shown, the channel type of the anode reset transistor T7 is different from that of the data write transistor T1. The anode reset transistor is a P-type transistor.

[0083] For example, such as Figure 8 As shown, the multiple peripheral driving circuits 30 also include a second peripheral driving circuit 32' and a light-emitting peripheral driving circuit 30E. The shift register unit 301 in the second peripheral driving circuit 32' is electrically connected to the pixel circuit 10 through the second scan line S2. In the second peripheral driving circuit 32', the shift register unit 301 is electrically connected to the second scan line S2 in a one-to-one correspondence, and the shift register unit 301 sequentially transmits scanning signals to the second scan line S2. Among them, the second scan line S2 connected to the anode reset transistor T7 in the nth level pixel circuit 10 is the nth level second scan line S2, and the nth level second scan line S2 is electrically connected to the nth level shift register unit 301 in the second peripheral driving circuit 32'.

[0084] The shift register unit 301 in the light-emitting peripheral driving circuit 30E is electrically connected to the pixel circuit 10 via the light-emitting control signal line EM. In the light-emitting peripheral driving circuit 30E, the shift register unit 301 is electrically connected to the corresponding light-emitting control signal line EM, and the shift register unit 301 sequentially transmits scan signals to the light-emitting control signal line EM. The light-emitting control signal line EM connected to the light-emitting control transistor T6 in the nth-level pixel circuit 10 can be referred to as the nth-level light-emitting control signal line EM. One shift register unit 301 in the light-emitting peripheral driving circuit 30E can be electrically connected to one or two levels of light-emitting control signal lines EM. Figure 8 This only illustrates the electrical connection between a shift register unit 301 in the light-emitting peripheral driving circuit 30E and the primary light-emitting control signal line EM.

[0085] It should be noted that, Figure 3 The display panel 01 shown also includes, for example,Figure 8 The light-emitting peripheral driving circuit 30E shown is... Figure 8 The second set of peripheral drive circuits 32' in the display panel 01 shown are... Figure 3 The second set of peripheral driving circuits 32 in the display panel 01 shown are not the same, and the transistors in the pixel circuit 10 connected to them are different. Figure 8 The display panel shown is relative to Figure 3 The display panel shown further reduces the number of groups of peripheral drive circuits 30.

[0086] Furthermore, in combination Figure 7 and Figure 8 As shown, the bias adjustment transistor T2 is electrically connected to the first scan line S1 of the (n+m)th stage. Figure 8 The display panel 01 shown is illustrated with m=1 and p=1 as an example.

[0087] Figure 10 for Figure 7 The diagram shown is a timing diagram of the pixel circuit. To facilitate understanding of this scheme, the following is combined with... Figure 10 and Figure 7 right Figure 7 The working process of the pixel circuit shown is described.

[0088] The operation of the pixel circuit 10 includes a reset stage t1, a data writing stage t2, a bias adjustment stage t3, and a light emission stage t4.

[0089] During the reset phase t1, the first scan line S1 of the np-th stage transmits an enable signal (such as a high-level signal), the gate reset transistor T4 is turned on, and the first reset voltage Vref1 is transmitted to the gate of the driving transistor Td through the gate reset transistor T4 to reset the gate potential of the driving transistor Td.

[0090] Simultaneously, the second scan line S2 of the nth stage transmits an enable signal (such as a low-level signal), the anode reset transistor T7 is turned on, and the second reset voltage Vref2 is transmitted to the first electrode of the light-emitting device 20 through the anode reset transistor T7 to reset the first electrode of the light-emitting device 20.

[0091] During the data writing phase t2, the first scan line S1 of the nth stage transmits an enable signal (such as a high-level signal), and the data writing transistor T1 and the threshold compensation transistor T3 are turned on. The data voltage Vdata is transmitted to the first terminal of the driving transistor Td through the data writing transistor T1. Since the data voltage Vdata is greater than the first reset voltage Vref1, the driving transistor Td is turned on, and the data voltage Vdata is transmitted to the gate of the driving transistor Td through the turned-on driving transistor Td and the threshold compensation transistor T3.

[0092] During the bias adjustment phase t3, the first scan line S1 of the (n+m)th stage transmits an enable signal (such as a high-level signal), the bias adjustment transistor T2 is turned on, and the adjustment voltage DVH is transmitted to the driving transistor Td through the bias adjustment transistor T2 to adjust the bias state of the driving transistor Td.

[0093] During the light-emitting stage t4, the light-emitting control signal line EM transmits an enable signal (such as a low-level signal), the power supply voltage is written to transistor T5 and the light-emitting control transistor T6, and the driving transistor Td generates a light-emitting driving current and transmits it to the light-emitting device 20, driving the light-emitting device 20 to emit light.

[0094] It should be noted that when a frame of the display panel 01 includes a data frame and a sustain frame, the data frame can be set to include a reset phase t1, a data writing phase t2, a bias adjustment phase t3, and an emission phase t4. The sustain frame includes the emission phase t4, but does not include the data writing phase t2 and the bias adjustment phase t3. The brightness difference between the sustain frame and the data frame can be improved by adjusting the emission duration and / or the difference in the second reset voltage Vref2 between the sustain frame and the data frame, thereby improving the flicker problem of the display panel 01.

[0095] In one embodiment of this application, such as Figure 11 As shown, Figure 11 for Figure 1 Another schematic diagram of the mid-pixel circuit shows that the gate of the power supply voltage writing transistor T5, the gate of the light-emitting control transistor T6, and the gate of the anode reset transistor T7 are all electrically connected to the light-emitting control signal line EM.

[0096] The channel type of the anode reset transistor T7 is different from that of the light-emitting control transistor T6.

[0097] For example, such as Figure 11 As shown, the power supply voltage writing transistor T5 and the light-emitting control transistor T6 are both P-type transistors, while the anode reset transistor T7 is an N-type transistor.

[0098] Furthermore, the anode reset transistor T7 comprises a metal oxide, such as indium gallium zinc oxide (IGZO). The anode reset transistor T7 can be a top-bottom dual-gate structure, with the top and bottom gates connected. The top and bottom gates work together in the transistor's channel region, providing a more uniform and powerful electric field. This makes the control of carrier concentration and mobility in the channel more effective, thereby improving the driving capability of the anode reset transistor T7.

[0099] In this embodiment, the anode reset transistor T7, the light-emitting control transistor T6, and the power supply voltage writing transistor T5 are all electrically connected to the light-emitting control signal line EM. Therefore, the control signal line connected to the pixel circuit 10 can only include the first scan line S1 and the light-emitting control signal line EM. As can be seen from the above analysis, the first scan line S1 is electrically connected to the first group of peripheral driving circuits 31, and the light-emitting control signal line EM is electrically connected to the light-emitting peripheral driving circuit 30E. Therefore, it is only necessary to set the first group of peripheral driving circuits 31 and the light-emitting peripheral driving circuit 30E in the bezel area NA of the display panel 01, which is beneficial to further reduce the number of peripheral driving circuits, thereby further realizing the narrow bezel of the display panel 01.

[0100] Figure 12 for Figure 1 Another schematic diagram of a mid-pixel circuit.

[0101] In one embodiment of this application, such as Figure 12 As shown, the gate of the power supply voltage writing transistor T5 and the gate of the anode reset transistor T7 are both electrically connected to the second scan line S2, and the gate of the light emission control transistor T6 is electrically connected to the light emission control signal line EM.

[0102] The inventors of this application have discovered through research that when the gate of the anode reset transistor T7 is electrically connected to the light-emitting control signal line EM, since the channel type of the anode reset transistor T7 is different from that of the light-emitting control transistor T6, if the light-emitting control signal line EM transmits multiple enable pulse signals to control the power supply voltage to write to the transistor T5 and the light-emitting control transistor T6 to turn on multiple times during the light-emitting stage, the non-enable signal transmitted by the light-emitting control signal line EM will also control the anode reset transistor T7 to turn on multiple times, which can easily cause the first electrode of the light-emitting device 20 to be reset multiple times, affecting the light-emitting effect of the light-emitting device 20.

[0103] In view of this, in the embodiments of this application, the gate of the light-emitting control transistor T6 is electrically connected to the light-emitting control signal line EM, and the gates of the power supply voltage writing transistor T5 and the anode reset transistor T7 are both electrically connected to the second scan line S2. In the light-emitting stage, the light-emitting control transistor T6, the anode reset transistor T7, and the power supply voltage writing transistor T5 can be controlled separately. When the light-emitting control transistor T6 is turned on multiple times, the anode reset transistor T7 will not be turned on multiple times, which helps to improve the problem of the first electrode of the light-emitting device 20 being reset multiple times.

[0104] Furthermore, during the light-emitting stage, the second scan line S2 can transmit an enable signal to control the power supply voltage writing transistor T5 to remain in the on state. Since the channel type of the anode reset transistor T7 is different from that of the power supply voltage writing transistor T5, the anode reset transistor T7 can be in the off state at this time. Without affecting the light-emitting device 20 to emit light multiple times, the second reset voltage Vref2 is prevented from resetting the first electrode of the light-emitting device 20 through the anode reset transistor T7.

[0105] In addition, such as Figure 13 As shown, Figure 13 for Figure 1 Another schematic diagram of the mid-pixel circuit can be configured such that the gate of the light-emitting control transistor T6 and the gate of the anode reset transistor T7 are both electrically connected to the second scan line S2, and the gate of the power supply voltage writing transistor T5 is electrically connected to the light-emitting control signal line EM.

[0106] Based on this configuration, during the light-emitting stage, the power supply voltage writing transistor T5, the anode reset transistor T7, and the light-emitting control transistor T6 can be controlled separately. When the power supply voltage writing transistor T5 is turned on multiple times, the anode reset transistor T7 will not be turned on multiple times, which helps to improve the problem of the first electrode of the light-emitting device 20 being reset multiple times.

[0107] Furthermore, during the light-emitting stage, the second scan line S2 can transmit an enable signal to control the light-emitting control transistor T6 to remain in the on state. Since the channel type of the anode reset transistor T7 is different from that of the light-emitting control transistor T6, the anode reset transistor T7 can be in the off state at this time. Without affecting the light-emitting device 20 to emit light multiple times, the second reset voltage Vref2 is prevented from resetting the first electrode of the light-emitting device 20 through the anode reset transistor T7.

[0108] Figure 14 for Figure 1 Another schematic diagram of a mid-pixel circuit.

[0109] In one embodiment of this application, such as Figure 14 As shown, the input terminal of the threshold compensation module 13 is electrically connected to the second electrode of the driving transistor Td, and the output terminal is electrically connected to the gate of the driving transistor Td. The input terminal of the gate reset module 14 is electrically connected to the first reset voltage signal line XL1, and the output terminal is electrically connected to the second electrode of the driving transistor Td.

[0110] The threshold compensation module 13 includes a threshold compensation transistor T3, the first terminal of which is electrically connected to the second terminal of the driving transistor Td, and the second terminal of which is electrically connected to the gate of the driving transistor Td.

[0111] The gate reset module 14 includes a gate reset transistor T4. The first terminal of the gate reset transistor T4 is electrically connected to the first reset voltage signal line XL1, and the second terminal of the gate reset transistor T4 is electrically connected to the second terminal of the driving transistor Td.

[0112] The active layers of both the threshold compensation transistor T3 and the gate reset transistor T4 consist of metal oxide.

[0113] For example, the active layers of both the threshold compensation transistor T3 and the gate reset transistor T4 include indium gallium zinc oxide, and both the threshold compensation transistor T3 and the gate reset transistor T4 are N-type transistors.

[0114] Optional, such as Figure 14 As shown, the gate of the gate reset transistor T4 is electrically connected to the gate reset scan line S1N, and the gate of the threshold compensation transistor T3 is electrically connected to the threshold compensation scan line S2N.

[0115] Optional, such as Figure 15 As shown, Figure 15 for Figure 1 Another schematic diagram of the mid-pixel circuit shows that in the nth-level pixel circuit 10, the gate of the gate reset transistor T4 is electrically connected to the first scan line S1 of the np-th level, where p is a positive integer. The gate of the threshold compensation transistor T3 is electrically connected to the third scan line S3.

[0116] Combination Figure 16 As shown, Figure 16 for Figure 15 The pixel circuit shown is a timing diagram. In the reset phase t1, the first scan line S1 and the third scan line S3 of the np-th stage both transmit enable signals (such as high-level signals). The threshold compensation transistor T3 and the gate reset transistor T4 are turned on. The first reset voltage Vref1 is transmitted to the gate of the driving transistor Td through the threshold compensation transistor T3 and the gate reset transistor T4 to reset the gate of the driving transistor Td.

[0117] Simultaneously, the light-emitting control signal line EM transmits a non-enable signal (such as a high-level signal), controls the power supply voltage to write transistor T5 and light-emitting control transistor T6 to turn off, and controls the anode reset transistor T7 to turn on. The second reset voltage Vref2 is transmitted to the first electrode of the light-emitting device 20 through the anode reset transistor T7 to reset the first electrode of the light-emitting device 20.

[0118] During the data writing stage t2, both the first scan line S1 and the third scan line S3 of the nth stage transmit enable signals (such as high-level signals). The data writing transistor T1 and the threshold compensation transistor T3 are turned on, and the data voltage Vdata is transmitted to the gate of the driving transistor Td through the data writing transistor T1, the driving transistor Td, and the threshold compensation transistor T3.

[0119] During the bias adjustment phase t3, the first scan line S1 of the (n+m)th stage transmits an enable signal (such as a high-level signal), the bias adjustment transistor T2 is turned on, and the adjustment voltage DVH is transmitted to the driving transistor Td through the bias adjustment transistor T2 to adjust the bias state of the driving transistor Td.

[0120] Meanwhile, the third scan line S3 transmits a non-enable signal (such as a low-level signal), and the threshold compensation transistor T3 is turned off to prevent the adjustment voltage DVH from being transmitted to the gate of the driving transistor Td through the threshold compensation transistor T3, thus affecting the gate potential of the driving transistor Td.

[0121] During the light-emitting stage t4, the light-emitting control signal line EM transmits an enable signal (such as a low-level signal), the power supply voltage is written to transistor T5 and the light-emitting control transistor T6, and the driving transistor Td generates a light-emitting driving current and transmits it to the light-emitting device 20, driving the light-emitting device 20 to emit light.

[0122] It should be noted that when the bias adjustment transistor T2 is electrically connected to the first scan line S1 of the nm level, m ≠ p can be set so that the bias adjustment transistor T2 and the gate reset transistor T4 can be turned on at different times. This helps to avoid the gate reset process of the driving transistor Td and the bias adjustment process from interfering with each other.

[0123] Figure 17 for Figure 1 Another schematic diagram of a mid-pixel circuit.

[0124] In yet another embodiment of this application, as Figure 17 As shown, the input terminal of the bias adjustment module 12 is electrically connected to the adjustment voltage signal line DL2, and the output terminal is electrically connected to the second pole of the drive transistor Td.

[0125] The bias adjustment module 12 includes a bias adjustment transistor T2, the first terminal of which is electrically connected to the adjustment voltage signal line DL2, and the second terminal is electrically connected to the second terminal of the drive transistor Td.

[0126] In other words, in this embodiment, the bias adjustment transistor T2 can also transmit the adjustment voltage DVH to the second terminal of the driving transistor Td to adjust the bias state of the driving transistor Td. This increases the structural diversity of the pixel circuit and allows for flexible placement of the bias adjustment transistor T2 according to actual needs.

[0127] Figure 18 for Figure 1 Another schematic diagram of a mid-pixel circuit.

[0128] This application embodiment also provides a display panel 01, combined with...Figure 1 and Figure 18 As shown, the display panel 01 includes a pixel circuit 10 and a light-emitting device 20 that are electrically connected. The pixel circuit 10 includes a driving transistor Td, a data writing transistor T1, a bias adjustment transistor T2, a threshold compensation transistor T3, and a gate reset transistor T4. The driving transistor Td is used to generate a light-emitting driving current.

[0129] The first terminal of data writing transistor T1 is electrically connected to data signal line DL1, and the second terminal of data writing transistor T1 is electrically connected to the first terminal of driving transistor Td. Data signal line DL1 is used to transmit data voltage Vdata. The first terminal of bias adjustment transistor T2 is electrically connected to adjustment voltage signal line DL2, and the second terminal of bias adjustment transistor T2 is electrically connected to either the first or second terminal of driving transistor Td. Figure 18 This diagram only illustrates the electrical connection between the bias control transistor T2 and the second terminal of the drive transistor Td. The control voltage signal line DL2 is used to transmit the control voltage DVH.

[0130] The first terminal of the threshold compensation transistor T3 is electrically connected to the second terminal of the driving transistor Td, and the second terminal is electrically connected to the gate of the driving transistor Td. The first terminal of the gate reset transistor T4 is electrically connected to the first reset voltage signal line XL1, and the second terminal is electrically connected to the second terminal of the driving transistor Td. The gate reset transistor T4 is used to transmit the first reset voltage Vref1 on the first reset voltage signal line XL1 to the gate of the driving transistor Td.

[0131] In the nth pixel circuit 10, the gate of the bias adjustment transistor T2 is electrically connected to the nth second scan line S2, and the gate of the gate reset transistor T4 is electrically connected to the nmth second scan line S2, where m is a positive integer.

[0132] For example, such as Figure 18 As shown, in the nth-level pixel circuit 10, the gate of the data writing transistor T1 is electrically connected to the first scan line S1, and the gate of the threshold compensation transistor T3 is electrically connected to the third scan line S3.

[0133] In addition, the pixel circuit 10 also includes a power supply voltage writing transistor T5, a light emission control transistor T6, and an anode reset transistor T7. The first terminal of the power supply voltage writing transistor T5 is electrically connected to the first power supply voltage signal line DL3, and the second terminal is electrically connected to the first terminal of the driving transistor Td. The first power supply voltage signal line DL3 is used to transmit the power supply voltage PVDD.

[0134] The first terminal of the light-emitting control transistor T6 is electrically connected to the second terminal of the driving transistor Td, and the second terminal is electrically connected to the first terminal of the light-emitting device 20. The light-emitting device 20 can be an organic light-emitting diode, and the first terminal of the light-emitting device 20 can be its anode. The second terminal of the light-emitting device 20 receives the power supply voltage PVEE.

[0135] The first terminal of the anode reset transistor T7 is electrically connected to the second reset voltage signal line XL2, and the second terminal is electrically connected to the first terminal of the light-emitting device 20. The second reset voltage signal line XL2 is used to transmit the second reset voltage Vref2. The anode reset transistor T7 can transmit the second reset voltage Vref2 to the first terminal of the light-emitting device 20 to reset the first terminal of the light-emitting device 20.

[0136] In the nth-level pixel circuit 10, the gates of the power supply voltage writing transistor T5 and the light emission control transistor T6 are both electrically connected to the light emission control signal line EM, and the gate of the anode reset transistor T7 is electrically connected to the nth-level second scan line S2.

[0137] For example, in combination Figure 19 As shown, Figure 19 for Figure 18 The diagram shows a timing diagram of a pixel circuit. During the reset phase t1, the second scan line S2 and the third scan line S3 of the nm-th stage transmit enable signals (such as high-level signals). The threshold compensation transistor T3 and the gate reset transistor T4 are turned on. The first reset voltage Vref1 is transmitted to the gate of the driving transistor Td through the threshold compensation transistor T3 and the gate reset transistor T4 to reset the gate of the driving transistor Td.

[0138] During the data writing phase t2, the first scan line S1 transmits an enable signal (e.g., a low-level signal), the third scan line S3 transmits an enable signal (e.g., a high-level signal), the data writing transistor T1 and the threshold compensation transistor T3 are turned on, and the data voltage Vdata is transmitted to the gate of the driving transistor Td through the data writing transistor T1, the driving transistor Td and the threshold compensation transistor T3.

[0139] During the bias adjustment phase t3, the second scan line S2 of the nth stage transmits an enable signal (such as a high-level signal), and the third scan line S3 transmits a de-enable signal. The bias adjustment transistor T2 is turned on, the threshold compensation transistor T3 is turned off, and the adjustment voltage DVH is transmitted to the driving transistor Td through the bias adjustment transistor T2 to adjust the bias state of the driving transistor Td.

[0140] At the same time, the enable signal transmitted by the second scan line S2 of the nth stage controls the anode reset transistor T7 to turn on, and the second reset voltage Vref2 is transmitted to the first electrode of the light-emitting device 20 through the anode reset transistor T7 to reset the first electrode of the light-emitting device 20.

[0141] During the light-emitting stage t4, the light-emitting control signal line EM transmits an enable signal (such as a low-level signal), the power supply voltage is written to transistor T5 and the light-emitting control transistor T6, and the driving transistor Td generates a light-emitting driving current and transmits it to the light-emitting device 20, driving the light-emitting device 20 to emit light.

[0142] It should be noted that when a frame of the display panel 01 includes a data frame and a sustain frame, the data frame can be configured to include a reset phase t1, a data writing phase t2, a bias adjustment phase t3, and a light emission phase t4. The sustain frame includes the light emission phase t4 and the bias adjustment phase t3, but does not include the data writing phase t2 and the reset phase t1. By adjusting the bias state of the driving transistor Td in the sustain frame, the brightness difference between the sustain frame and the data frame can be improved, thereby improving the flickering problem of the display panel 01.

[0143] In this embodiment, the bias adjustment transistor T2 in the nth pixel circuit 10 is electrically connected to the nth second scan line S2, and the gate reset transistor T4 is electrically connected to the nmth second scan line S2. Then, the bias adjustment transistor T2 and the gate reset transistor T4 can share the same set of peripheral driving circuits, which helps to reduce the number of sets of peripheral driving circuits in the display panel 01, thereby helping to reduce the bezel width of the display panel 01 and achieve a narrow bezel of the display panel 01.

[0144] Figure 20 This is a schematic diagram of a display device provided in an embodiment of this application.

[0145] This application provides a display device 02, such as... Figure 20 As shown, the display device 02 includes the display panel 01 as provided in the above embodiments. Exemplarily, the display device 02 can be an electronic device such as a mobile phone, computer, vehicle display, television, or wearable display, and this application does not specifically limit it.

[0146] In the display device 02, the data writing module 11 and the bias adjustment module 12 in the same pixel circuit 10 can share the same set of peripheral driving circuits, or the setting adjustment transistor T2 and the gate reset transistor T4 can share the same set of peripheral driving circuits. This is beneficial to reduce the number of sets of peripheral driving circuits in the display panel 01, thereby reducing the bezel width of the display device 02 and achieving a narrow bezel in the display device 02.

[0147] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, characterized by, The pixel circuit comprises a light-emitting device and a pixel circuit electrically connected to the light-emitting device, and the pixel circuit comprises: a driving transistor for generating a light-emitting driving current; a data writing module, an input end of the data writing module being electrically connected to a data signal line and an output end of the data writing module being electrically connected to the driving transistor; a bias adjustment module, an input end of the bias adjustment module being electrically connected to an adjustment voltage signal line and an output end of the bias adjustment module being electrically connected to the driving transistor; wherein, in the nth stage of the pixel circuit, a control end of the data writing module is electrically connected to an nth stage of a first scan line, and a control end of the bias adjustment module is electrically connected to an nth+m stage or an nth-m stage of the first scan line, m being a positive integer.

2. The display panel of claim 1, wherein, The data writing module comprises a data writing transistor, a first pole of the data writing transistor being electrically connected to the data signal line, a second pole of the data writing transistor being electrically connected to a first pole of the driving transistor, and a gate of the data writing transistor being electrically connected to a control end of the data writing module. The bias adjustment module comprises a bias adjustment transistor, a first pole of the bias adjustment transistor being electrically connected to the adjustment voltage signal line, a second pole of the bias adjustment transistor being electrically connected to the first pole of the driving transistor, and a gate of the bias adjustment transistor being electrically connected to a control end of the bias adjustment module. The data writing transistor and the bias adjustment transistor both comprise metal oxide.

3. The display panel of claim 2, wherein, The pixel circuit further comprises:

4. The display panel of claim 1, wherein, a threshold compensation module, an input end of the threshold compensation module being electrically connected to a second pole of the driving transistor and an output end of the threshold compensation module being electrically connected to a gate of the driving transistor; a gate reset module, an input end of the gate reset module being electrically connected to a first reset voltage signal line and an output end of the gate reset module being electrically connected to the driving transistor, the gate reset module being configured to transmit a first reset voltage on the first reset voltage signal line to the gate of the driving transistor; The threshold compensation module and the gate reset module both comprise metal oxide transistors. The threshold compensation module comprises a threshold compensation transistor, a first pole of the threshold compensation transistor being electrically connected to the second pole of the driving transistor and a second pole of the threshold compensation transistor being electrically connected to the gate of the driving transistor.

5. The display panel of claim 4, wherein, The gate reset module comprises a gate reset transistor, a first pole of the gate reset transistor being electrically connected to the first reset voltage signal line and a second pole of the gate reset transistor being electrically connected to the gate of the driving transistor. The threshold compensation transistor and the gate reset transistor both comprise metal oxide. In the nth stage of the pixel circuit, a gate of the threshold compensation transistor is electrically connected to an nth stage of the first scan line, and a gate of the gate reset transistor is electrically connected to an nth-p stage of the first scan line, p being a positive integer.

6. The display panel of claim 5, wherein, The pixel circuit further comprises:

7. The display panel of claim 5, wherein, a power voltage writing transistor, a first pole of the power voltage writing transistor being electrically connected to a first power voltage signal line and a second pole of the power voltage writing transistor being electrically connected to the first pole of the driving transistor; a light-emitting control transistor, a first pole of the light-emitting control transistor being electrically connected to the second pole of the driving transistor and a second pole of the light-emitting control transistor being electrically connected to a first pole of the light-emitting device. ​ an anode reset transistor, a first electrode of the anode reset transistor being electrically connected with the second reset voltage signal line, a second electrode of the anode reset transistor being electrically connected with the first electrode of the light emitting device; wherein the channel type of the power voltage writing transistor is the same as the channel type of the light emitting control transistor.

8. The display panel of claim 7, wherein, the gate electrode of the power voltage writing transistor, the gate electrode of the light emitting control transistor and the gate electrode of the anode reset transistor are electrically connected with the light emitting control signal line; the channel type of the anode reset transistor is different from the channel type of the light emitting control transistor.

9. The display panel of claim 8, wherein, the anode reset transistor comprises metal oxide.

10. The display panel of claim 7, wherein, the gate electrode of the power voltage writing transistor and the gate electrode of the anode reset transistor are electrically connected with the second scan line, and the gate electrode of the light emitting control transistor is electrically connected with the light emitting control signal line.

11. The display panel of claim 7, wherein, the gate electrode of the light emitting control transistor and the gate electrode of the anode reset transistor are electrically connected with the second scan line, and the gate electrode of the power voltage writing transistor is electrically connected with the light emitting control signal line.

12. The display panel of claim 7, wherein, the gate electrode of the power voltage writing transistor and the gate electrode of the light emitting control transistor are electrically connected with the light emitting control signal line, and the gate electrode of the anode reset transistor is electrically connected with the second scan line.

13. The display panel of claim 4, wherein, the threshold value compensation module comprises a threshold value compensation transistor, a first electrode of the threshold value compensation transistor being electrically connected with a second electrode of the driving transistor, a second electrode of the threshold value compensation transistor being electrically connected with a gate electrode of the driving transistor; the gate reset module comprises a gate reset transistor, a first electrode of the gate reset transistor being electrically connected with the first reset voltage signal line, a second electrode of the gate reset transistor being electrically connected with the second electrode of the driving transistor; wherein the threshold value compensation transistor and the gate reset transistor both comprise metal oxide.

14. The display panel of claim 13, wherein, in the nth stage pixel circuit, the gate electrode of the gate reset transistor is electrically connected with the nth-p first scan line, and p is a positive integer; the gate electrode of the threshold value compensation transistor is electrically connected with the third scan line.

15. The display panel of claim 13, wherein, the bias adjustment module comprises a bias adjustment transistor, a first electrode of the bias adjustment transistor being electrically connected with the adjustment voltage signal line, a second electrode of the bias adjustment transistor being electrically connected with the second electrode of the driving transistor.

16. A display panel, characterized by a pixel circuit and a light emitting device electrically connected, the pixel circuit comprising: a driving transistor for generating a light emitting driving current; a data writing transistor, a first electrode of the data writing transistor being electrically connected with a data signal line, a second electrode of the data writing transistor being electrically connected with a first electrode of the driving transistor; a bias adjustment transistor, a first electrode of the bias adjustment transistor being electrically connected with an adjustment voltage signal line, a second electrode of the bias adjustment transistor being electrically connected with the first electrode or the second electrode of the driving transistor; a threshold value compensation transistor, a first electrode of the threshold value compensation transistor being electrically connected with a second electrode of the driving transistor, a second electrode of the threshold value compensation transistor being electrically connected with a gate electrode of the driving transistor; a gate reset transistor, a first electrode of the gate reset transistor being electrically connected with a first reset voltage signal line, a second electrode of the gate reset transistor being electrically connected with the second electrode of the driving transistor, the gate reset transistor being used for transmitting a first reset voltage on the first reset voltage signal line to the gate electrode of the driving transistor; In the nth stage pixel circuit, a gate of the bias adjusting transistor is electrically connected with the nth second scanning line, a gate of the gate reset transistor is electrically connected with the nth-m second scanning line, and m is a positive integer.

17. A display device comprising: A display panel comprising the display panel according to any one of claims 1-16.

Images