A multi-battery group cooperative equalization method and system based on a direct current bus

Abstract

The application discloses a kind of based on multi-group battery coordination equalization method and system of DC bus, method includes: real-time monitoring the terminal voltage of each battery group in multiple battery groups and DC bus voltage, and the dynamic deviation of each battery group voltage and bus voltage is calculated;Based on dynamic deviation generation cross-group energy scheduling demand, and according to real-time bus voltage fluctuation amplitude determines the priority sequence of each group energy transfer;According to priority sequence and bus voltage real-time value, using voltage following strategy, the direction and amplitude of equalization current are dynamically adjusted by bidirectional DC-DC converter, and adaptive equalization control signal is generated;Adaptive equalization control signal is executed, cross-group energy is transferred by DC bus to realize high-frequency pulse, and the coordination voltage equalization of multiple battery groups is completed.Utilize the embodiment of the application, can realize efficient, adaptive energy scheduling based on DC bus voltage state between multiple groups of batteries, improve system overall equalization speed and energy efficiency.

Description

Technical Field

[0001] This invention belongs to the field of battery technology, specifically a method and system for coordinated balancing of multiple battery groups based on a DC bus. Background Technology

[0002] In recent years, with the rapid development of large-scale energy storage systems and new energy electric vehicles, the application of multiple battery packs connected in series has become increasingly widespread. However, due to differences in battery characteristics and operating environments, voltage inconsistencies can easily occur between battery packs, leading to a decrease in system usable capacity, a shortened cycle life, and even safety hazards such as overcharging and over-discharging. Existing balancing methods mostly focus on energy adjustment between individual cells within a pack, lacking an efficient energy dispatch mechanism between packs; common passive balancing methods are energy-intensive and inefficient, while active balancing schemes are mostly limited to energy transfer between adjacent packs, resulting in slow cross-pack balancing speed and lag, making it difficult to adapt to the impact of bus voltage fluctuations under dynamic loads. Summary of the Invention

[0003] The purpose of this invention is to provide a method and system for coordinated balancing of multiple battery groups based on a DC bus, in order to overcome the shortcomings of the prior art. This method enables efficient and adaptive energy scheduling among multiple battery groups based on the DC bus voltage state, thereby improving the overall balancing speed and energy efficiency of the system.

[0004] One embodiment of this application provides a multi-cell collaborative equalization method based on a DC bus, the method comprising:

[0005] Real-time monitoring of the terminal voltage and DC bus voltage of each battery pack in multiple battery packs, and calculation of the dynamic deviation between the voltage of each battery pack and the bus voltage;

[0006] Based on the dynamic deviation, cross-group energy dispatch requirements are generated, and the priority sequence of energy transfer for each group is determined according to the real-time bus voltage fluctuation amplitude.

[0007] Based on the priority sequence and the real-time value of the bus voltage, a voltage following strategy is adopted, and the direction and amplitude of the equalization current are dynamically adjusted through a bidirectional DC-DC converter to generate an adaptive equalization control signal.

[0008] By executing the adaptive equalization control signal, high-frequency pulsed energy transfer across multiple battery packs is achieved through the DC bus, thus completing the coordinated voltage equalization of multiple battery packs.

[0009] Another embodiment of this application provides a multi-battery collaborative balancing system based on a DC bus, the system comprising:

[0010] The monitoring module is used to monitor the terminal voltage and DC bus voltage of each battery pack in multiple battery packs in real time, and to calculate the dynamic deviation between the voltage of each battery pack and the bus voltage.

[0011] The determination module is used to generate cross-group energy dispatch requirements based on the dynamic deviation, and determine the priority sequence of energy transfer for each group according to the real-time bus voltage fluctuation amplitude.

[0012] The adjustment module is used to dynamically adjust the direction and amplitude of the equalization current through a bidirectional DC-DC converter based on the priority sequence and the real-time value of the bus voltage, using a voltage following strategy, to generate an adaptive equalization control signal.

[0013] The equalization module is used to execute the adaptive equalization control signal and realize high-frequency pulsed energy transfer across multiple battery packs through the DC bus to achieve coordinated voltage equalization of multiple battery packs.

[0014] Another embodiment of this application provides a storage medium storing a computer program, wherein the computer program is configured to execute the method described in any of the preceding claims when running.

[0015] Another embodiment of this application provides an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the method described in any of the preceding claims.

[0016] Compared with the prior art, the present invention provides a multi-group battery collaborative balancing method based on DC bus, which can realize efficient and adaptive energy scheduling among multiple groups of batteries based on DC bus voltage state, thereby improving the overall balancing speed and energy efficiency of the system. Attached Figure Description

[0017] Figure 1 A hardware structure block diagram of a computer terminal for a multi-battery collaborative balancing method based on a DC bus, provided in an embodiment of the present invention;

[0018] Figure 2 A flowchart illustrating a multi-cell collaborative balancing method based on a DC bus provided in an embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of a multi-battery collaborative balancing system based on a DC bus, provided as an embodiment of the present invention. Detailed Implementation

[0020] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0021] Figure 1 This is a hardware structure block diagram of a computer terminal for a multi-battery collaborative balancing method based on a DC bus, provided as an embodiment of the present invention. Figure 1As shown, the computer device includes a processor, memory, and network interface connected via a system bus, wherein the memory may include non-volatile storage media and internal memory.

[0022] See Figure 2 The present invention provides a method for coordinated equalization of multiple battery groups based on a DC bus, which may include the following steps:

[0023] S201 monitors the terminal voltage and DC bus voltage of each battery pack in multiple battery packs in real time, and calculates the dynamic deviation between the voltage of each battery pack and the bus voltage.

[0024] Specifically, it can collect the terminal voltage data of each battery pack in multiple battery packs in real time, and at the same time collect the DC bus voltage data to generate the raw voltage sampling dataset.

[0025] Battery pack configuration: Multiple battery packs are set up, including 5 parallel battery packs (numbered C1-C5). Each pack consists of 16 lithium iron phosphate batteries with a nominal voltage of 3.2V connected in series. The rated voltage of a single pack is 51.2V. The DC bus is the common bus after all the packs are connected in parallel, with a rated voltage of 51.2V. The bus load is an energy storage inverter (rated power 10kW).

[0026] Sampling point layout: Battery pack terminal voltage sampling points: Each group has one voltage sampling terminal (using gold-plated terminals to reduce contact resistance) at the positive and negative output terminals. For example, the sampling terminals of group C1 are connected to the positive output terminal (near the positive terminal of the last battery in the group) and the negative output terminal (near the negative terminal of the first battery in the group) to ensure that the total terminal voltage of the group is collected.

[0027] DC bus voltage sampling point: set between the positive bus (near the parallel node) and the negative bus (common ground terminal) of the bus. The sampling terminal is fixed to the bus copper bus with bolts and an insulating sleeve is installed to prevent short circuit, ensuring that the real-time total voltage of the bus is collected.

[0028] Sampling chip selection: The high-precision analog-to-digital converter (ADC) chip ADS1256 is selected. This chip features 16-bit effective precision, 23-bit lossless resolution, and a maximum sampling rate of 10kHz. It is suitable for sampling battery voltage (single group 51.2V, voltage divider required for acquisition) and bus voltage. The core parameters are as follows:

[0029] Sampling accuracy: 16-bit effective accuracy (error ≤ ±0.0015%FSR, FSR is full scale, set to 60V here, corresponding to absolute error ≤ 0.0009V = 0.9mV).

[0030] Resolution: 23-bit lossless, capable of capturing minute changes in battery pack voltage;

[0031] Sampling rate: set to 1kHz (1000 samples per second), balancing real-time performance (meeting millisecond-level equalization control requirements) and data volume (6 signals in total, 5 groups + 1 bus at 1kHz sampling rate, generating 6000 data points per second, with controllable storage pressure).

[0032] Input method: Differential input (suppresses common-mode interference, such as common-mode noise generated by changes in bus current), and each pair of ADC channels acquires one voltage (e.g., channel 0-1 acquires the voltage of group C1, channel 2-3 acquires the voltage of group C2, and channel 8-9 acquires the bus voltage).

[0033] Data Acquisition Start-up and Initialization: After the system is powered on, the sampling controller initializes the ADS1256, configuring the sampling rate of 1kHz, input channels, and gain (set to 1x to avoid introducing additional errors), and calibrating the ADC's zero point and full scale (using a standard voltage source, inputting 0V and 5V to calibrate the zero point and full scale).

[0034] Synchronous data collection and execution:

[0035] Triggering method: Hardware triggering is adopted. The sampling controller generates a trigger signal every 1ms (corresponding to a 1kHz sampling rate) to synchronously start the 6-channel voltage acquisition of ADS1256 (C1-C5 groups + bus) to ensure that the acquisition time difference of each channel data is ≤1μs (negligible, meeting the synchronization requirements).

[0036] Data reading: After the ADC completes acquisition, it generates an interrupt signal, and the sampling controller reads the V_adc value of each channel through the SPI interface;

[0037] Actual voltage conversion: Based on a voltage division ratio of 1:12, calculate the actual voltage V_actual = V_adc × 12;

[0038] Abnormal data handling: If the V_adc value of a certain channel exceeds the 0-5V range (e.g., a line open circuit causing V_adc=0V, or a short circuit causing V_adc=5V), it is marked as "abnormal data". The previous valid data is temporarily used to replace it, and the abnormality identifier is recorded (e.g., if V_adc=0V in a certain acquisition of group C3, it is marked as abnormal, and the previous 4.26V is converted to 51.12V).

[0039] Data format definition: Each piece of raw data includes "timestamp, group number / bus identifier, V_adc value, actual voltage value, data status (normal / abnormal)", the timestamp is in milliseconds, the group number is identified by C1-C5, and the bus is identified by BUS.

[0040] The original voltage sampling dataset is filtered, and the Kalman filter algorithm is used to eliminate measurement noise and interference, generating a denoised and accurate voltage dataset.

[0041] Kalman filtering is a recursive filtering algorithm based on the state equations of a linear system. Through two steps—"state prediction" and "observation update"—it continuously corrects the state estimate by combining process noise and observation noise, ultimately approximating the true value. For the battery pack and bus voltage sampling scenario, a discrete-time linear system model is established:

[0042] State equation: Assuming that the battery pack / bus voltage changes approximately uniformly over a short period of time (1ms sampling period), the state variable x_k is the actual voltage value at time k, and the state equation is x_k=A×x_{k-1}+w_{k-1}, where: A is the state transition matrix, where A=1 (the voltage is stable in the short term and changes very little when there is no external charging / discharging); w_{k-1} is the process noise (such as the slow voltage change caused by battery self-discharge, which follows a Gaussian distribution with a mean of 0 and a variance of Q).

[0043] Observation equation: The observed variable z_k is the original sampled voltage value at time k (already converted to actual voltage). The observation equation is z_k = H × x_k + v_k, where: H is the observation matrix, here H = 1 (the observed value directly reflects the state variable); v_k is the observation noise (such as ADC quantization noise, electromagnetic interference, which follows a Gaussian distribution with mean 0 and variance R). Filtering iteration steps:

[0044] Prediction step: Calculate the prior state estimate at time k (hat{x}_k^-)=A×(hat{x}_{k-1}^+)+w_{k-1}, and the prior error covariance matrix P_k^-=A×P_{k-1}^+×A^T+Q;

[0045] Update step: Calculate the Kalman gain K_k = P_k^- × H^T × (H × P_k^- × H^T + R)^{-1}, the posterior state estimate (hat{x}_k^+) = (hat{x}_k^-) + K_k × (z_k - H × (hat{x}_k^-)), and the posterior error covariance matrix P_k^+ = (I - K_k × H) × P_k^- (I is the identity matrix).

[0046] Process noise variance Q: Process noise mainly comes from short-term fluctuations in battery voltage (such as voltage changes caused by small current charging and discharging of the energy storage system). According to the characteristics of lithium iron phosphate batteries, the voltage change within 1ms is usually ≤0.0001V. Therefore, Q is set as (0.0001V)²=1×10^{-8}V² (small variance, indicating that process noise has a very small impact on voltage).

[0047] Observation noise variance R: Observation noise comes from ADC sampling error and external interference. The sampling error of ADS1256 is ≤0.9mV. Combined with the interference amplitude of the actual test (about 0.5mV), the total observation error is ≤1.4mV. Therefore, R is set as (0.0014V)²≈2×10^{-6}V² (variance reflects the intensity of observation noise).

[0048] Initial value setting: The initial state estimate (hat{x}_0^+) at k=0 is taken as the first valid value of the original sampled data (such as the initial value of group C1 (hat{x}_0^+)=51.300V), and the initial error covariance matrix P_0^+ is set as (0.001V)²=1×10^{-6}V² (the uncertainty of the initial estimate).

[0049] Precise Voltage Dataset Format: The dataset includes "timestamp, group number / bus identifier, filtered voltage value, and filter error covariance (P_k^+)". Example data are: 20250922-143000-001,C1,51.3000V,6.72×10^{-7}; 20250922-143000-002,C1,51.3005V,5.09×10^{-7}; 20250922-143000-001,BUS,51.2160V,6.68×10^{-7}; Storage and Transmission: The precise dataset is stored synchronously with the original dataset, using the same CSV file format, and is simultaneously transmitted in real time to the equalization controller via the CAN bus to provide input for subsequent deviation calculations.

[0050] Based on the denoised accurate voltage dataset, the instantaneous difference between the terminal voltage of each battery pack and the DC bus voltage is calculated in real time to generate an initial voltage deviation dataset.

[0051] I. Calculation Logic and Physical Meaning of Instantaneous Difference

[0052] Calculation formula definition: Let the filtered voltage of a certain battery pack i at time k be V_ci(k), and the filtered voltage of the DC bus be V_bus(k), then the instantaneous voltage deviation of the pack ΔV_i(k) = V_ci(k) - V_bus(k), where:

[0053] ΔV_i(k)>0: This means that the voltage of battery pack i is higher than the bus voltage. This pack can release energy to the bus through discharge to balance the low voltage pack.

[0054] ΔV_i(k)=0: This indicates that the voltage of battery pack i is consistent with the bus voltage, and no energy transfer is required;

[0055] ΔV_i(k)<0: This means that the voltage of battery pack i is lower than the bus voltage, and the pack needs to absorb energy from the bus to raise the voltage.

[0056] Accuracy Guarantee: Due to the resolution of the precise voltage data of 7.15μV, the difference calculation adopts 32-bit floating-point arithmetic to ensure that the accuracy of the deviation value is ≤0.0001V (100μV), avoiding the accuracy loss caused by integer arithmetic.

[0057] II. Real-time Calculation Mechanisms and Processes

[0058] Calculation triggering conditions: Synchronized with the update frequency of accurate voltage data (1kHz), every time one frame of accurate voltage data (including C1-C5 groups and bus voltage) is received, an deviation calculation is immediately triggered to ensure the real-time performance of the calculation;

[0059] The computation execution module: The computation is performed by the floating-point unit (FPU) of the equalizer controller (using an STM32F407 microcontroller), and the process is as follows:

[0060] Data reading: Receive precise voltage data frames from the CAN bus and parse out V_c1, V_c2, V_c3, V_c4, V_c5, and V_bus;

[0061] Loop calculation: For each group, execute ΔV_i=V_ci-V_bus in sequence, such as ΔV_1=V_c1-V_bus, ΔV_2=V_c2-V_bus;

[0062] Data temporary storage: The calculated ΔV_1-ΔV_5 is temporarily stored in the controller's RAM buffer (size 1000 bytes, which can store the results of 100 calculations);

[0063] Anomaly Handling: If the precise voltage data of a certain group is marked as "invalid" (e.g., sensor failure), the deviation value of that group is marked as "NaN (non-numeric)" and will not participate in subsequent equalization scheduling. At the same time, the fault identifier is recorded (e.g., V_c3 of group C3 is invalid, ΔV_3=NaN, marked as "C3 deviation calculation invalid").

[0064] III. Example of Initial Voltage Deviation Calculation

[0065] Taking the precise voltage data at a certain moment (20250922-143000-005) as an example, the deviation calculation process is shown:

[0066] Precise voltage data: V_c1=51.3002V, V_c2=51.1440V, V_c3=51.1200V (invalid data), V_c4=51.2400V, V_c5=51.1800V; V_bus=51.2160V.

[0067] Deviation calculation results: ΔV_1=51.3002V-51.2160V=+0.0842V (C1 group voltage is higher than the bus, discharge is required); ΔV_2=51.1440V-51.2160V=-0.0720V (C2 group voltage is lower than the bus, charging is required); ΔV_3=NaN (C3 group data is invalid, marked as invalid); ΔV_4=51.2400V-51.2160V=+0.0240V (C4 group voltage is higher than the bus, a small amount of discharge is required); ΔV_5=51.1800V-51.2160V=-0.0360V (C5 group voltage is lower than the bus, a small amount of charging is required).

[0068] IV. Generation and Validation of Initial Voltage Deviation Dataset

[0069] Dataset format definition: Each deviation data entry includes "timestamp, group number, group voltage (V_ci), bus voltage (V_bus), instantaneous deviation (ΔV_i), and data status (valid / invalid)". The timestamp is consistent with the precise voltage data to ensure data traceability.

[0070] Storage and Application: The initial deviation dataset is stored as a CSV file at the specified path, and is simultaneously transmitted in real time to the dynamic deviation analysis module for calculating the rate of change and trend of deviation.

[0071] A time-series analysis is performed on the initial voltage deviation dataset to calculate the rate of change and trend of the deviation, generating a voltage dynamic deviation vector containing dynamic change characteristics.

[0072] I. Calculation Method and Physical Significance of Deviation Change Rate

[0073] Definition of the rate of change: The rate of change of deviation reflects the magnitude of the change in deviation per unit time. Let the instantaneous deviation at time k be ΔV_i(k), the instantaneous deviation at time k-1 be ΔV_i(k-1), and the sampling period be T (1ms=0.001s). Then, the rate of change of deviation of group i at time k is r_i(k)=[ΔV_i(k)-ΔV_i(k-1)] / T, with units of V / s. Where: r_i(k)>0: indicates that the deviation is increasing (e.g., ΔV_i increases from +0.08V to +0.09V, r_i=10V / s, indicating that the group voltage is higher than the bus voltage, and the discharge needs to be accelerated); r_i(k)=0: indicates that the deviation is stable (no change); r_i(k)<0: indicates that the deviation is decreasing (e.g., ΔV_i increases from -0.07V to -0.06V, r_i=10V / s, indicating that the group voltage is lower than the bus voltage, and the charging demand is reduced).

[0074] Calculation precision control: 32-bit floating-point calculation is used, and the time interval T is accurate to 1μs (obtained by the controller's timer counting) to ensure that the calculation accuracy of the rate of change is ≤0.1V / s.

[0075] II. Logic for Judging Deviation Trends

[0076] Trend judgment is based on the "sign consistency of the rate of change of N consecutive sampling points". N=5 (5ms, balancing response speed and anti-interference capability). The judgment rules are as follows:

[0077] Trend type definition: Increasing trend: The rate of change r_i(k), r_i(k-1), ..., r_i(k-4) of 5 consecutive sampling points are all ≥0, and r_i>0 of at least 3 points (excluding misjudgments caused by small fluctuations); Decreasing trend: The rate of change of 5 consecutive sampling points is ≤0, and r_i<0 of at least 3 points; Stable trend: The case that does not meet the increasing or decreasing trend (such as alternating positive and negative rates of change, or absolute value ≤0.1V / s).

[0078] Trend judgment example: The rate of change (unit V / s) of the 5 consecutive sampling points in group C1 is [8,9,7,8.5,9.2], all >0, and is judged as "increasing trend"; the rate of change of group C2 is [-6,-5.5,-7,-6.2,-5.8], all <0, and is judged as "decreasing trend"; the rate of change of group C4 is [1.2,-0.8,0.5,-0.3,0.2], alternating between positive and negative, and is judged as "stable trend".

[0079] III. Example of constructing and generating dynamic deviation vectors

[0080] Vector Composition: The voltage dynamic deviation vector is a five-dimensional feature vector containing "group number, current instantaneous deviation ΔV_i(k), current rate of change r_i(k), deviation trend, and the average deviation of the most recent N points (bar{ΔV}_i)", denoted as VEC_i(k)=[i,ΔV_i(k),r_i(k),Trend_i,(bar{ΔV}_i)], where: the average deviation of the most recent N points (bar{ΔV}_i)=[ΔV_i(k)+ΔV_i(k-1)+…+ΔV_i(k-N+1)] / N (N=10, the average within 10ms, reflecting the short-term deviation level); Trend_i is the trend indicator (increasing / decreasing / stable).

[0081] Example of generation: Taking the time series data of group C1 at time k=10 (20250922-143000-010) as an example: the instantaneous deviation (unit V) of the last 10 sampling points: 0.0842, 0.0850, 0.0855, 0.0862, 0.0870, 0.0875, 0.0882, 0.0890, 0.0895, 0.0900; the current instantaneous deviation ΔV_1(10)=0.0900V; the current rate of change r_1(10)= [0.0900-0.0895] / 0.001=50V / s; Trend judgment: The five consecutive rates of change [50,55,48,52,49] are all >0, which is judged as "increasing trend"; The average value of the last 10 points (bar{ΔV}_1)=(0.0842+0.0850+…+0.0900) / 10≈0.0872V; Dynamic deviation vector VEC_1(10)=[1,0.0900V,50V / s,increasing,0.0872V].

[0082] IV. Real-time performance assurance and dynamic deviation dataset generation in time series analysis

[0083] Real-time performance guarantee: Data caching: A sliding window is used to cache the initial deviation data of the 10 most recent sampling points (window size 10, the oldest data is removed for each new data received) to avoid frequent file reading; Parallel computing: Multi-threaded processing is used in the controller, with the main thread performing deviation calculation and the sub-thread performing time series analysis (rate of change and trend judgment) to ensure that the dynamic vector generation of all groups is completed within 1ms;

[0084] Dynamic deviation dataset format: The dataset contains "timestamp, dynamic deviation vector (group number, ΔV_i, r_i, Trend_i, (bar{ΔV}_i))", and the example data is: 20250922-143000-010,C1,0.0900V,50V / s,increasing,0.0872V; 20250922-143000-010,C2,-0.0700V,-45V / s,decreasing,-0.0715V; 20250922-143000-010,C4,0.0250V,2V / s,stable,0.0245V;

[0085] Storage and Application: The dynamic deviation dataset is stored in JSON format (for easy parsing by subsequent algorithms) at the path " / data / deviation / dynamic / 20250922 / 1430.json". It is also transmitted to the energy scheduling module in real time, providing dynamic feature basis for cross-group energy scheduling requirement generation and priority ranking.

[0086] S202, Generate cross-group energy dispatch requirements based on the dynamic deviation, and determine the priority sequence of energy transfer for each group according to the real-time bus voltage fluctuation amplitude;

[0087] Specifically, the magnitude and trend of the voltage dynamic deviation vector can be analyzed, and combined with the battery pack's capacity and SOC state, the required energy transfer amount and direction for each group can be calculated to generate a cross-group energy dispatch demand table.

[0088] I. Multidimensional Analysis of Voltage Dynamic Deviation Vector

[0089] Deviation amplitude analysis: Using the "current instantaneous deviation ΔV_i" and the "average of the last 10 points (bar{ΔV}_i)" in the dynamic deviation vector as the core, the severity of voltage deviation is assessed, and thresholds are set to classify deviation levels.

[0090] Severe deviation: |ΔV_i|≥0.1V (e.g., ΔV=+0.09V for group C1, which is close to severe deviation and requires a large amount of energy transfer).

[0091] Moderate deviation: 0.05V≤|ΔV_i|<0.1V (e.g., ΔV=-0.07V for group C2, which is considered a moderate deviation and requires moderate energy transfer).

[0092] Slight deviation: |ΔV_i| < 0.05V (e.g., ΔV = +0.025V for group C4, which is a slight deviation and requires a small amount of energy transfer).

[0093] Impact assessment of changing trends: The urgency of energy demand is determined by combining the "deviation trend" analysis. The correction factor for demand based on the trend is as follows:

[0094] Increasing trend: Correction coefficient 1.2 (the deviation continues to widen, requiring an increase of 12% in energy transfer to accelerate equilibrium).

[0095] Stable trend: Correction coefficient 1.0 (deviation stable, transferred according to the base quantity);

[0096] Decreasing trend: Correction coefficient 0.8 (the deviation is naturally alleviated, which can reduce the amount of energy transferred by 20%).

[0097] II. Acquisition and Characterization of Battery Pack Capacity and State of Charge (SOC)

[0098] Capacity parameters: The rated capacity of each battery pack is obtained from the factory parameters. Assuming that the rated capacity of all 5 packs is 100Ah (ampere-hour, which represents the battery's ability to store charge), the actual usable capacity decreases according to the number of cycles. The actual capacities of C1-C5 are set to 95Ah, 90Ah, 85Ah (faulty group, not included for now), 98Ah, and 92Ah, respectively.

[0099] SOC (State of Charge) calculation: The "ampere-hour integration method" combined with open-circuit voltage correction is used. SOC_i(t) = SOC_i(t0) - (1 / C_i) × ∫I_i(τ)dτ, where: SOC_i(t0) is the initial state of charge (assuming that the SOC of C1 at time t0 is 80%); I_i(τ) is the charging and discharging current of group i (discharging is positive and charging is negative); C_i is the actual capacity (e.g., C1 = 95Ah).

[0100] Example: If the discharge current of group C1 is 10A within 10 seconds, then the change in SOC is -(10A×10s) / (95Ah×3600s / h)≈-0.03%, and the current SOC = 80%-0.03%=79.97%. III. Calculation Model for Energy Transfer Amount and Direction: Determination of Transfer Direction: Based on the sign of ΔV_i: ΔV_i>0 (group voltage higher than bus): direction is "discharge" (energy flows from group to bus); ΔV_i<0 (group voltage lower than bus): direction is "charging" (energy flows from bus to group). Basic energy transfer calculation: The energy transfer amount E_i (unit: Wh) is positively correlated with the deviation amplitude and capacity. The formula is E_i=k×|(bar{ΔV}_i)|×C_i×SOC_i, where: k is the proportional coefficient, which is taken as 0.5 according to the system design (empirical value, balancing transfer speed and safety); |(bar{ΔV}_i)| is the absolute value of the average deviation (V); C_i is the actual capacity (Ah); and SOC_i is the current state of charge (decimal form).

[0101] Example: Group C1 ((bar{ΔV}_i)=0.0872V, C_i=95Ah, SOC_i=0.7997, increasing trend):

[0102] The basic E_i = 0.5 × 0.0872 × 95 × 0.7997 ≈ 0.5 × 0.0872 × 75.97 ≈ 0.5 × 6.63 ≈ 3.315 Wh;

[0103] After correction, E_i = 3.315 × 1.2 ≈ 3.98Wh (take 4.0Wh). Constraint verification: Discharge group: Ensure SOC_i ≥ 20% after transfer (avoid over-discharge). For example, after C1 discharges 4.0Wh, the SOC becomes 79.97% - (4.0Wh) / (51.2V × 95Ah) ≈ 79.97% - 0.08% ≈ 79.89% (constraint satisfied); Charging group: Ensure SOC_i ≤ 95% after transfer (avoid overcharging). For example, in group C2 (SOC = 60%, charging E = 3.0Wh), the SOC becomes 60% + (3.0Wh) / (51.2V × 90Ah) ≈ 60% + 0.07% ≈ 60.07% (constraint satisfied). IV. Generation of Cross-Group Energy Dispatch Demand Table The demand table includes eight fields: "Group Number, Deviation Level, Trend, Capacity, SOC, Transfer Direction, Energy Transfer Amount (Wh), and Constraint Status". Example data is as follows: C1: Severe Deviation (Approaching), Increasing Trend, 95Ah, 79.97%, Discharging, 4.0Wh, Constraints Met; C2: Moderate Deviation, Decreasing Trend, 90Ah, 60.00%, Charging, 3.0Wh, Constraints Met; C4: Slight Deviation, Stable Trend, 98Ah, 75.00%, Discharging, 1.2Wh, Constraints Met; C5: Moderate Deviation, Stable Trend, 92Ah, 65.00%, Charging, 1.8Wh, Constraints Met;

[0104] The demand table is updated in real time (update frequency 1kHz) and stored in “ / data / scheduling / demandtable_202509221430.csv”, providing a basis for energy demand analysis and optimization function construction for subsequent bus fluctuation analysis.

[0105] The fluctuation amplitude and frequency of DC bus voltage are monitored in real time, and the main frequency components of voltage fluctuation are analyzed by fast Fourier transform to generate a characteristic spectrum of bus voltage fluctuation.

[0106] I. Real-time monitoring parameters for bus voltage fluctuations

[0107] Fluctuation amplitude: Quantified using "peak-to-peak value" and "root mean square deviation". Peak-to-peak value V_pp = V_max - V_min (the difference between the highest and lowest voltages within a certain period), root mean square deviation V_rms = √[(1 / N)Σ(V_k - V_avg)²] (N is the number of sampling points, V_avg is the average voltage). Example: The bus voltage sampling values ​​within 10ms are 51.216V, 51.220V, 51.212V, ..., 51.218V, V_max = 51.220V, V_min = 51.212V, V_pp = 0.008V; V_avg = 51.216V, V_rms ≈ 0.003V.

[0108] Fluctuation frequency: refers to the rate at which voltage changes periodically with time. It is calculated by the time interval between adjacent peaks. For example, if the time difference between two consecutive peaks is 0.02s (20ms), then the frequency f = 1 / 0.02 = 50Hz.

[0109] II. Parameter Design and Implementation of Fast Fourier Transform (FFT)

[0110] FFT principle: Convert the voltage fluctuation signal in the time domain into frequency components in the frequency domain to reveal the proportion of fluctuation energy at different frequencies. The formula is X(k)=Σx(n)e^(-j2πkn / N) (n=0,1,…,N-1), where x(n) is the time domain sample value, X(k) is the complex amplitude at frequency k, and N is the number of sampling points.

[0111] Sampling parameter settings: Sampling frequency f_s = 10kHz (more than twice the highest possible fluctuation frequency, satisfying the Nyquist criterion, with a maximum analysis frequency within 5kHz); Number of sampling points N = 1024 (an integer power of 2, optimizing FFT calculation efficiency); Frequency resolution Δf = f_s / N = 10kHz / 1024 ≈ 9.766Hz (the smallest resolvable frequency interval). FFT calculation example: Performing FFT on 1024 bus voltage sampling points (time 0-102.3ms):

[0112] Time-domain data: x(n) = 51.216 + 0.002sin(2π×50n / f_s) + 0.001sin(2π×100n / f_s) (including 50Hz and 100Hz fluctuations);

[0113] Frequency domain transformation: The calculation shows that X(k) has obvious peaks at k=5 (f=5×9.766≈48.83Hz) and k=10 (f=10×9.766≈97.66Hz), corresponding to the fluctuation components at 50Hz and 100Hz.

[0114] III. Generation and Interpretation of Bus Voltage Fluctuation Characteristic Spectrum

[0115] Characteristic spectrum construction: The horizontal axis is plotted as frequency f (0-5kHz), and the vertical axis is plotted as the amplitude A (half of the voltage peak-to-peak value) of that frequency component. The frequencies and amplitudes of the main peaks are marked. Example characteristic spectrum data:

[0116] 50Hz: A=0.001V (possibly from grid frequency interference); 100Hz: A=0.0005V (second harmonic of 50Hz); 2kHz: A=0.0008V (inverter switching frequency interference).

[0117] Fluctuation level classification: Evaluate the fluctuation severity according to the total harmonic distortion rate THD = √(ΣA_k²) / V_avg×100%, where A_k is the amplitude of each harmonic and V_avg is the average bus voltage: THD ≤ 1%: slight fluctuation (e.g., THD ≈ 0.5% in the example, the system is stable); 1% < THD ≤ 5%: moderate fluctuation (large power energy transfer needs to be restricted); THD > 5%: severe fluctuation (suspend energy transfer and stabilize the bus first).

[0118] Characteristic spectrum storage: Store in CSV format, including "Frequency (Hz), Amplitude (V), Energy proportion (%)", providing a basis for stability constraints for subsequent multi-objective optimization.

[0119] Based on the bus voltage fluctuation characteristic spectrum and the cross-group energy scheduling requirement table, comprehensively consider the balancing speed, system stability and efficiency, and construct a multi-objective optimization function;

[0120] I. Balancing speed objective function (f1)

[0121] The balancing speed objective is to "minimize the total balancing time". The time is positively correlated with the energy transfer amount and negatively correlated with the allowed transfer power. The function is defined as f1 = Σ(E_i / P_i), where: E_i is the energy transfer amount (Wh) of group i; P_i is the maximum allowed transfer power (W) of group i, which is positively correlated with the deviation level (severe deviation P_i = 50W, moderate 30W, slight 10W).

[0122] Example: C1 (4.0Wh, 50W), C2 (3.0Wh, 30W), C4 (1.2Wh, 10W), C5 (1.8Wh, 30W), f1 = 4.0 / 50 + 3.0 / 30 + 1.2 / 10 + 1.8 / 30 = 0.36 hours (21.6 minutes), and the goal is to minimize f1.

[0123] II. System stability objective function (f2)

[0124] The system stability objective is to "minimize the risk of increased bus voltage fluctuation", which is related to the main frequency components and energy transfer power in the fluctuation characteristic spectrum. The function is defined as f2 = Σ(P_i×S(f_i)), where:

[0125] S(f_i) is the sensitivity coefficient at frequency f_i, which is positively correlated with the amplitude of this frequency (the larger the amplitude, the larger S(f_i), e.g., 50Hz amplitude 0.001V corresponds to S = 1.5, 2kHz amplitude 0.0008V corresponds to S = 2.0);

[0126] P_i is the transfer power of group i, and the greater the power, the greater the disturbance to the bus.

[0127] Example: C1 (50W, discharge frequency close to 50Hz), C2 (30W, charging frequency close to 2kHz), f2=50×1.5+30×2.0=75+60=135, the goal is to minimize f2.

[0128] III. Energy efficiency objective function (f3)

[0129] The energy efficiency objective is to "maximize energy transfer efficiency". Efficiency is related to the operating point of the DC-DC converter and is defined by the function f3=1-Σ(E_i×(1-η_i)), where: η_i is the transfer efficiency of group i, which is positively correlated with the power P_i (η=95% when P_i=50W, η=92% when 30W, and η=85% when 10W); (1-η_i) is the energy loss rate.

[0130] Example: C1 (4.0Wh, η=95%), C2 (3.0Wh, η=92%), f3=1-[4.0×(1-0.95)+3.0×(1-0.92)+1.2×(1-0.85)+1.8×(1-0.92)]= 0.236, the goal is to maximize f3 (i.e. minimize 1-f3).

[0131] IV. Combination and Constraints of Multi-Objective Optimization Functions

[0132] Weighted combination function: The three objectives are combined into a single objective F=w1×f1+w2×f2+w3×(1-f3) using a linear weighting method, where the weights are w1=0.4 (prioritizing speed), w2=0.3 (secondary priority for stability), and w3=0.3 (considering efficiency). For example, F=0.4×0.36+0.3×135+0.3×(1-0.236)≈40.87, and the objective is to minimize F.

[0133] Constraints:

[0134] Power constraint: ΣP_i≤P_max (maximum power that the bus can withstand, set to 100W, in the example 50+30+10+30=120W>100W, needs to be adjusted); Frequency constraint: avoid large power transfer at the main fluctuation frequency (such as 50Hz, 2kHz), the frequency needs to be staggered or the power reduced.

[0135] Solve the multi-objective optimization function to determine the urgency and benefit assessment of energy transfer for each battery pack, and generate a priority sequence for energy transfer for each pack according to priority.

[0136] I. Selection and Solution Process of Multi-Objective Optimization Algorithm

[0137] The "Non-dominated sorting genetic algorithm (NSGA-II)" is selected to solve the problem. This algorithm finds the Pareto optimal solution in the objective space through fast non-dominated sorting and crowding distance calculation (it cannot simultaneously improve the solution for all objectives). The specific steps are as follows:

[0138] Initialize the population: randomly generate 50 feasible solutions (each solution is a power allocation scheme for each group, satisfying the power constraint ΣP_i≤100W);

[0139] Non-dominated sorting: For each solution, calculate the F value and sort them according to the "dominance relationship" (solution A is better than solution B if the F value of A is smaller) to obtain different levels of non-dominated layers;

[0140] Selection and crossover: High-quality solutions are selected using a tournament selection method, and then crossover and mutation are performed (crossover probability 0.8, mutation probability 0.1) to generate a new population;

[0141] Iterative convergence: After 50 iterations, the solution with the highest congestion is selected as the optimal solution. Example optimal power allocation: C1=40W, C2=30W, C4=10W, C5=20W (total power 100W).

[0142] II. Urgency Level and Benefit Evaluation Indicators

[0143] Urgency score (U_i): Combining deviation level, trend, and SOC status, with a maximum score of 10 points: Deviation level: severe 5 points, moderate 3 points, slight 1 point; Trend: increasing 3 points, stable 2 points, decreasing 1 point; SOC: discharge group SOC>80% add 2 points (avoid overcharge risk), charging group SOC<30% add 2 points (avoid over-discharge risk).

[0144] Example: C1 (Severe 5 + Increased 3 + SOC>80% + 2 = 10 points), C2 (Moderate 3 + Decreased 1 + Normal SOC 0 = 4 points), C4 (Mild 1 + Stable 2 + Normal SOC 0 = 3 points), C5 (Moderate 3 + Stable 2 + Normal SOC 0 = 5 points).

[0145] Benefit assessment (B_i): The improvement in F value per unit of energy transfer, B_i=ΔF / E_i, where ΔF is the change in F value after energy transfer for this group. For example, B_i=5.2 / 4.0=1.3 for C1 (the F value decreases by 1.3 per Wh of energy transfer), and B_i=1.8 / 1.8=1.0 for C5.

[0146] III. Priority Sorting Rules and Sequence Generation

[0147] Sorting criteria: Prioritize descending order of urgency U_i; if U_i are the same, then descending order of benefit B_i.

[0148] Sequence adjustment: If the total power of high priority groups exceeds the bus limit, reduce the power of low efficiency groups proportionally to ensure that the total power is ≤100W;

[0149] Final priority sequence: Level 1: C1 (U=10, B=1.3, power 40W); Level 2: C5 (U=5, B=1.0, power 20W); Level 3: C2 (U=4, B=0.8, power 30W); Level 4: C4 (U=3, B=0.5, power 10W).

[0150] The sequence is updated in real time (update frequency 100Hz) and stored in JSON format to guide the generation of subsequent equalization control signals.

[0151] S203, based on the priority sequence and the real-time value of the bus voltage, adopts a voltage following strategy and dynamically adjusts the direction and amplitude of the equalization current through a bidirectional DC-DC converter to generate an adaptive equalization control signal;

[0152] Specifically, it can parse the priority sequence of each energy transfer group, determine the battery pack that needs to perform energy transfer and its transfer direction, and generate the current scheduling instruction set;

[0153] I. Priority Sequence Parsing Logic and Data Extraction

[0154] Review of input priority sequence format: The priority sequence generated above is in JSON format, containing "group number, priority level (level 1-4, level 1 is the highest), rated transfer power (W), urgency score (1-10 points), transfer direction identifier (DISCHARGE / CHARGE)".

[0155] Key data extraction: During parsing, four core fields need to be extracted: "cluster_id", "level", "power", and "direction". Redundant information (such as urgency rating, which is already reflected in the priority) should be ignored, and the data validity should be verified.

[0156] Group number verification: The group must be in the list of valid groups (C1-C5), and faulty groups (such as C3, marked as "FAULT") must be excluded.

[0157] Power verification: The rated power must be within the rated power range of the DC-DC converter (assuming the converter's rated power is 50W, 40W, 20W, 30W, and 10W are all valid).

[0158] Direction verification: Only "DISCHARGE" (discharge, group → bus) or "CHARGE" (charge, bus → group) are allowed to avoid invalid direction markings.

[0159] II. Selection Rules and Direction Determination for the Current Execution Group

[0160] Execution group selection: Based on a dual selection process of "priority level + total power constraint", the total power of the execution group is ensured to not exceed the maximum power that the DC bus can withstand (set to 100W to avoid bus overload).

[0161] Total power of priority groups 1-3: 40W (C1) + 20W (C5) + 30W (C2) = 90W ≤ 100W, all of which are included in the current execution;

[0162] Priority Level 4 Group (C4, 10W): If the total power included is 100W, it just reaches the upper limit, but considering the bus fluctuation redundancy, it is temporarily listed as the "standby group" (if the power of the subsequent execution group decreases, it will be started again).

[0163] Fault group (C3): Directly eliminate, no instruction generated.

[0164] The physical meaning and determination of the transfer direction:

[0165] “DISCHARGE”: When the group voltage is higher than the bus voltage (e.g., C1 voltage 51.300V > bus voltage 51.216V), energy is injected into the bus after being stepped down from the group by the DC-DC converter. The current direction is “group → DC-DC → bus”.

[0166] “CHARGE”: When the group voltage is lower than the bus voltage (e.g., C5 voltage 51.180V < bus 51.216V), energy flows from the bus to the group after being boosted by the DC-DC converter. The current direction is “bus → DC-DC → group”.

[0167] III. Generation and Format of the Current Scheduling Instruction Set

[0168] The scheduling instruction set adopts a "structured instruction" format. Each instruction corresponds to an execution group and contains seven fields: "Instruction ID, Group Number, Transfer Direction, Rated Power, Priority, Execution Status, and Generation Timestamp". The meanings and examples of the fields are as follows:

[0169] Command ID: A unique identifier, in the format "CMD-YYYYMMDD-HHMMSS-XXX", such as "CMD-20250922-143000-001";

[0170] Group Number: The unique number of the execution group, such as "C1"; Transfer Direction: "DISCHARGE" or "CHARGE", such as "DISCHARGE"; Rated Power: The target transfer power (W) of the current instruction, such as "40W"; Priority: The original priority level, such as "Level 1"; Execution Status: "PENDING", "RUNNING", "PAUSED", initially "PENDING";

[0171] Generate timestamp: The precise time generated by the instruction, such as "20250922-143000-001" (milliseconds).

[0172] Example of the current scheduling instruction set:

[0173] Instruction ID: CMD-20250922-143000-001; Group Number: C1; Transfer Direction: DISCHARGE; Rated Power: 40W; Priority: Level 1; Execution Status: PENDING; Generation Timestamp: 20250922-143000-001;

[0174] Command ID: CMD-20250922-143000-002; Group Number: C5; Transfer Direction: CHARGE; Rated Power: 20W; Priority: Level 2; Execution Status: PENDING; Generation Timestamp: 20250922-143000-001;

[0175] Command ID: CMD-20250922-143000-003; Group number: C2; Transfer direction: CHARGE; Rated power: 30W; Priority: Level 3; Execution status: PENDING; Generation timestamp: 20250922-143000-001.

[0176] The instruction set is stored in the controller's RAM cache and simultaneously synchronized to the local controller of each DC-DC converter via the CAN bus, providing an execution target for subsequent equalization parameter calculations.

[0177] The DC bus voltage value is collected in real time, and combined with the current dispatch instruction set, the required equalization current amplitude and direction are calculated to generate preliminary equalization parameters;

[0178] I. Real-time Acquisition and Preprocessing of DC Bus Voltage

[0179] Hardware and parameters for data acquisition: The ADS1256ADC chip is used to acquire the bus voltage. The sampling frequency is increased to 10kHz (higher than the equalization control frequency to ensure real-time data). The sampling accuracy is ±0.9mV. The acquisition point is located between the common terminals of the positive and negative terminals of the bus to avoid errors caused by line voltage drop.

[0180] Real-time acquisition and filtering: One raw voltage value is acquired every 100μs (10kHz sampling rate). A "moving average filter" (window size 10 points) is used to eliminate high-frequency ripple, resulting in a smooth real-time bus voltage value V_bus_real. Example acquisition sequence (raw values, unit V): 51.216, 51.218, 51.215, 51.217, 51.216, 51.219, 51.215, 51.217, 51.216, 51.218. After moving average, V_bus_real = (51.216 + 51.218 + ... + 51.218) / 10 ≈ 51.2167V, retaining 4 decimal places to ensure calculation accuracy.

[0181] Voltage fluctuation judgment: Set the rated value of bus voltage V_bus_rated=51.2V, and allow fluctuation range of ±0.1V (51.1V~51.3V). If V_bus_real exceeds the range (such as 51.0V or 51.4V), trigger the "voltage abnormality" flag. The fluctuation compensation coefficient needs to be added to the subsequent current calculation (to avoid overcurrent or insufficient power).

[0182] II. Calculation Model and Compensation Mechanism for Equalization Current Amplitude

[0183] Basic current calculation: Based on the power formula P=U×I (ignoring the minor losses of the DC-DC converter and assuming 100% efficiency for now), the equalization current amplitude I_eq=P_cmd / V_bus_real is derived, where:

[0184] P_cmd is the rated power (W) in the dispatch instruction set, such as P_cmd=40W for C1; V_bus_real is the real-time bus voltage (V), such as 51.2167V; I_eq is the equalization current amplitude (A), with 3 decimal places, reflecting the current magnitude.

[0185] Example calculation (C1 group, discharge direction): I_eq_C1=40W / 51.2167V≈0.781A;

[0186] Example calculation (C5 group, charging direction): I_eq_C5=20W / 51.2167V≈0.390A;

[0187] Example calculation (C2 group, charging direction): I_eq_C2=30W / 51.2167V≈0.586A.

[0188] Voltage fluctuation compensation: If V_bus_real deviates from the rated value, a compensation coefficient k_comp is introduced to adjust the current, ensuring that the actual transferred power is close to P_cmd.

[0189] Compensation coefficient formula: k_comp=V_bus_rated / V_bus_real (when V_bus_real<V_bus_rated, k_comp>1, increase current; when V_bus_real>V_bus_rated, k_comp<1, decrease current); Compensated current: I_eq_comp=I_eq×k_comp.

[0190] Example (V_bus_real=51.1V, lower than the rated value, C1 group): k_comp=51.2V / 51.1V≈1.002; I_eq_comp_C1=0.781A×1.002≈0.782A (slightly increase the current to ensure 40W power).

[0191] Current upper limit constraint: Set the rated current of the bidirectional DC-DC converter I_dcdc_rated=2A (to avoid damage to the device due to overcurrent). If I_eq_comp>I_dcdc_rated (e.g., when P_cmd=100W, I_eq=1.95A, after compensation 2.05A), then force I_eq_comp=I_dcdc_rated, and at the same time reduce P_cmd (P_cmd=I_dcdc_rated×V_bus_real) to ensure safety.

[0192] III. Identification and Physical Significance of the Direction of Equilibrium Current

[0193] Direction identification rules: The current direction is defined in conjunction with the transfer direction, and is distinguished by either a "positive or negative sign" or a "text label". Here, a "positive or negative sign" is used (for ease of subsequent numerical calculations for PID control):

[0194] Discharge direction (DISCHARGE, group → bus): The current direction is "positive" (I_eq_comp > 0), indicating that the current flows out of the group;

[0195] Charging direction (CHARGE, bus → group): The current direction is "negative" (I_eq_comp < 0), indicating that the current flows into the group.

[0196] Example (Group C1, discharging): I_eq_dir_C1=+0.781A; Example (Group C5, charging): I_eq_dir_C5=-0.390A; Example (Group C2, charging): I_eq_dir_C2=-0.586A.

[0197] Relationship between current direction and DC-DC topology: The direction of current directly determines the operating mode of the DC-DC converter.

[0198] Positive current (discharge): The converter operates in "Buck mode" (the group voltage is higher than the bus voltage, and the power is supplied to the bus after stepping down).

[0199] Negative current (charging): The converter operates in "Boost mode" (the bus voltage is higher than the group voltage, and the converter charges the group after boosting).

[0200] IV. Generation and Verification of Preliminary Equilibrium Parameters

[0201] Parameter format definition: The preliminary balancing parameters are a set of parameters corresponding to each execution group instruction, containing nine fields: "Parameter ID, Group Number, Real-time Bus Voltage, Rated Power, Compensation Coefficient, Balancing Current Amplitude, Balancing Current Direction, Calculation Timestamp, and Voltage Status". An example is shown below:

[0202] Parameter ID: PARAM-20250922-143000-001; Group No.: C1; Real-time Bus Voltage: 51.2167V; Rated Power: 40W; Compensation Coefficient: 1.000 (Voltage is normal, no compensation required); Equalizing Current Amplitude: 0.781A; Equalizing Current Direction: +0.781A; Calculation Timestamp: 20250922-143000-001; Voltage Status: Normal (51.1V~51.3V).

[0203] Parameter verification: Verify the correctness of the parameters through "power inverse calculation", i.e., P_calc = V_bus_real × |I_eq_dir|. If |P_calc - P_cmd| ≤ 0.5W (allowable error), then the parameters are valid.

[0204] Example (Group C1): P_calc = 51.2167V × 0.781A ≈ 40.0W, with 0 error compared to P_cmd = 40W, therefore valid;

[0205] Example (C5 group): P_calc=51.2167V×0.390A≈20.0W, with an error of 0 compared to P_cmd=20W, so it is valid.

[0206] Parameter storage and transmission: The initial equalization parameters are stored in CSV format and transmitted in real time to the PID controller module via the SPI interface as the target value for current control.

[0207] A voltage follower control strategy is adopted, and the duty cycle and phase of the bidirectional DC-DC converter are dynamically adjusted by the PID controller to generate a PWM control signal;

[0208] I. Principles and Objectives of Voltage Follower Control Strategy

[0209] The core idea of ​​the strategy is voltage following, which means that the "output voltage" of the bidirectional DC-DC converter always tracks the "input voltage" (during discharge, the DC-DC output voltage = bus voltage, and the input voltage = group voltage; during charging, the DC-DC output voltage = group voltage, and the input voltage = bus voltage). By maintaining the stability of the input-output voltage, the smoothness of the balanced current is ensured, and current spikes caused by voltage fluctuations are avoided.

[0210] Control objective: With the "current direction and amplitude in the preliminary equalization parameters" as the target, the "actual equalization current I_eq_actual" is adjusted by adjusting the duty cycle to make the "target equalization current I_eq_target (i.e., I_eq_dir in the preliminary parameters)" infinitely close to the "target equalization current I_eq_target". The control error is ≤ ±50mA (e.g., if the target is 0.781A, an actual value of 0.731A to 0.831A is acceptable).

[0211] II. Parameter Design and Deviation Calculation of PID Controller

[0212] Inputs and outputs of a PID controller:

[0213] Input: Current deviation e(t) = I_eq_target - I_eq_actual, which is the difference between the target current and the actual sampled current (in A).

[0214] Output: Duty cycle adjustment ΔD (unitless, range -0.1 to +0.1, to avoid the duty cycle exceeding the safe range of 0.1 to 0.9), used to correct the reference duty cycle of the DC-DC converter.

[0215] Selection and meaning of PID parameters:

[0216] The proportional coefficient Kp amplifies the current deviation and speeds up the response. The value is 2.0 (an empirical value that needs to be optimized based on system debugging). Its function is that "the larger the deviation, the more significant the duty cycle adjustment."

[0217] Integral coefficient Ki: eliminates static deviation (small deviations that have existed for a long time), with a value of 0.5. Its function is to "the longer the accumulated deviation time, the larger the adjustment amount, so as to avoid the current from always failing to reach the target."

[0218] Differential coefficient Kd: suppresses overshoot (avoids the current from rapidly approaching the target and then exceeding it), with a value of 0.1. Its function is to "the faster the deviation changes, the larger the adjustment amount in the opposite direction, thus slowing down the rate of change".

[0219] Real-time calculation of current deviation: The actual current I_eq_actual is acquired by connecting a shunt resistor (e.g., 0.1Ω, accuracy ±1%) in series at the output of the DC-DC converter. An ADC chip (ADS1256) is used to convert the resistor voltage into a current value. Example: Target current I_eq_target_C1 = +0.781A; Actual current sampling: Shunt resistor voltage V_R = 0.078V (current flows into one end of the resistor during discharge, voltage is positive); Actual current I_eq_actual_C1 = V_R / R_shunt = 0.078V / 0.1Ω = 0.780A; Current deviation e(t) = 0.781A - 0.780A = +0.001A (positive deviation, actual current is slightly lower than the target, duty cycle needs to be increased).

[0220] III. PID Output Calculation and Duty Cycle Adjustment

[0221] Discretization calculation of PID output: Since the system is digitally controlled (controller sampling period T=1ms), the output ΔD(k) is calculated using the discretized PID formula (k is the current sampling period): ΔD(k)=Kp×e(k)+Ki×T×Σe(i) (i=0 to k)+Kd×[e(k)-e(k-1)] / T.

[0222] Where: Σe(i) is the cumulative sum of deviations from the initial time to the current time (unit A·s); e(k)-e(k-1) is the difference between the current deviation and the deviation of the previous period (unit A); T is the sampling period (0.001s).

[0223] Example calculation (Group C1, time k):

[0224] e(k) = +0.001A (current deviation); Σe(i) = 0.005A·s (cumulative deviation of the previous 5 cycles: 0.001 + 0.001 + 0.001 + 0.001); e(k) - e(k-1) = 0.001A - 0.002A = -0.001A (previous cycle deviation was 0.002A, current deviation decreases);

[0225] ΔD(k) = 2.0 × 0.001 + 0.5 × 0.001 × 0.005 + 0.1 × (-0.001) / 0.001 ≈ -0.0979975 (Note that if ΔD exceeds the range of -0.1 to +0.1, it is forcibly truncated to -0.1).

[0226] The actual ΔD(k) = -0.1 (the upper limit is taken because the calculated result is close to -0.1).

[0227] Determining the baseline duty cycle: Calculate the baseline duty cycle D_base based on the DC-DC operating mode (Buck / Boost):

[0228] Discharge (Buck mode): D_base=V_out / V_in=V_bus_real / V_cluster (V_in is the group voltage, V_out is the bus voltage);

[0229] Example (Group C1, V_cluster_C1=51.300V, V_bus_real=51.2167V): D_base_C1=51.2167V / 51.300V≈0.9984;

[0230] Charging (Boost mode): D_base=1-V_in / V_out=1-V_bus_real / V_cluster (V_in is the bus voltage, V_out is the cluster voltage);

[0231] Example (C5 group, V_cluster_C5=51.180V, V_bus_real=51.2167V):

[0232] D_base_C5=1-51.2167V / 51.180V≈1-1.0007≈-0.0007 (The duty cycle in Boost mode is positive. Here, because the bus voltage is close to the group voltage, D_base is set to 0.05, which will be adjusted later by PID).

[0233] Final duty cycle calculation: D_final(k) = D_base + ΔD(k). It is necessary to ensure that D_final is within the range of 0.1 to 0.9 (to avoid an excessively low duty cycle leading to too low an output voltage, or an excessively high duty cycle leading to severe overheating of the switching transistor).

[0234] Example (Group C1, Buck mode): D_final_C1=0.9984+(-0.1)=0.8984 (valid in the range of 0.1~0.9);

[0235] Example (C5 group, Boost mode): D_final_C5=0.05+0.02 (assuming ΔD=+0.02)=0.07 (valid).

[0236] IV. Phase Adjustment and PWM Control Signal Generation

[0237] Purpose and method of phase adjustment: When multiple groups perform energy transfer simultaneously, if the PWM signals have the same phase, the switching actions will be synchronized, which will lead to the superposition of bus current ripple (increased ripple, affecting stability). Therefore, it is necessary to stagger the phases of each group of PWM signals.

[0238] Phase allocation rules: Phases are allocated according to priority level. Priority level 1 (C1) has a phase of 0°, level 2 (C5) has a phase of 120°, and level 3 (C2) has a phase of 240° (the three-phase phase difference is 120°, which provides the best ripple cancellation effect).

[0239] Phase adjustment method: It is achieved by delaying the trigger time of the PWM signal. For example, the PWM signal of C5 is delayed by (120° / 360°) × T_pwm compared with C1. T_pwm is the PWM period (T_pwm=50μs at 20kHz). The delay time is (1 / 3) × 50μs≈16.67μs.

[0240] PWM control signal parameters and format: The PWM signal is a high-frequency square wave. The core parameters include "signal ID, group number, operating mode, PWM frequency, final duty cycle, phase, and output status", as shown in the example below:

[0241] Signal ID: PWM-20250922-143000-001; Group Number: C1; Operating Mode: Buck (Discharge); PWM Frequency: 20kHz (period 50μs, high frequency reduces current ripple); Final Duty Cycle: 0.8984 (high level time = 50μs × 0.8984 ≈ 44.92μs); Phase: 0° (no delay); Output Status: Enabled.

[0242] Hardware generation of PWM signal: The controller generates PWM signal through a timer (such as TIM1 of STM32). The timer prescaler is set to 8 (system clock 72MHz, 72MHz / 8=9MHz), and the auto-reload value is set to 449 (9MHz / 450=20kHz). The comparison value = auto-reload value × D_final = 449 × 0.8984 ≈ 403. In the timer output comparison mode, when the count reaches 403, the PWM signal changes from high level to low level, generating a square wave with the required duty cycle.

[0243] The PWM control signal is fused with the initial equalization parameters to generate an adaptive equalization control signal that includes at least the parameters of current amplitude, direction, and duration.

[0244] I. Fusion Logic and Field Mapping of Multi-Source Parameters

[0245] Integration principle: Using "group number" as the unique association key, the fields of PWM control signal and preliminary equalization parameter are integrated according to "execution requirement priority". The priority from high to low is: execution target (current direction, amplitude) → control parameters (PWM frequency, duty cycle, phase) → status information (bus voltage, compensation coefficient) to ensure that the core execution parameters are not missing.

[0246] Field mapping relationships: Preliminary equalization parameter "Group Number" → Fusion signal "Group Number"; Preliminary equalization parameter "Equalization Current Direction" → Fusion signal "Current Direction"; Preliminary equalization parameter "Equalization Current Amplitude" → Fusion signal "Target Current Amplitude"; Preliminary equalization parameter "Real-time Bus Voltage" → Fusion signal "Bus Voltage Reference"; PWM control signal "Operating Mode" → Fusion signal "DC-DC Operating Mode"; PWM control signal "PWM Frequency" → Fusion signal "PWM Frequency"; PWM control signal "Final Duty Cycle" → Fusion signal "PWM Duty Cycle"; PWM control signal "Phase" → Fusion signal "PWM Phase"; Added "Energy Transfer Duration" → Fusion signal "Duration".

[0247] II. Calculation Model for Energy Transfer Duration

[0248] The duration reflects "how long the current balancing operation needs to be performed," and is calculated based on "energy transfer amount" and "rated power," using the formula t_duration = E_cmd / P_cmd, where:

[0249] E_cmd is the amount of energy transferred (Wh) in the cross-group energy dispatch demand, such as E_cmd=4.0Wh for group C1;

[0250] P_cmd is the rated power (W) in the scheduling instruction set, such as P_cmd=40W for group C1;

[0251] t_duration is the duration (s, seconds), rounded to the nearest integer. If the calculated result is too long (e.g., more than 3600s = 1 hour), it will be truncated to 3600s (to avoid battery overheating due to prolonged equalization), and the remaining energy will be processed later.

[0252] Example calculation (Group C1): t_duration_C1 = 4.0Wh / 40W = 0.1h = 360s;

[0253] Example calculation (group C5, E_cmd=1.8Wh, P_cmd=20W): t_duration_C5=1.8Wh / 20W=0.09h=324s;

[0254] Example calculation (Group C2, E_cmd=3.0Wh, P_cmd=30W): t_duration_C2=3.0Wh / 30W=0.1h=360s.

[0255] III. Format and Examples of Adaptive Equalization Control Signals

[0256] The adaptive equalization control signal adopts a "binary structured format" (which facilitates hardware parsing and avoids the parsing delay of text format). The signal length is fixed at 32 bytes, and the meaning and example of each byte (Group C1) are as follows:

[0257] Bytes 0-1: Signal identifier (0xAA55, fixed start identifier, used for signal synchronization);

[0258] Byte 2: Group number encoding (0x01 represents C1, 0x02 represents C2, ..., 0x05 represents C5);

[0259] Byte 3: Current direction code (0x01 represents discharge "+", 0x02 represents charging "-");

[0260] Bytes 4-7: Target current amplitude (IEEE 754 single-precision floating-point number, such as 0.781A, hexadecimal 0x3F46D99A);

[0261] Bytes 8-11: Bus voltage reference (IEEE 754 single-precision floating-point number, such as 51.2167V, hexadecimal 0x424A1666);

[0262] Byte 12: DC-DC operating mode (0x01 represents Buck, 0x02 represents Boost);

[0263] Bytes 13-14: PWM frequency (unit: Hz, little-endian, 20kHz = 0x4E20, byte 13 = 0x20, byte 14 = 0x4E).

[0264] Bytes 15-18: PWM duty cycle (IEEE 754 single-precision floating-point number, such as 0.8984, hexadecimal 0x3F6F385C);

[0265] Bytes 19-20: PWM phase (unit: °, little-endian, 0° = 0x0000, byte 19 = 0x00, byte 20 = 0x00);

[0266] Bytes 21-24: Duration (in seconds, little-endian, 360s=0x0168, byte 21=0x68, byte 22=0x01, bytes 23-24=0x0000).

[0267] Bytes 25-30: Reserved bytes (padded with 0x00 for future feature expansion);

[0268] Byte 31: Checksum (the XOR sum of the first 30 bytes, used for error detection; for example, if the XOR result of the first 30 bytes is 0x3A, then byte 31 = 0x3A).

[0269] IV. Adaptive Adjustment Mechanism and Signal Update

[0270] Adaptive adjustment trigger conditions: The parameters of the adaptive equalization control signal will be automatically updated when the following conditions are met:

[0271] If the bus voltage fluctuation exceeds ±0.1V (e.g., from 51.2167V to 51.05V), update the "Bus Voltage Reference" and "Target Current Amplitude" (recalculate I_eq_comp).

[0272] If the actual current deviates from the target current by more than 100mA for 50ms (e.g., target 0.781A, actual 0.680A), update the "PWM duty cycle" (recalculate the PID output).

[0273] When there are 10 seconds left in the energy transfer duration, the "target current amplitude" is gradually reduced (from 0.781A to 0.1A) to avoid voltage surges caused by a sudden stop in the current.

[0274] Signal update frequency: The adaptively adjusted signal update frequency is consistent with the PID sampling period (1ms) to ensure that the parameters can track system changes in real time. The updated signal is resent to the DC-DC converter through the SPI interface to overwrite the old signal, realizing balanced control of "real-time adjustment and dynamic adaptation".

[0275] S204, execute the adaptive equalization control signal to realize high-frequency pulsed energy transfer across multiple battery packs through the DC bus, and complete the coordinated voltage equalization of multiple battery packs.

[0276] Specifically, the adaptive equalization control signal can be sent to each bidirectional DC-DC converter to drive the power switching devices to perform corresponding switching actions;

[0277] I. Control Signal Issuance, Communication, and Verification

[0278] Communication method selection and parameter configuration: Signals are transmitted using the SPI (Serial Peripheral Interface) communication protocol. This protocol features high speed (supports frequencies above 10MHz), low latency (single transmission delay ≤1μs), and full-duplex operation, adapting to the real-time update requirements of high-frequency PWM signals (updating once every 1ms). Communication parameter configuration is as follows:

[0279] Communication rate: 10MHz (ensuring that a 32-byte control signal can be transmitted within 3.2μs, much less than the 1ms update cycle);

[0280] Data bits: 8 bits (standard SPI data length); Clock polarity: CPOL=0 (clock low when idle); Clock phase: CPHA=1 (data is sampled on the second edge of the clock); Slave address: Each DC-DC converter is assigned a unique slave address (e.g., C1 group converter address 0x01, C5 group 0x05) to avoid signal transmission conflicts.

[0281] Signal transmission process and verification:

[0282] Step 1: The master controller (system level) selects the target converters sequentially according to the slave addresses (e.g., first select the C1 group converter with address 0x01).

[0283] Step 2: Send a "signal start identifier" (0xAA55, 2 bytes) to inform the converter that it is ready to receive data;

[0284] Step 3: Send a 32-byte adaptive equalization control signal (including PWM frequency, duty cycle, current direction, etc.);

[0285] Step 4: Send a "checksum" (the XOR result of the first 32 bytes, 1 byte). After receiving it, the converter recalculates the checksum. If it matches the sent value, it returns a "successful reception" response (0x00); if it does not match, it returns a "retransmission request" (0x01). The main controller will retry a maximum of 3 times to ensure error-free signal transmission.

[0286] II. Selection and Parameters of Power Switching Devices

[0287] Component selection criteria: The power switch of the bidirectional DC-DC converter needs to meet the requirements of "high withstand voltage (to adapt to battery pack voltage), large current (to carry equalization current), and low conduction loss (to improve efficiency)". The IRF3205 N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is selected, with the following core parameters:

[0288] Drain-source voltage Vds: 55V (higher than the battery pack's rated voltage of 51.2V, with a safety margin of 7.8V to avoid voltage spikes causing breakdown);

[0289] Continuous drain current Id: 110A (far greater than the maximum equalization current of 0.781A, meeting overload capacity requirements);

[0290] On-resistance Rds(on): 8mΩ (@Vgs=10V), conduction loss P_loss=I²R=0.781²×0.008≈0.0049W, extremely low loss;

[0291] Switching speed: On time t_on = 12ns, off time t_off = 9ns (supports high-frequency PWM above 20kHz to avoid excessive switching losses).

[0292] Device layout and drive circuit: Each DC-DC converter adopts a "half-bridge topology" and includes two IRF3205 MOSFETs (Q1 and Q2). Q1 is the high-side switch (close to the positive terminal of the group / bus), and Q2 is the low-side switch (close to the negative terminal of the group / bus). The drive circuit uses an IR2104 driver chip (to provide a 10V gate voltage to the MOSFET to ensure full conduction). A 10Ω current-limiting resistor is connected in series between the driver chip and the MOSFET to prevent excessive gate current from damaging the device.

[0293] III. Timing Logic of Switching Actions (in conjunction with DC-DC Operating Mode)

[0294] Discharge mode (Buck mode, taking C1 group as an example): C1 group voltage 51.3V > bus voltage 51.2167V, energy needs to be injected from the group into the bus. The DC-DC converter operates in Buck mode, and the switching sequence is as follows:

[0295] When the PWM signal is high (duty cycle 0.8984, duration 44.92μs): the driver chip IR2104 outputs a high level to the gate of Q1, and Q1 is turned on; when the gate of Q2 outputs a low level, Q2 is turned off; the current path is "C1 group positive terminal → Q1 → inductor L → bus positive terminal → bus load / charging group → C1 group negative terminal", the inductor stores energy, and the energy is injected into the bus;

[0296] When the PWM signal is low (lasting 5.08μs): Q1 gate is low, Q1 is off; Q2 gate is high, Q2 is on; the inductor releases stored energy, and the current path is "inductor L → Q2 → negative terminal of C1 group → positive terminal of C1 group → inductor L", to avoid sudden changes in inductor current and maintain stable current.

[0297] Dead time: A 5ns dead time (built into IR2104) is set between Q1 turning off and Q2 turning on to prevent Q1 and Q2 from turning on simultaneously and causing a short circuit between the positive and negative terminals of the group.

[0298] Charging mode (Boost mode, taking C5 group as an example): C5 group voltage 51.18V < bus voltage 51.2167V, needs to absorb energy from the bus. The DC-DC converter operates in Boost mode, and the switching sequence is as follows:

[0299] When the PWM signal is high (duty cycle 0.07, lasting 3.5μs): Q2 is turned on and Q1 is turned off; the current path is "bus positive terminal → inductor L → Q2 → bus negative terminal", and the inductor stores energy.

[0300] When the PWM signal is low (lasting 46.5μs): Q2 is turned off and Q1 is turned on; the inductor releases its stored energy, which is then superimposed on the bus voltage and output to group C5. The current path is "inductor L → Q1 → positive terminal of group C5 → negative terminal of group C5 → negative terminal of bus → inductor L", thus achieving boost charging.

[0301] The switching action in both modes is precisely controlled by the high and low levels of the PWM signal to ensure that the energy transfer direction and current amplitude meet the requirements of the initial equalization parameters.

[0302] The width and interval of the high-frequency pulse are adjusted according to the adaptive equalization control signal to achieve quantitative energy transfer and obtain pulse energy flow;

[0303] I. Correlation Adjustment of Pulse Width and Duty Cycle

[0304] The physical meaning of pulse width: The width of a high-frequency pulse, i.e., the high-level duration t_high of the PWM signal, directly determines the conduction time of the power switching device, thus affecting the energy transfer of a single pulse. t_high is calculated from the "PWM duty cycle D" and "PWM period T" in the adaptive equalization control signal, using the formula t_high = D × T, where:

[0305] D is the duty cycle (0~1), such as D=0.8984 for group C1; T is the PWM period (1 / frequency), such as T=50μs for group C1 with a frequency of 20kHz.

[0306] Energy impact of pulse width adjustment: The larger the duty cycle and the longer t_high, the more energy is transmitted in a single pulse.

[0307] II. Relationship between pulse interval time and frequency

[0308] Definition of pulse interval time: The pulse interval time is the time difference between the start of two adjacent pulses, which is equal to the PWM period T (for high-frequency PWM signals, which are continuous pulses, the interval time = period). For example, a 20kHz frequency corresponds to an interval time of 50μs, and a 10kHz frequency corresponds to 100μs. The interval time determines the pulse frequency. The higher the frequency, the more pulses per unit time, and the faster the energy transfer rate (under the same duty cycle).

[0309] Interval time adjustment constraints: The interval time must match the switching speed of the power switching device to avoid excessive switching losses due to excessively high frequency. The maximum switching frequency of IRF3205 is 1MHz, so the minimum interval time can be set to 1μs (1MHz frequency). However, considering the requirement for balanced current stability, it is actually set to 50μs (20kHz). At this time, the switching loss P_switch=2×f×Q_g×V_gs (Q_g is the gate charge, Q_g≈60nC for IRF3205; V_gs=10V), and the calculated P_switch=2×20×10^3×60×10^-9×10=0.024W, which is much smaller than the conduction loss, ensuring efficiency.

[0310] III. Calculation and Verification of Quantitative Energy Transfer

[0311] The relationship between total energy and the number of pulses: The total energy transfer amount E_total (e.g., 4.0Wh = 14400J for group C1) is equal to the energy of a single pulse E_single multiplied by the total number of pulses N, with the formula N = E_total / E_single. Combining E_single = P × T, we can deduce that N = E_total / (P × T) = t_duration / T (t_duration is the duration, 360s for group C1), ensuring that the energy quantification is consistent with the time quantification.

[0312] Dynamic adjustment mechanism: If energy transfer deviation is detected in real time (e.g., the actual current is lower than the target current, resulting in a small E_single), the duty cycle is increased (e.g., from 0.8984 to 0.91) to improve E_single, while keeping the interval time constant, ensuring that the total number of pulses decreases but the total energy still meets the target. For example, with an actual current of 0.77A, E_single = 51.2167 × 0.77 × 50e-6 ≈ 0.00197J, requiring N = 14400 / 0.00197 ≈ 7.31 × 10^6 pulses. After adjusting the duty cycle to 0.91, the current rises back to 0.79A, E_single = 0.00202J, and N = 14400 / 0.00202 ≈ 7.13 × 10^6 pulses, returning to the target range.

[0313] IV. Characteristics and Monitoring of Pulse Energy Flow

[0314] The pulsed energy flow is a "high-frequency, quantitative, and continuous" energy sequence, with the following characteristic parameters:

[0315] Frequency: 20kHz (50μs interval); Single energy: 0.002J (C1 group); Duration: 360s (7.2×10^6 pulses); Current pattern: continuous pulse current, peak value 0.781A, valley value close to 0 (no interruption under inductor freewheeling);

[0316] The pulse energy flow current amplitude is monitored in real time by a current sensor (such as ACS712, accuracy ±1.5%) connected in series at the DC-DC output terminal to ensure consistency with the target. If the deviation exceeds ±5%, the duty cycle / frequency adjustment is triggered.

[0317] Through the DC bus medium, the pulse energy flow is directionally transmitted between battery packs, completing the transfer of energy from the high voltage pack to the low voltage pack, and realizing the cross-pack flow of energy;

[0318] I. Hardware Structure and Function of DC Bus

[0319] Bus Topology and Core Components: The DC bus adopts a "single-pole bus topology," including a positive bus (copper bus cross-sectional area 10mm², current carrying capacity ≥50A), a negative bus (same as the positive bus), bus capacitors (470μF / 100V, electrolytic capacitors and ceramic capacitors in parallel), and fuses (10A / 60V, overcurrent protection). The functions of the core components are as follows:

[0320] Bus capacitors: absorb the high-frequency ripple of pulsed energy flow (ripple current generated by 20kHz PWM), stabilize the bus voltage, and prevent voltage fluctuations from exceeding ±0.05V (e.g., when energy is injected into C1 group, the capacitors charge, and the voltage rises from 51.2167V to 51.220V; when C5 group absorbs energy, the capacitors discharge, and the voltage drops back to remain stable).

[0321] Fuse: When the bus current exceeds 10A (such as in the case of a short circuit fault), the fuse will blow within 10ms, cutting off the bus and protecting all groups and converters.

[0322] Bus voltage stabilization control: The bus voltage is set to the rated value of 51.2V, with an allowable fluctuation range of ±0.1V (51.1V~51.3V). Stability is achieved through the charging and discharging of the bus capacitor and the "injection-absorption" balance of energy in each group.

[0323] II. Path Logic of Energy Injection and Absorption

[0324] Energy injection path for the high-voltage group (C1 group, discharge mode):

[0325] Physical path: C1 group positive terminal → C1 group DC-DC converter (Buck mode, Q1 is on) → inductor L → bus positive terminal → bus capacitor (charging) → bus negative terminal → C1 group negative terminal;

[0326] Energy form: Chemical energy of group C1 → Electrical energy of DC-DC converter (pulse form) → Electric field energy of bus capacitor → Bus electrical energy;

[0327] Current direction: The current flowing out of group C1 is in the direction of "group → converter → bus", with a current amplitude of 0.781A and a pulse frequency of 20kHz.

[0328] Energy absorption path for the low-voltage group (C5 group, charging mode):

[0329] Physical path: Bus positive terminal → C5 group DC-DC converter (Boost mode, Q1 is on) → Inductor L → C5 group positive terminal → C5 group negative terminal → Bus negative terminal → Bus capacitor (discharging);

[0330] Energy form: Bus electrical energy → Electric field energy of bus capacitor → Electrical energy of DC-DC converter (after boost) → Chemical energy of C5 group;

[0331] Current direction: The current flowing into group C5 is in the direction of "bus → converter → group", with a current amplitude of 0.390A and a pulse frequency of 20kHz.

[0332] Example of multiple coordinated transport: When C1 (40W injection), C5 (20W absorption), and C2 (30W absorption) operate simultaneously, the energy flow balance process is as follows:

[0333] Initial moment: C1 injects 40W, C5 and C2 absorb 50W, the bus capacitor discharges 10W, and the voltage drops by 0.0067V (from 51.2167V to 51.210V).

[0334] Adjustment timing: The main controller detects a voltage drop, increases the duty cycle of the C1 group DC-DC converter to 0.91, and the injected power rises to 41W. At the same time, it decreases the duty cycle of the C2 group to 0.065, and the absorbed power drops to 28W. The total absorbed power is 48W. The difference of 7W between the absorbed power and the injected power of 41W is supplemented by the bus capacitor, and the voltage stabilizes at 51.212V.

[0335] At equilibrium: C1 duty cycle is further fine-tuned to 0.92, with an injected power of 42W. C2 duty cycle is restored to 0.07, with an absorbed power of 30W, for a total absorbed power of 50W. At this point, C1 duty cycle is increased again to 0.95, with an injected power of 44W. The difference of 6W is supplemented by the capacitor. Finally, through multiple fine-tuning, the injected power is approximately equal to the absorbed power, and the voltage is stabilized at 51.215V ± 0.002V.

[0336] III. Protection Mechanisms for Directed Transmission (Anti-Backflow and Overcurrent)

[0337] Reverse current protection: A Schottky diode (e.g., SS34, forward voltage drop 0.5V, rated current 3A) is connected in series at the output of each DC-DC converter. The diode orientation is consistent with the energy transfer direction.

[0338] Discharge group (C1): The positive terminal of the diode is connected to the output terminal of the converter, and the negative terminal is connected to the positive terminal of the bus to prevent current from flowing back into the group when the bus voltage is higher than the group voltage.

[0339] Charging group (C5): The positive terminal of the diode is connected to the positive terminal of the bus, and the negative terminal is connected to the input terminal of the converter to prevent current from flowing back to the bus when the group voltage is higher than the bus voltage;

[0340] Overcurrent protection: Each DC-DC converter has a built-in current sampling resistor (0.1Ω / 2W) to monitor the output current in real time. If the current exceeds 1.5 times the rated value (e.g., C1 group is rated at 0.781A, and the overcurrent threshold is 1.17A), the MOSFET will be turned off within 1μs to stop energy transfer and send an "overcurrent fault" message (0xEE01) to the main controller. After receiving the message, the main controller will mark the group as "fault state" and suspend its energy transfer until the fault is cleared.

[0341] The voltage changes of each battery pack are monitored in real time. When the voltage reaches the equalization target, the equalization current is gradually reduced until it stops, and a voltage equalization completion signal is obtained, thus completing the coordinated voltage equalization of multiple battery packs.

[0342] I. Real-time monitoring of the voltage of each battery pack

[0343] Monitoring hardware and parameters: The ADS1256ADC chip is used. Each group is configured with an independent sampling channel, a sampling frequency of 1kHz (balancing real-time performance and data volume), a sampling accuracy of ±0.9mV, and sampling points are located at the positive and negative output terminals of the group to eliminate line voltage drop errors.

[0344] Monitoring data processing: One group voltage value is collected every 1ms. Kalman filtering is used to eliminate noise and obtain a smooth group voltage value V_cluster_filtered. At the same time, the real-time deviation between the group voltage and the bus voltage ΔV_real=V_cluster_filtered-V_bus_real is calculated. The deviation is retained to 4 decimal places (e.g., for group C1, ΔV_real=51.2200V-51.2167V=0.0033V).

[0345] II. Basis and Judgment for Setting Balance Targets

[0346] Equalization target setting: The equalization target is "the deviation between each group voltage and the bus voltage ΔV_target ≤ ±0.01V (10mV)", and the basis for setting this threshold is as follows:

[0347] Battery characteristics: The voltage consistency requirement for lithium iron phosphate batteries is typically ±10mV (a deviation exceeding 10mV will result in a decrease in capacity utilization of more than 5%).

[0348] System requirements: The energy storage system's charge and discharge efficiency must be equalized, with a capacity deviation of ≤2% and a corresponding voltage deviation of ≤10mV.

[0349] Example: The balancing target for group C1 is V_cluster_filtered∈[51.2067V,51.2267V] (bus voltage 51.2167V±0.01V).

[0350] Target determination logic: Continuously monitor for 10 sampling periods (10ms). If the absolute value of ΔV_real is ≤0.01V, the group is determined to have reached the equilibrium target; if ΔV_real is >0.01V in any period, the equilibrium continues.

[0351] III. Soft Stop Implementation Logic for Equalizing Current

[0352] The gradient and interval of current reduction: A "linear gradient reduction" method is used, reducing the current by 10% each time, with a reduction interval of 100ms (to avoid voltage surges caused by sudden current changes), until the current drops to 0.01A (considered the stopping threshold). The specific steps are as follows:

[0353] Step 1: After reaching the equilibrium target, the current I_current = 0.781A. It decreases by 10% for the first time, I_new = 0.781A × 0.9 = 0.703A, and is maintained for 100ms.

[0354] Step 2: After 100ms, decrease by 10% for the second time, I_new = 0.703A × 0.9 = 0.632A, and maintain for 100ms;

[0355] Step 3: Repeat the reduction process until I_new≤0.01A, then stop the current output.

[0356] Voltage maintenance after stopping: After the current stops, continue to monitor the group voltage deviation. If ΔV_real exceeds 0.01V again (e.g., the voltage of group C1 drops to 51.205V, ΔV_real = -0.0117V), then restart the equalization process. The current will gradually increase from 0.05A until the deviation returns to ≤0.01V, ensuring the equalization effect is lasting.

[0357] IV. Equalization completes signal generation and overall coordinated completion.

[0358] Single group completion signal: When a group completes a soft stop and the deviation is ≤0.01V for 200ms, the main controller generates a "balanced completion signal" for that group. The signal format is a CAN message.

[0359] Message ID: 0x123 (Dedicated ID for load balancing completion);

[0360] Data segment: 1 byte group number (0x01 represents C1) + 1 byte status (0x00 represents completion) + 6 bytes reserved (0x00);

[0361] Example: The CAN message for the C1 group completion signal is 0x123,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00.

[0362] Overall coordination completion determination: When all execution groups (C1, C5, C2) send "balancing completion signal" and the bus voltage stabilizes at 51.2V±0.01V, the main controller generates an "overall balancing completion signal" and sends it to the system monitoring terminal via the CAN bus. The terminal displays "Multiple battery groups coordinated balancing completed" and records balancing data (such as initial voltage, completed voltage, energy transfer amount, and balancing time for each group). Example record:

[0363] Group C1: Initial 51.300V → Completed 51.219V, transferred energy 4.0Wh, duration 360.8s;

[0364] Group C5: Initial 51.180V → Completed 51.215V, energy transferred 1.8Wh, duration 324.5s;

[0365] Group C2: Initial 51.144V → Completed 51.213V, energy transferred 3.0Wh, duration 360.2s;

[0366] Overall balancing time: 361s, bus voltage stabilized at 51.215V±0.002V.

[0367] At this point, the coordinated voltage equalization process of multiple battery packs is complete, the voltage consistency of each pack meets the requirements, and energy is transferred directionally and quantitatively from the high-voltage pack to the low-voltage pack through the DC bus. The entire process is highly stable and safe.

[0368] Another embodiment of the present invention provides a multi-cell coordinated balancing system based on a DC bus, see [link to relevant documentation]. Figure 3 The system may include:

[0369] The monitoring module 301 is used to monitor the terminal voltage and DC bus voltage of each battery pack in multiple battery packs in real time, and to calculate the dynamic deviation between the voltage of each battery pack and the bus voltage.

[0370] The determination module 302 is used to generate cross-group energy dispatch requirements based on the dynamic deviation, and determine the priority sequence of energy transfer for each group according to the real-time bus voltage fluctuation amplitude.

[0371] The adjustment module 303 is used to dynamically adjust the direction and amplitude of the equalization current through a bidirectional DC-DC converter based on the priority sequence and the real-time value of the bus voltage, using a voltage following strategy, to generate an adaptive equalization control signal.

[0372] The equalization module 304 is used to execute the adaptive equalization control signal and realize high-frequency pulse energy transfer across multiple battery packs through the DC bus to achieve coordinated voltage equalization of multiple battery packs.

[0373] The above description, based on the embodiments shown in the figures, details the structure, features, and effects of the present invention. The above description is only a preferred embodiment of the present invention, but the present invention is not limited to the scope of implementation shown in the figures. Any changes made in accordance with the concept of the present invention, or equivalent embodiments modified to have equivalent changes, that do not exceed the spirit covered by the specification and figures, should be within the protection scope of the present invention.

Claims

1. A method for multi-battery group cooperative equalization based on DC bus, characterized in that, The method comprises: Real-time monitoring of the terminal voltage of each battery group in the multiple battery groups and the DC bus voltage, and calculating the dynamic deviation of the voltage of each battery group and the bus voltage; Based on the dynamic deviation, generate the cross-group energy scheduling requirement, and determine the priority sequence of energy transfer of each group according to the real-time bus voltage fluctuation amplitude; wherein, analyze the amplitude and change trend of the voltage dynamic deviation vector, combine the capacity and SOC state of the battery group, calculate the required energy transfer amount and direction of each group, and generate the cross-group energy scheduling requirement table; real-time monitoring of the fluctuation amplitude and frequency of the DC bus voltage, using fast Fourier transform to analyze the main frequency component of the voltage fluctuation, generating the bus voltage fluctuation characteristic spectrum; based on the bus voltage fluctuation characteristic spectrum and the cross-group energy scheduling requirement table, comprehensively considering the balancing speed, system stability and efficiency, constructing a multi-objective optimization function; solving the multi-objective optimization function, determining the emergency degree and benefit evaluation of the energy transfer of each battery group, and generating the priority sequence of the energy transfer of each group according to the priority sequence; According to the priority sequence and the real-time value of the bus voltage, using the voltage following strategy, dynamically adjusting the direction and amplitude of the balancing current through the bidirectional DC-DC converter, generating the adaptive balancing control signal; Executing the adaptive balancing control signal, realizing high-frequency pulse energy cross-group transfer through the DC bus, and completing the collaborative voltage balancing of the multiple battery groups.

2. The method of claim 1, wherein, The real-time monitoring of the terminal voltage of each battery group in the multiple battery groups and the DC bus voltage, and calculating the dynamic deviation of the voltage of each battery group and the bus voltage, comprises: Real-time acquisition of the terminal voltage data of each battery group in the multiple battery groups, and acquisition of the DC bus voltage data at the same time, generating the original voltage sampling data set; Filtering the original voltage sampling data set, using Kalman filtering algorithm to eliminate measurement noise and interference, generating the accurate voltage data set after denoising; Based on the accurate voltage data set after denoising, real-time calculation of the instantaneous difference value of the terminal voltage of each battery group and the DC bus voltage, generating the initial voltage deviation data set; Time series analysis of the initial voltage deviation data set, calculating the change rate and trend of the deviation, generating the voltage dynamic deviation vector containing dynamic change characteristics.

3. The method of claim 2, wherein, According to the priority sequence and the real-time value of the bus voltage, using the voltage following strategy, dynamically adjusting the direction and amplitude of the balancing current through the bidirectional DC-DC converter, generating the adaptive balancing control signal, comprising: Analyzing the priority sequence of each group energy transfer, determining the battery group and its transfer direction that need to perform energy transfer at present, generating the current scheduling instruction set; Real-time acquisition of the DC bus voltage value, combining the current scheduling instruction set, calculating the required balancing current amplitude and direction, generating the preliminary balancing parameters; Using the voltage following control strategy, dynamically adjusting the duty ratio and phase of the bidirectional DC-DC converter through the PID controller, generating the PWM control signal; Fusing the PWM control signal and the preliminary balancing parameters, generating the adaptive balancing control signal containing at least the current amplitude, direction and duration parameters.

4. The method of claim 3, wherein, The adaptive equalization control signal is executed to realize high-frequency pulse energy transfer across groups through a DC bus, and to complete collaborative voltage equalization of multiple battery groups, including: The adaptive equalization control signal is sent to each bidirectional DC-DC converter to drive the power switch device to perform corresponding switching actions; The width and interval time of the high-frequency pulse are adjusted according to the adaptive equalization control signal to realize quantitative energy transfer and obtain pulse energy flow; The pulse energy flow is transmitted between the battery groups through the DC bus medium to complete energy transfer from the high-voltage group to the low-voltage group and realize energy flow across groups; The voltage of each battery group is monitored in real time, and when the voltage reaches the equalization target, the equalization current is gradually reduced until it stops to obtain a voltage equalization completion signal, and collaborative voltage equalization of multiple battery groups is completed.

5. A multi-bank battery cooperative equalization system based on DC bus, characterized in that, The system comprises: A monitoring module for monitoring the terminal voltage of each battery group in multiple battery groups and the DC bus voltage in real time, and calculating the dynamic deviation of the voltage of each battery group from the bus voltage; A determination module for generating a cross-group energy scheduling requirement based on the dynamic deviation, and determining a priority sequence of energy transfer of each group according to the real-time bus voltage fluctuation amplitude; wherein the amplitude and trend of the voltage dynamic deviation vector are analyzed, the capacity and SOC state of the battery group are combined, the required energy transfer amount and direction of each group are calculated, and a cross-group energy scheduling requirement table is generated; the fluctuation amplitude and frequency of the DC bus voltage are monitored in real time, the main frequency components of the voltage fluctuation are analyzed by using fast Fourier transform to generate a bus voltage fluctuation characteristic spectrum; based on the bus voltage fluctuation characteristic spectrum and the cross-group energy scheduling requirement table, the equalization speed, system stability and efficiency are considered comprehensively to construct a multi-objective optimization function; the multi-objective optimization function is solved to determine the urgency and benefit evaluation of the energy transfer of each battery group, and a priority sequence of the energy transfer of each group is generated according to the priority sequence; An adjustment module for generating an adaptive equalization control signal by dynamically adjusting the direction and amplitude of the equalization current through the bidirectional DC-DC converter according to the priority sequence and the real-time value of the bus voltage by using a voltage following strategy; An equalization module for executing the adaptive equalization control signal to realize high-frequency pulse energy transfer across groups through a DC bus and complete collaborative voltage equalization of multiple battery groups.

6. The system of claim 5, wherein, The monitoring module is specifically configured to: Collect terminal voltage data of each battery group in multiple battery groups in real time, and collect DC bus voltage data to generate an original voltage sampling data set; Filter the original voltage sampling data set to eliminate measurement noise and interference by using a Kalman filtering algorithm to generate an accurate voltage data set after denoising; Real-time calculate the instantaneous difference between the terminal voltage of each battery group and the DC bus voltage based on the accurate voltage data set after denoising to generate an initial voltage deviation data set; Perform time series analysis on the initial voltage deviation data set to calculate the change rate and trend of the deviation to generate a voltage dynamic deviation vector containing dynamic change characteristics.

7. A storage medium, characterized by The storage medium stores a computer program, wherein the computer program is configured to execute the method of any one of claims 1-4 when running.

8. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to execute the method of any one of claims 1-4.

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