A fast amplitude and phase calibration method and system for phased array terminals

Abstract

The present application relates to the technical field of satellite communication, and particularly relates to a fast amplitude and phase calibration method and system for a phased array terminal. Main steps include: 1. A PS side queries a pre-stored compensation table according to frequency and temperature information to generate amplitude and phase compensation values; 2. The compensation values are written into a dual-port RAM on a PL side, and a flag bit is used to manage the writing state; 3. The PL side reads data in an active main table in parallel to perform high-speed operation; 4. The final compensation values are quickly configured to a beamforming chip through an SPI interface; 5. When parameters change, the main and backup tables are switched through updating the backup table and triggering a flag. The present application has the following beneficial effects: the compensation speed is greatly improved through hardware acceleration, the continuity and real-time performance of the compensation process are ensured through ping-pong switching, and the beam pointing accuracy and communication link stability of the phased array terminal in a complex temperature and frequency change environment are effectively guaranteed.

Description

Technical Field

[0001] This invention belongs to the field of phased array antenna calibration in satellite communication technology, specifically relating to a fast amplitude and phase calibration method and system for phased array terminals, used to achieve high real-time amplitude and phase calibration. Background Technology

[0002] Phased array terminals are key equipment in current low-Earth orbit (LEO) satellite internet communication systems. They achieve directional scanning and tracking of the beam by controlling the amplitude and phase of each radiating element in the antenna array. Because LEO satellites move at high speeds relative to the ground, the terminal must be able to adjust the beam direction with extremely high real-time precision (milliseconds or even higher) to continuously and stably track the satellite. The short wavelength of the phased array terminal results in highly directional beams, meaning that even slight deviations in beam direction can cause a sharp drop in the signal-to-noise ratio or even interruption of the communication link.

[0003] The performance of a phased array antenna is highly dependent on the amplitude and phase consistency of each channel. However, during operation, changes in ambient temperature and the power consumption of the chip itself can cause drift in the performance parameters of active components such as amplifiers, phase shifters, and attenuators in the RF path. This drift directly manifests as amplitude and phase errors in the channels, resulting in beam pointing deviation, beam shape distortion, and increased sidelobe levels. Therefore, it is essential to compensate for amplitude and phase errors caused by temperature and frequency variations in real time (i.e., temperature-frequency compensation).

[0004] In existing technologies, common temperature and frequency compensation schemes are mainly implemented by software on the PS side. The basic process is as follows: the software application periodically reads temperature sensor data, combines it with the current operating frequency, queries a compensation coefficient table stored in a file or database, calculates the required amplitude and phase compensation values, and then sends them to the hardware circuit (such as a beamforming chip) via a bus interface such as SPI or I2C. This software approach has significant drawbacks: the software runs on top of the operating system and is affected by task scheduling, interrupt response mechanisms, etc., resulting in long cycle times and large response delays (typically tens of milliseconds or more), making it difficult to meet the stringent real-time requirements for beam pointing in low-Earth orbit satellite communication scenarios. In high-dynamic conditions with rapid temperature changes or frequent beam switching, the delay in software compensation leads to untimely updates of amplitude and phase parameters, degrading terminal performance and becoming a bottleneck for system reliability.

[0005] Therefore, there is an urgent need in this field for a new temperature and frequency compensation technology that can overcome software processing bottlenecks, achieve microsecond-level fast response, and ensure continuous and accurate beam pointing. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of existing software-based temperature and frequency compensation methods, such as poor real-time performance and slow update rate, and to provide a fast amplitude and phase calibration method based on PL that has a fast response speed, can achieve seamless hot updates, and can significantly improve the working stability of phased array terminals in complex environments.

[0007] To achieve the above objectives, the technical solution adopted in this invention is a rapid amplitude and phase calibration method for phased array terminals. The core of this method lies in efficiently dividing the compensation task between the PS (Power Switch) and PL (Power Array Controller), and utilizing the hardware parallel processing capabilities and ping-pong buffering mechanism of the PL to achieve high-speed processing and seamless switching of compensation data.

[0008] The specific implementation steps of the method are as follows:

[0009] Step 1: Data Preparation

[0010] The PS (Power Switch) acquires the operating frequency information of the phased array terminal and the ambient temperature information collected by a temperature sensor in real time or periodically. Then, based on these parameters, the PS queries and matches them against a pre-generated and stored compensation data file (such as a CSV file) to obtain the corresponding preliminary amplitude compensation and phase compensation values. To simplify subsequent processing, the amplitude compensation value is usually given as an absolute gain value (such as dB), while the phase compensation value is given as the phase difference relative to a reference channel.

[0011] Step 2: Data writing and handshake

[0012] The PS side transmits and writes the amplitude and phase compensation values ​​generated in step 1 into the dual-port RAM inside the PL chip via the system bus AXI. The PL side reserves two independent storage areas, serving as the "master table" and "backup table" respectively, forming the basis of the ping-pong operation. When writing data, the PS side follows a strict handshake protocol: before writing data to a table (master or backup), it first clears the corresponding bit in a dedicated 2-bit completion flag to 0 (indicating that the table data is invalid or being updated); after all compensation data is successfully written to the RAM area corresponding to the table, the corresponding flag is then set to 1 (indicating that the table data is ready and available).

[0013] Step 3: Parallel Reading and Computation

[0014] The PL (Programmable Logic Unit) incorporates dedicated control logic that continuously monitors the write completion flag. When the flag corresponding to the main table is detected as 1, the data reading and calculation process is immediately initiated. To minimize configuration time, the PL instantiates multiple parallel read engines, capable of simultaneously reading compensation data from multiple channels in RAM. These read base compensation values ​​are added to the dynamically adjusted compensation values ​​(used to compensate for more subtle instantaneous changes) calculated in real-time by the PL, ultimately yielding precise amplitude and phase compensation values ​​for each channel, suitable for the current temperature and frequency.

[0015] Step 4: Chip Configuration and Calibration

[0016] PL uses multiple high-speed SPI interfaces to quickly and sequentially write the final compensation values ​​for each channel calculated in step 3 into the corresponding beamforming chip, according to the register mapping format of the beamforming chip. This configuration process directly changes the settings of the attenuators and phase shifters inside the chip, thereby calibrating the amplitude and phase characteristics of the RF channel in real time and offsetting the effects of temperature drift and frequency drift.

[0017] Step 5: Dynamic Updates and Ping Pong Switching

[0018] When the system detects a change in operating frequency or a temperature sensor reading exceeding a preset threshold, a dynamic update process is triggered. The PS (Power Supply) immediately executes step 1 based on the new frequency and temperature parameters, generating a new set of compensation values. Subsequently, it writes this new data to the PL (Power Supply Module) storage area corresponding to the currently unused backup table, strictly adhering to the protocol operation flag bit in step 2. After completing the data writing to the backup table, the PS sets an independent refresh flag signal. The PL's control logic checks this refresh flag after completing the current round of configuration operations based on the old master table. Once the refresh flag is found to be valid, a master-slave table switch is immediately executed: the currently updated backup table is promoted to the new master table for all subsequent data reads; while the original master table is downgraded to the new backup table, its contents overwritten by subsequent update operations. This ping-pong switching mechanism achieves seamless and uninterrupted updates of compensation data, ensuring the system continuously receives accurate compensation when parameters change.

[0019] The present invention also provides a rapid amplitude and phase calibration system applying the above method, comprising:

[0020] A ZYNQ chip integrating a processing system (PS) and programmable logic (PL);

[0021] Multiple high-precision temperature sensors are distributed throughout the system to collect temperature information from key modules in real time.

[0022] Multiple beamforming chips are connected to the PL side of the ZYNQ chip and communicate with each other via a high-speed SPI interface;

[0023] The PS side is configured as the system's control and decision-making center, responsible for acquiring the operating frequency, reading temperature data from the temperature sensor, querying compensation parameters based on temperature and frequency, and issuing update commands to the PL side. The PL side is configured as the system's real-time execution and hardware acceleration engine, containing dedicated hardware modules such as dual-port RAM, flag monitoring, ping-pong table management, parallel computing, and SPI control. It receives compensation data from the PS side and performs compensation value calculation and rapid configuration of the beamforming chip in hardware parallel mode, thereby collaboratively achieving microsecond-level, uninterrupted amplitude and phase calibration.

[0024] Within the ZYNQ chip, the PL side and the PS side work together to form a complete hardware-accelerated pipeline. The PS side acts as the control and scheduling center, responsible for decision-making and management tasks; the PL side, as the real-time execution engine, receives instructions and data from the PS side and performs high-speed, deterministic processing through dedicated hardware modules. The two sides work closely together via an internal AXI bus using shared memory and a flag mechanism, specifically including:

[0025] The PL-side hardware acceleration pipeline includes the following logic modules:

[0026] The flag monitoring and arbitration module is connected to the PS side and is used to monitor the write completion flag and refresh flag written by the PS side in real time, and issue control commands to subsequent modules based on the status of these flags.

[0027] The ping-pong table management module is connected to the flag monitoring and arbitration module and the dual-port RAM shared by the PS side. It is used to respond to the update triggers on the PS side, manage the role switching of the primary and backup storage areas according to the control instructions, and ensure that when the PS writes new data to the backup table, the PL can continuously read the current valid data from the primary table.

[0028] A multi-channel parallel reading and calculation engine, connected to the ping-pong table management module, is used to read multiple compensation data in parallel from the activated main storage area in each processing cycle and perform real-time compensation value calculation. This hardware parallel mechanism replaces the software serial calculation on the PS side.

[0029] The SPI configuration controller, connected to the multi-channel parallel read and compute engine, is used to configure the calculated final compensation parameters to an external beamforming chip via a high-speed SPI interface.

[0030] The PS side, acting as the control and scheduling center, is responsible for the following upper-level management tasks:

[0031] System environment monitoring, including reading temperature sensor data and obtaining the current operating frequency through the interface;

[0032] The compensation strategy is executed by querying the compensation parameter table based on temperature and frequency, and preparing the compensation data to be sent out.

[0033] Task assignment and synchronization are achieved by writing data to the shared dual-port RAM on the PL side and setting the corresponding write completion flag and refresh flag, thereby sending precise execution instructions to the PL side.

[0034] Through the above architecture, the flexible control on the PS side and the deterministic high-speed processing capability on the PL side are closely integrated, realizing full-process hardware acceleration from instruction issuance and data processing to chip configuration.

[0035] Compared with the prior art, the technical solution provided by the present invention has the following technical effects:

[0036] (1) Achieve high-speed real-time calibration at the microsecond level: By processing the core process in hardware using PL, the response time is improved from the millisecond level to the microsecond level, which meets the stringent real-time requirements of high dynamic scenarios.

[0037] (2) Ensure continuous and stable system during parameter updates: Based on the ping-pong dual-table and hardware switching mechanism, hot updates and seamless switching of compensation data are realized, avoiding beam interruption and jitter.

[0038] (3) Provides high-precision adaptive compensation: The software and hardware collaborative two-level compensation mechanism of "pre-stored curve + real-time fine adjustment" is adopted, which significantly improves the calibration accuracy in the full temperature and full frequency range.

[0039] (4) Simplify system design and hardware complexity: By leveraging the high integration of the ZYNQ chip, the functions of the traditional multi-chip architecture can be realized with a single chip, reducing power consumption, cost and size.

[0040] (5) Enhance system flexibility and scalability: The rich software stack running on the PS side facilitates complex monitoring, debugging and upper-layer protocol stacks, while the hardware logic on the PL side can be flexibly configured to adapt to various beamforming chips with different channel numbers and different interface protocols. Attached Figure Description

[0041] Figure 1 This is an overall block diagram of the fast amplitude and phase calibration system for the phased array terminal in this embodiment.

[0042] Figure 2 This is a schematic diagram illustrating the implementation steps of the rapid amplitude and phase calibration method for a phased array terminal in this embodiment. Detailed Implementation

[0043] The present invention will be further described in detail below with reference to a preferred embodiment, but the implementation of the present invention is not limited thereto.

[0044] In this embodiment, as Figure 1 As shown, a rapid amplitude and phase calibration system for a phased array terminal includes: a ZYNQ chip, which integrates a PS (Processing System) and a PL (Programmable Logic); multiple high-precision temperature sensors distributed throughout the system for real-time acquisition of temperature information from key modules, including the ZYNQ chip and beamforming chips; and multiple beamforming chips connected to the PL side of the ZYNQ chip and communicating via an SPI interface.

[0045] The temperature sensor sends the collected temperature data to the PS side. The PS side queries the compensation table based on the temperature and operating frequency, and writes the compensation value into the dual-port RAM of the PL side. The PL side reads the data from the dual-port RAM, calculates the data, and then configures the beamforming chip through the SPI interface.

[0046] The ZYNQ chip is internally divided into:

[0047] On the PS side, it is configured to perform a data preparation step, a data writing and handshake step, and a dynamic update trigger operation; wherein, the data preparation step includes acquiring temperature and operating frequency information and querying the compensation table; the data writing and handshake step includes writing the compensation value into the dual-port RAM and setting the write completion flag; the dynamic update trigger operation includes triggering the refresh flag when the parameters change;

[0048] On the PL side, connected to the PS side via a high-speed AXI bus, it contains the dual-port RAM and is configured to perform PL-related operations in the data writing and handshake steps, parallel reading and calculation steps, chip configuration steps, and dynamic update and ping-pong switching steps. The PL-related operations include monitoring flags to manage read and write access to the dual-port RAM; the parallel reading and calculation steps include reading data from the RAM in parallel and performing calculations; the chip configuration steps include configuring the beamforming chip via the SPI interface; and the ping-pong switching steps include managing the switching of primary and backup storage roles.

[0049] Inside the ZYNQ chip, the PL-side hardware acceleration pipeline includes the following logic modules:

[0050] The flag monitoring and arbitration module is connected to the PS side and is used to monitor the write completion flag and refresh flag written by the PS side in real time, and issue control commands to subsequent modules based on the status of these flags.

[0051] The ping-pong table management module is connected to the flag monitoring and arbitration module and the dual-port RAM shared by the PS side. It is used to respond to the update triggers on the PS side, manage the role switching of the primary and backup storage areas according to the control instructions, and ensure that when the PS writes new data to the backup table, the PL can continuously read the current valid data from the primary table.

[0052] A multi-channel parallel reading and calculation engine, connected to the ping-pong table management module, is used to read multiple compensation data in parallel from the activated main storage area in each processing cycle and perform real-time compensation value calculation.

[0053] An SPI configuration controller, connected to the multi-channel parallel read and compute engine, is used to configure the calculated final compensation parameters to an external beamforming chip via a high-speed SPI interface.

[0054] The PS side, acting as the control and scheduling center, is responsible for the following upper-level management tasks:

[0055] System environment monitoring includes reading temperature sensor data via an interface to obtain the current operating frequency;

[0056] The compensation strategy is executed by querying the compensation parameter table based on temperature and frequency, and preparing the compensation data to be sent out.

[0057] Task assignment and synchronization are achieved by writing data to the shared dual-port RAM on the PL side and setting the corresponding write completion flag and refresh flag, thereby sending precise execution instructions to the PL side.

[0058] like Figure 2 As shown, a fast amplitude and phase calibration method for a phased array terminal is implemented as follows:

[0059] System initialization: After the system is powered on, the PS side loads the compensation data CSV file stored in Flash into memory. The PL completes the initialization of hardware logic and register configuration. In the initial state, the PS side writes a set of default compensation data into the dual-port RAM of the PL and sets it as the main table (corresponding to write_done[0] being set to 1), and the backup table area is empty (corresponding to write_done[1] being 0).

[0060] Normal calibration cycle: The PL executes the calibration process in a fixed clock cycle (e.g., 10µs). Within each cycle, the PL uses data from the current master table. Its control logic generates multiple parallel addresses and simultaneously reads compensation data from 8 channels (assuming a 64-channel array). The read data is fed into the pipeline and added to the dephase data. The result is then sent to the beamforming chip at the highest possible rate via the SPI controller.

[0061] Triggered update: When the temperature sensor detects an ambient temperature change exceeding ±5°C, or when the terminal receives an instruction to switch operating frequencies, the PS side is interrupted and woken up or actively initiates the update process.

[0062] Data update and switching: The PS side queries the compensation table based on the new temperature or frequency and generates a new 64-channel compensation value array. The PS side starts writing new data to the backup table area of ​​the PL through the bus. Before writing, the write_done[1] bit is cleared to 0.

[0063] After the data is written, the write_done[1] bit is set to 1, and the refresh_flag signal is set to 1 at the same time. After the PL completes the current calibration cycle, it detects that refresh_flag is high. At the beginning of the next cycle, a switch is performed: the storage mapping relationship is switched so that the original standby table becomes the new data source (new master table), and the original master table area becomes the new standby table. At the same time, refresh_flag is cleared to zero.

[0064] After this, the PL calibration cycle will run based on the new master table data. The PS side can write the next update data into the new backup table (i.e., the old master table) whenever needed.

[0065] Through the above implementation methods, the present invention successfully achieves hardware acceleration and seamless updates for temperature and frequency compensation, providing key technical support for the stable and reliable operation of phased array terminals in harsh environments.

[0066] While the present invention has been disclosed above with reference to preferred embodiments, these embodiments and accompanying drawings are not intended to limit the invention. Any person skilled in the art can make various changes or modifications without departing from the spirit and scope of the invention, and these modifications are also within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims of this application.

Claims

1. A fast amplitude and phase calibration method for a phased array terminal, characterized in that, The method comprises the following steps: Step 1: data preparation step: the PS side queries the corresponding amplitude compensation value and phase compensation value from the pre-stored compensation data table according to the current working frequency and real-time temperature information of the terminal; Step 2: data writing and handshake step: the PS side writes the amplitude compensation value and phase compensation value obtained in step 1 into the dual-port memory inside the PL; the dual-port memory is divided into a main storage area and a backup storage area, which are used to store the main compensation table and the backup compensation table respectively; after completing the data writing to any storage area, the PS side indicates the data validity of the storage area to the PL side by setting the corresponding bit in the write completion flag bit; Step 3: parallel reading and calculation step: the PL side monitors the write completion flag bit in real time, and when it is determined that the flag bit corresponding to the main storage area is valid, the amplitude and phase compensation data of multiple channels are read from the main storage area in parallel, and the read compensation values are operated with the reference compensation values calculated in real time to generate the final frequency and temperature compensation values of each channel; Step 4: chip configuration step: the PL side writes the final compensation values of each channel generated in step 3 into the corresponding beamforming chip through the SPI interface, and completes the amplitude and phase calibration; Step 5: dynamic updating and ping-pong switching step: when the working frequency or environmental temperature changes, the PS side performs the following operations: according to the new frequency and temperature parameters, new compensation values are queried and generated, which are written into the backup storage area, and then the refresh flag is triggered; after detecting that the refresh flag is valid, the PL side controls the role switching of the main storage area and the backup storage area, that is, the backup storage area currently storing new data is used as the new main storage area for subsequent data reading, and the original main storage area is used as the new backup storage area for accepting the next update.

2. The method of claim 1, wherein: In step 1, the amplitude compensation value is given in the form of an absolute value, and the phase compensation value is given in the form of a relative value.

3. The method of claim 1, wherein: In step 2, the write completion flag bit is a 2-bit signal, wherein the first bit corresponds to the write state of the main storage area, and the second bit corresponds to the write state of the backup storage area; before the PS side starts writing data to any storage area, the flag bit corresponding to the storage area is set to a first logic state to indicate that the data is invalid or being written; after the data is completely written, the bit is set to a second logic state to indicate that the data is valid and ready.

4. The method of claim 1, wherein: In step 3, the parallel reading is realized by instantiating multiple parallel memory reading control logics inside the PL, so that the PL can simultaneously initiate reading operations on multiple channel compensation data, thereby reducing the overall reading time of a large amount of data.

5. The method of claim 1, wherein: In step 5, the ping-pong switching mechanism is: when the system is working normally, the PL continuously reads data from the area currently designated as the main storage area for compensation; when the compensation data needs to be updated, the PS side asynchronously writes new data to the area currently designated as the backup storage area and triggers the refresh flag; After the PL detects that the refresh flag is valid after completing the current round of compensation calculation, the storage area role switching is performed, and thereafter all data reading operations will be switched to the new main storage area.

6. A fast amplitude and phase calibration system for implementing the method of any of claims 1-5, characterized by The system comprises: a ZYNQ chip internally integrated with a PS and a PL; a plurality of high-precision temperature sensors distributed throughout the system for real-time acquisition of temperature information of each module of the system; a plurality of beamforming chips connected with the PL side of the ZYNQ chip and communicating through an SPI interface; The temperature sensor sends the collected temperature data to the PS side, and the PS side queries a compensation table according to the temperature and working frequency and writes the compensation value into the dual-port RAM of the PL side; the PL side reads data from the dual-port RAM and calculates, and then configures the beamforming chip through the SPI interface.

7. The system of claim 6, wherein, The ZYNQ chip is internally divided into: the PS side configured to perform a data preparation step, a data writing and handshake step, and a dynamic update triggering operation; wherein the data preparation step includes acquiring temperature and working frequency information and querying a compensation table; the data writing and handshake step includes writing a compensation value into a dual-port RAM and setting a write completion flag; and the dynamic update triggering operation includes triggering a refresh flag when parameters change; the PL side connected with the PS side through a high-speed AXI bus, internally containing the dual-port RAM, and configured to perform PL-related operations in the data writing and handshake step, parallel reading and calculation, chip configuration, and PL-related operations in the dynamic update and ping-pong switching step; wherein the PL-related operations include monitoring flag bits and managing read and write access of the dual-port RAM; the parallel reading and calculation step includes parallel reading data from the RAM and performing operations; the chip configuration step includes configuring the beamforming chip through the SPI interface; and the ping-pong switching step includes managing the role switching of the main and backup storage areas.

8. The system of claim 6 or 7, wherein, In the ZYNQ chip, the PL side hardware acceleration pipeline comprises the following logical modules: a flag bit monitoring and arbitration module connected with the PS side, for real-time monitoring of a write completion flag and a refresh flag written by the PS side, and issuing control instructions to subsequent modules according to the states of the flag bits; a ping-pong table management module connected with the dual-port RAM shared by the flag bit monitoring and arbitration module and the PS side, for responding to update triggering by the PS side, managing the role switching of the main and backup storage areas according to the control instructions, and ensuring that the PL can continuously read current valid data from the main table when the PS writes new data to the backup table; a multi-channel parallel reading and calculation engine connected with the ping-pong table management module, for parallel reading of multiple compensation data from the activated main storage area and real-time compensation value calculation in each processing period; an SPI configuration controller connected with the multi-channel parallel reading and calculation engine, for configuring the final compensation parameters obtained by calculation to the external beamforming chip through the high-speed SPI interface; the PS side as a control and scheduling center is responsible for the following upper-layer management tasks: system environment monitoring, including reading temperature sensor data through an interface and obtaining the current working frequency; Compensation strategy execution, i.e. according to temperature and frequency query compensation parameter table, and prepare to be issued compensation data; Task assignment and synchronization, through the data write into the PL side shared dual-port RAM and set the corresponding write completion flag and refresh flag, to the PL side issued accurate execution instructions.

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