Micro-LED display chip and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor devices, and discloses a Micro-LED display chip and a preparation method thereof. The Micro-LED display chip comprises a substrate, a plurality of LED light-emitting units, a planarization layer and a conductive reflecting wall. The LED light-emitting unit comprises a first doping type semiconductor layer, an active layer and a second doping type semiconductor layer, and at least the first doping type semiconductor layer and the active layer are processed to form an LED mesa. And a channel is formed between the adjacent LED mesas. The planarization layer is located between the LED light-emitting unit and the substrate, and the planarization layer is in bonding connection with the substrate. The planarization layer is filled in the channel and covers the LED mesa. The planarization layer has a groove corresponding to the channel. The conductive reflecting wall is arranged in the groove and surrounds the LED table top. The light-emitting efficiency and the brightness of the LED light-emitting unit on the main light-emitting angle can be improved, and then the light-emitting efficiency and the brightness of the Micro-LED display chip are improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor devices, and particularly relates to a Micro-LED display chip and a preparation method thereof. BACKGROUND

[0002] Micro-LED display technology, i.e., micro light-emitting diode display technology, has advantages of high brightness, high contrast, low power consumption, long service life, and fast response speed.

[0003] At present, wearable devices, virtual reality (VR) / augmented reality (AR) devices, and the like are gradually developing towards ultra-high pixel density and miniaturization, so that the size of the Micro-LED display chip is also continuously reduced. The reduction of the size of the Micro-LED display chip makes it difficult for the side light of the LED light-emitting unit to be guided into the observation viewing angle in front of the chip, resulting in reduced light-emitting efficiency and brightness. SUMMARY

[0004] The present application aims to at least solve one of the technical problems in the related art.

[0005] Therefore, a first aspect of the present application provides a Micro-LED display chip.

[0006] A second aspect of the present application provides a preparation method of a Micro-LED display chip.

[0007] Therefore, a first aspect of the present application provides a Micro-LED display chip.

[0008] In an alternative embodiment, the Micro-LED display chip further comprises: a connecting electrode disposed on the LED mesa and electrically connected to the corresponding first doped semiconductor layer; an electrode layer disposed on the surface of the adjacent region of the second doped semiconductor layer of the adjacent LED light emitting unit and located in the channel, one end of the conductive reflection wall being electrically connected to the electrode layer; the substrate comprises a plurality of electrode contacts and at least one common electrode, a plurality of the electrode contacts being electrically connected to a plurality of the connecting electrodes one by one, and the electrode layer being electrically connected to the common electrode through the conductive reflection wall.

[0009] In an alternative embodiment, the planarization layer is provided with an opening that exposes at least part of the surface of the side of the connecting electrode away from the LED mesa; the Micro-LED display chip further comprises a conductive bump disposed in the opening and electrically connected to the corresponding connecting electrode, one end of the conductive bump away from the connecting electrode being bonded to the corresponding electrode contact.

[0010] In an alternative embodiment, the Micro-LED display chip further comprises: a conductive layer disposed on the surface of the first doped semiconductor layer of the LED mesa and located between the LED mesa and the connecting electrode.

[0011] In an alternative embodiment, the Micro-LED display chip further comprises: a passivation layer disposed on the surface of the LED mesa and the surface of the second doped semiconductor layer between adjacent LED mesas and exposing the surfaces of the corresponding positions of the LED light emitting unit, the connecting electrode and the electrode layer.

[0012] In an alternative embodiment, the Micro-LED display chip further comprises: a microlens formed by etching the second doped semiconductor layer and located on the side of the second doped semiconductor layer away from the LED mesa, a plurality of the microlenses corresponding to a plurality of the LED mesas one by one; when etching the second doped semiconductor layer, the second doped semiconductor layers of adjacent LED light emitting units are arranged separately or integrally.

[0013] In an alternative embodiment, the focal point of the microlens is located at the active layer.

[0014] In an alternative embodiment, in the direction perpendicular to the top surface of the substrate, the microlens covers the corresponding LED mesa and covers the sidewall of the corresponding conductive reflection wall towards the side of the LED mesa.

[0015] In one optional embodiment, the Micro-LED display chip further includes: an undoped material layer disposed on the side of the second doped semiconductor layer facing away from the LED mesa; a microlens formed by etching the undoped material layer and the second doped semiconductor layer, and located on the side of the second doped semiconductor layer facing away from the LED mesa, wherein a plurality of microlenses correspond one-to-one with a plurality of LED mesas; when etching the second doped semiconductor layer, the second doped semiconductor layers of adjacent LED light-emitting units are spaced apart or integrally disposed.

[0016] In one alternative embodiment, the Micro-LED display chip further includes a reflective layer disposed between the conductive reflective wall and the planarization layer.

[0017] According to a second aspect of the embodiments of this application, a method for fabricating a Micro-LED display chip is provided, comprising the following steps: providing a substrate; fabricating an LED light-emitting unit, the LED light-emitting unit comprising a first doped semiconductor layer, an active layer, and a second doped semiconductor layer stacked thereon, at least the first doped semiconductor layer and the active layer being processed to form an LED mesa, a plurality of LED mesa arrays being arranged, and a channel being formed between adjacent LED mesa; forming a planarization layer, the planarization layer filling the channel and covering the LED mesa, the planarization layer having a groove corresponding to the channel; forming a conductive reflective wall, the conductive reflective wall being disposed in the groove and surrounding the LED mesa; connecting the LED light-emitting unit to the substrate, wherein the planarization layer is bonded to the substrate and located between the LED light-emitting unit and the substrate, the plurality of LED light-emitting units being located above the substrate, and the first doped semiconductor layer being closer to the surface of the substrate.

[0018] In one optional embodiment, the step of fabricating an LED light-emitting unit includes: providing a substrate on which an LED epitaxial structure is disposed, the LED epitaxial structure including a first doped semiconductor layer, an active layer and a second doped semiconductor layer stacked together; etching at least the first doped semiconductor layer and the active layer to form a plurality of LED mesa arranged in an array, and forming the channel between adjacent LED mesa to obtain a plurality of LED light-emitting units.

[0019] In one optional embodiment, a current spreading layer is provided on the LED epitaxial structure, and the step of fabricating the LED light-emitting unit further includes: etching the current spreading layer to form a conductive layer, wherein the conductive layer is located on the surface of the first doped semiconductor layer of the LED mesa.

[0020] In an optional embodiment, prior to the step of forming the planarization layer, the method for fabricating the Micro-LED display chip further includes: forming a contact metal layer on the surface of the LED light-emitting unit; processing the contact metal layer to form a connecting electrode and an electrode layer, wherein the connecting electrode is disposed on the LED mesa and electrically connected to the corresponding first doped semiconductor layer; the electrode layer is disposed on the surface of an adjacent region of the second doped semiconductor layer of an adjacent LED light-emitting unit and is located within the channel.

[0021] In one alternative embodiment, the step of forming a planarization layer includes: forming a planarization material layer covering the LED mesa, the connecting electrode, and the electrode layer, and filling the channel; forming the groove in the planarization material layer to obtain the planarization layer, wherein the planarization layer covers the LED mesa, the groove corresponds to the channel, and exposes at least a portion of the surface of the electrode layer on the side opposite to the second doped semiconductor layer; the step of forming the planarization layer further includes: while forming the groove in the planarization material layer, forming an opening in the planarization material layer, the opening exposing at least a portion of the surface of the connecting electrode on the side opposite to the LED mesa.

[0022] In one optional embodiment, the step of forming the conductive reflective wall includes: filling the groove with metal to form the conductive reflective wall; the method for fabricating the Micro-LED display chip further includes: while forming the conductive reflective wall, filling the opening with metal to form conductive bumps.

[0023] In one optional embodiment, the substrate includes a plurality of electrode contacts and at least one common electrode. The step of connecting the LED light-emitting unit to the substrate includes: the planarization layer is bonded to the substrate, the plurality of conductive bumps are bonded to and electrically connected to the plurality of electrode contacts in a one-to-one correspondence, and the conductive reflective wall is bonded to and electrically connected to the common electrode.

[0024] In one alternative embodiment, prior to the step of forming the conductive reflective wall, the method for fabricating the Micro-LED display chip further includes: forming a reflective layer that at least covers the inner surface of the groove.

[0025] In an optional embodiment, the method for fabricating a Micro-LED display chip further includes: etching the side of the second doped semiconductor layer away from the LED mesa to form a microlens, wherein a plurality of microlenses correspond one-to-one with a plurality of LED mesas; and when etching the second doped semiconductor layer, the second doped semiconductor layers of adjacent LED light-emitting units are spaced apart or integrally formed.

[0026] In one optional embodiment, the step of etching the side of the second doped semiconductor layer away from the LED mesa to form a microlens includes: forming an array of photoresist pillars on the side of the second doped semiconductor layer away from the LED mesa; forming a photoresist lens from the photoresist pillars; and transferring the morphology of the photoresist lens to the second doped semiconductor layer to obtain the microlens.

[0027] The Micro-LED display chip and its fabrication method provided in this application can achieve at least the following technical effects: In this application, the LED light-emitting unit includes a first doped semiconductor layer, an active layer, and a second doped semiconductor layer stacked together. The first doped semiconductor layer and the active layer are processed to form an LED mesa, that is, forming an independent LED mesa, simplifying the processing technology and improving the uniformity of current injection into the active layer. Compared to the second doped semiconductor layer, the first doped semiconductor layer is closer to the surface of the substrate. A channel is formed between adjacent LED mesas. A planarization layer fills the channel and covers the LED mesa. The planarization layer has grooves corresponding to the channels. Conductive reflective walls are disposed in the grooves and surround the LED mesas. That is, a reflector cup structure is formed around the LED mesa, which can effectively collect the light emitted from the sidewalls of the LED mesa, so that the light emitted from the sidewalls is guided into the viewing angle directly in front of the chip, improving the luminous efficiency and brightness of the LED light-emitting unit at the main emission angle, thereby improving the luminous efficiency and brightness of the Micro-LED display chip. The planarization layer is also located between the LED light-emitting unit and the substrate, and is bonded to the substrate, which helps to achieve hybrid bonding, thereby simplifying the fabrication process and improving the integration and yield of Micro-LED display chips.

[0028] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0029] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of the structure of a Micro-LED display chip provided in an embodiment of this disclosure; Figure 2 A partial structural diagram of the fabrication process of the Micro-LED display chip provided in this embodiment of the disclosure. Figure 1 ; Figure 3 A partial structural diagram of the fabrication process of the Micro-LED display chip provided in this embodiment of the disclosure.Figure 2 ; Figure 4 A partial structural diagram of the fabrication process of the Micro-LED display chip provided in this embodiment of the disclosure. Figure 3 ; Figure 5 A partial structural diagram of the fabrication process of the Micro-LED display chip provided in this embodiment of the disclosure. Figure 4 ; Figure 6 A partial structural diagram of the fabrication process of the Micro-LED display chip provided in this embodiment of the disclosure. Figure 5 ; Figure 7 A partial structural diagram of the fabrication process of the Micro-LED display chip provided in this embodiment of the disclosure. Figure 6 ; Figure 8 A partial structural diagram of the fabrication process of the Micro-LED display chip provided in this embodiment of the disclosure. Figure 7 ; Figure 9 A partial structural diagram of the fabrication process of the Micro-LED display chip provided in this embodiment of the disclosure. Figure 8 ; Figure 10 A partial structural diagram of the fabrication process of the Micro-LED display chip provided in this embodiment of the disclosure. Figure 9 ; Figure 11 A partial structural diagram of the fabrication process of the Micro-LED display chip provided in this embodiment of the disclosure. Figure 10 ; Figure 12 A schematic diagram showing the arrangement of the LED tabletop and the conductive reflective wall provided in an embodiment of this disclosure; Figure 13 A flowchart illustrating a method for fabricating a Micro-LED display chip according to an embodiment of this disclosure; Figure 14 A flowchart illustrating a method for fabricating a Micro-LED display chip according to another embodiment of this disclosure.

[0030] The reference numerals in the attached figures are as follows: 1: Micro-LED display chip; 10: Substrate; 11: Electrode contact; 12: Common electrode; 20: LED light-emitting unit; 21: First doped semiconductor layer; 22: Active layer; 23: Second doped semiconductor layer; 24: LED mesa; 25: Channel; 30: Planarization layer; 31: Groove; 32: Opening; 40: Conductive reflective wall; 41: Reflective layer; 50: Connecting electrode; 51: Electrode layer; 52: Conductive bump; 53: Conductive layer; 60: Microlens; 70: Substrate; 71: Current spreading layer; 72: Photoresist pillar; 73: Photoresist lens; 74: LED epitaxial structure. Detailed Implementation

[0031] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0032] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0033] In this disclosure, the terms "upper," "lower," "inner," "middle," "outer," "front," and "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for better description of the embodiments of this disclosure and their implementations, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to require them to be constructed and operated in a specific orientation. Furthermore, some of the aforementioned terms may be used to indicate other meanings besides orientation or positional relationship; for example, the term "upper" may in some cases indicate a dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in the embodiments of this disclosure according to the specific circumstances.

[0034] Furthermore, the terms "set up," "connect," and "fix" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0035] Unless otherwise stated, the term "multiple" means two or more.

[0036] It should be noted that, unless otherwise specified, the embodiments and features described in the present disclosure can be combined with each other.

[0037] It should be noted that, as used in the embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having a certain thickness. A layer may extend over the entire lower or upper structure, or may have a extent smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a conical surface.

[0038] Combination Figures 1 to 12 As shown, this disclosure provides a Micro-LED display chip 1, including a substrate 10, a plurality of LED light-emitting units 20 located above the substrate 10, a planarization layer 30, and a conductive reflective wall 40. Each LED light-emitting unit 20 includes a first doped semiconductor layer 21, an active layer 22, and a second doped semiconductor layer 23 stacked on top of each other, with the first doped semiconductor layer 21 closer to the surface of the substrate 10. At least the first doped semiconductor layer 21 and the active layer 22 are processed to form LED mesa 24, and the plurality of LED mesa 24 are arranged in an array, with channels 25 formed between adjacent LED mesa 24. The planarization layer 30 is located between the LED light-emitting units 20 and the substrate 10, and is bonded to the substrate 10. The planarization layer 30 fills the channels 25 and covers the LED mesa 24. The planarization layer 30 has grooves 31 corresponding to the channels 25. The conductive reflective wall 40 is disposed in the grooves 31 and surrounds the LED mesa 24.

[0039] In this context, substrate 10 refers to the material on which subsequent material layers are added. Substrate 10 itself may be patterned. The material added to the top of substrate 10 may be patterned or may remain unpatterned. Furthermore, substrate 10 may comprise a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, and indium phosphide. Alternatively, substrate 10 may be made of a non-conductive material, such as glass, plastic, or sapphire wafer. Further alternatively, substrate 10 may have semiconductor devices or circuits formed therein.

[0040] Multiple LED light-emitting units 20 are disposed above the substrate 10. Each LED light-emitting unit 20 includes a first doped semiconductor layer 21, an active layer 22, and a second doped semiconductor layer 23 stacked together. At least the first doped semiconductor layer 21 and the active layer 22 are processed to form an LED mesa 24. Specifically, the LED mesa 24 can be formed by processing the first doped semiconductor layer 21 and the active layer 22, or it can be formed by processing the first doped semiconductor layer 21, the active layer 22, and a portion of the second doped semiconductor layer 23 to form an independent LED mesa 24, simplifying the processing technology. The first doped semiconductor layer 21 can be a p-type semiconductor layer, for example, p-type gallium nitride (GaN). The second doped semiconductor layer 23 can be an n-type semiconductor layer, for example, n-type gallium nitride (GaN). The active layer 22 may include an indium gallium nitride quantum well (i.e., an InGaN quantum well) for enabling the LED light-emitting unit 20 to emit light.

[0041] Compared to the second doped semiconductor layer 23, the first doped semiconductor layer 21 is closer to the surface of the substrate 10. Multiple LED mesa 24 are arranged in an array, that is, multiple LED mesa 24 of multiple LED light-emitting units 20 are arranged in an array. A channel 25 is formed between adjacent LED mesa 24, that is, a channel 25 is formed between adjacent LED mesa 24 of LED light-emitting units 20. Figure 1 , Figure 7 and Figure 9Arrow group A in the diagram illustrates the light path through which the conductive reflector 40 reflects the light emitted from the sidewalls of the LED mesa 24. The planarization layer 30 fills the channel 25 and covers the LED mesa 24. The planarization layer 30 has grooves 31 corresponding to the channel 25. The conductive reflector 40 is disposed in the grooves 31 and surrounds the LED mesa 24. This forms a reflector cup structure around the LED mesa 24, effectively collecting the light emitted from the sidewalls of the LED mesa 24. This guides the sidewall light to the viewing angle directly in front of the chip, improving the luminous efficiency and brightness of the LED light-emitting unit 20 at the main emission angle, thereby enhancing the luminous efficiency and brightness of the Micro-LED display chip 1. The planarization layer 30 is also located between the LED light-emitting unit 20 and the substrate 10 and is bonded to the substrate 10. Therefore, the planarization layer 30 can serve as an interface layer for hybrid bonding, simplifying the fabrication process and improving the integration and yield of the Micro-LED display chip 1. The planarization layer 30 also provides electrical isolation between the LED surfaces 24 and protects the LED surfaces 24. The size of the LED surfaces 24 is not limited; for example, Figure 1 The L in the figure is used to indicate the width of the LED tabletop 24, and L is less than 5μm.

[0042] The planarization layer 30 has grooves 31 corresponding to the channels 25. Specifically, the grooves 31 extend along the extension direction of the channels 25. For example, by extending the channels 25, channels 25 are formed around the LED platform 24, corresponding to... Figure 12 As shown, the LED platform 24 has grooves 31 around its perimeter, so that the conductive reflective wall 40 fills the grooves 31 to form a structure surrounding the LED platform 24.

[0043] The planarization layer 30 is made of materials such as silicon dioxide or silicon nitride.

[0044] The conductive reflective wall 40 is made of materials such as copper (Cu) or tungsten (W).

[0045] Combination Figures 4 to 11 As shown, in some embodiments, the Micro-LED display chip 1 further includes a connecting electrode 50 and an electrode layer 51. The connecting electrode 50 is disposed on the LED mesa 24 and is electrically connected to the corresponding first doped semiconductor layer 21. The electrode layer 51 is disposed on the surface of an adjacent region of the second doped semiconductor layer 23 of an adjacent LED light-emitting unit 20, and is located within a channel 25. One end of the conductive reflective wall 40 is electrically connected to the electrode layer 51. The substrate 10 includes a plurality of electrode contacts 11 and at least one common electrode 12. The plurality of electrode contacts 11 are electrically connected to the plurality of connecting electrodes 50 in a one-to-one correspondence, and the electrode layer 51 is electrically connected to the common electrode 12 through the conductive reflective wall 40.

[0046] Specifically, the connecting electrode 50 is disposed on the side of the LED mesa 24 facing the substrate 10, and the connecting electrode 50 is electrically connected to the first doped semiconductor layer 21 of the LED mesa 24. The material of the connecting electrode 50 includes a conductive metal, such as gold.

[0047] An electrode layer 51 is disposed on the surface of an adjacent region of the second doped semiconductor layer 23 of an adjacent LED light-emitting unit 20. That is, when the second doped semiconductor layers 23 of adjacent LED light-emitting units 20 are a continuous, integral structure, the electrode layer 51 is disposed on a portion of the surface of the second doped semiconductor layer 23 and located within the channel 25. The integrally disposed second doped semiconductor layer 23 improves the uniformity of current injection into the active layer 22. When the second doped semiconductor layers 23 of adjacent LED light-emitting units 20 are spaced apart, the electrode layer 51 is located on the surface of an adjacent region of the adjacent second doped semiconductor layer 23 and within the channel 25. Electrical connection between the second doped semiconductor layers 23 of adjacent LED light-emitting units 20 can be achieved through the electrode layer 51. The material of the electrode layer 51 includes a conductive metal, such as gold.

[0048] Multiple electrode contacts 11 are electrically connected to multiple connecting electrodes 50 in a one-to-one correspondence. The electrode layer 51 is electrically connected to the common electrode 12 through the conductive reflective wall 40, so that each LED light-emitting unit 20 can be driven individually, that is, the active layer 22 of each LED light-emitting unit 20 can emit light.

[0049] For example, electrode contact 11 can be an anode metal contact. The first doped semiconductor layer 21 can be a p-type semiconductor layer, and the second doped semiconductor layer 23 can be an n-type semiconductor layer. The first doped semiconductor layer 21 of each LED light-emitting unit 20 is electrically connected to an electrode contact 11 through a connecting electrode 50. The second doped semiconductor layers 23 of multiple LED light-emitting units 20 can be electrically connected to a common electrode (GND) 12 through electrode layer 51 and conductive reflector 40, thereby forming a common cathode structure so that each LED light-emitting unit 20 can be driven individually.

[0050] In this example, the substrate 10 may be provided with a circuit layer including complementary metal oxide semiconductor (CMOS) devices or thin film field effect transistor (TFT) devices, which can constitute a driving circuit.

[0051] Combination Figures 5 to 7As shown, in some embodiments, the planarization layer 30 is provided with an opening 32, which exposes at least a portion of the surface of the connecting electrode 50 on the side opposite to the LED mesa 24. The Micro-LED display chip 1 also includes a conductive bump 52 disposed within the opening 32. The conductive bump 52 is electrically connected to the corresponding connecting electrode 50, and the end of the conductive bump 52 opposite to the connecting electrode 50 is bonded to the corresponding electrode contact 11.

[0052] At least a portion of the surface of the connecting electrode 50 facing away from the LED mesa 24 is exposed through the opening 32. Conductive bumps 52 are disposed within the opening 32 and are electrically connected to the corresponding connecting electrode 50 to achieve hybrid bonding. Specifically, while the planarization layer 30 is bonded to the substrate 10, the end of the conductive bump 52 facing away from the connecting electrode 50 is bonded to the corresponding electrode contact 11, and the conductive reflective wall 40 is bonded to the corresponding common electrode 12, achieving hybrid bonding. This simplifies the fabrication process, improves the integration and yield of the Micro-LED display chip 1, and helps to further reduce the size of the Micro-LED display chip 1.

[0053] The conductive bumps 52 are made of materials such as copper (Cu) or tungsten (W).

[0054] Combination Figures 3 to 11 As shown, in some embodiments, the Micro-LED display chip 1 further includes a conductive layer 53, which is disposed on the surface of the first doped semiconductor layer 21 of the LED mesa 24. The conductive layer 53 is also located between the LED mesa 24 and the connecting electrode 50. The conductive layer 53 enables electrical connection between the connecting electrode 50 and the corresponding first doped semiconductor layer 21. The material of the conductive layer 53 includes nickel-gold (NiAu) or indium tin oxide (ITO), etc.

[0055] In some embodiments, the Micro-LED display chip 1 further includes a passivation layer disposed on the surface of the LED mesa 24 and the surface of the second doped semiconductor layer 23 between adjacent LED mesa 24, and the passivation layer exposes the surfaces of the LED light-emitting units 20 corresponding to the positions of the connecting electrodes 50 and the electrode layer 51.

[0056] A passivation layer is disposed on the surface of the LED mesa 24, and also on the surface of the second doped semiconductor layer 23 between adjacent LED mesa 24, to achieve electrical isolation and improve insulation performance and reliability. The passivation layer exposes the surfaces of the LED light-emitting unit 20 corresponding to the connecting electrode 50 and the electrode layer 51, providing areas for the subsequent formation of the connecting electrode 50 and the electrode layer 51, which helps to achieve electrical connection between the connecting electrode 50 and the conductive layer 53, and electrical connection between the electrode layer 51 and the second doped semiconductor layer 23.

[0057] The passivation layer is made of materials such as silicon dioxide or silicon nitride.

[0058] For example, during processing, a passivation layer is formed on the surface of the LED mesa 24 having the conductive layer 53, extending to the surface of the second doped semiconductor layer 23 between adjacent LED mesa 24. The passivation layer is etched to expose at least a portion of the surface of the conductive layer 53 and the surface of the second doped semiconductor layer 23 corresponding to the electrode layer 51. Subsequently, a connection electrode 50 can be formed in the exposed surface region of the conductive layer 53, and an electrode layer 51 can be formed in the exposed surface region of the second doped semiconductor layer 23. It is understood that the processing order of the passivation layer, conductive layer 53, connection electrode 50, and electrode layer 51 is not limited to the processing order shown in this example.

[0059] A passivation layer can be formed using atomic layer deposition (ALD) technology.

[0060] Combination Figure 1 As shown, in some embodiments, the Micro-LED display chip 1 further includes a microlens 60, which is formed by etching a second doped semiconductor layer 23 and located on the side of the second doped semiconductor layer 23 facing away from the LED mesa 24. Multiple microlenses 60 correspond one-to-one with multiple LED mesa 24s. During etching of the second doped semiconductor layer 23, the second doped semiconductor layers 23 of adjacent LED light-emitting units 20 are spaced apart or integrally formed.

[0061] The microlens 60 is formed by etching the second doped semiconductor layer 23. That is, the microlens 60 and the second doped semiconductor layer 23 are made of the same material, such as GaN. This allows the microlens 60 of this embodiment to have a higher refractive index compared to conventional silicone or inorganic oxide lenses; for example, the refractive index of GaN can be 2.45. The microlens 60 with its higher refractive index can effectively collimate the divergent light of the LED light-emitting unit 20 and reduce internal total internal reflection, thereby improving the collimation of the LED light-emitting unit 20 and its brightness within the main emission angle. Furthermore, the fact that the microlens 60 is formed by etching the second doped semiconductor layer 23 simplifies the fabrication process and improves yield.

[0062] The microlens 60 is located on the side of the second doped semiconductor layer 23 away from the LED mesa 24. Multiple microlenses 60 correspond one-to-one with multiple LED mesa 24. That is to say, each microlens 60 improves the collimation of each LED light-emitting unit 20 and the brightness within the main emission angle, thereby improving the luminous efficiency and brightness of the Micro-LED display chip 1.

[0063] When etching the second doped semiconductor layer 23, the second doped semiconductor layers 23 of adjacent LED light-emitting units 20 are spaced apart, which helps to further reduce the spacing between adjacent LED light-emitting units 20, thereby increasing the integration density. When etching the second doped semiconductor layer 23, the second doped semiconductor layers 23 of adjacent LED light-emitting units 20 are integrally formed, which can improve the uniformity of current injection and further simplify the processing technology, thereby increasing the yield.

[0064] In some embodiments, the focal point of the microlens 60 is located at the active layer 22.

[0065] With the focus of the microlens 60 located on the active layer 22, the omnidirectional light emitted by the active layer 22 can be collected and extracted efficiently and converted into a collimated beam, thereby improving brightness and light energy utilization, reducing optical crosstalk between pixels, and thus improving the luminous efficiency and brightness of the LED light-emitting unit 20 at the main emission angle.

[0066] like Figure 1 As shown, arrow group B indicates that the microlens 60 collimates the light emitted from the LED mesa 24. The microlens 60, with its focal point on the active layer 22, works in conjunction with the conductive reflective wall 40 surrounding the LED mesa 24. Specifically, the conductive reflective wall 40 reflects the light emitted from the sidewalls of the LED mesa 24 and guides it to the top. The microlens 60, with its focal point on the active layer 22, efficiently collimates the reflected light with the light emitted from the LED mesa 24, effectively improving the luminous efficiency and brightness of the LED light-emitting unit 20 at the main emission angle.

[0067] Combination Figure 1 As shown, in some embodiments, in a direction perpendicular to the top surface of the substrate 10, the microlens 60 covers the corresponding LED mesa 24 and the sidewall of the corresponding conductive reflective wall 40 facing the LED mesa 24.

[0068] like Figure 1 As shown, Figure 1 The top-to-bottom direction in the diagram can be used to indicate a direction perpendicular to the top surface of the substrate 10. The microlens 60 covers the corresponding LED mesa 24; that is, the area where each microlens 60 is located covers the LED mesa 24 directly below it. The microlens 60 covers the sidewall of the corresponding conductive reflective wall 40 facing the LED mesa 24; that is, for the LED mesa 24 directly below the microlens 60, the area where the microlens 60 is located also covers the sidewall of the conductive reflective wall 40 surrounding the LED mesa 24 facing that LED mesa 24. This allows light emitted through the conductive reflective wall 40 to effectively enter the optical range of the microlens 60, achieving efficient coupling of the optical path, reducing light loss and crosstalk, and thus improving the chip's light extraction efficiency and light output quality.

[0069] In some embodiments, the Micro-LED display chip 1 further includes an undoped material layer and microlenses 60. The undoped material layer is disposed on the side of the second doped semiconductor layer 23 facing away from the LED mesa 24. The microlenses 60 are formed by etching the undoped material layer and the second doped semiconductor layer 23, and are located on the side of the second doped semiconductor layer 23 facing away from the LED mesa 24. A plurality of microlenses 60 correspond one-to-one with a plurality of LED mesa 24s. When etching the second doped semiconductor layer 23, the second doped semiconductor layers 23 of adjacent LED light-emitting units 20 are spaced apart or integrally disposed.

[0070] An undoped material layer is disposed on the side of the second doped semiconductor layer 23 facing away from the LED mesa 24. The microlens 60 is obtained by etching the undoped material layer and the second doped semiconductor layer 23, which helps to obtain a microlens 60 with the target height and other dimensional requirements. This provides a material layer for the fabrication of the microlens 60 and improves fabrication efficiency. Other technical effects of the microlens 60 are described in the foregoing embodiments of this application and will not be repeated here.

[0071] The undoped material layer includes GaN.

[0072] Combination Figure 1 as well as Figures 6 to 11 As shown, in some embodiments, the Micro-LED display chip 1 further includes a reflective layer 41 disposed between the conductive reflective wall 40 and the planarization layer 30.

[0073] Specifically, a reflective layer 41 is formed on the sidewall of the groove 31, so that the reflective layer 41 is disposed between the conductive reflective wall 40 and the planarization layer 30, for efficient reflection of photons, so that the light emitted from the sidewall is guided into the viewing angle directly in front of the chip, thereby improving the luminous efficiency and brightness of the LED light-emitting unit 20 at the main emission angle. The material of the reflective layer 41 includes chromium-aluminum alloy (CrAl) or silver (Ag), etc.

[0074] In one optional embodiment, the Micro-LED display chip 1 further includes a barrier layer formed on the sidewall of the recess 31, and a reflective layer 41 formed on the surface of the barrier layer. That is, the barrier layer is disposed between the planarization layer 30 and the reflective layer 41 to improve the stability of the interface between the planarization layer 30 and the reflective layer 41. The barrier layer also protects the reflective layer 41, improving its reliability. The material of the barrier layer includes tantalum nitride (TaN), tantalum (Ta), or cobalt (Co), etc.

[0075] Combination Figure 13 As shown in the embodiments of this disclosure, a method for fabricating a Micro-LED display chip is also provided, comprising the following steps: S1301. Provide substrate.

[0076] The substrate provides the structural basis and the foundation for hybrid bonding.

[0077] S1302. Prepare an LED light-emitting unit. The LED light-emitting unit includes a first doped semiconductor layer, an active layer, and a second doped semiconductor layer stacked together. At least the first doped semiconductor layer and the active layer are processed to form LED mesa. Multiple LED mesa are arranged in an array, and a channel is formed between adjacent LED mesa.

[0078] LED light-emitting units 20 are fabricated to form a core light-emitting structure. LED mesa 24 are formed by processing the first doped semiconductor layer 21 and the active layer 22. Multiple LED mesa 24 are arranged in an array, and channels 25 are formed between adjacent LED mesa 24 to provide space for the subsequent formation of the planarization layer 30.

[0079] In some embodiments, the steps for fabricating the LED light-emitting unit 20 include: as follows Figure 2 As shown, a substrate 70 is provided, on which an LED epitaxial structure 74 is disposed. The LED epitaxial structure 74 includes a first doped semiconductor layer 21, an active layer 22, and a second doped semiconductor layer 23 stacked together. Figure 3 As shown, at least the first doped semiconductor layer 21 and the active layer 22 are etched to form a plurality of LED mesa 24 arranged in an array, and a channel 25 is formed between adjacent LED mesa 24 to obtain a plurality of LED light-emitting units 20.

[0080] Support is provided by substrate 70. An LED epitaxial structure 74 is grown on substrate 70. The LED epitaxial structure 74 includes a first doped semiconductor layer 21, an active layer 22, and a second doped semiconductor layer 23 stacked together, providing a functional structure for forming LED light-emitting units 20. By etching the first doped semiconductor layer 21 and the active layer 22, multiple LED mesas 24 arranged in an array are formed, and channels 25 are formed between adjacent LED mesas 24 to obtain multiple LED light-emitting units 20.

[0081] The substrate 70 is made of materials such as silicon or sapphire.

[0082] The LED epitaxial structure 74 includes a red LED epitaxial structure 74, a green LED epitaxial structure 74, or a blue LED epitaxial structure 74.

[0083] The specific method of growing the LED epitaxial structure 74 on the substrate 70 is not limited. For example, a buffer layer may be grown on the substrate 70, and the material of the buffer layer may include GaN. An undoped material layer may be grown on the buffer layer, and the material of the undoped material layer may include GaN. A second doped semiconductor layer 23 may be grown on the undoped material layer. An active layer 22 may be grown on the second doped semiconductor layer 23. A first doped semiconductor layer 21 may be grown on the active layer 22.

[0084] In some embodiments, such as Figure 2 As shown, a current spreading layer 71 is disposed on the LED epitaxial structure 74, and the steps for fabricating the LED light-emitting unit 20 further include: Figure 3 As shown, the etching current extension layer 71 forms a conductive layer 53, which is located on the surface of the first doped semiconductor layer 21 of the LED mesa 24.

[0085] A current spreading layer 71 is grown on the side of the LED epitaxial structure 74 opposite to the substrate 70. The material of the current spreading layer 71 includes nickel gold (NiAu) or indium tin oxide (ITO). The current spreading layer 71 is etched to form a conductive layer 53, so that the conductive layer 53 is located on the surface of the first doped semiconductor layer 21 of the LED mesa 24, so that the first doped semiconductor layer 21 can be connected to the corresponding connection electrode 50 through the conductive layer 53.

[0086] For example, the overall structure of the substrate 70, the LED epitaxial structure 74, and the current spreading layer 71 is etched, such as... Figure 2 and Figure 3 As shown, the current spreading layer 71 and the first doped semiconductor layer 21, active layer 22 and part of the second doped semiconductor layer 23 of the LED epitaxial structure 74 are specifically etched to form a plurality of LED mesa 24 arranged in an array in the first doped semiconductor layer 21, active layer 22 and part of the second doped semiconductor layer 23, and a conductive layer 53 is formed on the surface of the LED mesa 24 away from the substrate 70.

[0087] S1303. A planarization layer is formed, which fills the channel and covers the LED platform. The planarization layer has grooves corresponding to the channel.

[0088] By forming a planarization layer 30, which fills the channel 25 and covers the LED mesa 24, the planarization layer 30 protects the LED mesa 24 and facilitates bonding between the planarization layer 30 and the substrate 10. The planarization layer 30 has grooves 31 corresponding to the channel 25, providing space for forming the conductive reflective wall 40.

[0089] In some embodiments, prior to the step of forming the planarization layer 30, the fabrication method of the Micro-LED display chip 1 further includes: forming a contact metal layer on the surface of the LED light-emitting unit 20. For example... Figure 4 As shown, a contact metal layer is processed to form a connecting electrode 50 and an electrode layer 51. The connecting electrode 50 is disposed on the LED mesa 24 and electrically connected to the corresponding first doped semiconductor layer 21. The electrode layer 51 is disposed on the surface of an adjacent region of the second doped semiconductor layer 23 of the adjacent LED light-emitting unit 20 and is located within the channel 25.

[0090] Specifically, before the planarization layer 30 is formed, the basic structure consists of a substrate 70, an LED epitaxial structure 74 grown on the substrate 70, and a current spreading layer 71. At least the first doped semiconductor layer 21 and the active layer 22 are etched to form a plurality of LED mesa 24 arranged in an array. A conductive layer 53 is formed on the surface of each LED mesa 24 facing away from the substrate 70. A contact metal layer is grown on the surface of this basic structure. The material of the contact metal layer includes a conductive metal, such as gold. The contact metal layer is etched to form a connection between the electrode 50 and the electrode layer 51, wherein, for example... Figure 4 As shown, the connecting electrode 50 is located on the conductive layer 53, so that the connecting electrode 50 is electrically connected to the corresponding first doped semiconductor layer 21 through the conductive layer 53. The electrode layer 51 is located on the surface of the adjacent region of the second doped semiconductor layer 23 of the adjacent LED light-emitting unit 20, and is located in the channel 25. The electrode layer 51 is electrically connected to the second doped semiconductor layer 23.

[0091] In some embodiments, the step of forming the planarization layer 30 includes: as Figure 5 As shown, a planarization material layer is formed, covering the LED mesa 24, the connecting electrode 50, and the electrode layer 51, and filling the channel 25. A groove 31 is formed in the planarization material layer to obtain a planarization layer 30, wherein the planarization layer 30 covers the LED mesa 24, the groove 31 corresponds to the channel 25, and exposes at least a portion of the surface of the electrode layer 51 on the side opposite to the second doped semiconductor layer 23. The step of forming the planarization layer 30 further includes: while forming the groove 31 in the planarization material layer, forming an opening 32 in the planarization material layer, the opening 32 exposing at least a portion of the surface of the connecting electrode 50 on the side opposite to the LED mesa 24.

[0092] A planarization material layer is formed, the material of which includes silicon dioxide or silicon nitride. The planarization material layer covers the LED mesa 24, the connecting electrode 50, and the electrode layer 51, and fills the channel 25. The planarization material layer is etched to create openings, forming grooves 31 and openings 32, to obtain a planarization layer 30 with grooves 31 and openings 32. The grooves 31 correspond to the channels 25; that is, the grooves 31 are formed within the channels 25, exposing at least a portion of the surface of the electrode layer 51 facing away from the second doped semiconductor layer 23, so that the electrode layer 51 can be smoothly electrically connected to the conductive reflector wall 40 during its formation. The openings 32 expose at least a portion of the surface of the connecting electrode 50 facing away from the LED mesa 24, so that the connecting electrode 50 can be smoothly electrically connected to the conductive bump 52 during its formation.

[0093] A flat material layer can be formed using plasma-enhanced chemical vapor deposition (PECVD).

[0094] S1304. A conductive reflective wall is formed, which is set in the groove and surrounds the LED platform.

[0095] like Figure 7 As shown, the conductive reflective wall 40 is formed in the groove 31 and surrounds the LED platform 24 to reflect the light emitted from the side wall of the LED platform 24 and improve the light emission efficiency.

[0096] In some embodiments, prior to the step of forming the conductive reflective wall 40, the fabrication method of the Micro-LED display chip 1 further includes: Figure 6 As shown, a reflective layer 41 is formed, which at least covers the inner surface of the groove 31.

[0097] Prior to the step of forming the conductive reflective wall 40, a reflective layer 41 is formed on the planarization layer 30 having grooves 31 and openings 32. The reflective layer 41 can cover the inner surface of the grooves 31 and the inner surface of the openings 32. The reflective layer 41 can be formed using a metal sputtering process.

[0098] In actual processing, tantalum nitride, tantalum, or cobalt can be deposited on the inner surface of the groove 31 and the inner surface of the opening 32 to form a barrier layer. Then, chromium-aluminum alloy or silver can be sputtered on the surface of the barrier layer to form a reflective layer 41.

[0099] In some embodiments, the step of forming the conductive reflective wall 40 includes: Figure 7 As shown, metal is filled in the groove 31 to form a conductive reflective wall 40. The fabrication method of the Micro-LED display chip 1 further includes: while forming the conductive reflective wall 40, metal is filled in the opening 32 to form a conductive bump 52.

[0100] Specifically, metal can be electroplated into the groove 31 and opening 32 containing the reflective layer 41, and then polished to form a conductive reflective wall 40 in the groove 31 and conductive bumps 52 in the opening 32. The metal filled into the groove 31 and opening 32 can be copper or tungsten, etc.

[0101] S1305. Connect the LED light-emitting unit to the substrate, wherein the planarization layer is bonded to the substrate and located between the LED light-emitting unit and the substrate, the plurality of LED light-emitting units are located above the substrate, and the first doped semiconductor layer is closer to the surface of the substrate.

[0102] The planarization layer 30 is located not only in the channel 25 but also on a portion of the surface of the LED light-emitting unit 20 facing the substrate 10. It is bonded to the substrate 10 via the planarization layer 30. Simultaneously, multiple conductive bumps 52 are bonded and electrically connected to multiple electrode contacts 11 in a one-to-one correspondence, and the conductive reflective wall 40 is bonded and electrically connected to the common electrode 12, achieving hybrid bonding and positioning the multiple LED light-emitting units 20 above the substrate 10. Furthermore, compared to the second doped semiconductor layer 23, the first doped semiconductor layer 21 is closer to the surface of the substrate 10.

[0103] In some embodiments, the substrate 10 includes a plurality of electrode contacts 11 and at least one common electrode 12, and the step of connecting the LED light-emitting unit 20 to the substrate 10 includes: Figure 9 The planarization layer 30 is bonded to the substrate 10, the multiple conductive bumps 52 are bonded to and electrically connected to the multiple electrode contacts 11 in a one-to-one correspondence, and the conductive reflective wall 40 is bonded to and electrically connected to the common electrode 12 in a corresponding manner.

[0104] By bonding the planarization layer 30 to the substrate 10, multiple conductive bumps 52 are bonded to and electrically connected to multiple electrode contacts 11 in a one-to-one correspondence, and the conductive reflective wall 40 is bonded to and electrically connected to the common electrode 12, thus achieving hybrid bonding, simplifying the overall fabrication process, and improving yield.

[0105] Combination Figure 1 , Figure 10 and Figure 11 As shown, in some embodiments, the fabrication method of the Micro-LED display chip 1 further includes: etching the side of the second doped semiconductor layer 23 away from the LED mesa 24 to form a microlens 60, wherein multiple microlenses 60 correspond one-to-one with multiple LED mesa 24. When etching the second doped semiconductor layer 23, the second doped semiconductor layers 23 of adjacent LED light-emitting units 20 are spaced apart or integrally formed.

[0106] Specifically, in combination Figure 1 as well as Figures 8 to 11As shown, after the LED light-emitting unit 20 is connected to the substrate 10, the substrate 70 is removed to expose the second doped semiconductor layer 23. The side of the second doped semiconductor layer 23 facing away from the LED mesa 24 is etched to form a microlens 60, and multiple microlenses (MLAs) 60 are arranged in a one-to-one correspondence with multiple LED mesa 24, that is, multiple microlenses 60 are located above multiple LED mesa 24 in a one-to-one correspondence.

[0107] In some embodiments, the step of etching the side of the second doped semiconductor layer 23 away from the LED mesa 24 to form the microlens 60 includes: combining Figure 10 As shown, an array of photoresist pillars 72 are formed on the side of the second doped semiconductor layer 23 facing away from the LED mesa 24. Figure 11 As shown, the photoresist pillar 72 is formed into a photoresist lens 73. Combined with... Figure 1 As shown, the morphology of the photoresist lens 73 is transferred to the second doped semiconductor layer 23 to obtain the microlens 60.

[0108] Specifically, photoresist material is spin-coated on the side of the second doped semiconductor layer 23 facing away from the LED mesa 24, and an array of photoresist pillars 72 are formed through exposure and development, wherein each photoresist pillar 72 corresponds one-to-one with the LED mesa 24. Heating causes the photoresist to reflow, transforming the photoresist pillars 72 into a roughly hemispherical shape, resulting in a photoresist lens 73 in the shape of a microlens 60. The morphology of the photoresist lens 73 can be transferred to the second doped semiconductor layer 23 by dry etching to obtain the microlens 60. This process is simple, has high processing precision, and uses the same material for both the microlens 60 and the second doped semiconductor layer 23, resulting in a higher refractive index. This effectively collimates the divergent light of the LED light-emitting unit 20, reduces internal total internal reflection, and improves the collimation of the Micro-LED display chip 1 and its brightness within the main emission angle. The specific type of photoresist material is not limited, as long as it achieves the above functions. The size of the microlens 60 is not limited; for example, Figure 1 The letter H is used to indicate the thickness of the microlens 60, where H is less than 10 μm.

[0109] Combination Figures 1 to 11 as well as Figure 14 As shown in the embodiments of this disclosure, a method for fabricating a Micro-LED display chip is also provided, comprising the following steps: S1401, Provide a substrate.

[0110] S1402. A substrate is provided, on which an LED epitaxial structure is disposed, and a current spreading layer is disposed on the LED epitaxial structure. The LED epitaxial structure includes a first doped semiconductor layer, an active layer, and a second doped semiconductor layer stacked together.

[0111] S1403, an etched current spreading layer, a first doped semiconductor layer, and an active layer are used to form multiple LED mesa arranged in an array. The conductive layer is located on the surface of the first doped semiconductor layer of the LED mesa, and a channel is formed between adjacent LED mesa to obtain multiple LED light-emitting units.

[0112] S1404. A contact metal layer is formed on the surface of the LED light-emitting unit.

[0113] S1405. Processing a contact metal layer to form a connecting electrode and an electrode layer, wherein the connecting electrode is disposed on the LED mesa and electrically connected to the corresponding first doped semiconductor layer; the electrode layer is disposed on the surface of an adjacent region of the second doped semiconductor layer of an adjacent LED light-emitting unit and is located in a channel.

[0114] S1406. Form a flat material layer, which covers the LED mesa, connecting electrodes and electrode layers, and fills the channels.

[0115] S1407. A groove and an opening are formed in a planarization material layer to obtain a planarization layer, wherein the planarization layer covers the LED mesa, the groove corresponds to the channel and exposes at least a portion of the surface of the electrode layer on the side away from the second doped semiconductor layer; the opening exposes at least a portion of the surface of the connecting electrode on the side away from the LED mesa.

[0116] S1408. Form a reflective layer that at least covers the inner surface of the groove.

[0117] S1409. A conductive reflective wall is formed by filling the groove with metal, and a conductive bump is formed by filling the opening with metal.

[0118] S1410. The planarization layer is bonded to the substrate, and multiple conductive bumps are bonded to and electrically connected to multiple electrode contacts in a corresponding manner. The conductive reflective wall is bonded to and electrically connected to the common electrode in a corresponding manner, so as to connect the LED light-emitting unit to the substrate.

[0119] S1411, Remove substrate.

[0120] S1412, an array of photoresist pillars is formed on the side of the second doped semiconductor layer away from the LED mesa.

[0121] S1413. Form a photoresist lens from the photoresist pillars.

[0122] S1414. The morphology of the photoresist lens is transferred to the second doped semiconductor layer to obtain a microlens.

[0123] The Micro-LED display chip 1 is fabricated through the above steps.

[0124] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application. The above are merely preferred embodiments of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of this application, and these improvements and modifications should also be considered within the protection scope of this application.

Claims

1. A Micro-LED display chip, characterized in that, The Micro-LED display chip comprises: a substrate; a plurality of LED light emitting units above the substrate, the LED light emitting units comprising a first doped semiconductor layer, an active layer and a second doped semiconductor layer arranged in layers, the first doped semiconductor layer being closer to the surface of the substrate, at least the first doped semiconductor layer and the active layer being processed into LED mesas, a plurality of the LED mesas being arranged in an array, and a channel being formed between adjacent LED mesas; a planarization layer between the LED light emitting units and the substrate and bonded to the substrate, the planarization layer filling the channel and covering the LED mesas, the planarization layer having a groove corresponding to the channel; a conductive reflecting wall arranged in the groove and surrounding the LED mesas.

2. The Micro-LED display chip of claim 1, wherein, Further comprising: a connecting electrode arranged on the LED mesa and electrically connected to the corresponding first doped semiconductor layer; an electrode layer arranged on the surface of the adjacent area of the second doped semiconductor layer of adjacent LED light emitting units and located in the channel, one end of the conductive reflecting wall being electrically connected to the electrode layer; the substrate comprising a plurality of electrode contacts and at least one common electrode, a plurality of the electrode contacts being electrically connected to a plurality of the connecting electrodes one by one, and the electrode layer being electrically connected to the common electrode through the conductive reflecting wall.

3. The Micro-LED display chip according to claim 2, wherein the planarization layer is provided with an opening, the opening exposing at least part of the surface of the side of the connecting electrode away from the LED mesa; the Micro-LED display chip further comprises a conductive bump arranged in the opening and electrically connected to the corresponding connecting electrode, one end of the conductive bump away from the connecting electrode being bonded to the corresponding electrode contact.

4. The Micro-LED display chip of claim 2, wherein, Further comprising: a conductive layer arranged on the surface of the first doped semiconductor layer of the LED mesa and located between the LED mesa and the connecting electrode.

5. The Micro-LED display chip of claim 2, wherein, Further comprising: a passivation layer arranged on the surface of the LED mesa and the surface of the second doped semiconductor layer between adjacent LED mesas and exposing the surfaces of the LED light emitting units and the connecting electrodes and the electrode layer at the corresponding positions.

6. The Micro-LED display chip of claim 1, wherein, Further comprising: a microlens formed by etching the second doped semiconductor layer and located on the side of the second doped semiconductor layer away from the LED mesa, a plurality of the microlenses corresponding to a plurality of the LED mesas one by one; when etching the second doped semiconductor layer, the second doped semiconductor layers of adjacent LED light emitting units are arranged separately or integrally.

7. The Micro-LED display chip according to claim 6, wherein the focal point of the microlens is located on the active layer.

8. The Micro-LED display chip according to claim 6, wherein In a direction perpendicular to the top surface of the substrate, the microlens covers the corresponding LED mesa and covers the sidewall of the corresponding conductive reflective wall towards the side of the LED mesa.

9. The Micro-LED display chip of claim 1, wherein, Further comprising: An undoped material layer disposed on the side of the second doped semiconductor layer away from the LED mesa; A microlens formed by etching the undoped material layer and the second doped semiconductor layer and located on the side of the second doped semiconductor layer away from the LED mesa, a plurality of microlenses corresponding to a plurality of LED mesas; When etching the second doped semiconductor layer, the second doped semiconductor layers of adjacent LED light emitting units are spaced apart or integrally disposed.

10. The Micro-LED display chip of claim 1, wherein, Further comprising: A reflective layer disposed between the conductive reflective wall and the planarization layer. 11.A method for manufacturing a Micro-LED display chip, characterized in that, Comprising the following steps: Providing a substrate; Preparation of LED light emitting units, the LED light emitting units comprising a first doped semiconductor layer, an active layer and a second doped semiconductor layer arranged in layers, at least the first doped semiconductor layer and the active layer are processed to form LED mesas, a plurality of LED mesas are arranged in an array, and a channel is formed between adjacent LED mesas; Forming a planarization layer, the planarization layer filling the channel and covering the LED mesas, the planarization layer having a groove corresponding to the channel; Forming a conductive reflective wall disposed in the groove and surrounding the LED mesa; Bonding the planarization layer to the substrate and locating it between the LED light emitting units and the substrate, a plurality of LED light emitting units are located above the substrate, and the first doped semiconductor layer is closer to the surface of the substrate.

12. The method of claim 11, wherein the method further comprises: The step of preparing LED light emitting units comprises: Providing a substrate having an LED epitaxial structure disposed thereon, the LED epitaxial structure comprising a first doped semiconductor layer, an active layer and a second doped semiconductor layer arranged in layers; Etching at least the first doped semiconductor layer and the active layer to form a plurality of LED mesas arranged in an array and a channel between adjacent LED mesas, thereby obtaining a plurality of LED light emitting units.

13. The method of claim 12, wherein the method further comprises: The LED epitaxial structure is provided with a current spreading layer, and the step of preparing LED light emitting units further comprises: Etching the current spreading layer to form a conductive layer on the surface of the first doped semiconductor layer of the LED mesa.

14. The method of claim 11, wherein the method further comprises: Before the step of forming a planarization layer, the method for preparing a Micro-LED display chip further comprises: Forming a contact metal layer on the surface of the LED light emitting unit; Processing the contact metal layer to form a connection electrode and an electrode layer, wherein the connection electrode is disposed on the LED mesa and electrically connected to the corresponding first doped semiconductor layer; and the electrode layer is disposed on the surface of the adjacent region of the second doped semiconductor layer of adjacent LED light emitting units and located in the channel.

15. The method of claim 14, wherein the method further comprises: The step of forming a planarization layer comprises: forming a flat material layer covering the LED mesa, the connecting electrode and the electrode layer, and filling the trench; forming the recess in the flat material layer to obtain the planarization layer, wherein the planarization layer covers the LED mesa, the recess corresponds to the trench, and exposes at least part of the surface of the side of the electrode layer facing away from the second doped semiconductor layer; The step of forming the planarization layer further comprises: forming an opening in the flat material layer while forming the recess in the flat material layer, the opening exposing at least part of the surface of the side of the connecting electrode facing away from the LED mesa.

16. The method of claim 15, wherein the method further comprises: The step of forming the conductive reflective wall comprises: filling the recess with metal to form the conductive reflective wall; The method for manufacturing the Micro-LED display chip further comprises: filling the opening with metal to form a conductive bump while forming the conductive reflective wall.

17. The method of claim 16, wherein the method further comprises: The substrate comprises a plurality of electrode contacts and at least one common electrode, and the step of connecting the LED light emitting unit to the substrate comprises: The planarization layer is bonded to the substrate, a plurality of the conductive bumps are bonded and electrically connected to a plurality of the electrode contacts one by one, and the conductive reflective wall is bonded and electrically connected to the common electrode.

18. The method of claim 11, wherein the method further comprises: Before the step of forming the conductive reflective wall, the method for manufacturing the Micro-LED display chip further comprises: forming a reflective layer covering at least the inner surface of the recess.

19. The method of claim 11, wherein the method further comprises: Further comprising: etching the side of the second doped semiconductor layer facing away from the LED mesa to form a microlens, a plurality of the microlenses corresponding to a plurality of the LED mesas one by one; When etching the second doped semiconductor layer, the second doped semiconductor layers of adjacent LED light emitting units are arranged separately or integrally.

20. The method of claim 19, wherein the method further comprises: The step of etching the side of the second doped semiconductor layer facing away from the LED mesa to form a microlens comprises: forming an array of photoresist columns on the side of the second doped semiconductor layer facing away from the LED mesa; forming a photoresist lens from the photoresist columns; transferring the topography of the photoresist lens to the second doped semiconductor layer to obtain the microlens.

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