Driving method and apparatus for short-circuit testing of power semiconductor devices

Abstract

This disclosure provides a driving method and apparatus for short-circuit testing of power semiconductor devices, belonging to the field of semiconductor testing technology. The driving apparatus includes an isolated power supply circuit; a driving circuit electrically connected to the secondary side of the isolated power supply circuit, the driving circuit being configured to trigger a short-circuit test on the device under test (DUT) based on an external control signal; the isolated power supply circuit being configured to: enter a stopped operating state during the short-circuit test based on the external control signal; and utilize the energy stored in the isolated power supply circuit before entering the stopped operating state to provide operating power to the driving circuit during the short-circuit test. Through the technical solution of this disclosure, damage to low-voltage side devices in the driving apparatus due to exposure to high voltage and high current conditions during the short-circuit test of the DUT can be avoided.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor testing technology, and in particular to a driving method and apparatus for short-circuit testing of power semiconductor devices. Background Technology

[0002] Short-circuit testing of power semiconductor devices, such as insulated-gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs), is a critical test for evaluating their withstand capability and robustness, and is considered a limit test for the device. In a short-circuit test, the device under test (DUT) withstands high voltage and high current for an extremely short period of time (typically a few microseconds).

[0003] Currently, short-circuit testing platforms typically include fast-acting fuses or overcurrent protection circuits to prevent catastrophic failures of the device under test (DUT) or damage to expensive high-voltage power supply equipment. However, protection measures for the low-voltage drive mechanism that provides the gate drive signal to the DUT are relatively insufficient.

[0004] In related solutions, low-voltage drive devices typically consist of isolated driver chips and isolated power supply modules. In the high-voltage and high-current environment of short-circuit testing, strong electromagnetic interference can couple to the low-voltage drive device through parasitic parameters such as parasitic capacitance and inductance on the circuit board. This coupling raises the normal operating voltage on the low-voltage side. Once this voltage exceeds the maximum voltage that the low-voltage devices (such as the driver chip or the power supply module powering it) can withstand, it will cause these low-voltage devices to break down or be damaged. Therefore, in related solutions, low-voltage drive devices frequently exhibit high failure rates and are easily damaged during short-circuit testing. Summary of the Invention

[0005] This disclosure provides a driving method and apparatus for short-circuit testing of power semiconductor devices; it can prevent low-voltage side devices in the driving device from being damaged by exposure to high voltage and high current conditions during short-circuit testing of the device under test.

[0006] The technical solution disclosed herein is implemented as follows:

[0007] In a first aspect, this disclosure provides a driving device for short-circuit testing of power semiconductor devices, comprising: an isolation power supply circuit; a driving circuit electrically connected to the secondary side of the isolation power supply circuit, the driving circuit being configured to trigger a device under test to perform a short-circuit test based on an external control signal; the isolation power supply circuit being configured to: enter a stop-operation state during the short-circuit test based on the external control signal; and utilize the energy stored in the isolation power supply circuit before entering the stop-operation state to provide operating power to the driving circuit during the short-circuit test.

[0008] In a second aspect, this disclosure provides a driving method for short-circuit testing of power semiconductor devices. This driving method is applied to the driving apparatus for short-circuit testing of power semiconductor devices described in the first aspect, and includes:

[0009] Receive external control signals to trigger the device under test to perform a short-circuit test;

[0010] In response to external control signals, it synchronously performs the following: controls the drive circuit to operate, driving the device under test (DUT) to perform a short-circuit test, and controls the isolation power supply circuit to enter a stopped state during the short-circuit test; and

[0011] The energy stored in the isolation power supply circuit before entering the stop working state is used to provide operating power to the drive circuit during short-circuit testing.

[0012] Thirdly, this disclosure provides a computer-readable storage medium storing at least one instruction that is executed by a processor to implement the driving method for short-circuit testing of power semiconductor devices as described in the second aspect.

[0013] This disclosure provides a driving method and apparatus for short-circuit testing of power semiconductor devices. During the short-circuit test, the isolation power supply circuit protects its internal low-voltage components by entering a stopped state, while the driving circuit relies on the energy stored in the energy storage unit of the isolation power supply circuit to complete the driving task. This avoids damage to the low-voltage components in the driving device used for short-circuit testing of power semiconductor devices due to excessively high transient voltage, improves the robustness of the driving device during short-circuit testing, and reduces the failure rate. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the system provided in this disclosure for short-circuit testing of power semiconductor devices.

[0015] Figure 2 This is a schematic diagram of the drive device for short-circuit testing of power semiconductor devices provided in this disclosure.

[0016] Figure 3This is a detailed circuit diagram of a drive device for short-circuit testing of power semiconductor devices provided in this disclosure.

[0017] Figure 4 This is a schematic diagram of the driving method for short-circuit testing of power semiconductor devices provided in this disclosure. Detailed Implementation

[0018] The technical solutions in this disclosure will now be clearly and completely described with reference to the accompanying drawings.

[0019] Figure 1 This is a schematic diagram of a system for short-circuit testing of power semiconductor devices provided in this disclosure. The system 100 is used to perform short-circuit testing on a device under test (DUT) 130 to evaluate the device under test 130's tolerance and robustness under short-circuit conditions.

[0020] In this disclosure, the device under test 130 can be a power semiconductor device, such as an insulated gate bipolar transistor (IGBT) or a power MOSFET. Specifically, the device under test 130 has a control terminal 131, such as the gate G of an IGBT or MOSFET, a first power terminal 132, such as the collector C of an IGBT or the drain D of a MOSFET, and a second power terminal 133, such as the emitter E of an IGBT or the source S of a MOSFET.

[0021] exist Figure 1 In the system 100, a high-voltage power source 140 is included. The high-voltage power source 140 is connected to the first power terminal 132 and the second power terminal 133 of the device under test 130 via high-voltage buses HV+ and HV-, respectively, to provide high voltage and large current, such as 300V to 1500V high-voltage DC, during short-circuit testing.

[0022] exist Figure 1 In this system, a drive unit 120 is included to provide drive signals to the device under test 130. For example, the output terminals of the drive unit 120, such as port OUT+ and port OUT-, are respectively connected to the control terminal 131 (G) and the second power terminal 133 (E / S) of the device under test 130.

[0023] exist Figure 1In this system 100, an external controller 110 is also included for providing an external control signal, such as a 0-5V pulse signal. This external control signal is sent to a drive unit 120 to trigger the drive unit 120 to drive the device under test 130 to perform a short-circuit test. In this disclosure, the external controller 110 can be implemented as a microcontroller (MCU), a digital signal processor (DSP), or a field-programmable gate array (FPGA).

[0024] After receiving an external control signal from the external controller 110, the drive device 120 converts the external control signal into a high-power drive signal required to drive the control terminal 131 (e.g., gate G) of the device under test 130, such as a +15 / 0V pulse signal, thereby driving the device under test 130 to turn on and perform a short-circuit test.

[0025] Specifically, the short-circuit test is very short; for example, the external control signal can have a duration of... The pulse signal is within the range of [insert range here]. Typically, when an external control signal triggers a short-circuit test, the device under test (DUT) 130 instantly conducts. At this time, the high-voltage power source 140 forms a short-circuit loop through the DUT 130, causing the current in the loop to rise sharply in a very short time, resulting in an extremely high rate of current change. Furthermore, the voltage on the device under test 130 will also change drastically, resulting in an extremely high rate of voltage change. .

[0026] Such rapid changes in voltage and current in a short period of time will be coupled to the drive device 120 through parasitic parameters, thereby raising the voltage of the low-voltage devices in the drive device 120, causing the low-voltage devices in the drive device 120 to be broken down and damaged due to excessive transient voltage.

[0027] To prevent low-voltage components within the drive unit 120 from being damaged by excessive transient voltage, this disclosure provides an application for... Figure 1 The driving device of the system 100 for short-circuit testing of power semiconductor devices as described herein. Figure 2 and Figure 3 The components of the drive unit 120 are shown in both examples. Figure 2 As shown, the drive device 120 includes an isolation power supply circuit 201 and a drive circuit 202.

[0028] exist Figure 2In this circuit, the isolation power supply circuit 201 is used to convert a low-voltage DC power supply into an isolated bias power supply suitable for the drive circuit 202. For example, the isolation power supply circuit 201 generates the positive and negative power supplies required by the drive circuit 202. Figure 3 As shown, the voltage of the positive power supply VDD is The negative power supply is grounded (GND).

[0029] An energy storage unit 205 is provided on the secondary side of the isolation power supply circuit 201. Specifically, this energy storage unit 205 is typically implemented as an output filter capacitor or energy storage capacitor of the isolation power supply circuit 201. Its function is to filter out ripple and provide DC power to the drive circuit 202 during short-circuit testing, such as... Figure 3 The positive power supply VDD and ground GND are shown in the diagram.

[0030] exist Figure 2 In this circuit, the drive circuit 202 is the unit that performs the drive task. Its power supply terminal (not shown) is electrically connected to the secondary side of the isolation power supply circuit 201, and particularly to the energy storage unit 205, to receive the isolated power supplied by the isolation power supply circuit 201. Figure 2 In this configuration, the output of the drive circuit 202 is connected to the control terminal of the device under test 130, such as the gate G, to transmit a drive signal to the device under test 130. In some examples, although... Figure 2 As not shown in the diagram, the output of the drive circuit is also connected to a second power terminal 133, such as the emitter E or the source S.

[0031] exist Figure 2 In this embodiment, the drive device 120 also includes a logic controller 203. It is a logic interface circuit, which can be implemented using one or more logic gates (such as inverters or AND gates), a simple transistor switching circuit, or an I / O unit of a programmable logic device (such as a CPLD or FPGA). In this disclosure, the logic controller 203 is implemented using an inverter as an example.

[0032] Combination Figure 2 The drive unit 120 shown is configured such that when an external control signal is transmitted into the system, the external control signal is synchronously or in parallel distributed to two paths.

[0033] The external control signal is transmitted to the drive circuit 202 via the first path as a drive command. Upon receiving this command, the drive circuit 202 immediately begins to operate, outputting a drive signal from its output terminal to the device under test (DUT) 130, thereby driving the DUT 130 into the conduction state and initiating a short-circuit test.

[0034] At almost the same moment, an external control signal is sent to the logic controller 203 via the second path. Based on the arrival of the external control signal, for example, by detecting its rising edge or high level state, the logic controller 203 immediately outputs a low-level control signal, which is sent to the control terminal of the isolated power supply circuit 201.

[0035] The isolation power supply circuit 201 is configured to enter a stop-operation state during the short-circuit test in response to the control signal from the logic controller 203.

[0036] Specifically, the aforementioned shutdown state has a different meaning from power-off. When the isolation power supply circuit 201 is in the shutdown state, the energy conversion unit inside the isolation power supply circuit 201 (such as its internal DC-DC controller chip) stops switching. For example, when the isolation power supply circuit 201 is a switching power supply, its internal switching transistors stop high-frequency switching, and the energy transfer from the primary side to the secondary side is cut off. By entering the shutdown state, the isolation power supply circuit 201 forms a passive circuit during short-circuit testing; it no longer actively performs high-frequency switching, thereby avoiding high-frequency switching. and high By mitigating the risk of parasitic coupling within the isolation power supply circuit 201, the risk of low-voltage components in the isolation power supply circuit 201 being damaged by excessive transient voltage is reduced.

[0037] Furthermore, in order to ensure that the isolation power supply circuit 201 can still provide operating power to the drive circuit 202 during a short-circuit test when it is in a stopped state, this disclosure utilizes the energy stored in the isolation power supply circuit 201 before it enters the stopped state to provide operating power to the drive circuit 202 during the short-circuit test. Specifically, this energy is the charge stored in the energy storage unit 205 during the normal operation of the isolation power supply circuit 201 before the start of the short-circuit test (at time T<0).

[0038] Understandably, on the one hand, the quiescent current consumed by the drive circuit 202 is very small. Its main energy consumption occurs at the instant when the gate of the device under test 130 is turned on at T=0, i.e., charging the gate capacitance of the device under test 130. Once the gate of the device under test 130 is fully charged, during the short-circuit test, the drive circuit 202 only needs to maintain the gate voltage of the device under test 130, and the energy consumed is extremely low. On the other hand, although the capacitance of the energy storage unit 205, for example, tens to hundreds of microfarads, is not large, the charge it stores is still sufficient to support the drive circuit 202 in completing the task of transiently charging the gate capacitance of the device under test 130 at T=0, and to maintain the operation of the drive circuit 202 during the subsequent short-circuit test.

[0039] Therefore, through this concept of synchronous shutdown and temporary energy storage, the isolation power supply circuit 201 protects its internal low-voltage components by entering a stopped state during short-circuit testing, while the drive circuit 202 relies on the energy stored in the energy storage unit 205 to complete the driving task. This avoids damage to the low-voltage components in the drive device 120 due to excessive transient voltage, improves the robustness of the drive device 120 during short-circuit testing, and reduces the failure rate.

[0040] Figure 3 This is a detailed circuit diagram of a drive device 120 provided in this disclosure. Figure 3 The document details the specific configuration of the isolation power supply circuit 201 and the drive circuit 202.

[0041] like Figure 3 As shown in this disclosure, the isolation power supply circuit 201 is constructed using discrete components. This is because integrated power modules suffer from two major drawbacks: low common-mode rejection ratio (CMRR) and uncontrollable operating states. Specifically, the isolation transformer, control chip, and feedback path within the integrated power module are highly integrated, resulting in a fixed and difficult-to-optimize parasitic capacitance coupling path between the primary and secondary sides, leading to high resistance during short-circuit testing. During common-mode surges, the suppression capability is poor, and it is easily affected by interference and fails. In addition, integrated power modules usually do not provide an external enable pin, which means that these integrated power modules are always working once powered on, and their operating state cannot be controlled.

[0042] Based on this, the isolation power supply circuit 201 is implemented using a forward converter topology, such as... Figure 3 As shown, the isolated power supply circuit 201 includes: a DC-DC chip 301, a transformer 302, a rectifier bridge 303 formed by secondary diodes, and a secondary capacitor 304.

[0043] exist Figure 3 In this circuit, the DC-DC chip 301 is the core of the power supply. It can be implemented by a forward DC-DC chip and is located on the primary side of the isolation boundary. The transformer 302 provides electrical isolation and performs voltage transformation according to the turns ratio. The diode-formed rectifier bridge 303 is located on the secondary side and is used to rectify the pulse voltage output from the secondary side of the transformer 302. The secondary capacitor 304 is... Figure 2 One implementation example of the energy storage unit 205 shown has a capacitor 304 located on the secondary side, used to filter the rectified pulsating voltage to form a stable DC output, while simultaneously storing energy under normal operating conditions and providing operating power to the drive circuit during short-circuit testing.

[0044] exist Figure 3 In this circuit, the DC-DC chip 301 has an enable pin 305. This is a digital logic input pin that can control the operating state of the DC-DC chip 301 according to external control signals. For example, the enable pin 305 can be designed to be "high-active". That is, when the enable pin 305 is high, the DC-DC chip 301 operates normally, generating a PWM signal, and energy is transferred from the primary side to the secondary side; when the enable pin 305 is pulled low, the DC-DC chip 301 immediately stops its internal oscillator and PWM output, and the isolation power supply circuit 201 enters a stopped state.

[0045] exist Figure 3 In this circuit, the logic controller 203 can be implemented as a simple logic inverter. When an external control signal (assuming it is active high) is input to the logic controller 203, the logic controller 203 outputs an inverted signal (i.e., a low-level signal) to the enable signal pin 305 of the DC-DC chip 301, thereby pulling the Enable pin 305 low. The DC-DC chip 301 immediately stops working, causing the isolation power supply circuit 201 to enter a stopped state. When the external control signal is low (not a short-circuit test), the logic controller 203 outputs a high level, the enable signal pin 305 is high, the DC-DC chip 301 works normally, and the secondary capacitor 304 stores energy until it is fully charged.

[0046] like Figure 3 As shown, in this disclosure, the driving circuit 202 is located on the secondary side of the isolation boundary, and its operating power supply comes from the secondary side of the isolation power supply circuit 201, namely the secondary side capacitor 304.

[0047] exist Figure 3 In this circuit, the driving circuit 202 includes an optocoupler isolation driving chip 306. External control signals are sent to the primary side of the optocoupler isolation driving chip 306, i.e., the input side, via a first path. Optical signals pass through the isolation gap and are received by the secondary side of the optocoupler isolation driving chip 306, i.e., the output side, thus achieving isolation of the control signals.

[0048] In short-circuit testing, the driver circuit 202 must not only quickly turn on the device under test 130, but also possess extremely strong sink current capability to keep the gate in a controlled state when the device under test 130 malfunctions or the gate voltage rises due to the Miller effect. Since the optocoupler isolation driver chip 306 has limited output current capability, typically only tens to hundreds of milliamps (mA), the driver circuit 202 also includes a push-pull circuit 307 located on the secondary side of the optocoupler isolation driver chip 306, i.e., the output side.

[0049] like Figure 3 As shown, the push-pull circuit 307 is composed of a complementary pair (CMOS) consisting of an NMOS transistor Q1 and a PMOS transistor Q2. Specifically, the output signal of the optocoupler isolation driver chip 306, such as a logic level, is connected to the gates of Q1 and Q2. When the optocoupler isolation driver chip 306 outputs a high level to indicate that the device under test 130 is turned on, Q1 (NMOS) is turned on and Q2 (PMOS) is turned off. The current from the secondary capacitor 304 flows from the secondary side VDD through Q1 and quickly flows into the gate of the device under test 130, causing it to turn on quickly. When the optocoupler isolation driver chip 306 outputs a low level to indicate that the device under test 130 is turned off, Q1 (NMOS) is turned off and Q2 (PMOS) is turned on. The charge stored on the gate of the device under test 130 is quickly pulled out to the secondary ground GND through Q1.

[0050] Understandably, since Q1 and Q2 are power transistors, rather than the small transistors inside the optocoupler isolation driver chip 306, Q1 and Q2 can provide transient peak currents of several amperes (A) or even tens of amperes, thereby increasing the drive power to withstand the instantaneous current during short-circuit testing.

[0051] In the short-circuit test, high It will generate a spike voltage through Miller capacitance coupling, high Transient voltages are generated through the common emitter / source (E / S) inductance of the power circuit and the drive circuit. These voltage spikes impact the drive circuit 202. To absorb these voltage spikes, the drive circuit 202 also includes one or more transient voltage suppression (TVS) diodes 308 disposed on the drive circuit, such as... Figure 3 As shown, there are two TVS 308s, and the TVS 308 is connected in parallel between the output of the push-pull circuit 307 and the secondary ground (GND), that is, it is connected in parallel with the gate (G) and emitter / source (E / S) pins of the device under test 130.

[0052] Understandably, the TVS 308 is an avalanche breakdown diode. Under normal operating voltage (e.g.) arrive It is in a high-impedance state (off). When a voltage spike attempts to pull the gate voltage out of its clamping voltage, the TVS 308 will momentarily (picoseconds / ps) avalanche breakdown, exhibiting extremely low impedance, bypassing the transient spike current and clamping the gate voltage to a safe value (e.g., ...). or This protects the secondary side of the push-pull circuit 307 (Q1, Q2) and the optocoupler isolation driver chip 306 connected in parallel with it.

[0053] Based on the above-described drive device 120 for short-circuit testing of power semiconductor devices, its workflow during short-circuit testing includes:

[0054] First, the short-circuit test starts at T=0. Before the short-circuit test (T<0), the external control signal is at a low level.

[0055] The external control signal is transmitted to the optocoupler isolation driver chip 306 through the first path, and the secondary side of the optocoupler isolation driver chip 306 outputs a low level. In this case, Q2 (PMOS) in the push-pull circuit 307 is turned on, and Q1 (NMOS) is turned off. The drive output is low. At this time, the gate of the device under test 130 is low, and it is in a reliable off state.

[0056] On the other hand, the external control signal is transmitted to the logic controller 203 through the second path. The logic controller 203 outputs a high-level control signal inverted and sends it to the enable signal pin 305 of the DC-DC chip 301. Since the enable pin 305 receives a high-level signal, the DC-DC chip 301 is in normal working condition. Energy is continuously transferred from the primary side to the secondary side through the transformer 302, and after passing through the rectifier bridge 303, it charges the secondary capacitor 304 until the secondary capacitor 304 is fully charged and maintained at a stable VDD voltage (e.g., +15V).

[0057] Next, when the short-circuit test begins, i.e., at T=0, the external control signal goes high to indicate that the short-circuit test has been triggered. The high-level pulse of the external control signal will continue. .

[0058] At this moment, two operations are executed simultaneously:

[0059] The first operation involves the external control signal being transmitted to the optocoupler isolation driver chip 306 via the first path, and the secondary side of the optocoupler isolation driver chip 306 outputting a high level. In this case, Q1 (NMOS) in the push-pull circuit 307 is turned on, and Q2 (PMOS) is turned off. The output drive signal is high, and the gate voltage of the device under test 130 is rapidly pulled from 0V to +15V and turned on. The short-circuit test officially begins at this moment; the high-voltage power source 140 forms a short circuit through the device under test 130, generating a high voltage. and high .

[0060] The second operation involves the external control signal being transmitted to the logic controller 203 via a second path. The logic controller 203 inverts the output and sends a low-level control signal to the enable pin 305 of the DC-DC chip 301. Since the enable pin 305 receives a low-level signal, the DC-DC chip 301 immediately stops operating, for example, by stopping its internal oscillator and PWM signal output. The energy transfer from the primary to the secondary side of the isolation power supply circuit 201 is cut off. The charge stored in the secondary capacitor 304 injects a large current into the gate capacitor of the device under test 130 through Q1 (NMOS) to turn on the device under test 130. The secondary capacitor 304 also utilizes the stored charge to provide operating power to the drive circuit.

[0061] Then, during the short-circuit test, i.e. During the entire short-circuit test, the isolation power supply circuit 201, especially the DC-DC chip 301, remained in a stopped state. In this way, high voltage in the power circuit was successfully avoided. and high The resulting electrical stress is thus effectively protected. The static sustaining energy required by the drive circuit 202, including the optocoupler isolation driver chip 306 and the push-pull circuit 307—for example, to keep the optocoupler LED lit and Q2 conducting—is entirely provided by the pre-stored charge in the secondary capacitor 304. Due to the extremely short time (e.g.) Furthermore, it has very low static power consumption and minimal voltage drop on the secondary capacitor 304, which is sufficient to maintain a gate voltage of +15V.

[0062] Furthermore, during short-circuit testing, any transient voltage spikes coupled in the power loop that attempt to impact the gate will be absorbed and clamped by the TVS 308, protecting the push-pull circuit 307 and the optocoupler isolation driver chip 306.

[0063] Subsequently, when the short-circuit test ended, that is At this time, the high-level pulse of the external control signal ends, and it returns to a low level. Thus, after the short-circuit test is completed, i.e. The process will then be restored to the state before the short-circuit test (T<0), which will not be repeated here, and we will wait for the next short-circuit test.

[0064] Figure 4 This is a schematic flowchart of a driving method for short-circuit testing of power semiconductor devices provided in this disclosure. The method is executed by the driving device 120 described in the foregoing technical solution, and may include:

[0065] S401: Receives an external control signal used to trigger the device under test to perform a short-circuit test.

[0066] In this disclosure, the external control signal has a defined time characteristic, i.e., its activation state, such as the duration of a high level, corresponds to the desired duration of the short-circuit test. In this disclosure, the duration of the short-circuit test is... Therefore, the pulse width of the external control signal is also set accordingly. Or even shorter.

[0067] S402: In response to an external control signal, execute S403 and S404 synchronously.

[0068] In this disclosure, after the drive device 120 receives an external control signal, it will execute steps S403 and S404 synchronously and in parallel. This means that steps S403 and S404 are triggered by the same event, namely the arrival of the external control signal, such as its rising edge. Furthermore, steps S403 and S404 occur simultaneously or are processed in parallel in time (or logic), rather than sequentially.

[0069] S403: Controls the operation of the drive circuit to drive the device under test to perform a short-circuit test.

[0070] In this disclosure, the drive circuit 202 is activated in response to an external control signal. Specifically, the drive circuit 202 includes an optocoupler-isolated drive chip 306 and a push-pull circuit 307. The activation of the drive circuit in step S403 to drive the device under test (DUT) to perform a short-circuit test may include:

[0071] External control signals are applied to the primary side of the optocoupler isolation driver chip 306;

[0072] The secondary side of the optocoupler isolation driver chip 306 outputs a corresponding control level, such as a high level;

[0073] The push-pull circuit 307 responds to the control level by outputting a high-power drive signal to drive the gate of the device under test 130 to turn on, thereby initiating a short-circuit test.

[0074] S404: Controls the isolated power supply circuit to enter a stopped state during short-circuit testing.

[0075] In this disclosure, the isolated power supply circuit 201 is a forward converter built using discrete components, the core of which is a DC-DC chip 301 with an enable signal pin (305). Based on this, step S404 may include:

[0076] An external control signal is applied to the logic controller 203, which inverts the external control signal, converting the high-level pulse into a low-level pulse.

[0077] The logic controller 203 outputs a low-level control signal and applies it to the Enable pin 305 of the DC-DC chip 301;

[0078] In response to a low level on the Enable pin 305, the DC-DC chip 301 immediately stops its internal switching action, thereby causing the isolation power supply circuit 201 to enter a stopped working state, and the energy transfer from the primary side to the secondary side is cut off.

[0079] S405: Utilizes the energy stored in the isolation power supply circuit before entering the stop working state to provide operating power to the drive circuit during short-circuit testing.

[0080] In this disclosure, after the isolation power supply circuit 201 enters the stop working state according to step S404 (starting from time T=0), the drive circuit 202 executes step S403 during the short circuit test (i.e., from T=0 to T= All the power required for operation is provided by the energy stored in the isolation power supply circuit 201 before entering the stop operation state (i.e., at time T<0).

[0081] In this disclosure, this energy is stored in the secondary capacitor 304 of the isolated power supply circuit 201. Step S405 is specifically the process by which the drive circuit 202 (including optocoupler 306 and push-pull circuit 307) draws charge from the two ends (VDD and GND) of the secondary capacitor 304 to maintain its operation.

[0082] It is understood that, through the methods of steps S401 to S405 above, this disclosure actively shuts off the isolation power supply during the dangerous transient period of performing a short-circuit test, protecting it from electrical stress damage; at the same time, it relies on the energy stored in the secondary capacitor to complete the necessary test drive task, thereby effectively protecting the low-voltage circuit and significantly reducing the failure rate of the drive device.

[0083] This disclosure also provides a computer-readable storage medium storing at least one instruction that is executed by a processor to implement the driving method for testing power semiconductor short-circuit devices as described in the various embodiments above.

[0084] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computing device to perform the driving method for short-circuit testing of power semiconductor devices as described in the above embodiments.

[0085] Those skilled in the art will recognize that the functions described in this disclosure in one or more of the examples above can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0086] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0087] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A driving device for short-circuit testing of power semiconductor devices, characterized in that, The driving device includes: Isolated power supply circuit; A drive circuit electrically connected to the secondary side of the isolation power supply circuit, the drive circuit being configured to trigger the device under test to perform a short-circuit test based on an external control signal; The isolation power supply circuit is configured to: enter a stopped operating state based on the external control signal during the short-circuit test; and The energy stored in the isolation power supply circuit before entering the stopped working state is used to provide operating power to the drive circuit during the short circuit test. The isolated power supply circuit is constructed from discrete components, including a DC-DC converter chip, a transformer, a diode, and at least one capacitor; wherein the stored energy is stored in the secondary capacitor of the at least one capacitor located in the isolated power supply circuit.

2. The driving device according to claim 1, characterized in that, The isolated power supply circuit includes a DC-DC converter chip with an enable signal pin; the level of the enable signal pin is used to control the DC-DC converter chip to stop working and to cause the isolated power supply circuit to enter the stopped working state.

3. The driving device according to claim 1, characterized in that, The driving circuit includes: an optocoupler isolation driving chip; and a push-pull circuit disposed on the secondary side of the optocoupler isolation driving chip.

4. The driving device according to claim 3, characterized in that, The push-pull circuit includes NMOS transistors and PMOS transistors.

5. The driving device according to claim 3, characterized in that, The driving circuit also includes a transient voltage suppression diode, which is used to absorb the voltage spikes coupled by the device under test during switching.

6. A driving method for short-circuit testing of power semiconductor devices, characterized in that, The driving method is applied to the driving device for short-circuit testing of power semiconductor devices as described in any one of claims 1 to 5, the driving method comprising: Receive external control signals to trigger the device under test to perform a short-circuit test; In response to the external control signal, the following actions are performed synchronously: controlling the drive circuit to operate, thereby driving the device under test to perform the short-circuit test; and controlling the isolation power supply circuit to enter a stopped state during the short-circuit test; and The energy stored in the isolation power supply circuit before entering the stopped working state is used to provide operating power to the drive circuit during the short-circuit test.

7. The driving method according to claim 6, characterized in that, Controlling the isolated power supply circuit to enter a stopped operating state during the short-circuit test includes: Control the level of the enable signal pin of the DC-DC chip in the isolated power supply circuit to stop the DC-DC chip in the isolated power supply circuit from working.

8. The driving method according to claim 6, characterized in that, The control of the drive circuit includes: The device under test is driven by the optocoupler-isolated driver chip and push-pull circuit of the driving circuit.

9. The driving method according to claim 6, characterized in that, The duration of the short-circuit test is Within.

Images