Test board for chip aging test

Abstract

The invention provides a test board for a chip aging test, and relates to the technical field of chips. In the test board, the input end of a micro buffer circuit is used for inputting an initial high-frequency square wave signal, and the output end of the micro buffer circuit is used for being electrically connected with the input end of an N-order passive LC low-pass filter; the output end of the N-order passive LC low-pass filter is used for being electrically connected with one end of the impedance matching resistor and the input end of the chip to be tested so as to input a target sine wave signal to the chip to be tested, the other end of the impedance matching resistor is grounded, and the value of N is an even number larger than 2; the micro buffer circuit is used for adjusting the input initial high-frequency square wave signal into a target high-frequency square wave signal; and the N-order passive LC low-pass filter is used for converting the target high-frequency square wave signal into a target sine wave signal, so that a test board can be arranged based on fewer basic circuit elements, the test cost is low, the occupied space is small, and the output target sine wave signal can meet the signal quality requirement.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a test board for chip aging testing. Background Technology

[0002] Chip aging testing is a core step in verifying the long-term reliability of chips. In the testing of analog chips, radio frequency chips, mixed signal chips, and other chips with analog input signals, chip aging testing requires inputting a stable, low-distortion sine wave signal to the chip under test to simulate the actual working environment and detect the performance degradation of the chip after long-term operation. Precise and controllable analog input signals are the key foundation for achieving accurate assessment of performance degradation during the aging process.

[0003] In existing technologies, when performing chip aging tests, a fixed-frequency sine wave signal is often output through an integrated filter chip.

[0004] It can be seen that existing tests for chip aging mainly rely on integrated filter chips, which results in high testing costs. Summary of the Invention

[0005] The purpose of this application is to address the shortcomings of the prior art by providing a test board for chip aging testing. This test board can be set up with fewer basic circuit components, resulting in low testing cost and small footprint. It can also ensure that the output target sine wave signal meets the signal quality requirements and is suitable for chip aging testing of the chip under test.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, the present invention provides a test board for chip aging testing, the test board comprising: a test PCB board, a miniature buffer circuit located on the test PCB board, an N-order passive LC low-pass filter, an impedance matching resistor, and a chip under test; The micro buffer circuit is used to adjust the input initial high-frequency square wave signal to a target high-frequency square wave signal, wherein the amplitude of the initial high-frequency square wave signal is smaller than the amplitude of the target high-frequency square wave signal. The Nth-order passive LC low-pass filter is used to convert the target high-frequency square wave signal into a target sine wave signal, wherein the target frequency of the target sine wave signal is the same as the initial frequency of the initial high-frequency square wave signal. The chip under test is used to receive the target sine wave signal and perform chip aging test under the excitation of the target sine wave signal to verify the performance stability and reliability of the chip under test. The micro buffer circuit has an input terminal for inputting an initial high-frequency square wave signal, an output terminal for electrically connecting to the input terminal of the Nth-order passive LC low-pass filter, an output terminal for electrically connecting to one end of the impedance matching resistor and the input terminal of the chip under test, and the other end of the impedance matching resistor is grounded. The value of N is an even number greater than 2.

[0007] In an optional implementation, the miniature buffer circuit includes: a first resistor, a third resistor, an NPN transistor, and a preset power supply. An initial high-frequency square wave signal is input to one end of the first resistor, and the other end of the first resistor is electrically connected to the base of the NPN transistor. One end of the preset power supply is grounded, and the other end is electrically connected to the collector of the NPN transistor; The emitter of the NPN transistor and one end of the third resistor are electrically connected to the input of the Nth-order passive LC low-pass filter. One end of the third resistor is connected to the emitter of the NPN transistor, and the other end of the third resistor is grounded.

[0008] In an optional implementation, the Nth-order passive LC low-pass filter includes N capacitors and N inductors, the capacitance value of each capacitor and the inductance value of each inductor being determined based on the target frequency of the target sine wave signal, a Butterworth normalized parameter table and / or preset simulation software.

[0009] In an optional implementation, the capacitance value of each capacitor is determined based on the normalized capacitance value corresponding to each capacitor and the target frequency of the target sine wave signal. The normalized capacitance value corresponding to each capacitor is determined based on the target frequency of the target sine wave signal according to the Butterworth normalization parameter table. The inductance value of each inductor is determined based on the normalized inductance value corresponding to each inductor and the target frequency of the target sine wave signal. The normalized inductance value corresponding to each inductor is determined based on the target frequency of the target sine wave signal according to the Butterworth normalization parameter table.

[0010] In an optional implementation, the attenuation of the target sinusoidal signal within the passband corresponding to the Nth-order passive LC low-pass filter is less than a first attenuation threshold. The third harmonic of the target sine wave signal is located within the stopband of the Nth-order passive LC low-pass filter, and the attenuation of the third harmonic is greater than the second attenuation threshold. The Mth harmonic of the target sine wave signal is located within the stopband of the Nth-order passive LC low-pass filter, and the attenuation of the Mth harmonic is greater than the third attenuation threshold. M is an odd number greater than 5, and the second attenuation threshold is less than the third attenuation threshold.

[0011] In an optional implementation, the micro buffer circuit, the Nth-order passive LC low-pass filter, the impedance matching resistor, and the chip under test are mounted on the test PCB using surface mount technology.

[0012] In an alternative embodiment, the third resistor is used to match the impedance between the output of the micro-buffer circuit and the input of the Nth-order passive LC low-pass filter.

[0013] In an optional implementation, the impedance matching resistor is used to match the impedance between the output of the Nth-order passive LC low-pass filter and the input of the chip under test.

[0014] In an optional implementation, the total harmonic distortion value of the target sine wave signal is less than a first preset value, so that the distortion of the target sine wave signal input to the chip under test meets the preset distortion test requirements.

[0015] In an optional implementation, the total harmonic distortion value of the target sine wave signal under a preset temperature condition within a preset time period is less than a second preset value, and the amplitude parameter of the target sine wave signal meets the preset amplitude parameter requirements, so that the stability of the target sine wave signal input to the chip under test meets the preset stability requirements.

[0016] The beneficial effects of this application are: The test board for chip aging testing provided in this application includes: a test PCB board, a miniature buffer circuit, an N-order passive LC low-pass filter, an impedance matching resistor, and a chip under test (DUT). The miniature buffer circuit adjusts an initial high-frequency square wave signal to a target high-frequency square wave signal, where the amplitude of the initial high-frequency square wave signal is smaller than the amplitude of the target high-frequency square wave signal. The N-order passive LC low-pass filter converts the target high-frequency square wave signal into a target sine wave signal, where the target frequency of the target sine wave signal is the same as the initial frequency of the initial high-frequency square wave signal. The DUT receives the target sine wave signal and performs chip aging testing under the excitation of the target sine wave signal to verify the performance stability and reliability of the DUT. The input terminal of the miniature buffer circuit is used to input the initial high-frequency square wave signal, and the output terminal of the miniature buffer circuit is used to connect to the N-order passive LC low-pass filter. The input of the LC low-pass filter is electrically connected, and the output of the N-order passive LC low-pass filter is electrically connected to one end of the impedance matching resistor and the input of the chip under test (DUT). The other end of the impedance matching resistor is grounded. The value of N is an even number greater than 2. This allows for setup with fewer basic circuit components, resulting in low testing cost and small footprint. The test board can be integrated into the aging test PCB board. Furthermore, through the combined action of the micro buffer circuit, the N-order passive LC low-pass filter, the impedance matching resistor, and the DUT, not only can the initial high-frequency square wave signal be converted into the target sine wave signal, but the provided test board can also operate stably in high-frequency, long-term, and high-temperature aging test scenarios. This significantly improves the signal quality of the target sine wave signal, enabling the DUT to undergo chip aging tests under the excitation of the target sine wave signal to verify the performance stability and reliability of the DUT. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of a test board for chip aging testing provided in an embodiment of this application; Figure 2 A schematic diagram of another test board for chip aging testing provided in an embodiment of this application; Figure 3 A comparison waveform diagram of an initial high-frequency square wave signal and a target sine wave signal provided in an embodiment of this application; Figure 4A schematic flowchart of a test method for chip aging test provided in an embodiment of this application; Figure 5 A schematic flowchart of another test method for chip aging test provided in an embodiment of this application; Figure 6 A schematic flowchart of another test method for chip aging test provided in an embodiment of this application; Figure 7 This is a schematic diagram of an electronic device structure provided in an embodiment of this application.

[0019] Icon labels: 110 - Test PCB board; 120 - Miniature buffer circuit; 130 - N-order passive LC low-pass filter; 140 - Chip under test; R1 - First resistor; R3 - Third resistor; R4 - Impedance matching resistor; VS - Preset power supply; L1 - First inductor; C1 - First capacitor; L2 - Second inductor; C2 - Second capacitor; L3 - Third inductor; C3 - Third capacitor; L4 - Fourth inductor; C4 - Fourth capacitor; 200 - Test board; 230 - Driver board. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0023] Chip aging testing is a core step in verifying the long-term reliability of chips. In the testing of analog chips, radio frequency chips, mixed signal chips, and other chips with analog input signals, accurate and controllable analog input signals are the key foundation for achieving accurate assessment of performance degradation during the aging process.

[0024] Compared to conventional chip testing, chip aging testing requires inputting stable, low-distortion excitation signals (such as sine waves) to the chip under test to simulate the actual working environment and detect the performance degradation of the chip after long-term operation. In particular, it is necessary to run the chip continuously for hundreds to thousands of hours under accelerated stress environments such as high temperature and high pressure. Therefore, higher requirements are placed on the stability, durability, and adaptability of the analog input signal. That is, the analog input signal input to the chip under test must have low noise and high long-term stability characteristics, while supporting real-time fine-tuning of parameters such as amplitude and frequency to adapt to the dynamic changes in the chip's input characteristics during the aging process.

[0025] In related technologies, chip aging tests often involve using integrated filter chips to output a fixed-frequency sine wave signal. Therefore, existing chip aging tests primarily rely on integrated filter chips. When testing another chip at a different frequency, the integrated filter chip needs to be replaced, resulting in high testing costs for existing methods.

[0026] In addition, other methods for generating analog input signals exist in related technologies, but they all have various problems. For example, generating analog input signals through a separate signal generator is problematic because such generators cannot be integrated into the aging test PCB board, occupying test space and incurring extremely high costs for multi-channel testing. Furthermore, the signal transmission process is susceptible to interference, affecting test accuracy. Another example is using an active filtering scheme to generate analog input signals. However, active filtering schemes rely on operational amplifiers and power supply modules, occupying a large area when integrated into the PCB board. Moreover, the temperature drift characteristics of the operational amplifiers can cause instability in the amplitude and frequency of the excitation signal, failing to meet the stability requirements of long-term aging tests (≥1000h). Furthermore, combining traditional RLC filter circuits to generate analog input signals is also problematic. However, traditional RLC filter circuits are significantly affected by temperature drift, and their filtering characteristics deteriorate in the high-temperature environment (40℃-125℃) of aging tests, leading to distortion of the excitation signal and misjudgment of chip performance.

[0027] In view of this, embodiments of this application provide a test board for chip aging testing. The test board can be set up with fewer basic circuit components, has low testing cost and small footprint, and can ensure that the output target sine wave signal meets the signal quality requirements. Thus, the chip under test can be subjected to chip aging testing under the excitation of the target sine wave signal to verify the performance stability and reliability of the chip under test.

[0028] Figure 1 This is a schematic diagram of a test board for chip aging testing provided in an embodiment of this application, as shown below. Figure 1As shown, the test board may include: a test PCB board 110, a miniature buffer circuit 120 located on the test PCB board 110, an N-order passive LC low-pass filter 130, an impedance matching resistor R4, and a chip under test 140.

[0029] A miniature buffer circuit 120 is used to adjust the input initial high-frequency square wave signal to a target high-frequency square wave signal, wherein the amplitude of the initial high-frequency square wave signal is smaller than the amplitude of the target high-frequency square wave signal; an N-order passive LC low-pass filter 130 is used to convert the target high-frequency square wave signal into a target sine wave signal, wherein the target frequency of the target sine wave signal is the same as the initial frequency of the initial high-frequency square wave signal; and a chip under test 140 is used to receive the target sine wave signal and perform chip aging tests under the excitation of the target sine wave signal to verify the performance stability and reliability of the chip under test 140.

[0030] The micro buffer circuit 120 is used to input an initial high-frequency square wave signal. The output of the micro buffer circuit 120 is electrically connected to the input of an N-order passive LC low-pass filter 130. The output of the N-order passive LC low-pass filter 130 is electrically connected to one end of an impedance matching resistor R4 and the input of the chip under test 140. The other end of the impedance matching resistor R4 is grounded. The value of N is an even number greater than 2.

[0031] Optionally, the initial high-frequency square wave signal can be generated by a square wave generator such as a CMOS crystal oscillator, a 555 timer, or a driver board. The frequency of the initial high-frequency square wave signal can be any frequency from 1MHz to 100MHz, and is not limited here.

[0032] In some implementations, the miniature buffer circuit 120 can be implemented using a miniature emitter follower. The miniature buffer circuit 120 can adjust the initial high-frequency square wave signal input through the target input interface (VF1 interface) into a target high-frequency square wave signal with a larger amplitude, thereby improving the driving capability of the initial high-frequency square wave signal. At the same time, it can also achieve electrical isolation and impedance transformation, avoiding the influence of the internal resistance of the square wave generator on the Nth-order passive LC low-pass filter 130, so as to improve the stability of the target high-frequency square wave signal input to the Nth-order passive LC low-pass filter 130.

[0033] Among them, the N-order passive LC low-pass filter 130 can convert the target high-frequency square wave signal input by the micro buffer circuit 120 into a target sine wave signal. The converted target sine wave signal can be input into the chip under test 140 for chip aging test through the target output interface (VF2 interface).

[0034] Optionally, the order of the passive LC low-pass filter can be an integer greater than 2, such as a 4th-order passive LC low-pass filter or a 6th-order passive LC low-pass filter. The value of N can be adjusted according to the signal quality of the target sine wave signal. In some methods, the signal quality of the target sine wave signal can be measured based on its target frequency, amplitude, signal attenuation, signal distortion, etc.

[0035] It is understandable that the N-order passive LC low-pass filter 130 is affected by temperature changes, which causes the LC element parameters to drift. This results in the output impedance of the N-order passive LC low-pass filter 130 being unstable, making it difficult to match the input impedance of the chip under test 140. As a result of the impedance mismatch, the signal will be reflected at the interface, causing waveform distortion (such as superimposed noise and amplitude fluctuations), which affects the accuracy of the aging test.

[0036] Optionally, an impedance matching resistor R4 can be introduced. One end of the impedance matching resistor R4 is electrically connected to the output terminal of the N-order passive LC low-pass filter 130 and the input terminal of the chip under test 140, and the other end is grounded. The impedance matching resistor R4 matches the impedance between the output terminal of the N-order passive LC low-pass filter 130 and the input terminal of the chip under test 140 (for example, it can be matched to 50Ω). Impedance matching can prevent signal reflection, reduce distortion, and improve signal quality stability, making the test board provided in this application suitable for aging test scenarios with high frequency (1MHz–100MHz), long-term operation, and high temperature (40℃–125℃), significantly improving the signal quality of the target sine wave signal and the reliability of the test board. In some embodiments, the impedance matching resistor R4 is used to match the impedance between the output terminal of the N-order passive LC low-pass filter and the input terminal of the chip under test. This impedance matching resistor R4 can be a surface-mount metal film resistor with a value of 50Ω.

[0037] It should be noted that, optionally, the output of the N-order passive LC low-pass filter 130, which is electrically connected to the input of the chip under test 140, can be in the form of a spring pin interface, a gold finger interface, etc., with a contact resistance ≤10mΩ and a temperature resistance of -40℃ to 125℃.

[0038] As can be seen, the test board provided in this application embodiment can be set up with fewer basic circuit components, resulting in low testing cost and small footprint. It can not only be integrated into the aging test PCB board 110, but also avoid the risk of test board failure due to excessive components. In addition, since the miniature buffer circuit 120 can achieve electrical isolation and impedance transformation, it avoids the influence of the square wave generator's internal resistance on the N-order passive LC low-pass filter 130, thereby improving the stability of the target high-frequency square wave signal input to the N-order passive LC low-pass filter 130. Through the combined effect of the N-order passive LC low-pass filter 130 and the impedance matching resistor, the test board provided in this application can work stably in high-frequency, long-term operation, and high-temperature aging test scenarios, significantly improving the signal quality of the target sine wave signal.

[0039] In summary, this application provides a test board for chip aging testing. The test board includes: a test PCB board, a miniature buffer circuit, an N-order passive LC low-pass filter, an impedance matching resistor, and a chip under test (DUT). The miniature buffer circuit adjusts an input initial high-frequency square wave signal to a target high-frequency square wave signal, where the amplitude of the initial high-frequency square wave signal is smaller than the amplitude of the target high-frequency square wave signal. The N-order passive LC low-pass filter converts the target high-frequency square wave signal into a target sine wave signal, where the target frequency of the target sine wave signal is the same as the initial frequency of the initial high-frequency square wave signal. The DUT receives the target sine wave signal and performs chip aging testing under the excitation of the target sine wave signal to verify the performance stability and reliability of the DUT. The input terminal of the miniature buffer circuit is used to input the initial high-frequency square wave signal, and the output terminal of the miniature buffer circuit is used to connect with the N-order passive LC low-pass filter. The input of the source LC low-pass filter is electrically connected, and the output of the N-order passive LC low-pass filter is electrically connected to one end of the impedance matching resistor and the input of the chip under test. The other end of the impedance matching resistor is grounded. The value of N is an even number greater than 2. This allows for setup based on fewer basic circuit components, resulting in low testing cost and small footprint. The test board can be integrated into the aging test PCB board. Furthermore, through the combined action of the micro buffer circuit, the N-order passive LC low-pass filter, the impedance matching resistor, and the chip under test, not only can the initial high-frequency square wave signal be converted into the target sine wave signal, but the provided test board can also operate stably in high-frequency, long-term operation, and high-temperature aging test scenarios, significantly improving the signal quality of the target sine wave signal. This allows the chip under test to undergo chip aging tests under the excitation of the target sine wave signal to verify the performance stability and reliability of the chip under test.

[0040] Figure 2 This is a schematic diagram of another test board for chip aging testing provided in an embodiment of this application. In optional embodiments, such as... Figure 2As shown, the miniature buffer circuit 120 may include: a first resistor R1, a third resistor R3, an NPN transistor, and a preset power supply VS.

[0041] Wherein, one end of the first resistor R1 is used to input the initial high-frequency square wave signal, and the other end of the first resistor R1 is electrically connected to the base of the NPN transistor; one end of the preset power supply VS is grounded, and the other end is electrically connected to the collector of the NPN transistor; the emitter of the NPN transistor is electrically connected to one end of the third resistor R3 and the input terminal of the N-order passive LC low-pass filter 130; one end of the third resistor R3 is connected to the emitter of the NPN transistor, and the other end of the third resistor R3 is grounded.

[0042] The first resistor R1 can be considered as a base current limiting resistor, used to limit the base current of the NPN transistor and protect the square wave source that generates the initial high-frequency square wave signal. The other end of the preset power supply VS is electrically connected to the collector of the NPN transistor, which can provide the necessary DC operating power to the NPN transistor, enabling it to exhibit high input impedance and low output impedance characteristics. This effectively isolates the front-stage square wave generator from the rear-stage N-order passive LC low-pass filter 130, thereby improving the signal integrity and high-temperature stability of the entire square wave to sine wave circuit.

[0043] Of course, depending on the actual application scenario, a resistor can also be set between the preset power supply VS and the collector of the NPN transistor to limit the collector current, prevent overcurrent damage, stabilize the DC operating point, suppress power supply noise coupling, and improve the power supply rejection ratio.

[0044] Secondly, such as Figure 2 As shown, the third resistor R3 can be regarded as another impedance matching circuit. The impedance between the third resistor R3 and the output terminal of the miniature buffer circuit 120 and the input terminal of the N-order passive LC low-pass filter 130 is matched (for example, it can be matched to 50Ω) to avoid attenuation of the initial high-frequency square wave signal input to the square wave generator.

[0045] In addition, combined Figure 2 As shown, optionally, the first resistor R1, the third resistor R3, the impedance matching resistor R4, and the chip under test can be surface-mount metal film resistors with a temperature resistance of -55℃ to 150℃.

[0046] Optionally, the above-mentioned NPN transistor can be a surface-mount NPN transistor. When selecting an NPN transistor, the following conditions can also be considered: characteristic frequency f_T≥300MHz, collector current I_C≥200mA, input impedance≥10kΩ, output impedance≤100Ω, and temperature resistance -55℃~150℃.

[0047] It should be noted that in some embodiments, the NPN transistor can also be replaced with a PNP transistor or a field-effect transistor (e.g., NMOS or PMOS), which is not limited here. It is understood that if it is replaced with a PNP transistor or a field-effect transistor, the peripheral circuit can be adapted to the role of the NPN transistor in this application.

[0048] As can be seen from the embodiments of this application, the micro buffer circuit 120 has fewer circuit elements, thus reducing the volume occupied by the test board.

[0049] In an optional implementation, the N-order passive LC low-pass filter 130 includes N capacitors and N inductors. The capacitance value of each capacitor and the inductance value of each inductor are determined based on the target frequency of the target sine wave signal according to the Butterworth normalized parameter table and / or preset simulation software.

[0050] In the N-order passive LC low-pass filter 130, the number of capacitors and inductors can be the same. The capacitor and inductor units adopt a compact alternating cascaded design, with each stage consisting of an inductor (L...) arranged in series. n ) and capacitors connected in parallel (C n The circuit consists of capacitors, one end of which is reliably grounded through a grounding via on the test PCB board 110. Optionally, each capacitor can be a surface-mount capacitor, and each inductor can be a surface-mount inductor.

[0051] Optionally, considering that Butterworth low-pass filters have the advantages of flat passband amplitude-frequency characteristics and steep transition band attenuation, and that Butterworth low-pass filters are set based on the Butterworth normalized parameter table, in some embodiments, the capacitance values ​​of each capacitor and the inductance values ​​of each inductor in the N-order passive LC low-pass filter 130 can be set according to the Butterworth normalized parameter table. This ensures that the signal quality of the target sine wave signal output by the N-order passive LC low-pass filter 130 meets the performance testing requirements of the chip under test, thereby improving the calculation efficiency of the capacitance and inductance values ​​and increasing the production efficiency of the test board.

[0052] It should be noted that in some implementations, the test board can be simulated using simulation software, and the capacitance value of each capacitor and the inductance value of each inductor can be determined based on the simulation results; this is not limited here. Alternatively, the Butterworth normalized parameter table can be used to determine the parameters first, and then simulation software can be used for simulation testing; this is also not limited here.

[0053] In an optional implementation, the capacitance value of each capacitor is determined based on the normalized capacitance value corresponding to each capacitor and the target frequency of the target sine wave signal. The normalized capacitance value corresponding to each capacitor is determined based on the target frequency of the target sine wave signal and the Butterworth normalization parameter table. The inductance value of each inductor is determined based on the normalized inductance value corresponding to each inductor and the target frequency of the target sine wave signal. The normalized inductance value corresponding to each inductor is determined based on the target frequency of the target sine wave signal and the Butterworth normalization parameter table.

[0054] Optionally, in specific calculations, the capacitance value of each capacitor can be determined based on the actual cutoff frequency corresponding to the target sine wave signal, the input impedance of the chip under test, and the normalized capacitance value of each capacitor; the inductance value of each inductor can be determined based on the actual cutoff frequency corresponding to the target sine wave signal, the input impedance of the chip under test, and the normalized inductance value of each inductor.

[0055] In some implementations, the capacitance values ​​of each capacitor and the inductance values ​​of each inductor in the N-order passive LC low-pass filter 130 can be calculated using the following formulas:

[0056]

[0057] Where n is a series, and n takes the value of a positive integer between 1 and N. This represents the normalized inductance value corresponding to the nth stage inductor, and its value is taken as the coefficient of the nth stage Butterworth polynomial. This represents the normalized capacitance value corresponding to the nth stage capacitor, and its value is taken as the coefficient of the (n+1)th stage Butterworth polynomial. This represents the inductor corresponding to the nth level inductance. This represents the capacitance value corresponding to the nth capacitor. This represents the actual cutoff frequency determined based on the target frequency of the target sinusoidal signal. This represents the input impedance of the chip under test, and optionally, the value can be 50Ω.

[0058] It should be noted that the coefficients of the nth-level Butterworth polynomial and the (n+1)th-level Butterworth polynomial can be obtained by querying the Butterworth normalization parameter table.

[0059] Furthermore, the actual cutoff frequency can be a preset multiple of the target frequency, that is, assuming the target frequency of the target sine wave signal is... That is, the fundamental frequency of the square wave f0 = The relationship between the two is: =E Where E represents the preset multiple, which can be any value between 1 and 2. For example, in some scenarios, the value can be 1.5, but it is not limited to this.

[0060] For example, a fourth-order passive LC low-pass filter will be used as an example for illustration, such as... Figure 2 As shown, one end of the first inductor L1 is electrically connected to one end of the third resistor R3, and the other end of the first inductor L1 is electrically connected to one end of the first capacitor C1 and one end of the second inductor L2. The other end of the second inductor L2 is electrically connected to one end of the second capacitor C2 and one end of the third inductor L3. The other end of the third inductor L3 is electrically connected to one end of the third capacitor C3 and one end of the fourth inductor L4. The other end of the fourth inductor L4 is electrically connected to one end of the fourth capacitor C4 and one end of the impedance matching resistor R4. The other ends of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are grounded.

[0061] Optionally, the coefficients of the 4th-order Butterworth polynomial corresponding to the 4th-order passive LC low-pass filter are as follows: , , , It can be seen that it satisfies Symmetry characteristics. Taking a preset multiple of 1.5 as an example, when the chip under test requires a 10MHz sine wave signal (i.e.,...) =10MHz, =15MHz), input impedance of the chip under test When the resistance is 50Ω, the following calculation results can be obtained by referring to the above formula: L1=406nH (±5%), C1=392pF (±2%); L2=980nH (±5%), C2=162pF (±2%); L3=980nH (±5%), C3=162pF (±2%); L4=406nH (±5%), C4=392pF (±2%).

[0062] As can be seen, all inductors and capacitors are commercially available surface-mount components, suitable for PCB integration. For each inductor, it should be noted that its quality factor should meet the following conditions: Q value ≥ 50 (15MHz), and its DC resistance should meet the following condition: DC resistance ≤ 1Ω. For each capacitor, it should be noted that its parasitic resistance ESR should meet the following condition: ESR ≤ 0.1Ω (15MHz). Furthermore, all inductors and capacitors should meet the following temperature resistance requirements: -55℃ to 125℃.

[0063] By applying the embodiments of this application, by setting the capacitance value of each capacitor and the inductance value of each inductor in the N-order passive LC low-pass filter 130, and determining the target frequency of the target sine wave signal according to the Butterworth normalized parameter table, adjacent LC units can achieve impedance continuity through parameter optimization, with an inter-stage reflection coefficient ≤0.1, reducing signal reflection within the PCB board and ensuring the stability of the target sine wave signal.

[0064] In an optional implementation, the total harmonic distortion value of the target sine wave signal is less than a first preset value, so that the distortion of the target sine wave signal input to the chip under test meets the preset distortion test requirements.

[0065] In an optional implementation, the total harmonic distortion value of the target sine wave signal under a preset temperature condition within a preset time period is less than a second preset value, and the amplitude parameter of the target sine wave signal meets the preset amplitude parameter requirements, so that the stability of the target sine wave signal input to the chip under test meets the preset stability requirements.

[0066] When performing distortion testing on the target sine wave signal, the preset detection interface of the controller on the driver board can be connected to the output interface of the test board (i.e., Figure 2 The VF2 interface is used to calculate the total harmonic distortion (THD) of the output target sine wave signal using Fast Fourier Transform (FFT). If the THD of the target sine wave signal is less than a first preset value (e.g., 1.5%), then the distortion of the target sine wave signal meets the preset distortion test requirements, the target sine wave signal has no obvious distortion, and it meets the requirements of the chip under test for the excitation signal in the aging test scenario.

[0067] In some implementations, a high-temperature stability test can also be performed on the chip under test. Optionally, during the test, the test board can be placed in a constant temperature chamber at 40℃-125℃, and kept at 20℃ for 30 minutes at each interval. The THD and amplitude of the target sine wave signal are recorded at each temperature point. If the THD change of the target sine wave signal is ≤ a second preset value (e.g., 0.3%), and the amplitude fluctuation is ≤ a preset amplitude threshold (e.g., ±2%), then the test board is determined to meet the 1000h high-temperature aging test, and the high-temperature stability of the target sine wave signal generated by the test board meets the preset stability requirements and meets the requirements of the chip under test for the excitation signal in the aging test scenario.

[0068] In an optional implementation, the test board can also be subjected to frequency compatibility testing. For example, the Nth-order passive LC low-pass filter 130 in the test board can be replaced (e.g., to adapt to 5MHz excitation, a second-order passive LC low-pass filter can be set, where L1=812nH, C1=784pF; L2=1960nH, C2=324pF). If it is determined that the total harmonic distortion of the target sine wave signal under multiple initial high-frequency square wave signals is less than the third preset value, and the attenuation of the third harmonic corresponding to the target sine wave signal is greater than the preset attenuation threshold, then the compatibility of the test board is determined to meet the preset requirements.

[0069] In some implementations, a 5MHz target sine wave output by the test board can be tested, and the THD harmonic attenuation of the target sine wave signal can be obtained. If it is determined that the THD of the target sine wave signal is ≤ a third preset value (e.g., 1.5%), and the 3rd harmonic attenuation is ≥ a preset attenuation threshold (e.g., 45dB), it indicates that the multi-frequency adaptation capability of the test board meets the preset requirements.

[0070] In summary, by applying the embodiments of this application, the test board and the target sine wave signal output by the test board can be tested in multiple dimensions, which can improve the reliability of the test board of this application and ensure the applicability of the test board in chip aging test scenarios.

[0071] Figure 3 A comparison waveform diagram of an initial high-frequency square wave signal and a target sine wave signal provided in an embodiment of this application, wherein, as shown... Figure 3 As shown, the horizontal axis represents time (100ns / div), and the vertical axis represents voltage (1V / div). It can be seen that the amplitude of the initial high-frequency square wave signal is 3.3V (peak-to-peak), the rise time is ≤10ns, the duty cycle is 50%, and the frequency of the initial high-frequency square wave signal is 10MHz. The amplitude of the target sine wave signal is 1.5V (peak-to-peak), the total harmonic distortion (THD) is 1.2% (satisfying THD≤1.5%), the target frequency of the target sine wave signal is 10MHz, and the waveform has no obvious distortion, which meets the excitation requirements of the chip under test for aging test.

[0072] It should be noted that in practical applications, if the amplitude of the target sine wave signal does not meet the preset amplitude requirement, the amplitude of the initial high-frequency square wave signal can be adjusted until the amplitude of the target sine wave signal meets the amplitude requirement.

[0073] In summary, tests have shown that the test board provided in this application embodiment can ensure that the test frequency, amplitude, signal attenuation, and signal distortion of the sinusoidal signal input to the chip under test meet the signal quality requirements.

[0074] In an optional implementation, the target sinusoidal signal may further satisfy the following requirements: The attenuation of the target sinusoidal signal in the passband corresponding to the Nth-order passive LC low-pass filter 130 is less than the first attenuation threshold. The third harmonic of the target sinusoidal signal is within the stopband of the Nth-order passive LC low-pass filter 130, and the attenuation of the third harmonic is greater than the second attenuation threshold. The Mth harmonic of the target sine wave signal is located within the stopband of the Nth-order passive LC low-pass filter 130, and the attenuation of the Mth harmonic is greater than the third attenuation threshold. M is an odd number greater than 5, and the second attenuation threshold is less than the third attenuation threshold.

[0075] Optionally, the first attenuation threshold can be 0.1dB, the second attenuation threshold can be 40dB, and the third attenuation threshold can be 60dB.

[0076] It should be noted that, with a preset multiplier of 1.5, the target frequency of the target sine wave signal is set to f_s. (i.e., the fundamental frequency of the square wave f0 = f_s) Then the corresponding filter cutoff frequency f_c =1.5f_s To ensure that the Nth-order passive LC low-pass filter 130 meets the following conditions: The target sinusoidal signal attenuates by ≤0.1dB within the passband to ensure amplitude stability; the third harmonic (3f_s) The signal is located in the stopband, with attenuation ≥40dB, to avoid harmonic interference during chip testing; 5th and higher harmonics (≥5f_s) The attenuation is ≥60dB, which meets the stringent requirements of the chip under test for excitation signal distortion (THD≤1.5%).

[0077] In an optional implementation, the miniature buffer circuit 120, the N-order passive LC low-pass filter 130, and the impedance matching resistor are mounted on the test PCB board 110 using surface mount technology.

[0078] Optionally, during assembly, surface mount technology (SMT) can be used to sequentially solder surface mount resistors, capacitors, transistors and other electronic components to ensure that the component pins are aligned with the pads in the test PCB 110, with a soldering temperature of 230℃±5℃.

[0079] In addition, it should be noted that if the interface connecting the input terminal of the chip under test is a spring pin interface, the spring pin interface can be manually soldered to the designated position on the test PCB board 110 to ensure that the interface is firm and there is no cold solder joint; of course, after the assembly of the test PCB board 110 is completed, a multimeter can also be used to measure the continuity of the circuit to ensure that the grounding is reliable, there is no short circuit, and the capacitors are not broken down.

[0080] Regarding the setup of the test PCB 110, it should be noted that the test PCB 110 can use FR-4 material (dielectric constant 4.4±0.2) with a thickness of 1.6mm to accommodate aging tests; the spacing between the surface mount inductors and capacitors in the N-order passive LC low-pass filter 130 should be ≥0.5mm (to avoid magnetic coupling), and multi-point grounding should be used (one grounding via with a diameter of 0.6mm is set for every two LC units) to reduce grounding impedance; in addition, the input / output trace width can be 0.3mm (to match the characteristic impedance of 50Ω) and the length ≤8mm, using impedance-controlled routing to reduce signal loss within the test PCB 110; a 0.5mm×0.5mm copper area is reserved in the miniature buffer circuit 120 to enhance heat dissipation and prevent the NPN transistor from overheating during high-temperature testing.

[0081] Regarding the aforementioned test board, it should also be noted that if this test board is required to test and generate a target frequency of f_s... If the target value is a sinusoidal signal, the aforementioned method can be used to calculate each capacitor and inductor in the N-order passive LC low-pass filter 130. This allows for the replacement of each capacitor and inductor in the N-order passive LC low-pass filter 130 using SMT technology without changing the PCB topology. This enables convenient parameter optimization to adapt to the testing requirements of different chips (1MHz-100MHz), reducing testing costs and operational complexity.

[0082] In summary, it can be seen that the test board provided in this application embodiment can be miniaturized and integrated; it can improve the stability of the test board in high temperature environment (40℃-125℃), and ensure low excitation signal distortion and stable parameters during long-term aging test; in addition, it can reduce test cost and operation complexity by conveniently optimizing parameters to adapt to the test requirements of different chips (1MHz-100MHz).

[0083] Figure 4 This application provides a flowchart illustrating a test method for chip aging testing. The execution entity of this method can be a controller on a driver board in the test system. For a description of the test system, please refer to the relevant content below. Figure 4 As shown, the method may include: S101. Obtain the attribute parameters of the target sine wave signal output by the test board used for chip aging test.

[0084] The attribute parameters include at least one of the following: the target frequency of the target sine wave signal, the total harmonic distortion value, the third harmonic attenuation value, and the amplitude parameter.

[0085] S102. Based on the attribute parameters of the target sine wave signal, determine whether the target sine wave signal meets the requirements of the input terminal of the chip under test for the excitation signal.

[0086] The test board for chip aging testing, based on the above embodiments, can further test whether the target sine wave signal output by the test board meets the requirements of the input terminal of the chip under test for the excitation signal.

[0087] Optionally, the requirements for the excitation signal at the input of the chip under test may include: distortion requirements, stability requirements, etc. In some embodiments, the distortion requirement can be that the THD of the target sine wave signal is less than a first preset value (e.g., 1.5%), and the stability requirement can be that the total harmonic distortion of the target sine wave signal under a preset temperature condition within a preset time period is less than a second preset value (e.g., 0.3%), and the amplitude fluctuation is ≤ a preset amplitude threshold (e.g., ±2%). Of course, the specific settings of each requirement are not limited to these.

[0088] Optionally, the preset detection interface of the controller on the driver board can be connected to the output interface of the test board (i.e., Figure 2 The VF2 interface in the chip calculates the attribute parameters of the target sine wave signal through Fast Fourier Transform (FFT), such as total harmonic distortion, third harmonic attenuation, and amplitude parameters. By analyzing the attribute parameters of the target sine wave signal, it can be determined whether the target sine wave signal meets the requirements of the input terminal of the chip under test for the excitation signal.

[0089] In summary, the test method for chip aging testing provided in this application embodiment can achieve reliability testing of the test board and improve the applicability of the test board by determining whether the target sine wave signal meets the requirements of the input terminal of the chip under test for the excitation signal.

[0090] Figure 5 This is a schematic flowchart of another test method for chip aging testing provided in an embodiment of this application. In optional implementations, such as... Figure 5 As shown, the above determination of whether the target sine wave signal meets the requirements of the input terminal of the chip under test for the excitation signal based on the attribute parameters of the target sine wave signal includes: S201. If the total harmonic distortion value of the target sine wave signal is determined to be less than the first preset value, then the distortion of the target sine wave signal is determined to meet the preset distortion test requirements.

[0091] S202. If the total harmonic distortion of the target sine wave signal under the preset temperature condition within the preset time period is less than the second preset value, and the amplitude parameter of the target sine wave signal meets the preset amplitude parameter requirements, then the stability of the target sine wave signal is determined to meet the preset stability requirements.

[0092] Optionally, the testing of the target sinusoidal signal may include: distortion testing and high-temperature stability testing. For details on the specific test content, please refer to the relevant content mentioned above, which will not be repeated here. Figure 6 This is a schematic flowchart of another test method for chip aging testing provided in an embodiment of this application. In optional implementations, such as... Figure 6 As shown, the above method also includes: S301. If, based on the attribute parameters of the target sine wave signal, it is determined that the target sine wave signal does not meet the requirements of the input terminal of the chip under test for the excitation signal, then adjust the Nth order of the passive LC low-pass filter in the test board.

[0093] In some implementations, if the target sine wave signal is determined to be inconsistent with the excitation signal requirements of the input terminal of the chip under test based on the attribute parameters of the target sine wave signal, the order N of the passive LC low-pass filter in the test board can be adjusted by referring to the Butterworth normalized parameter table mentioned above. For example, the current order N can be adjusted to N+2, and then the test can be performed again until the target sine wave signal output by the test board meets the excitation signal requirements of the input terminal of the chip under test. This can improve the flexibility and applicability of the test board of this application.

[0094] Figure 7 This is a schematic diagram of a test system for chip aging testing provided in an embodiment of this application, wherein, as shown... Figure 7 As shown, the chip aging test system may include: a test board 200, at least one chip under test (DUT) 140, and a driver board 230. The output terminal of the driver board 230 is electrically connected to the input terminal of the micro-buffer circuit 120 in the test board 200, for inputting an initial high-frequency square wave signal to the micro-buffer circuit 120. The output terminal of the test board 200 (i.e., the output terminal of the Nth-order passive LC low-pass filter 130) is electrically connected to the input terminal of the DUT 140, for inputting a target sine wave signal to the DUT 140. It should be noted that, depending on the actual application scenario, this application does not limit the number of test boards 200 in the chip aging test system. It may include one or more, specifically determined based on the number of DUT chips 140 and the required sine wave signal for the DUT chips 140.

[0095] The target sine wave signal has a frequency of 1MHz-100MHz, and the chip under test 140 is a chip that needs to input the target sine wave signal, such as an analog chip, an RF chip, or a mixed signal chip.

[0096] Optionally, referring to the foregoing description, the test board 200 can convert a high-frequency square wave signal (1MHz-100MHz) into a low-distortion sine wave signal. In a specific setting, the chip under test 140 can be placed in a chip under test 140 fixture. The fixture is used to support the chip under test 140. Probes are set on the fixture. The chip under test 140 is electrically connected to the output terminal of the Nth-order passive LC low-pass filter in the test board 200 through the probes.

[0097] Optionally, the test board 200 can provide a mounting platform for at least one chip under test (DUT) 140, ensuring that the DUT 140 can be accurately fixed in a specific position. Simultaneously, the test board 200 indirectly connects the DUT 140 to the driver board 230 via spring pins or cables, establishing an electrical connection. This allows the initial high-frequency square wave signal output from the driver board 230 to be accurately transmitted to the DUT 140 after conversion during testing, and also allows the driver board 230 to feed back the response signal from the DUT 140, thus achieving the testing of the DUT 140.

[0098] In some implementations, during specific chip aging tests, the test board 200 and the chip under test 140 can be placed together in the aging chamber.

[0099] The driver board 230 is used to provide a continuous and stable initial excitation signal (such as an initial high-frequency square wave signal) to the chip under test 140, driving the chip under test 140 to operate for a long time under accelerated stress conditions such as high temperature and high voltage, simulating its working state during its life cycle; at the same time, the driver board 230 can also precisely control the parameters (amplitude, frequency, etc.) of the initial excitation signal to ensure that it matches the actual operating conditions of the chip and trigger potential failure mechanisms; the collaborative test system monitors the output changes of the chip during the aging process, providing dynamic driving support for evaluating performance degradation and reliability.

[0100] In summary, the embodiments of this application provide a testing system that enables the setup of a test board with fewer basic circuit components, resulting in low testing costs and a small footprint. Furthermore, through the combined action of the miniature buffer circuit 120, the N-order passive LC low-pass filter 130, and the impedance matching resistor in the test board, not only can the initial high-frequency square wave signal be converted into a target sine wave signal, but the provided test board can also operate stably in high-frequency, long-term operation, and high-temperature aging test scenarios, significantly improving the signal quality of the target sine wave signal.

[0101] In the embodiments provided in this application, for example, the division of units is merely a logical functional division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be indirect couplings or communication connections through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0102] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0103] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.

[0104] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0105] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

Claims

1. A test board for chip aging testing, characterized in that, The test board includes: a test PCB board, a miniature buffer circuit located on the test PCB board, an N-order passive LC low-pass filter, an impedance matching resistor, and a chip under test; The micro buffer circuit is used to adjust the input initial high-frequency square wave signal to a target high-frequency square wave signal, wherein the amplitude of the initial high-frequency square wave signal is smaller than the amplitude of the target high-frequency square wave signal. The Nth-order passive LC low-pass filter is used to convert the target high-frequency square wave signal into a target sine wave signal, wherein the target frequency of the target sine wave signal is the same as the initial frequency of the initial high-frequency square wave signal. The chip under test is used to receive the target sine wave signal and perform chip aging test under the excitation of the target sine wave signal to verify the stability and reliability of the chip under test. The micro buffer circuit has an input terminal for inputting an initial high-frequency square wave signal, an output terminal for electrically connecting to the input terminal of the Nth-order passive LC low-pass filter, an output terminal for electrically connecting to one end of the impedance matching resistor and the input terminal of the chip under test, and the other end of the impedance matching resistor is grounded. The value of N is an even number greater than 2.

2. The test board according to claim 1, characterized in that, The miniature buffer circuit includes: a first resistor, a third resistor, an NPN transistor, and a preset power supply. An initial high-frequency square wave signal is input to one end of the first resistor, and the other end of the first resistor is electrically connected to the base of the NPN transistor. One end of the preset power supply is grounded, and the other end is electrically connected to the collector of the NPN transistor; The emitter of the NPN transistor and one end of the third resistor are electrically connected to the input of the Nth-order passive LC low-pass filter. One end of the third resistor is connected to the emitter of the NPN transistor, and the other end of the third resistor is grounded.

3. The test board according to claim 1, characterized in that, The Nth-order passive LC low-pass filter includes N capacitors and N inductors. The capacitance value of each capacitor and the inductance value of each inductor are determined based on the target frequency of the target sine wave signal, the Butterworth normalized parameter table, and / or preset simulation software.

4. The test board according to claim 3, characterized in that, The capacitance value of each capacitor is determined based on the normalized capacitance value corresponding to each capacitor and the target frequency of the target sine wave signal. The normalized capacitance value corresponding to each capacitor is determined based on the target frequency of the target sine wave signal according to the Butterworth normalization parameter table. The inductance value of each inductor is determined based on the normalized inductance value corresponding to each inductor and the target frequency of the target sine wave signal. The normalized inductance value corresponding to each inductor is determined based on the target frequency of the target sine wave signal according to the Butterworth normalization parameter table.

5. The test board according to claim 1, characterized in that, The attenuation of the target sinusoidal signal in the passband corresponding to the Nth-order passive LC low-pass filter is less than the first attenuation threshold. The third harmonic of the target sine wave signal is located within the stopband of the Nth-order passive LC low-pass filter, and the attenuation of the third harmonic is greater than the second attenuation threshold. The Mth harmonic of the target sine wave signal is located within the stopband of the Nth-order passive LC low-pass filter, and the attenuation of the Mth harmonic is greater than the third attenuation threshold. M is an odd number greater than 5, and the second attenuation threshold is less than the third attenuation threshold.

6. The test board according to claim 1, characterized in that, The miniature buffer circuit, the Nth-order passive LC low-pass filter, the impedance matching resistor, and the chip under test are mounted on the test PCB using surface mount technology.

7. The test board according to claim 2, characterized in that, The third resistor is used to match the impedance between the output of the micro buffer circuit and the input of the Nth-order passive LC low-pass filter.

8. The test board according to claim 1, characterized in that, The impedance matching resistor is used to match the impedance between the output of the Nth-order passive LC low-pass filter and the input of the chip under test.

9. The test board according to any one of claims 1-8, characterized in that, The total harmonic distortion value of the target sine wave signal is less than a first preset value, so that the distortion of the target sine wave signal input to the chip under test meets the preset distortion test requirements.

10. The test board according to claim 9, characterized in that, The total harmonic distortion value of the target sine wave signal under a preset temperature condition within a preset time period is less than a second preset value, and the amplitude parameter of the target sine wave signal meets the preset amplitude parameter requirements, so that the stability of the target sine wave signal input to the chip under test meets the preset stability requirements.

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