Chip testing method, asynchronous testing device, computer equipment and medium

Abstract

The application relates to a chip testing method, an asynchronous testing device, computer equipment and a medium. The method comprises the following steps: when a testing machine is started, a testing start signal of the testing machine is received through an input and output interface; the testing start signal is transmitted to a chip to be tested through an asynchronous interface, so that the chip to be tested is started based on the testing start signal; a response signal of the chip to be tested is received through the asynchronous interface; the input and output interface is controlled to output a sampling signal to the testing machine based on the response signal, so that the testing machine starts sampling based on the sampling signal; a testing end signal of the chip to be tested is received through the asynchronous interface; the input and output interface is controlled to output the testing end signal to the testing machine based on the testing end signal, so that the testing machine ends sampling based on the testing end signal and generates a testing result. The method can improve the accuracy of the testing result without increasing the complexity of a script.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a chip testing method, asynchronous testing device, computer equipment, and medium. Background Technology

[0002] With the development of science and technology, the quality requirements for semiconductor chips are becoming increasingly stringent, making chip testing particularly important. However, during automated chip testing using Automatic Test Equipment (ATE), the ATE's digital channel card drives and samples the device under test (DUT) using a fixed-frequency clock signal. If the DUT interface is an asynchronous interface without a clock, the ATE cannot directly provide a clock that matches the DUT's asynchronous timing. This prevents the test equipment from knowing the valid data window, forcing it to blindly sample using oversampling. This sampling method is prone to problems such as sampling out-of-sync due to missing synchronous clocks, misjudgments caused by trigger alignment difficulties, sampling glitches caused by missing clock recovery circuits, and metastability caused by cross-domain issues between the ATE clock domain and the DUT clock domain, ultimately affecting the accuracy of the test results.

[0003] To address this issue, technicians typically compensate by designing complex test scripts. However, script-based compensation can lead to a significant increase in development time and maintenance costs.

[0004] Therefore, how to test the chip under test using a test machine without increasing the complexity of the script, so as to improve the accuracy of the test results, is a problem that needs to be solved. Summary of the Invention

[0005] Therefore, it is necessary to provide a chip testing method, asynchronous testing device, computer equipment, and medium to address the aforementioned technical problems, so as to improve the accuracy of test results without increasing script complexity.

[0006] In a first aspect, this application provides a chip testing method applied in an asynchronous testing device, wherein the asynchronous testing device is connected to a testing machine via an input / output interface and is connected to an asynchronous interface of the chip under test, the method comprising:

[0007] When the test equipment starts testing, the test start signal of the test equipment is received through the input / output interface;

[0008] The test start signal is transmitted to the chip under test through the asynchronous interface, so that the chip under test can start the test based on the test start signal;

[0009] The response signal from the chip under test is received through the asynchronous interface. The response signal is generated by the chip under test based on the test start signal.

[0010] Based on the response signal, the input / output interface is controlled to output a sampling signal to the test equipment, so that the test equipment starts to perform test sampling based on the sampling signal.

[0011] The test end signal of the chip under test is received through the asynchronous interface;

[0012] Based on the test end signal, the input / output interface is controlled to output a test end signal to the test machine, so that the test machine ends sampling based on the test end signal and generates test results.

[0013] In one embodiment, the input / output interface includes a first input / output interface, a second input / output interface, and a third input / output interface;

[0014] Receiving the test start signal of the test machine through the input / output interface includes: obtaining the test start signal of the test machine when the level signal of the first input / output interface changes from a first state to a second state, wherein the first state is the state of the level signal of the first input / output interface when the test machine is idle, and the second state is the state of the level signal of the first input / output interface when the test machine starts testing;

[0015] The step of controlling the input / output interface to output a sampling signal to the test equipment based on the response signal includes: controlling the state of the level signal of the second input / output interface to change from a third state to a fourth state based on the response signal, so that the second input / output interface outputs a sampling signal to the test equipment. The third state is the level signal state of the second input / output interface when the test equipment is not sampling, and the fourth state is the level signal state of the second input / output interface during the sampling process of the test equipment.

[0016] The step of controlling the input / output interface to output a test end signal to the test equipment based on the test end signal includes: controlling the level signal of the third input / output interface to change from a fifth state to a sixth state based on the test end signal, and controlling the level signal of the second input / output interface to switch from the fourth state to the third state, so that the third input / output interface outputs a test end signal to the test equipment until the test end signal of the chip under test is completed, and controlling the level signal of the third input / output interface to change from the sixth state to the fifth state, where the fifth state is the level signal state of the third input / output interface when the chip under test has not output a test end signal, and the sixth state is the level signal state of the third input / output interface when the chip under test outputs a test end signal.

[0017] In one embodiment, the method further includes:

[0018] When the test equipment is in an idle state, the idle signal of the test equipment is received through the first input / output interface;

[0019] The asynchronous testing device is controlled to be in an idle state based on the idle signal;

[0020] The idle signal is transmitted to the chip under test through the asynchronous interface, so that the asynchronous interface of the chip under test enters an idle state based on the idle signal.

[0021] In one embodiment, receiving the response signal from the chip under test via the asynchronous interface includes:

[0022] The initial response signal of the chip under test is received based on the asynchronous interface, and the initial response signal is generated by the chip under test based on the test start signal.

[0023] Based on the initial response signal and the transmission protocol of the chip under test, the initial response signal is converted to obtain the response signal of the chip under test.

[0024] In one embodiment, the input / output interface further includes a fourth input / output interface, and the method further includes:

[0025] The test pause signal from the test machine is received based on the fourth input / output interface;

[0026] Based on the pause test signal, the chip under test is controlled to pause the test via the asynchronous interface.

[0027] In one embodiment, a plurality of asynchronous testing devices are arranged between the testing machine and the chip under test, each of the asynchronous testing devices being used to test the function corresponding to the chip under test, and the method further includes:

[0028] The asynchronous test device switching signal of the test machine is received through the fifth interface corresponding to each of the asynchronous test devices.

[0029] Based on the asynchronous test device switching signal, the current asynchronous test device is disconnected from the chip under test, so that the test bench can be connected to the next asynchronous test device to perform the next function test on the chip under test.

[0030] In one embodiment, after controlling the input / output interface to output a test end signal to the test machine based on the test end signal, the method further includes:

[0031] The test completion signal of the chip under test is received through the asynchronous interface;

[0032] Based on the completion signal, the asynchronous testing device is controlled to be in an idle state.

[0033] Secondly, this application also provides an asynchronous testing device, which is connected to a testing machine via an input / output interface and to an asynchronous interface of the chip under test. The asynchronous testing device includes:

[0034] The first receiving unit is used to receive the test start signal of the test machine through the input / output interface when the test machine starts testing;

[0035] The first transmission unit is used to transmit the test start signal to the chip under test through the asynchronous interface, so that the chip under test can start the test based on the test start signal;

[0036] The second receiving unit is used to receive the response signal of the chip under test through the asynchronous interface. The response signal is generated by the chip under test based on the test start signal.

[0037] The second transmission unit is used to control the input / output interface to output a sampling signal to the test equipment based on the response signal, so that the test equipment can start performing test sampling based on the sampling signal.

[0038] The second receiving unit is also used to receive the test end signal of the chip under test through the asynchronous interface;

[0039] The third transmission unit is used to control the input / output interface to output a test end signal to the test machine based on the test end signal, so that the test machine ends sampling based on the test end signal and generates test results.

[0040] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the chip testing method in any of the above embodiments.

[0041] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the chip testing method in any of the above embodiments.

[0042] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the chip testing method in any of the above embodiments.

[0043] The aforementioned chip testing method, asynchronous testing device, computer equipment, and medium, by setting up an asynchronous testing device between the test bench and the chip under test (DUT), and connecting the asynchronous testing device to the test bench via an input / output interface and to the asynchronous interface of the DUT, respectively achieves connection between the asynchronous testing device and both the test bench and the DUT. When the test bench starts testing, the asynchronous testing device transmits a test start signal from the test bench to the DUT, thus notifying the test bench to begin testing the DUT. Further, the DUT performs testing according to the test start signal, and during the testing process, when the DUT begins generating test data, it sends a response signal to the asynchronous testing device. The asynchronous testing device, based on this response signal, sends a sampling signal to the test bench via the input / output interface, allowing the test bench to obtain the time of test data generation from the DUT and begin sampling the DUT at this time. Finally, when the DUT finishes testing, it sends a test end signal to the asynchronous testing device, which then transmits the test end signal to the test bench. The test bench then terminates sampling of the DUT based on this test end signal and outputs the test results. In asynchronous testing, this method enables the testing equipment to accurately determine the data generation and test end times of the chip under test (DUT), and to begin and end sampling at the corresponding times. This eliminates the need for blind sampling via oversampling, effectively resolving issues such as sampling synchronization problems caused by missing synchronous clocks of the DUT, misjudgments due to trigger alignment difficulties, sampling glitches caused by missing clock recovery circuits, and metastability caused by cross-domain communication between the ATE and DUT clocks. Furthermore, this process eliminates the need for technicians to add numerous test scripts for time synchronization and avoids increasing the clock load on the testing equipment. This allows for accurate testing of the DUT without increasing script complexity, ensuring precise control of sampling start and end times and effectively improving the accuracy of test results. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram illustrating an application scenario of a chip testing method provided in an embodiment of this application;

[0046] Figure 2 This is a flowchart of a chip testing method provided in an embodiment of this application;

[0047] Figure 3 This is a schematic diagram of the interface of an asynchronous testing device provided in an embodiment of this application;

[0048] Figure 4 This is a schematic diagram of the structure of an asynchronous testing device provided in an embodiment of this application;

[0049] Figure 5 This is a schematic diagram of the structure of a testing system provided in an embodiment of this application;

[0050] Figure 6 This is a timing diagram of each signal line during a test provided in an embodiment of this application;

[0051] Figure 7 This is a schematic diagram of the structure of the second asynchronous testing device provided in the embodiments of this application;

[0052] Figure 8 This is an internal structural diagram of a computer device provided in an embodiment of this application. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0054] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0055] With the development of science and technology, the quality requirements for semiconductor chips are becoming increasingly stringent, making chip testing particularly important. However, during automated chip testing using Automatic Test Equipment (ATE), the ATE's digital channel card drives and samples the device under test (DUT) using a fixed-frequency clock signal. If the DUT interface is an asynchronous interface without a clock, the ATE cannot directly provide a clock that matches the DUT's asynchronous timing. This prevents the test equipment from knowing the valid data window, forcing it to perform blind sampling via oversampling. However, blind sampling via oversampling is prone to the following problems:

[0056] (1) Sampling asynchrony caused by missing synchronization clock

[0057] In mainstream ATE (Advantest V93000, Teradyne UltraFLEX, NI STS) architectures, digital channel cards drive vector cycles with a fixed system clock (typically 50MHz to 1GHz). If the device under test (DUT) interface uses a clockless asynchronous protocol (such as UART, LIN, SWD, CAN-FD, I²C slave mode, etc.), the test equipment cannot know the effective data window and can only blindly sample using oversampling. Taking a 9600bps UART as an example, each bit width is approximately 104µs; if the test equipment oversamples at 100MHz, it needs to continuously sample 10400 times within each bit cycle and buffer the waveform, resulting in tens of MB of data per test. UltraFLEX single-channel onboard storage depth is only 32Msample. When parallel testing reaches ≥16 sites, storage resources are instantly exhausted, necessitating a reduction in parallelism or batch testing, leading to a decrease in throughput of over 30%.

[0058] (2) Misjudgment caused by difficulty in triggering alignment

[0059] ATE scripting languages ​​(such as Smarts, IG-XL, and TestStand) are all based on periodic vector descriptions. Test equipment script engineers need to manually estimate the arrival time of asynchronous events within the DUT and insert "wait" or "match loop" into the script. Due to process fluctuations and temperature drift, the event arrival time has a jitter of ±2% to ±5%; taking a 115200bps UART as an example, ±5% jitter ≈ ±43ns, while the minimum programmable step of an ATE channel is 1UI (10ns@100MHz). The script must widen the matching window to ±50ns, resulting in a false trigger probability P≈1-exp(-2×50ns / 104µs)=0.1%; in mass production of 1000 site-hours, the cumulative false alarm rate can reach 1%, seriously affecting yield statistics.

[0060] (3) Glitches caused by missing clock recovery circuit

[0061] For "semi-synchronous" interfaces like I²C and SPI-slave, the DUT only outputs data on the rising edge of the SCK, but the ATE cannot provide an SCK of the same origin as the DUT, and can only treat the SCK as a regular GPIO readback. If there is a 3ns skew on the SCK trace at the board level, the sampling edge of the test equipment will be misaligned with the DUT's output window, resulting in glitches in the data sampling. Taking a 1MHz SPI as an example, the effective data window is only 500ns, and a 3ns skew can cause a bit error rate of 0.6%; if we further consider the ±25ppm crystal oscillator drift, the cumulative drift after 24 hours of continuous testing is 2.16ms, which is completely outside the sampling window.

[0062] (4) Cross-domain problem between machine clock domain and DUT clock domain

[0063] Modern SoCs often dynamically switch their internal clocks (gating, frequency division, PLL switching). The fixed clock provided by the ATE (Automatic Test Equipment) cannot track changes in the DUT's clock domain, leading to cross-domain metastability. For example, if a BLE chip's clock jumps from 32kHz to 16MHz during the Sleep→Active switch, and the ATE still samples at a fixed 50MHz, a metastability window of >200ns will appear, making it impossible to capture the wake-up handshake sequence.

[0064] (5) Increased script complexity and maintenance costs

[0065] Existing ATE (Automatic Equipment) systems are generally based on a synchronous parallel architecture design, with their digital channel cards driving and sampling the DUT (Device Under Test) using a fixed-frequency clock signal. However, with the widespread adoption of asynchronous or half-duplex interfaces such as UART, I2C, CAN, LIN, and SPI-slave-mode by IoT chips, sensor modules, and low-power MCUs, ATE systems cannot directly provide a clock that matches the asynchronous timing of the DUT. For I²C, byte-by-byte ACK / NACK handshakes are required; for CAN-FD, real-time CRC calculation and bit stuffing detection are necessary. Taking a certain automotive-grade MCU project as an example, the traditional synchronous script is about 200 lines, while the asynchronous compatible script expands to 1800 lines, extending the development cycle from 1 person-week to 6 person-weeks; subsequent timing adjustments due to DUT firmware upgrades result in script maintenance costs exceeding 0.5 person-years per year.

[0066] Therefore, how to test the chip under test using a test machine without increasing the complexity of the script, so as to improve the accuracy of the test results, is a problem that needs to be solved.

[0067] The chip testing method provided in this application embodiment can be applied to, for example, Figure 1 The application environment shown. Figure 1 This is a schematic diagram illustrating an application scenario of a chip testing method provided in an embodiment of this application, such as... Figure 1 As shown, this chip testing method can be applied to Figure 1 In the asynchronous testing device, the asynchronous testing device 102 is connected to the testing machine 101 through the input / output interface and is also connected to the asynchronous interface of the chip under test 103. In addition, the testing machine 101 can also be directly connected to the synchronous interface of the chip under test 103 for synchronous data acquisition.

[0068] In one exemplary embodiment, Figure 2 This is a flowchart of a chip testing method provided in an embodiment of this application, which is applied to... Figure 1 The asynchronous test device 102 in the example is used for illustration. Figure 2As shown, the method may include the following steps:

[0069] Step 201: When the test machine starts testing, receive the test start signal from the test machine through the input / output interface.

[0070] Step 202: Transmit the test start signal to the chip under test through the asynchronous interface so that the chip under test can start the test based on the test start signal.

[0071] Step 203: Receive the response signal from the chip under test through the asynchronous interface. The response signal is generated by the chip under test based on the test start signal.

[0072] Step 204: Based on the response signal, control the input / output interface to output a sampling signal to the test equipment so that the test equipment can start testing based on the sampling signal.

[0073] Step 205: Receive the test completion signal from the chip under test via the asynchronous interface.

[0074] Step 206: Based on the test end signal, the control input / output interface outputs a test end signal to the test machine, so that the test machine ends sampling based on the test end signal and generates test results.

[0075] For example, the asynchronous test device 102 is connected to the test machine 101 through an input / output interface. Specifically, the input / output interface can be a general purpose input / output interface (GPIO), and the asynchronous test device 102 is connected to the asynchronous interface of the chip under test (DUT) 103.

[0076] When the test equipment starts testing, it sends a test start signal to the asynchronous test device, which then receives the signal through its input / output interface. Further, the asynchronous test device transmits this test start signal to the chip under test (DUT) via an asynchronous interface, allowing the DUT to receive the test start signal and initiate testing accordingly.

[0077] Furthermore, during the testing process, the chip under test (DUT) feeds back a response signal to the asynchronous testing device via an asynchronous interface. This allows the asynchronous testing device to receive the response signal from the DUT through the asynchronous interface. The response signal is generated by the DUT based on the test start signal and may include the test data of the DUT.

[0078] Furthermore, when the asynchronous testing device starts receiving the response signal, it controls the input / output interface to output a sampling signal to the testing machine based on the response signal. This causes the testing machine to start sampling the test data of the chip under test based on the sampling signal. In this way, the specific time point for the test sampling is notified to the testing machine, so that the testing machine does not need to blindly sample by oversampling.

[0079] Furthermore, when the test of the chip under test (DUT) ends, the DUT sends a test end signal to the asynchronous test device via an asynchronous interface. The asynchronous test device receives the test end signal from the DUT via an asynchronous interface and, based on this signal, controls the input / output interface to send a test end signal to the test machine. This notifies the test machine that the test of the DUT has ended, allowing the test machine to terminate the test sampling of the DUT based on the test end signal and output the test results based on the sampled data. As another example, the test end signal may include the test results. Taking the UART interface scenario as an example, the frame format of the 9600bps UART output test results can be: 0xAA (frame header) + 1 Byte result + 0x55 (frame tail).

[0080] In the above implementation process, an asynchronous testing device is set up between the test bench and the chip under test (DUT). This asynchronous testing device is connected to the test bench via an input / output interface and to the asynchronous interface of the DUT, thus achieving connections between the asynchronous testing device and both the test bench and the DUT. When the test bench starts testing, the asynchronous testing device transmits a test start signal from the test bench to the DUT, notifying the test bench to begin testing the DUT. Further, the DUT performs testing according to the test start signal. During the test, when the DUT begins generating test data, it sends a response signal to the asynchronous testing device. The asynchronous testing device then sends a sampling signal to the test bench via the input / output interface based on this response signal. This allows the test bench to obtain the time of test data generation from the DUT and begin sampling the DUT at this time. Finally, when the DUT finishes testing, it sends a test end signal to the asynchronous testing device, which then transmits the test end signal to the test bench. The test bench then terminates sampling of the DUT based on this test end signal and outputs the test results. In asynchronous testing, this method enables the testing equipment to accurately determine the data generation and test end times of the chip under test (DUT), and to begin and end sampling at the corresponding times. This eliminates the need for blind sampling via oversampling, effectively resolving issues such as sampling synchronization problems caused by missing synchronous clocks of the DUT, misjudgments due to trigger alignment difficulties, sampling glitches caused by missing clock recovery circuits, and metastability caused by cross-domain communication between the ATE and DUT clocks. Furthermore, this process eliminates the need for technicians to add numerous test scripts for time synchronization and avoids increasing the clock load on the testing equipment. This allows for accurate testing of the DUT without increasing script complexity, ensuring precise control of sampling start and end times and effectively improving the accuracy of test results.

[0081] In one embodiment, the input / output interface includes a first input / output interface, a second input / output interface, and a third input / output interface.

[0082] The test start signal of the test machine is received through the input / output interface, including: when the level signal of the first input / output interface changes from the first state to the second state, the test start signal of the test machine is obtained. The first state is the state of the level signal of the first input / output interface when the test machine is idle, and the second state is the state of the level signal of the first input / output interface when the test machine starts testing.

[0083] The input / output interface is controlled to output a sampling signal to the test equipment based on the response signal, including: controlling the state of the level signal of the second input / output interface to change from the third state to the fourth state based on the response signal, so that the second input / output interface outputs a sampling signal to the test equipment. The third state is the level signal state of the second input / output interface when the test equipment is not sampling, and the fourth state is the level signal state of the second input / output interface during the sampling process of the test equipment.

[0084] The system controls the input / output interface to output a test result signal to the test equipment based on the test result signal. This includes: controlling the level signal of the third input / output interface to change from the fifth state to the sixth state based on the test result signal, and controlling the level signal of the second input / output interface to switch from the fourth state to the third state, so that the third input / output interface outputs a test end signal to the test equipment until the test end signal of the chip under test is completed. The system then controls the level signal of the third input / output interface to change from the sixth state to the fifth state. The fifth state is the level signal state of the third input / output interface when the chip under test has not output a test end signal, and the sixth state is the level signal state of the third input / output interface when the chip under test outputs a test end signal.

[0085] For example, Figure 3 This is a schematic diagram of the interface of an asynchronous testing device provided in an embodiment of this application, such as... Figure 3 As shown, the input / output interface of the asynchronous testing device includes a first input / output interface, a second input / output interface, and a third input / output interface. Each input / output interface corresponds to a signal; specifically, the first input / output interface corresponds to the start signal, the second input / output interface corresponds to the test state signal, and the third input / output interface corresponds to the result signal.

[0086] As an example, taking the UART interface scenario, when the test equipment is idle, it controls the first input / output interface to output an IDLE level. At this time, the level of the first input / output interface is in the first state, which can be low. The asynchronous test device is in a high-impedance state, not driving the bus to avoid conflicts with the ATE (Automatic Test Equipment), and the asynchronous interface is idle. When the test equipment starts testing, it pulls the level of the first input / output interface high, switching it from a waiting level to a working level, i.e., switching the level of the first input / output interface from the first state to the second state, which is high. This allows the asynchronous test device to receive the high-level signal from the test equipment, i.e., the asynchronous test device receives the test start signal from the test equipment through the first input / output interface. This test start signal is then transmitted to the chip under test (DUT), causing the DUT to begin testing. At this point, the asynchronous test device exits the high-impedance state and takes over the first, second, and third input / output interfaces, maintaining the level of the first input / output interface at a high level within the same clock cycle to ensure a glitch-free bus.

[0087] Further, a start bit condition is generated based on the test protocol (such as UART) of the chip under test (DUT), and the formal test process begins. Specifically, when the DUT receives the test start signal, it enters the test process and generates test data. Then, when it begins generating test data, it sends a response signal to the asynchronous test device via an asynchronous interface. The asynchronous test device pulls the level signal of the second input / output interface high based on the response signal, allowing the test equipment to acquire the high-level signal through the second input / output interface. After acquiring the high-level signal, the test equipment begins to sample the DUT, thereby obtaining sampled data. In other words, when the test equipment does not need to sample, the level of the second input / output interface is low (third state). When the asynchronous test device receives the response signal, the level of the second input / output interface switches from low (third state) to high (fourth state), thus controlling the second input / output interface to output a sampling signal to the test equipment. Specifically, the sampled data can be obtained from the bus between the test equipment and the DUT. During the test sampling phase, the second input / output interface remains high until the asynchronous test device receives the test end signal from the DUT.

[0088] When the chip under test (DUT) finishes testing, it outputs a test completion signal to the asynchronous test state via an asynchronous interface. This signal may include the DUT's test result. Further, the asynchronous test device controls the level signal of the third input / output interface to switch from a fifth state to a sixth state. Specifically, the fifth state can be a reference state where the level signal of the third input / output interface is higher or lower than the reference state. As an example, the asynchronous test device determines whether the DUT's test result passes based on the test result in the test completion signal. When the DUT's test result passes, the sixth state is where the level signal of the third input / output interface is higher than the reference state; when the DUT's test result fails, the sixth state is where the level signal of the third input / output interface is lower than the reference state. This allows the test equipment to acquire the DUT's test completion signal. Furthermore, the asynchronous test device controls the level signal of the second input / output interface to switch from a high level to a low level, causing the test equipment to end the test sampling based on the low-level signal of the second input / output interface.

[0089] It should be noted that, in this embodiment of the application, the example is only taken as the test start signal being a high-level signal of the first input / output interface and the sampling signal being a high-level signal of the first input / output interface. In time-based applications, the test start signal can be a low-level signal of the first input / output interface and the sampling signal can be a low-level signal of the first input / output interface. The level of the signal is determined by the protocol of the chip under test, for example, when UART is high and CAN is recessive.

[0090] In the above implementation, the test bench and the asynchronous test device are connected via three general-purpose input / output interfaces. When the test bench starts testing, it switches the level signal of the first input / output interface to generate and transmit the test start signal. Then, the asynchronous test device switches the level signal of the corresponding second input / output interface to generate and transmit the sampling signal. Finally, the asynchronous test device switches the level signal of the corresponding second input / output interface to generate and transmit the sampling end signal. This method is extremely resource-efficient, requiring no additional scripts. The test bench does not need to provide any clock synchronization; only three level signal lines are needed to achieve asynchronous testing between the test bench and the chip under test, effectively improving the accuracy of the test results.

[0091] In one embodiment, the method may further include the following steps:

[0092] Step 1: When the test machine is in an idle state, receive the idle signal of the test machine through the first input / output interface.

[0093] Step 2: Control the asynchronous test device to be in an idle state based on the idle signal.

[0094] Step 3: Transmit the idle signal to the chip under test through the asynchronous interface so that the asynchronous interface of the chip under test enters the idle state based on the idle signal.

[0095] For example, when the test equipment is in an idle state, the test equipment can control the level of the first input / output interface to the IDLE level. At this time, the IDLE level is a low level with a falling edge, thereby enabling the asynchronous test device to receive the idle signal of the test equipment, and control the asynchronous test device to be in a high impedance state (Hi-Z) according to the idle signal, so as not to drive the bus, thereby avoiding conflict between the asynchronous test device and the ATE.

[0096] Furthermore, the asynchronous test device transmits an idle signal to the chip under test, thereby causing the asynchronous interface of the chip under test to enter an idle state and wait for triggering.

[0097] In the above implementation process, when the test equipment is in an idle state, the asynchronous test device and the asynchronous interface are controlled to be in an idle state, so that the test equipment does not need to continuously drive the bus, thereby achieving zero-conflict bus handover and minimum power consumption standby.

[0098] In one embodiment, receiving the response signal from the chip under test via an asynchronous interface may include the following steps:

[0099] Step 1: Receive the initial response signal from the chip under test (DUT) via an asynchronous interface. The initial response signal is generated by the DUT based on the test start signal.

[0100] Step 2: Based on the initial response signal and the transmission protocol of the chip under test, perform protocol conversion on the initial response signal to obtain the response signal of the chip under test.

[0101] For example, the transmission protocols corresponding to different functions of the chip under test may be different. Therefore, after the chip under test outputs an initial response signal according to the test start signal, the asynchronous test device performs protocol conversion on the initial response signal according to the transmission protocol of the chip under test to obtain a response signal, so that the obtained response signal can be adapted to the input / output interface.

[0102] Figure 4 This is a schematic diagram of the structure of an asynchronous testing device provided in an embodiment of this application, as shown below. Figure 4As shown, the asynchronous testing device 102 may include an asynchronous interface circuit 1021, a main control unit 1022, and a switch control path 1023. The asynchronous interface circuit 1021 is connected to the asynchronous interface of the chip under test and is used to perform protocol conversion on the initial response signal and test signal of the chip under test. The main control unit 1022 can control the switch control path 1023 according to the converted response signal and test signal, so that the switch control path 1023 controls the first input / output interface, the second input / output interface, and the third input / output interface respectively.

[0103] In addition, the asynchronous testing device 102 may include other control circuits connected to the main control unit 1022, which are used to control the pause test signal and other control signals between the asynchronous testing device and the testing machine.

[0104] In the above implementation process, by performing protocol conversion on the initial response signal of the chip under test, the converted response signal can be adapted to the input / output interface in the asynchronous test device.

[0105] In one embodiment, the input / output interface further includes a fourth input / output interface, and the method may further include the following steps:

[0106] Step 1: Receive the pause test signal from the test machine based on the fourth input / output interface.

[0107] Step 2: Based on the pause test signal, control the chip under test to pause the test via an asynchronous interface.

[0108] For example, the input / output interface between the test bench and the asynchronous test device may also include a fourth input / output interface, which can receive a pause test signal from the test bench and transmit the pause test signal to the chip under test through the asynchronous interface, thereby pausing the test of the chip under test.

[0109] In addition, the test bench and the asynchronous test device can also include other functional input / output interfaces, such as control signal interfaces and debug indicator signal interfaces. The debug indicator signal can work in conjunction with the pause test signal to enable the test bench to track and debug problems encountered during debugging. Furthermore, during the formal mass production process of the chip, the debug indicator signal or the pause test signal can be turned off or masked.

[0110] In the above implementation process, a fourth input / output interface for pausing test signals is set between the test machine and the asynchronous test device, so that problems in the test process can be tracked and investigated through pausing test signals during the test.

[0111] In one embodiment, multiple asynchronous testing devices are set between the test bench and the chip under test. Each asynchronous testing device is used to test the corresponding function of the chip under test. The method may further include the following steps:

[0112] Step 1: Receive the asynchronous test device switching signal from the test machine through the fifth interface corresponding to each asynchronous test device.

[0113] Step 2: Based on the asynchronous test device switching signal, control the current asynchronous test device to disconnect from the chip under test, so that the test machine can connect to the next asynchronous test device to perform the next function test on the chip under test.

[0114] For example, the chip under test (DUT) may include multiple functions, and an asynchronous test device can test at least one function. Therefore, multiple asynchronous test devices can be set between the test bench and the DUT. Each asynchronous test device is used to test a corresponding function of the DUT. When testing multiple functions of the DUT, each asynchronous test device can also be connected to the test bench through a fifth interface. The method may further include:

[0115] The asynchronous test device receives the asynchronous test device switching signal from the test machine via the fifth interface corresponding to each asynchronous test device. This asynchronous test device switching signal can be a BYPASS signal. The asynchronous test device controls the current asynchronous test device to disconnect from the chip under test according to the received asynchronous test device switching signal, thereby enabling the test machine to connect to the next asynchronous test device, thus realizing the testing of the next function of the chip under test.

[0116] Figure 5 This is a schematic diagram of the structure of a testing system provided in an embodiment of this application, such as... Figure 5 As shown, the testing system may include a test bench 101, a chip under test 103, and multiple asynchronous testing devices as described in any of the above embodiments. If the testing system includes N asynchronous testing devices, they can be bound to the corresponding asynchronous testing devices according to the function of the chip under test, so that each asynchronous testing device can perform the corresponding function test. As an example, when the asynchronous testing device 1 completes the corresponding function test, the test bench sends a BYPASS1 signal to the asynchronous testing device 1. After receiving the BYPASS1 signal, the asynchronous testing device 1 controls the asynchronous testing device 1 to disconnect from the test bench 101 according to the BYPASS1 signal. The test bench 101 can also send a BYPASSN signal to other asynchronous testing devices, such as asynchronous testing device N, so that asynchronous testing device N connects to the test bench 101 and performs the corresponding function test of the chip under test through asynchronous testing device N.

[0117] In the above implementation process, multiple asynchronous test devices are set in the test machine and the chip under test. The asynchronous test device receives the asynchronous test device switching signal of the test machine through the fifth interface of the corresponding asynchronous test device, and disconnects the current asynchronous test device from the test machine. The trigger signal of the test machine can be received through the fifth interface of the next asynchronous test device, and the connection between the next asynchronous test device and the test machine can be realized according to the trigger signal. In this way, the switching of multiple asynchronous test devices can be realized, thereby realizing the testing of different functions of the chip under test.

[0118] In one embodiment, after the test completion signal is output to the test machine via the control input / output interface based on the test completion signal, the following steps may also be included:

[0119] Step 1: Receive the completion signal of the test end signal from the chip under test through the asynchronous interface.

[0120] Step 2: Based on the completion signal, control the asynchronous test device to be in an idle state.

[0121] For example, after the chip under test (DUT) finishes testing, it sends a test end signal to the asynchronous testing device. This test signal may include test result data. Since the test result data has a certain amount of data, the test end signal will have a certain transmission time. After receiving the test end signal from the DUT, the device can also receive the completion signal of the test end signal from the DUT through the asynchronous interface. At this time, it indicates that the test end signal is complete.

[0122] Furthermore, once the test completion signal is received, the asynchronous test device can be controlled to enter an idle state based on the completion signal of the test completion signal. That is, the level signal of the corresponding first input / output interface is at the IDLE level, the asynchronous test device is in a high impedance state, and does not drive the bus.

[0123] Figure 6 This is a timing diagram of each signal line during a test provided in an embodiment of this application, such as... Figure 6 As shown, the signal lines during the test process can include a start signal line, a test signal line, a result signal line, a BYPASS signal line, a data transmit signal line, and a data receive signal line. The start signal line can be the signal line corresponding to the first input / output interface, the test signal line can be the signal line corresponding to the second input / output interface, the result signal line can be the signal line corresponding to the third input / output interface, the data transmit signal line can be the USART_TX signal line, and the data receive signal line can be the USART_RX signal line. Figure 6As shown, when the test equipment starts testing, it pulls the start signal line corresponding to the first input / output interface high and keeps it high throughout the test. When the asynchronous test device receives the response signal from the chip under test (DUT), it pulls the test signal line corresponding to the second input / output interface high, thus initiating test sampling. When the DUT outputs the test end signal, the asynchronous test device pulls the result signal line of the third input / output interface high and pulls the test signal line corresponding to the second input / output interface low, indicating the end of the current test sampling. This continues until the DUT outputs the test end signal. Then, it pulls the start signal line corresponding to the first input / output interface low, restoring the IDLE level of the first input / output interface, and pulls the result signal line of the third input / output interface low, indicating the completion of the current test. The asynchronous test device then enters a high-impedance state, waiting for the next trigger of the result signal line. Switching between asynchronous test devices can be achieved via the BYPASS signal line when the current asynchronous test device completes testing. Furthermore, during the test, test data can be sent and received via data transmission and data reception signal lines, respectively.

[0124] In the above implementation process, after the test is completed, the asynchronous test device is controlled to enter an idle state by the completion signal of the test end signal, so as to wait for the triggering of the next test start signal.

[0125] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0126] Based on the same inventive concept, this application also provides an asynchronous testing apparatus for implementing the chip testing method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more asynchronous testing apparatus embodiments provided below can be found in the limitations of the chip testing method described above, and will not be repeated here.

[0127] In one exemplary embodiment, Figure 7 This is a schematic diagram of the structure of the second asynchronous testing device provided in the embodiments of this application. The asynchronous testing device is connected to a testing machine via an input / output interface and to the asynchronous interface of the chip under test, such as... Figure 7 As shown, the asynchronous testing device includes:

[0128] The first receiving unit 701 is used to receive the test start signal of the test machine through the input / output interface when the test machine starts testing.

[0129] The first transmission unit 702 is used to transmit the test start signal to the chip under test through an asynchronous interface, so that the chip under test can start the test based on the test start signal.

[0130] The second receiving unit 703 is used to receive the response signal of the chip under test through an asynchronous interface. The response signal is generated by the chip under test based on the test start signal.

[0131] The second transmission unit 704 is used to control the input / output interface based on the response signal to output a sampling signal to the test equipment, so that the test equipment can start testing based on the sampling signal.

[0132] The second receiving unit 703 is also used to receive the test end signal of the chip under test through an asynchronous interface.

[0133] The third transmission unit 705 is used to control the input / output interface to output a test end signal to the test machine based on the test end signal, so that the test machine ends sampling based on the test end signal and generates test results.

[0134] In one embodiment, the input / output interface includes a first input / output interface, a second input / output interface, and a third input / output interface;

[0135] The first receiving unit 701 is specifically used to: obtain the test start signal of the test machine when the level signal of the first input / output interface changes from the first state to the second state. The first state is the state of the level signal of the first input / output interface when the test machine is idle, and the second state is the state of the level signal of the first input / output interface when the test machine starts testing.

[0136] The second transmission unit 704 is specifically used to: control the state of the level signal of the second input / output interface from the third state to the fourth state based on the response signal, so that the second input / output interface outputs a sampling signal to the test equipment. The third state is the level signal state of the second input / output interface when the test equipment is not sampling, and the fourth state is the level signal state of the second input / output interface during the sampling process of the test equipment.

[0137] The third transmission unit 705 is specifically used to: control the level signal of the third input / output interface to change from the fifth state to the sixth state based on the test end signal, and control the level signal of the second input / output interface to switch from the fourth state to the third state, so that the third input / output interface outputs the test end signal to the test machine until the test end signal of the chip under test is completed, and control the level signal of the third input / output interface to change from the sixth state to the fifth state. The fifth state is the level signal of the third input / output interface when the chip under test has not output the test end signal, and the sixth state is the level signal of the third input / output interface when the chip under test outputs the test end signal.

[0138] In one embodiment, the first receiving unit 701 is further configured to:

[0139] When the test equipment is idle, the idle signal of the test equipment is received through the first input / output interface;

[0140] The asynchronous test device is controlled to be in an idle state based on the idle signal;

[0141] The idle signal is transmitted to the chip under test (DUT) through an asynchronous interface so that the asynchronous interface of the DUT enters an idle state based on the idle signal.

[0142] In one embodiment, the second receiving unit 703 is specifically used for:

[0143] The initial response signal of the chip under test is received based on the asynchronous interface. The initial response signal is generated by the chip under test based on the test start signal.

[0144] Based on the initial response signal and the transmission protocol of the chip under test, the initial response signal is converted to obtain the response signal of the chip under test.

[0145] In one embodiment, the input / output interface further includes a fourth input / output interface, the fourth input / output interface being used for:

[0146] Receive the pause test signal from the test machine based on the fourth input / output interface;

[0147] The test is paused via an asynchronous interface based on a pause test signal.

[0148] In one embodiment, multiple asynchronous testing devices are arranged between the test bench and the chip under test. Each asynchronous testing device is used to test the function corresponding to the chip under test. The asynchronous testing device is also used for:

[0149] The asynchronous test device switching signal of the test machine is received through the fifth interface corresponding to each asynchronous test device.

[0150] The asynchronous test device switching signal controls the current asynchronous test device to disconnect from the chip under test, so that the test bench can connect to the next asynchronous test device to perform the next function test on the chip under test.

[0151] In one embodiment, the second receiving unit 703 is further configured to:

[0152] The test completion signal is received from the chip under test via an asynchronous interface.

[0153] The asynchronous test device is in an idle state based on the completion signal control.

[0154] Each module in the aforementioned asynchronous testing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0155] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 8 As shown, Figure 8 This is an internal structural diagram of a computer device provided in an embodiment of this application. The computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores test data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a chip testing method.

[0156] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0157] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the chip testing method of any of the above embodiments.

[0158] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the chip testing method of any of the above embodiments.

[0159] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0160] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0161] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0162] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A chip testing method, characterized in that, The method, applied in an asynchronous testing device connected to a testing machine via an input / output interface and connected to the asynchronous interface of the chip under test, includes: When the testing equipment starts testing, the test start signal of the testing equipment is received through the input / output interface; the input / output interface includes a first input / output interface, a second input / output interface, and a third input / output interface; Receiving the test start signal of the test machine through the input / output interface includes: obtaining the test start signal of the test machine when the level signal of the first input / output interface changes from a first state to a second state, wherein the first state is the state of the level signal of the first input / output interface when the test machine is idle, and the second state is the state of the level signal of the first input / output interface when the test machine starts testing; The test start signal is transmitted to the chip under test through the asynchronous interface, so that the chip under test can start the test based on the test start signal; The asynchronous interface receives the response signal from the chip under test (DUT). The response signal is generated when the DUT starts generating test data during the test, based on the test start signal. Based on the response signal, the input / output interface is controlled to output a sampling signal to the test equipment, so that the test equipment starts to perform test sampling based on the sampling signal. The step of controlling the input / output interface to output a sampling signal to the test equipment based on the response signal includes: controlling the state of the level signal of the second input / output interface to change from a third state to a fourth state based on the response signal, so that the second input / output interface outputs a sampling signal to the test equipment. The third state is the level signal state of the second input / output interface when the test equipment is not sampling, and the fourth state is the level signal state of the second input / output interface during the sampling process of the test equipment. The test end signal of the chip under test is received through the asynchronous interface; Based on the test completion signal, the input / output interface is controlled to output a test completion signal to the test equipment, so that the test equipment ends sampling based on the test completion signal and generates test results; the step of controlling the input / output interface to output a test completion signal to the test equipment based on the test completion signal includes: controlling the level signal of the third input / output interface to change from the fifth state to the sixth state based on the test completion signal, and controlling the level signal of the second input / output interface to switch from the fourth state to the third state, so that the third input / output interface outputs a test completion signal to the test equipment, until the test completion signal of the chip under test is completed, and controlling the level signal of the third input / output interface to change from the sixth state to the fifth state, where the fifth state is the level signal state of the third input / output interface when the chip under test has not output a test completion signal, and the sixth state is the level signal state of the third input / output interface when the chip under test outputs a test completion signal.

2. The method according to claim 1, characterized in that, The method further includes: When the test equipment is in an idle state, the idle signal of the test equipment is received through the first input / output interface; The asynchronous testing device is controlled to be in an idle state based on the idle signal; The idle signal is transmitted to the chip under test through the asynchronous interface, so that the asynchronous interface of the chip under test enters an idle state based on the idle signal.

3. The method according to claim 1, characterized in that, Receiving the response signal from the chip under test via the asynchronous interface includes: The initial response signal of the chip under test is received based on the asynchronous interface, and the initial response signal is generated by the chip under test based on the test start signal. Based on the initial response signal and the transmission protocol of the chip under test, the initial response signal is converted to obtain the response signal of the chip under test.

4. The method according to claim 1, characterized in that, The input / output interface further includes a fourth input / output interface, and the method further includes: The test pause signal from the test machine is received based on the fourth input / output interface; Based on the pause test signal, the chip under test is controlled to pause the test via the asynchronous interface.

5. The method according to any one of claims 1-4, characterized in that, Multiple asynchronous testing devices are arranged between the testing machine and the chip under test. Each asynchronous testing device is used to test the function corresponding to the chip under test. The method further includes: The asynchronous test device switching signal of the test machine is received through the fifth interface corresponding to each of the asynchronous test devices. Based on the asynchronous test device switching signal, the current asynchronous test device is disconnected from the chip under test, so that the test bench can be connected to the next asynchronous test device to perform the next function test on the chip under test.

6. The method according to any one of claims 1-4, characterized in that, After controlling the input / output interface to output a test end signal to the test machine based on the test end signal, the method further includes: The test completion signal of the chip under test is received through the asynchronous interface; Based on the completion signal, the asynchronous testing device is controlled to be in an idle state.

7. An asynchronous testing device, characterized in that, The asynchronous testing device is connected to the testing machine via an input / output interface and to the asynchronous interface of the chip under test. The asynchronous testing device includes: The first receiving unit is used to receive the test start signal of the test equipment through the input / output interface when the test equipment starts testing; the input / output interface includes a first input / output interface, a second input / output interface and a third input / output interface; The first receiving unit is specifically used to: obtain the test start signal of the test machine when the level signal of the first input / output interface changes from the first state to the second state, wherein the first state is the state of the level signal of the first input / output interface when the test machine is idle, and the second state is the state of the level signal of the first input / output interface when the test machine starts testing; The first transmission unit is used to transmit the test start signal to the chip under test through the asynchronous interface, so that the chip under test can start the test based on the test start signal; The second receiving unit is used to receive the response signal of the chip under test through the asynchronous interface. The response signal is generated when the chip under test starts generating test data during the test based on the test start signal. The second transmission unit is used to control the input / output interface to output a sampling signal to the test equipment based on the response signal, so that the test equipment can start performing test sampling based on the sampling signal. The second transmission unit is specifically used to: control the state of the level signal of the second input / output interface to change from the third state to the fourth state based on the response signal, so that the second input / output interface outputs a sampling signal to the test equipment. The third state is the level signal state of the second input / output interface when the test equipment is not sampling, and the fourth state is the level signal state of the second input / output interface during the sampling process of the test equipment. The second receiving unit is also used to receive the test end signal of the chip under test through the asynchronous interface; The third transmission unit is used to control the input / output interface to output a test end signal to the test machine based on the test end signal, so that the test machine ends sampling based on the test end signal and generates test results; The third transmission unit is specifically used to: control the level signal of the third input / output interface to change from the fifth state to the sixth state based on the test end signal, and control the level signal of the second input / output interface to switch from the fourth state to the third state, so that the third input / output interface outputs a test end signal to the test machine until the test end signal of the chip under test is completed, and control the level signal of the third input / output interface to change from the sixth state to the fifth state, where the fifth state is the level signal state of the third input / output interface when the chip under test has not output a test end signal, and the sixth state is the level signal state of the third input / output interface when the chip under test outputs a test end signal.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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