Method and device for recognizing and extracting RTL code-based FPGA three-section finite state machine
By searching for timing and combination processes in RTL code and constructing a state transition diagram, the three-segment finite state machine of the FPGA can be directly extracted from the RTL code. This solves the problem of low identification efficiency in the existing technology and realizes efficient three-segment finite state machine detection and encoding rule checking.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN HUACHUANG (NANJING) INFORMATION TECHNOLOGY CO LTD
- Filing Date
- 2026-01-08
- Publication Date
- 2026-05-12
AI Technical Summary
Existing technologies struggle to directly identify and extract three-stage finite state machines from FPGAs using RTL code, resulting in low identification efficiency and an inability to meet application requirements in safety-critical fields.
By searching for the timing and combination process of internal signal updates in the RTL code, a three-segment finite state machine state transition diagram is constructed. The three-segment finite state machine of the FPGA is directly extracted and identified from the RTL code, avoiding reliance on the synthesized RTL netlist.
It achieves efficient identification and extraction of FPGA three-segment finite state machines, improves detection efficiency, meets the application needs of safety-critical fields, and can simultaneously check the compliance of coding rules.
Smart Images
Figure CN121478321B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic design automation technology, and in particular to a method and apparatus for identifying and extracting a three-segment finite state machine for FPGA based on RTL code. Background Technology
[0002] FPGAs have been widely adopted due to their powerful reconfigurability, low latency, real-time performance, and parallel computing capabilities. Among them, FSM (Finite State Machine) is a commonly used design pattern in FPGA development. It improves code readability, maintainability, and reliability, and is widely used in control systems, communication protocols, data processing, and timing control. Therefore, the correctness of FSM design is crucial. Almost all safety-critical fields require a comprehensive check for design flaws in FSMs and demand that their implementation conform to industry coding rules. Currently, there are three design patterns for FSMs: one-stage, two-stage, and three-stage. The three-stage pattern effectively eliminates the instability and glitches of combinational logic compared to the other two, making it the most widely used in safety-critical fields. However, the three-stage pattern is also the most complex FSM design pattern.
[0003] To verify the correctness of the Finite State Machine (FSM) and its adherence to coding rules, a correctness and compliance check of the FSM design is required. This necessitates the accurate identification and extraction of the FSM from the RTL code. However, since current FPGA designs are primarily based on RTL code, and RTL code syntax is highly flexible with no inherent restrictions on FSM design, there is no direct method for accurate FSM identification and extraction, especially for three-segment FSMs. While there is considerable research in the industry on FSM identification and extraction in FPGAs, no effective extraction and identification method has been provided. Patent CN112036104A discloses a finite state machine identification and extraction method based on an RTL netlist. This method synthesizes the FPGA's RTL code to generate an RTL netlist, then extracts the state signals from the netlist, thereby further identifying and extracting the FSM from the FPGA design. However, this method has many limitations. First, it requires the completion of the entire FPGA design and compilation to obtain the RTL netlist. Since the FPGA synthesis process is very time-consuming, the efficiency of this method is very low. Second, since this method is based on the RTL netlist, the extracted FSM cannot be directly mapped to the corresponding RTL code, and it cannot support the inspection of FSM encoding rules. Finally, this method is not suitable for three-segment FSMs and cannot meet the application needs of safety-critical fields.
[0004] To meet the requirements for checking the correctness and compliance of FSM designs with coding rules, there is an urgent need to propose an efficient technical means that can directly identify and extract FSMs in FPGA designs based on RTL code without relying on the FPGA's RTL netlist. In particular, it is necessary to extract and identify complex three-segment FSMs to meet the application needs of safety-critical fields, thereby improving the reliability and quality of FSM designs in FPGA designs. Summary of the Invention
[0005] To address the limitations and impracticality of existing FPGA finite state machine (FSM) identification and extraction methods, which are unsuitable for three-segment FSMs, this invention proposes a method and apparatus for identifying and extracting FPGA three-segment FSMs based on RTL code. This method can directly identify and extract the FPGA's three-segment FSM through RTL code, and simultaneously verify the correctness of the three-segment FSM design and compliance with coding rules.
[0006] The technical solution to achieve the purpose of this invention is: a method for identifying and extracting a three-segment finite state machine for FPGA based on RTL code, comprising the following steps:
[0007] Step 1: Obtain the RTL code module of the FPGA three-segment finite state machine to be identified and extracted;
[0008] Step 2: Locate and extract the timing process in the RTL code module that has internal signal updates. The timing process refers to the process that must be triggered by the clock edge to execute logic, and it satisfies that the results of all logic operations are updated uniformly when the next clock edge arrives.
[0009] Step 3: Locate and extract the combined processes with internal signal updates in the RTL code module. The combined process refers to a process that does not require a clock signal and is triggered to execute logic based on changes in the level of the input signal. It satisfies the requirement that the results of all logical operations are updated in real time as the triggering conditions change.
[0010] Step 4: Locate and extract processes or logic segments in the RTL code module that use internal signals as conditional signals and do not perform assignment operations on the internal signals under the conditional branches;
[0011] Step 5: Analyze all processes and logic segments extracted in Steps 2 to 4. If there are 3 processes or 2 processes and 1 logic segment that satisfy the three-segment finite state machine logic relationship, then it is determined that there is a three-segment finite state machine in the current RTL code module.
[0012] Step 6: From the combined process extracted in Step 5, find all the condition expressions, state assignment relationships and state signals corresponding to the internal signal update. Using each state signal as a node, the assignment relationship as the jump flow between nodes, and the condition expression as the jump condition, construct the state transition diagram of the three-segment finite state machine.
[0013] An FPGA three-segment finite state machine identification and extraction device based on RTL code is used to implement the above method. The device includes:
[0014] The code acquisition module is used to acquire and extract the RTL code of the FPGA three-segment finite state machine to be identified;
[0015] The feature recognition module is used to find and extract timing processes in the RTL code module that have internal signal updates, to find and extract combined processes in the RTL code module that have internal signal updates, and to find and extract processes or logic segments in the RTL code module that use internal signals as conditional signals and do not perform assignment operations on the internal signals under the conditional branches.
[0016] The state machine verification module is used to verify whether there are 3 processes or 2 processes and a logical segment that satisfy the three-segment finite state machine logical relationship. If they exist, it is determined that there is a three-segment finite state machine in the current RTL code module.
[0017] The state transition diagram construction module is used to find all condition expressions, state assignment relationships and state signals corresponding to internal signal updates from the combined process extracted by the state machine confirmation module. With each state signal as a node, the assignment relationship as the transition flow between nodes, and the condition expression as the transition condition, a three-segment finite state machine state transition diagram is constructed.
[0018] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described above.
[0019] A computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the above-described method.
[0020] A computer program product includes a computer program that, when executed by a processor, implements the above-described method.
[0021] Compared with the prior art, the beneficial effects of the present invention are as follows: 1) The method of the present invention can directly identify and extract the three-segment finite state machine of FPGA through RTL code, without relying on the synthesized RTL netlist. Therefore, when performing three-segment finite state machine identification, it is not necessary to develop separate RTL netlist parsers for different manufacturers and chip models. RTL code can be identified at any time without waiting for the entire FPGA project to be completed to generate the RTL netlist. Moreover, the identification is accurate and will not be affected by signal optimization during the synthesis of the RTL netlist; 2) The implementation of the method of the present invention can simultaneously satisfy the checks on the correctness of the three-segment finite state machine design and the compliance with the coding rules, making it highly practical; 3) The method of the present invention is easily implemented by a computer, which can improve the detection efficiency of three-segment finite state machine identification and extraction.
[0022] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description
[0023] Figure 1 The method flow proposed in this invention is as follows.
[0024] Figure 2 This is an example of the RTL source code to be tested.
[0025] Figure 3 For the identification of time-series process instances.
[0026] Figure 4 For the identified composite process instance.
[0027] Figure 5 To satisfy the combined process instance in step 3.
[0028] Figure 6 To satisfy the combined process instance in step 4.
[0029] Figure 7 To extract instances of state transition relationships.
[0030] Figure 8 This is an example of a state transition graph.
[0031] Figure 9 This is a schematic diagram of the detection device. Detailed Implementation
[0032] Combination Figure 1 This invention proposes a method for identifying and extracting three-segment finite state machines in FPGAs based on RTL code. This method can detect three-segment finite state machines in hardware description language code. The method specifically includes the following steps:
[0033] Step 1: Obtain the RTL code module of the FPGA three-segment finite state machine to be identified and extracted;
[0034] Step 2: Locate and extract the timing process in the RTL code module that has internal signal updates. The timing process refers to the process that must be triggered by the clock edge to execute logic, and it satisfies that the results of all logic operations are updated uniformly when the next clock edge arrives.
[0035] Step 21: Analyze the RTL code module and identify all processes in the sensitivity list that contain clock signals;
[0036] Step 22: Filter out all processes that perform assignment operations through assignment statements from all the time-series processes identified in Step 21. The assignment statements satisfy the condition that the left and right sides of the assignment operator each contain only one signal, denoted as A on the left and B on the right.
[0037] Step 3: Locate and extract the combined processes with internal signal updates in the RTL code module. The combined process refers to a process that does not require a clock signal and is triggered to execute logic based on changes in the level of the input signal. It satisfies the requirement that the results of all logical operations are updated in real time as the triggering conditions change.
[0038] Step 31: Analyze the RTL code module and identify all processes that do not contain clock signals in the sensitivity list;
[0039] Step 32: Filter out the processes that contain CASE or IF conditional statements from all the processes identified in Step 31. The CASE or IF conditional statement satisfies that there is an assignment statement under each conditional branch. The left and right ends of the assignment statement are both signals. The left end is an internal signal, denoted as C.
[0040] Step 4: Locate and extract a process or logic segment in the RTL code module that satisfies the condition that there exists an internal signal D as a conditional signal and that there is no assignment operation performed on signal D under the conditional branch.
[0041] Step 5: Analyze all processes and logic segments extracted in Steps 2 to 4. If there are 3 processes or 2 processes and 1 logic segment that satisfy the three-segment finite state machine logic relationship, then it is determined that there is a three-segment finite state machine in the current RTL code module.
[0042] Step 51: Analyze all the time-series processes extracted in Step 2, and identify the processes that have signals A and B and satisfy the characteristic that signal A is located on the left side of the assignment operator and signal B is located on the right side of the assignment operator.
[0043] Step 52: Analyze all the combined processes extracted in Step 3, and identify a process that satisfies the condition of a CASE or IF statement with signal A in Step 51 as the condition signal, and each condition branch has an assignment statement with signal B in Step 51 on the left and a vector signal or enumeration signal on the right.
[0044] Step 53: Analyze all processes or logic segments extracted in Step 4, identify a process or logic segment that satisfies the condition of containing a CASE or IF conditional statement with signal A in Step 51 as the conditional signal, and there are no signals A and B in Step 51 under each conditional branch.
[0045] Step 54: If and only if the conditions described in steps 51, 52 and 53 are all satisfied, then the three-segment finite state machine logic relationship is satisfied, and it is determined that a three-segment finite state machine exists in the current RTL code module.
[0046] Step 6: From the combined process extracted in Step 5, find all the condition expressions, state assignment relationships and state signals corresponding to the internal signal update. Using each state signal as a node, the assignment relationship as the jump flow between nodes, and the condition expression as the jump condition, construct the state transition diagram of the three-segment finite state machine.
[0047] Step 61: Analyze the CASE or IF conditional statements in the combined process obtained in Step 52, extract the conditional expression from each conditional control branch, take the signal on the right side of the assignment operator under each conditional control branch as the state signal (if the signal names are the same, they are merged into one signal), take the flow relationship from the right end to the left end of the assignment operator as the state jump flow, and record the conditional expression, state signal and state jump flow respectively.
[0048] Step 62: Using the state signals extracted in Step 61 as nodes and the conditional expressions as the transition conditions for each state signal, construct a three-segment finite state machine state transition diagram between the nodes according to the transition flow of each state signal.
[0049] Based on the same inventive concept, this invention also provides an FPGA three-segment finite state machine identification and extraction device based on RTL code, such as... Figure 9As shown, the device includes a code acquisition module, a feature recognition module, a state machine confirmation module, and a state transition diagram construction module. The code acquisition module acquires and extracts the RTL code module of the FPGA three-segment finite state machine to be identified and extracted. The feature recognition module searches for and extracts timing processes within the RTL code module that have internal signal updates, searches for and extracts combined processes within the RTL code module that satisfy the condition of internal signal updates, and searches for and extracts processes or logic within the RTL code module that use internal signals as conditional signals and do not perform assignment operations on those internal signals under the conditional branches. The fragment; the state machine confirmation module is used to confirm whether there are 3 processes or 2 processes and 1 logical fragment that satisfy the three-segment finite state machine logical relationship. If they exist, it is determined that there is a three-segment finite state machine in the current RTL code module; the state transition graph construction module is used to find all condition expressions, state assignment relationships and state signals corresponding to the internal signal update from the combined processes that have satisfied the three-segment finite state machine logical relationship. With each state signal as a node, the assignment relationship as the jump flow between nodes, and the condition expression as the jump condition, the three-segment finite state machine state transition graph is constructed.
[0050] The specific implementation methods of the above modules are the same as the steps of the aforementioned FPGA three-segment finite state machine identification and extraction method based on RTL code, and will not be repeated here.
[0051] The present invention will now be described in further detail with reference to the embodiments and accompanying drawings.
[0052] Example
[0053] This embodiment includes one code file written in VHDL, the source code of which is as follows: Figure 2 As shown. The following describes the method for identifying and extracting three-segment finite state machines in FPGA code files based on RTL code, as proposed in this invention. The specific processing steps are as follows:
[0054] Step 1: Obtain and extract the RTL code module of the FPGA three-segment finite state machine to be identified, such as... Figure 2 As shown;
[0055] Step 2: Locate and extract the timing process in the RTL code module that has internal signal updates. The timing process refers to the process that must be triggered by the clock edge to execute logic, and it satisfies that the results of all logic operations are updated uniformly when the next clock edge arrives.
[0056] Step 21: Analyze the RTL code module and identify a timing process in the sensitivity list that contains clock signals, such as... Figure 3 As shown;
[0057] Step 22: Analyze all the time-series processes identified in Step 21. Identify a process that satisfies the following condition: there exists an assignment statement "current_state <= next_state" performing an assignment operation, and the assignment statement satisfies that the left-hand side of the assignment operator contains only one signal, current_state, and the right-hand side contains only one signal, next_state. For example... Figure 3 As shown.
[0058] Step 3: Locate and extract the combined processes with internal signal updates in the RTL code module. The combined process refers to a process that does not require a clock signal and is triggered to execute logic based on changes in the level of the input signal. It satisfies the requirement that the results of all logical operations are updated in real time as the triggering conditions change.
[0059] Step 31: Analyze the RTL code module to identify the combined processes in two sensitivity lists that do not contain clock signals, such as... Figure 4 As shown;
[0060] Step 32: Analyze the combined processes obtained in Step 31, and identify a process containing a CASE conditional statement. This process satisfies the following condition: each CASE conditional branch contains an assignment statement, and the assignment statement satisfies that both the left and right sides of the assignment operator are signals. The left side is an internal signal next_state, such as... Figure 5 As shown.
[0061] Step 4: Locate and extract a composite process within the obtained RTL code module that satisfies the following conditions: there exists an internal signal `current_state` as the condition signal for an IF statement, and there are no update operations on `current_state` under the conditional branch. Figure 6 As shown;
[0062] Step 5: Analyze all processes and logic segments extracted in Steps 2 to 4. If there are 3 processes or 2 processes and 1 logic segment that satisfy the three-segment finite state machine logic relationship, then it is determined that there is a three-segment finite state machine in the current RTL code module.
[0063] Step 51: Analyze the time series processes extracted in Step 2, such as... Figure 3 As shown, the process satisfies the following characteristics: there are signals current_state and next_state, and the signal current_state is located on the left side of the assignment operator "current_state<=next_state", and the signal next_state is located on the right side of the assignment operator "current_state<=next_state".
[0064] Step 52: Analyze the combined processes extracted in Step 3, and identify a process containing a CASE conditional statement, such as... Figure 5 As shown, the CASE conditional statement satisfies the condition signal current_state in step 51 and each conditional branch has an assignment statement with the signal next_state in step 51 on the left and the enumeration type element {IDLE, WR_STATE, RD_STATE, SD_STATE} on the right.
[0065] Step 53: Analyze the combination process extracted in Step 4, such as... Figure 6 As shown, the process satisfies the existence of an IF conditional statement with the current_state signal in step 51 as the conditional signal, and the current_state and next_state signals in step 51 do not exist under each conditional branch.
[0066] Step 54: The conditions described in steps 51, 52 and 53 above are all satisfied. Therefore, the three processes extracted at the moment satisfy the three-stage finite state machine logic relationship, and it is determined that there is a three-stage finite state machine in the current RTL code module.
[0067] Step 6: From the combined process extracted in Step 5, find all the condition expressions, state assignment relationships and state signals corresponding to the internal signal update. Using each state signal as a node, the assignment relationship as the jump flow between nodes, and the condition expression as the jump condition, construct the state transition diagram of the three-segment finite state machine.
[0068] Step 61: Analyze the CASE conditional statements in the combined process obtained in Step 52, such as... Figure 5 As shown, four conditional expressions "start=1", "write_done=1", "read_done=1", and "send_done=1" are extracted from the four conditional control branches of the CASE conditional statement, respectively. Figure 7 As shown, the signals {IDLE, WR_STATE, RD_STATE, SD_STATE} on the right side of the assignment operators in the four conditional control branches "next_state<=WR_STATE", "next_state<=RD_STATE", "next_state<=SD_STATE", and "next_state<=IDLE" are used as state signals. The flow from the right end to the left end of the assignment operator is used as the state transition flow. The conditional expressions, state signals, and state transition flows are recorded respectively, as follows. Figure 7 As shown;
[0069] Step 62: Using the state signals extracted in Step 61 as nodes and the conditional expressions as the transition conditions for each state signal, construct a three-stage finite state machine state transition diagram based on the transition flow of each state signal, as follows: Figure 8 As shown.
[0070] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.
Claims
1. A method for identifying and extracting a three-segment finite state machine for FPGA based on RTL code, characterized in that, Includes the following steps: Step 1: Obtain the RTL code module of the FPGA three-segment finite state machine to be identified and extracted; Step 2: Locate and extract the timing process in the RTL code module that has internal signal updates. The timing process refers to the process that must be triggered by the clock edge to execute logic, and it satisfies that the results of all logic operations are updated uniformly when the next clock edge arrives. Step 3: Locate and extract the combined processes with internal signal updates in the RTL code module. The combined process refers to a process that does not require a clock signal and is triggered to execute logic based on changes in the level of the input signal. It satisfies the requirement that the results of all logical operations are updated in real time as the triggering conditions change. Step 4: Locate and extract processes or logic segments in the RTL code module that use internal signals as conditional signals and do not perform assignment operations on the internal signals under the conditional branches; Step 5: Analyze all processes and logic segments extracted in Steps 2 to 4. If there are 3 processes or 2 processes and 1 logic segment that satisfy the three-stage finite state machine logic relationship, then it is determined that there is a three-stage finite state machine in the current RTL code module. This includes the following steps: Step 51: Analyze all the time-series processes extracted in Step 2, and identify the processes that have signals A and B and satisfy the characteristic that signal A is located on the left side of the assignment operator and signal B is located on the right side of the assignment operator. Step 52: Analyze all the combined processes extracted in Step 3, and identify a process that satisfies the condition of a CASE or IF statement with signal A in Step 51 as the condition signal, and each condition branch has an assignment statement with signal B in Step 51 on the left and a vector signal or enumeration signal on the right. Step 53: Analyze all processes or logic segments extracted in Step 4, identify a process or logic segment that satisfies the condition of containing a CASE or IF conditional statement with signal A in Step 51 as the conditional signal, and there are no signals A and B in Step 51 under each conditional branch. Step 54: If and only if the conditions described in steps 51, 52 and 53 are all satisfied, then the three-segment finite state machine logic relationship is satisfied, and it is determined that a three-segment finite state machine exists in the current RTL code module. Step 6: From the combined process extracted in Step 5, find all condition expressions, state assignment relationships, and state signals corresponding to the internal signal updates. Using each state signal as a node, the assignment relationship as the jump flow between nodes, and the condition expression as the jump condition, construct the three-stage finite state machine state transition diagram, including the following steps: Step 61: Analyze the CASE or IF conditional statements in the combined process obtained in Step 52, extract the conditional expression from each conditional control branch, take the signal on the right side of the assignment operator under each conditional control branch as the state signal, and take the flow relationship from the right end to the left end of the assignment operator as the state jump flow direction, and record the conditional expression, state signal and state jump flow direction respectively. Step 62: Using the state signals extracted in Step 61 as nodes and the conditional expressions as the transition conditions for each state signal, construct a three-segment finite state machine state transition diagram between the nodes according to the transition flow of each state signal.
2. The method for identifying and extracting a three-segment finite state machine based on RTL code for FPGAs according to claim 1, characterized in that, In step 2, locate and extract timing processes within the RTL code module that contain internal signal updates, including: Step 21: Analyze the RTL code module and identify all processes in the sensitivity list that contain clock signals; Step 22: Filter out all processes that perform assignment operations through assignment statements from all the time-series processes identified in Step 21. The assignment statements satisfy the condition that the left and right sides of the assignment operator each contain only one signal, denoted as A on the left and B on the right.
3. The method for identifying and extracting a three-segment finite state machine based on RTL code for FPGAs according to claim 2, characterized in that, Step 3: Locate and extract combined processes in the RTL code module that contain internal signal updates, including: Step 31: Analyze the RTL code module and identify all processes that do not contain clock signals in the sensitivity list; Step 32: Select the processes that contain CASE or IF conditional statements from all the processes identified in Step 31. The CASE or IF conditional statement satisfies that there is an assignment statement under each conditional branch. The left and right ends of the assignment statement are both signals. The left end is an internal signal, denoted as C.
4. A device for identifying and extracting a three-segment finite state machine based on RTL code in an FPGA, characterized in that, The apparatus for implementing the method according to any one of claims 1 to 3 comprises: The code acquisition module is used to acquire and extract the RTL code of the FPGA three-segment finite state machine to be identified; The feature recognition module is used to find and extract timing processes in the RTL code module that have internal signal updates, to find and extract combined processes in the RTL code module that have internal signal updates, and to find and extract processes or logic segments in the RTL code module that use internal signals as conditional signals and do not perform assignment operations on the internal signals under the conditional branches. The state machine verification module is used to verify whether there are 3 processes or 2 processes and a logical segment that satisfy the three-segment finite state machine logical relationship. If they exist, it is determined that there is a three-segment finite state machine in the current RTL code module. The state transition diagram construction module is used to find all condition expressions, state assignment relationships and state signals corresponding to internal signal updates from the combined process extracted by the state machine confirmation module. With each state signal as a node, the assignment relationship as the transition flow between nodes, and the condition expression as the transition condition, a three-segment finite state machine state transition diagram is constructed.
5. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method described in any one of claims 1-3.
6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method described in any one of claims 1-3.
7. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1-3.