Cache consistency network-on-chip optimization method based on containability and expected propagation

Abstract

The invention relates to the technical field of network-on-chip of a multi-core processor, and discloses a cache coherence network-on-chip optimization method based on containeability and expected propagation, through three-stage optimization of ''containeability deadlock avoidance-containeability expected propagation-local load awareness routing'', and in combination with cache coherence protocol adaptation, the network-on-chip optimization of the cache coherence is realized. According to the technical scheme, the NoC performance in the virtual channel limited scene is improved, and the problem that in an existing technical scheme, in the virtual channel limited scene, a network-on-chip with no deadlock, high VC utilization rate and low load sensing overhead cannot be considered at the same time, and then the requirement of a cache consistency multi-core processor cannot be adapted is solved.

Description

Technical Field

[0001] This application relates to the field of on-chip network technology for multi-core processors, and for example to an on-chip network optimization method based on accommodateability and expected propagation cache coherence. Background Technology

[0002] With the widespread application of multi-core processors in cloud servers, smartphones, IoT gateways, and other fields, Network-on-Chip (NoC) has become the mainstream solution for inter-core communication in multi-core systems. However, existing NoC technologies face three key challenges: 1. Performance conflict between limited virtual channel resources and deadlock avoidance: To avoid protocol-level deadlock, cache coherence protocols (such as MOESI and MESI) need to allocate independent virtual networks (VNs) for different types of packets, leading to a shortage of virtual channel (VC) resources within a single virtual network (e.g., industrial products like TILE64 and Intel Xeon only configure 1-2 VCs per VN). While adaptive routing algorithms can alleviate load imbalance through path diversity, they are prone to deadlock. Traditional Duato deadlock avoidance theory uses "atomic virtual channel allocation" (allocating only when a VC is completely idle), resulting in insufficient VC utilization and significant performance loss.

[0003] 2. Limitations of existing deadlock avoidance solutions: Although the full packet forwarding strategy (WPF) relaxes the atomicity constraint, it requires that the downstream VC has idle resources ≥ the length of the complete packet. It has poor adaptability to long packets (length > VC depth) and limited performance improvement in mixed packet scenarios. Partial adaptive routing based on the redirection model (such as XY-YX) has low path diversity and cannot effectively alleviate congestion.

[0004] 3. Additional overhead of load-aware routing: Local / global load-aware routing requires building an independent load-aware network (such as RCA, DAR), which increases hardware wiring and power consumption overhead; routes that rely solely on local cached information (such as DyAD) are prone to greedy decisions, which exacerbate remote congestion.

[0005] Therefore, in existing technical solutions, in scenarios with limited virtual channels, it is impossible to simultaneously achieve deadlock-free, high VC utilization, and low load-aware overhead on-chip networks, thus failing to meet the requirements of cache-coherent multi-core processors.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application. Summary of the Invention

[0007] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0008] The cache coherence on-chip network optimization method, apparatus, device, and storage medium provided in this disclosure based on accommodateability and expected propagation can solve the problem that in existing technical solutions, in scenarios with limited virtual channels, it is impossible to simultaneously achieve deadlock-free, high VC utilization, and low load-aware overhead on-chip networks, thus failing to meet the requirements of cache coherent multi-core processors.

[0009] This disclosure provides an on-chip network optimization method based on accommodateability and expected propagation cache coherence, which may include: Virtual channel allocation is performed based on capacity conditions, and it is determined whether the idle resources of the downstream target virtual channel are greater than or equal to the current length of the upstream queue head message. When the accommodability condition is met, allocate an adaptive virtual channel or an escape virtual channel; The expected signal can be accommodated through backpropagation, allowing for advance virtual channel allocation decisions. Based on the local load information contained in the expected signal that can be accommodated, local load-aware adaptive routing is performed.

[0010] This disclosure provides an on-chip network optimization apparatus based on accommodativeness and expected propagation of cache coherence, the apparatus comprising: The capacity determination module is used to allocate virtual channels based on capacity conditions, and to determine whether the idle resources of the downstream target virtual channel are greater than or equal to the current length of the upstream queue head message; when the capacity conditions are met, an adaptive virtual channel or an escape virtual channel is allocated. The module can accommodate expected processing modules, which are used to make virtual channel allocation decisions in advance by backpropagating expected signals. The local load-aware adaptive routing module is used to perform local load-aware adaptive routing based on the local load information contained in the expected signal that can be accommodated.

[0011] This disclosure provides an electronic device that includes at least one processor; and memory that is communicatively connected to at least one processor; The memory stores instructions that can be executed by at least one processor, which enables the at least one processor to perform the above-described cache coherence on-chip network optimization method based on accommodateability and expected propagation.

[0012] This disclosure provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the above-described cache coherence on-chip network optimization method based on accommodateability and expected propagation.

[0013] The on-chip network optimization method, apparatus, device, and storage medium based on accommodateability and expected propagation of cache coherence provided in this disclosure can achieve the following technical effects: This disclosure improves NoC performance in virtual channel-constrained scenarios through a three-level optimization of "accommodative deadlock avoidance - accommodative expected propagation - local load-aware routing" combined with cache coherency protocol adaptation. It solves the problem that existing technical solutions cannot simultaneously achieve deadlock-free, high VC utilization and low load-aware overhead on-chip networks in virtual channel-constrained scenarios, thus failing to meet the cache coherency requirements of multi-core processors.

[0014] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0015] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a flowchart illustrating an on-chip network optimization method based on accommodability and expected propagation provided in an embodiment of this disclosure; Figure 2 This is a flowchart of a deadlock-free flow control mechanism based on accommodativeness provided in an embodiment of this disclosure; Figure 3 This is a flowchart illustrating a process for generating a accommodating signal using a backpropagation mechanism that accommodates the intended signal, as provided in this embodiment of the disclosure. Figure 4 This is a flowchart of a local load-aware adaptive routing method provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of an on-chip network optimization device based on accommodativeness and expected propagation of cache coherence provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the structure of an on-chip network optimization device based on caching consistency and expected propagation, provided in an embodiment of this disclosure. Detailed Implementation

[0016] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0017] The terms "first," "second," etc., used in the embodiments of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0018] Unless otherwise stated, the term "multiple" means two or more.

[0019] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0020] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0021] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0022] To address the aforementioned issues, this disclosure provides a method, apparatus, device, and storage medium for optimizing on-chip networks based on tolerance and expected propagation cache coherence.

[0023] The following description, in conjunction with the accompanying drawings, illustrates the on-chip network optimization method, apparatus, device, and storage medium based on tolerance and expected propagation for cache coherence.

[0024] Figure 1 This is a flowchart illustrating an on-chip network optimization method based on caching coherence and expected propagation provided in an embodiment of this disclosure.

[0025] Combination Figure 1 As shown, the on-chip network optimization method based on capacity and expected propagation cache coherence can include: S101, Based on the capacity condition, allocate virtual channels and determine whether the idle resources of the downstream target virtual channel are greater than or equal to the current length of the upstream queue head message; S102, when the accommodability condition is met, allocate an adaptive virtual channel or an escape virtual channel; S103 can accommodate the expected signal through back propagation and make virtual channel allocation decisions in advance; S104 performs local load-aware adaptive routing based on the local load information contained in the expected signal.

[0026] In some embodiments, the tolerance condition is determined by the following criteria: the credit counter value of the downstream virtual channel is greater than or equal to the remaining length counter value of the upstream head message.

[0027] In some embodiments, the accommodating expected signal includes a first accommodating expected signal and a second accommodating expected signal; The first accommodability expected signal is applicable to the first message scenario. The generation conditions include that the downstream virtual channel meets the accommodability requirement, there is only one message, it has been allocated, and the length of the queue head message does not exceed the virtual channel depth. The second accommodateable expectation signal is applicable to the second message scenario. The generation conditions include the downstream virtual channel meeting the accommodateability requirement and being allocated, or receiving a strong or weak accommodateable expectation signal propagated downstream and being allocated.

[0028] In some embodiments, the strength of the first accommodating expected signal decreases by 1 for each hop of propagation, and the strength of the second accommodating expected signal decreases by 2 for each hop of propagation, stopping propagation when the strength reaches zero.

[0029] In some embodiments, the path selection priority of local load-aware adaptive routing is: Prioritize paths that meet the capacity requirements; Secondly, choose a path with strong potential for inclusion; Finally, the weakly accommodative expected path was chosen; Under the same expected type, the path with higher signal strength is preferred.

[0030] Figure 2 This is a flowchart illustrating a deadlock-free flow control mechanism (CVA) based on accommodativeness, as provided in an embodiment of this disclosure. Figure 3 This is a flowchart illustrating the process of generating a accommodating signal using a accommodating anticipated backpropagation (CEF) mechanism, as provided in this disclosure embodiment. Figure 4 This is a flowchart of a Local Load Aware Adaptive Routing (CER) process provided in an embodiment of this disclosure, combined with... Figures 2 to 4 ,right Figure 1 The on-chip network optimization method based on caching consistency and expected propagation is further described in the paper.

[0031] To address the issue that existing technical solutions, in virtual channel-constrained scenarios, cannot simultaneously achieve deadlock-free operation, high VC utilization, and low load-aware overhead for NoC, thus failing to meet the requirements of cache-coherent multi-core processors, this invention achieves NoC performance improvement in virtual channel-constrained scenarios through a three-level optimization: "accommodative deadlock avoidance - accommodative expected propagation - local load-aware routing," combined with cache coherency protocol adaptation. The specific details are as follows: Capacity-based deadlock-free flow control mechanism (CVA) This patent is based on a deadlock-free flow control mechanism (CVA) with tolerance. It addresses the issues of limited virtual channels in cache-coherent on-chip networks due to protocol-based division of independent virtual networks, and the low utilization rate and poor adaptability to mixed long / short packets in traditional Duato schemes (atomic allocation, WPF). By extending the Duato theory, it uses "tolerance" as the core criterion: "downstream target virtual channel idle resources (Credit counter acquisition) ≥ current length of upstream queue head packet (Left Counter maintenance)". This relaxes the restrictions on virtual channel allocation without deadlock.

[0032] The workflow of the compatibility-based deadlock-free flow control mechanism (CVA) is as follows: Figure 2 As shown, each virtual network is configured with one adaptive virtual channel (AVC, primary transmission, supporting fully adaptive routing) and one escape virtual channel (EVC, XY-order deadlock-free routing). Four types of allocation validity conditions are set (AVC idle / incomplete allocation with congruent packet length and capacity / complete allocation with congruent packet length and downstream capacity, EVC with available slots), with AVC having higher priority. The hardware only adds a capacity judgment module (including Left / Credit counters and comparators) and a VC request validity judgment module to the traditional router, resolving resource contention through a separate two-level arbitration.

[0033] 2. Capable of accommodating the anticipated backpropagation mechanism (CEF) The Expected Accommodation Backpropagation (CEF) mechanism of this patent is an optimization of CVA, which aims to solve the problem of insufficient utilization caused by CVA having to wait for sufficient idle downstream virtual channels. The core is to realize advance allocation when the downstream is not completely idle by backpropagating the "Expected Accommodation" signal, while supporting load-aware routing.

[0034] The workflow for accommodating the expected backpropagation mechanism (CEF) to generate an accommodating signal is as follows: Figure 3As shown, it defines two types of signals: Strong Capacity Expectation (CEA, applicable to short message scenarios, generated when the downstream AVC meets the requirements of being capacitive, single message, already allocated, and queue head length ≤ VC depth) and Weak Capacity Expectation (CEB, applicable to long message scenarios, generated when the downstream AVC meets the requirements of being capacitive and already allocated, or when a downstream CEA / CEB is received and already allocated). The propagation rule is to reuse existing links for backpropagation, with differentiated attenuation (CEA decreases by 1 per hop, CEB decreases by 2 per hop, stopping at strength 0), and the initial CEB sending node cannot utilize the expected allocation. The hardware only adds generation (generating encapsulated signals according to state), propagation (attenuation through shift registers and subtractors), and consumption units (input routing decisions) to the CVA architecture, with no additional delay.

[0035] 3. Local Load Aware Adaptive Routing (CER) This patented Local Load Aware Adaptive Routing (CER) aims to solve the problems of high hardware overhead (global / regional awareness requires an additional load network) or low decision reliability of traditional load-aware routing (relying solely on local caching is prone to greedy congestion). Relying on CVA and CEF, it reuses the local load information contained in the CEA / CEB signals of CEF (CEA corresponds to short dependencies and fast release, CEB has no message length limit but slow release, and the signal strength reflects the distance from the dependency origin), and can achieve awareness and routing decisions without an additional load network.

[0036] Local Load Aware Adaptive Routing (CER) workflow is as follows: Figure 4 As shown, it follows the priority order of "CVA low-dependency path > CEA path > CEB path," prioritizing the low-dependency path corresponding to the CVA signal (the downstream virtual channel directly meets the capacity condition, with the lightest load and lowest latency). When there is no CVA signal to accommodate, it prioritizes the strong capacity expectation (CEA) path (fast dependency release, which can quickly alleviate congestion), and finally selects the weak capacity expectation (CEB) path. Under the same expectation type, it compares signal strength and prioritizes the port with the shorter dependency path. When the signal type and strength are the same, it selects the port with more sufficient downstream virtual channel idle resources (credit value) by comparing them, avoiding greedy decision-making. The hardware only modifies the traditional router routing calculation unit, adding an expectation resolution and priority comparison module. Combined with look-ahead routing, it compresses pipeline latency to 3 cycles (including VA / SA / ST), and adds only 1 cycle to link transmission, with no additional overhead.

[0037] 4. Cache consistency adaptation This patent addresses the issue that cache coherence protocols (such as MOESI and MESI) need to allocate independent virtual networks (VNs) for different packets to avoid protocol-level deadlocks, which limits the number of virtual channels (VCs) within a single VN (industrial chips such as TILE64 only have 1-2 VCs, while mainstream protocols like GEM5 require 4-5 VNs to share resources). The patent adapts this by "mechanism optimization instead of resource expansion," where each VN only needs to be equipped with 1 adaptive virtual channel (AVC) and 1 escape virtual channel (EVC) to meet the requirements.

[0038] Among them, CVA breaks through the Duato atomicity limitation by "accommodativeness". VC can be allocated as long as the downstream can accommodate the head of the queue when it is not idle. The utilization of 1 AVC is comparable to that of 2-4 traditional VCs. CEF reuses existing links to transmit CEA / CEB signals in reverse, realizing advance allocation when the downstream VC is not completely idle, adapting to mixed long / short messages, and avoiding long messages occupying VCs. CER relies on the dependency information of CEF signals to achieve local awareness without additional network load, alleviating hotspot congestion and prioritizing low-dependency paths to meet latency requirements. In terms of hardware, it reuses the traditional router architecture, adding only a small number of counters and logic, is compatible with credit backpressure, and seamlessly connects the protocol transmission process.

[0039] In summary, this disclosure improves NoC performance in virtual channel-constrained scenarios through a three-level optimization of "accommodative deadlock avoidance - accommodative expected propagation - local load-aware routing" combined with cache coherency protocol adaptation. It solves the problem that existing technical solutions cannot simultaneously achieve deadlock-free, high VC utilization and low load-aware overhead on-chip networks in virtual channel-constrained scenarios, thus failing to adapt to the cache coherency requirements of multi-core processors.

[0040] and Figure 1 Corresponding to the flowchart of the cache coherence on-chip network optimization method based on capacity and expected propagation, this disclosure also provides an on-chip network optimization device based on capacity and expected propagation, such as... Figure 5 As shown, an on-chip network optimization device based on caching coherence and expected propagation can include: The capacity determination module 501 is used to allocate virtual channels based on capacity conditions, and to determine whether the idle resources of the downstream target virtual channel are greater than or equal to the current length of the upstream queue head message; when the capacity conditions are met, an adaptive virtual channel or an escape virtual channel is allocated. The expected processing module 502 is used to make virtual channel allocation decisions in advance by back-propagating the expected signal. The local load-aware adaptive routing module 503 is used to perform local load-aware adaptive routing based on the local load information contained in the expected signal.

[0041] In some embodiments, the criteria for determining the above-mentioned tolerance condition are: the credit counter value of the downstream virtual channel is greater than or equal to the remaining length counter value of the upstream head message.

[0042] In some embodiments, the aforementioned accommodable expected signal includes a first accommodable expected signal and a second accommodable expected signal; The first accommodability expected signal is applicable to the first message scenario. The generation conditions include that the downstream virtual channel meets the accommodability requirement, there is only one message, it has been allocated, and the length of the queue head message does not exceed the virtual channel depth. The second accommodateable expectation signal is applicable to the second message scenario. The generation conditions include the downstream virtual channel meeting the accommodateability requirement and being allocated, or receiving a strong or weak accommodateable expectation signal propagated downstream and being allocated.

[0043] In some embodiments, the strength of the first accommodating expected signal decreases by 1 for each hop of propagation, and the strength of the second accommodating expected signal decreases by 2 for each hop of propagation, stopping propagation when the strength reaches zero.

[0044] In some embodiments, the path selection priority of the above-mentioned local load-aware adaptive routing is: Prioritize paths that meet the capacity requirements; Secondly, choose a path with strong potential for inclusion; Finally, the weakly accommodative expected path was chosen; Under the same expected type, the path with higher signal strength is preferred.

[0045] In some specific examples, the on-chip network disclosed herein can adopt a 2D-Mesh topology, with each node containing an IP core, a network interface (NI), and a router; the router supports one AVC and one EVC, with the EVC using XY dimensional order routing (no deadlock), and the AVC using CVA flow control and CER routing; the cache coherence protocol uses MOESI, and one virtual network (VN) is configured.

[0046] (a) Capacity assessment module left counter: A 4-bit counter. When the header slice enters the queue, the total length of the message (e.g., 1 / 3 / 5 slices) is loaded. It is decremented by 1 for each slice sent. Credit counter: A 4-bit counter. The downstream VC sends a credit pulse to the upstream for every slice it sends, and the counter increments by 1; the upstream sends a slice, and the counter decrements by 1. Comparator: Compares the left counter value with the credit value. If credit ≥ left counter, outputs capable=1 (can be accommodated); otherwise, capable=0.

[0047] (ii) Capable of accommodating the intended processing modules Expected generation unit: 1 combinational logic circuit, which generates CEA / CEB signals based on "downstream capable signals, number of VC messages, message length, and allocation status", and encapsulates them as "1 bit type + 4 bits strength" (initial strength = 4). Expected propagation unit: 1 shift register and subtractor. The strength of CEA decreases by 1 for each propagation hop, and the strength of CEB decreases by 2 for each propagation hop. Propagation stops when the strength = 0. Expected consumption unit: 1 selector, which inputs CEA / CEB signals into the CER routing module to participate in port decision-making.

[0048] (III) CER Routing Module Priority encoder: Sort candidate ports by "CVA > CEA > CEB", and select the port with higher signal strength under the same expectation; Credit comparator: Under the same expectation and strength, select the port with the larger credit value; Look-ahead RC Unit: Before the packet is transmitted to the current router, the RC is completed at the previous hop router, the result is stored in the header slice, and the current router directly enters the VA stage.

[0049] Combination Figure 6 As shown, this disclosure also provides an on-chip network optimization device 600 based on accommodateability and expected propagation of cache coherence, including a processor 604 and a memory 601. Optionally, the system may further include a communication interface 602 and a bus 603. The processor 604, communication interface 602, and memory 601 can communicate with each other via the bus 603. The communication interface 602 can be used for information transmission. The processor 604 can call logical instructions in the memory 601 to execute the on-chip network optimization method based on accommodateability and expected propagation of cache coherence in the above embodiments.

[0050] Furthermore, the logic instructions in the aforementioned memory 601 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0051] The memory 601, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 604 executes functional applications and data processing by running the program instructions / modules stored in the memory 601, thereby implementing the cache coherence on-chip network optimization method based on capacity and expected propagation in the above embodiments.

[0052] The memory 601 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 601 may include high-speed random access memory and may also include non-volatile memory.

[0053] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured as an on-chip network optimization method based on accommodability and expected propagation of cache coherence.

[0054] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0055] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0056] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. As used in the description of the embodiments, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used herein means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the terms “comprise” and its variations “comprises” and / or “comprising” refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Unless otherwise specified, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes the element. In this document, each embodiment may focus on describing the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, then the relevant parts can be referred to the description of the method section.

[0057] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0058] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0059] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0060] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0061] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0062] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0063] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0064] The systems and technologies described herein can be implemented in computing systems that include back-end components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0065] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0066] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this disclosure can be achieved, and this is not limited herein.

[0067] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A cache coherence on-chip network optimization method based on accommodateability and expected propagation, characterized in that, The method includes: Virtual channel allocation is performed based on capacity conditions, and it is determined whether the idle resources of the downstream target virtual channel are greater than or equal to the current length of the upstream queue head message. When the accommodability condition is met, allocate an adaptive virtual channel or an escape virtual channel; The expected signal can be accommodated through backpropagation, allowing for advance virtual channel allocation decisions. Based on the local load information contained in the expected signal that can be accommodated, local load-aware adaptive routing is performed.

2. The method according to claim 1, characterized in that, The criteria for determining the tolerance condition are: the credit counter value of the downstream virtual channel is greater than or equal to the remaining length counter value of the upstream head message.

3. The method according to claim 1, characterized in that, The accommodable expected signal includes a first accommodable expected signal and a second accommodable expected signal; The first accommodability expected signal is applicable to the first message scenario. The generation conditions include that the downstream virtual channel meets the accommodability requirement, there is only one message, it has been allocated, and the length of the queue head message does not exceed the virtual channel depth. The second accommodateable expected signal is applicable to the second message scenario. The generation conditions include the downstream virtual channel meeting the accommodateability requirement and being allocated, or receiving a strong or weak accommodateable expected signal propagated downstream and being allocated.

4. The method according to claim 3, characterized in that, The intensity of the first accommodating expected signal decreases by 1 for each hop it propagates, and the intensity of the second accommodating expected signal decreases by 2 for each hop it propagates, stopping propagation when the intensity reaches zero.

5. The method according to claim 1, characterized in that, The path selection priority of the local load-aware adaptive routing is as follows: Prioritize paths that meet the capacity requirements; Secondly, choose a path with strong potential for inclusion; Finally, the weakly accommodative expected path was chosen; Under the same expected type, the path with higher signal strength is preferred.

6. An on-chip network optimization device based on caching coherence and expected propagation, characterized in that, The device includes: The capacity determination module is used to allocate virtual channels based on capacity conditions, and to determine whether the idle resources of the downstream target virtual channel are greater than or equal to the current length of the upstream queue head message; when the capacity conditions are met, an adaptive virtual channel or an escape virtual channel is allocated. The module can accommodate expected processing modules, which are used to make virtual channel allocation decisions in advance by backpropagating expected signals. The local load-aware adaptive routing module is used to perform local load-aware adaptive routing based on the local load information contained in the expected signal that can be accommodated.

7. The apparatus according to claim 6, characterized in that, The criteria for determining the tolerance condition are: the credit counter value of the downstream virtual channel is greater than or equal to the remaining length counter value of the upstream head message.

8. The apparatus according to claim 6, characterized in that, The accommodateable expectation signal includes a first accommodateable expectation and a second accommodateable expectation; The first capacity expectation applies to the first message scenario, and the generation conditions include that the downstream virtual channel meets the capacity, there is only one message, it has been allocated and the length of the queue head message does not exceed the virtual channel depth; The second tolerance expectation applies to the second message scenario, and the generation conditions include the downstream virtual channel meeting tolerance and being allocated, or receiving a strong tolerance expectation or weak tolerance expectation signal propagated downstream and being allocated.

9. An electronic device, characterized in that, include: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-5.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-5.

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