Methods, apparatus, equipment and storage media for extracting semiconductor processing contour information

Abstract

This invention relates to the field of semiconductor processing and discloses a method, apparatus, device, and storage medium for extracting semiconductor processing contour information. The method includes obtaining a TEM image of the wafer under test and a design layout; searching within the design layout to determine a local layout corresponding to the TEM image; determining a preliminary screening contour imaging region in the TEM image based on the contour distribution position in the local layout; and performing contour edge detection based on the pixel values ​​of each pixel in the preliminary screening contour imaging region to obtain the contour information of the wafer under test's processing contour in the TEM image. This application utilizes the design layout of the wafer under test to achieve accurate and reliable contour information extraction from the TEM image, providing reliable data for the analysis of semiconductor process quality.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processing, and in particular to a method, apparatus, device, and computer-readable storage medium for extracting semiconductor processing contour information. Background Technology

[0002] An electron microscope (EM) is a type of microscope that uses an electron beam, rather than visible light, to illuminate an object and obtain an image. Because the wavelength of electrons is much shorter than that of photons, the resolution of images captured by an electron microscope is significantly higher than that of a photon microscope, and nanoscale differences can be reflected in the images.

[0003] Based on the characteristics of the generated images and their applications, EM images can be further divided into Scanning Electron Microscope Images (SEM images) and Transmission Electron Microscope Images (TEM images). TEM images are formed by using an electron beam to penetrate a tiny sample and detecting transmitted or diffracted electrons. Compared to SEM images, TEM images have a much higher resolution, typically below 1 nm, and therefore play a crucial role in semiconductor manufacturing, especially in advanced processes.

[0004] In the process of analyzing the quality of semiconductor processes using TEM images, the most important step is the extraction of contour information. Contour information is a graphical representation of the abstract image information of semiconductor structure imaging. By measuring the critical dimension of the contour, manufacturing errors in the process can be analyzed. By measuring the edge placement error between the contour and the design layout, the accuracy of corrections for specific computational lithography algorithms can be measured.

[0005] Common image contour extraction methods often involve converting the image into a binary image, dividing pixel blocks that meet threshold conditions into contour blocks, and merging the collected contour blocks into the final contour. This method is limited by both the relative size and relative brightness differences of the detected contours, and performs poorly in TEM images captured using high-precision (below 7nm) semiconductor processes.

[0006] Therefore, how to accurately extract the imaging contour information of semiconductor structures in TEM images is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] The purpose of this invention is to provide a method, apparatus, device, and computer-readable storage medium for extracting semiconductor processing contour information, which can improve the extraction accuracy of semiconductor structure imaging contour information in TEM images and provide reliable data for the analysis and evaluation of semiconductor structure processing quality.

[0008] To address the aforementioned technical problems, this invention provides a method for extracting semiconductor processing contour information, comprising:

[0009] Obtain the TEM image and design layout of the chip under test;

[0010] The local layout corresponding to the TEM image to be processed is determined by searching within the design layout.

[0011] Based on the contour distribution position in the local map, determine the corresponding initial screening contour imaging area in the TEM image to be processed;

[0012] Based on the pixel values ​​of each pixel in the initial screening contour imaging region, contour edge detection is performed to obtain the contour information of the processing contour of the wafer under test in the TEM image to be processed.

[0013] In one optional embodiment of this application, a local layout corresponding to the TEM image to be processed is determined by searching the design layout;

[0014] Based on the center point of the imaging structure region on the wafer under test from which the TEM image to be processed is generated, the initial center position point of the center point of the TEM image to be processed is determined in the design layout.

[0015] The initial local layout is divided in the design layout with the initial center position point as the center.

[0016] The similarity calculation is performed on the patterns of different regions in the TEM image to be processed and the initial local layout, and the local layout with the highest similarity to the TEM image to be processed is selected.

[0017] In an optional embodiment of this application, a similarity calculation is performed on the patterns of different regions in the TEM image to be processed and the initial local layout to select the local layout with the highest similarity to the TEM image to be processed, including:

[0018] The Canny edge extraction algorithm is used to perform edge extraction operations on the TEM image to be processed and the initial local layout to obtain a first edge image and a second edge image.

[0019] The similarity between different regions in the first edge map and the second edge map is calculated to obtain the local edge map with the highest similarity between the second edge map and the first edge map.

[0020] The local layout is defined as the layout of the region corresponding to the local edge map in the initial local layout.

[0021] In an optional embodiment of this application, determining the corresponding initial screening contour imaging region in the TEM image to be processed based on the contour distribution position in the local map includes:

[0022] Based on the mapping relationship between the local layout and the TEM image to be processed, the contour edge lines in the local layout are transformed into the pixel coordinate system of the TEM image to be processed to obtain the contour edge pixel lines.

[0023] The initial contour imaging region is determined based on the region enclosed in the TEM image to be processed by the contour edge pixel lines.

[0024] In an optional embodiment of this application, contour edge detection is performed based on the pixel values ​​of each pixel in the initial screening contour imaging region to obtain the contour information of the processing contour of the wafer under test in the TEM image to be processed, including:

[0025] Several contour seed points are selected in the initial contour imaging area.

[0026] Using each of the aforementioned contour seed points as the search starting point, SOBEL edge detection operation is performed to obtain the gradient contour corresponding to each of the aforementioned contour seed points.

[0027] Boolean merging is performed on each gradient contour to obtain the contour information.

[0028] In an optional embodiment of this application, screening a plurality of contour seed points in the initial contour imaging region includes:

[0029] An 8-neighbor sliding window is used to traverse the initial contour imaging area, and the center pixel of the window with the largest pixel value among all pixels in the 8-neighbor sliding window is identified as the initial contour seed point.

[0030] The initial screening contour seed points that are adjacent to each other are merged, and the merged initial screening contour seed points are used as contour seed points.

[0031] In an optional embodiment of this application, adjacent initial screening contour seed points are merged to form contour seed points, and the merged initial screening contour seed points are used as contour seed points. The method further includes:

[0032] For each of the initial screening contour seed points, a candidate bounding box centered on the initial screening contour seed point is drawn;

[0033] A merging ratio calculation is performed between each candidate box. The calculated merging ratio is compared with a set threshold. The initial screening contour seed points corresponding to candidate boxes with a merging ratio greater than the set threshold are mutually adjacent initial screening contour seed points.

[0034] The contour seed points are obtained by replacing each of the adjacent initial screening contour seed points with the centroid pixels of at least two mutually adjacent initial screening contour seed points.

[0035] A semiconductor processing contour information extraction device, comprising:

[0036] The image acquisition module is used to obtain the TEM image and design layout of the chip under test;

[0037] The local search module is used to search and determine the local layout corresponding to the TEM image to be processed in the design layout;

[0038] The initial screening contour module is used to determine the corresponding initial screening contour imaging area in the TEM image to be processed based on the contour distribution position in the local map.

[0039] The contour detection module is used to perform contour edge detection based on the pixel values ​​of each pixel in the initial screening contour imaging area, and obtain the contour information of the processing contour of the wafer under test in the TEM image to be processed.

[0040] A semiconductor processing contour information extraction device, comprising:

[0041] Memory, used to store computer programs;

[0042] A processor for executing the computer program to implement the steps of the semiconductor processing contour information extraction method as described in any of the preceding claims.

[0043] A computer-readable storage medium storing a computer program that is executed to implement the steps of the semiconductor processing contour information extraction method as described in any of the preceding claims.

[0044] The present invention provides a method, apparatus, device, and computer-readable storage medium for extracting semiconductor processing contour information. The method for extracting semiconductor processing contour information includes: obtaining a TEM image of a wafer under test and a design layout; searching and determining a local layout corresponding to the TEM image under test in the design layout; determining a preliminary screening contour imaging region in the TEM image under test based on the contour distribution position in the local layout; and performing contour edge detection based on the pixel values ​​of each pixel in the preliminary screening contour imaging region to obtain the contour information of the processing contour of the wafer under test in the TEM image under test.

[0045] In this application, the design layout of the wafer under test is used to first preliminarily screen and determine the initial contour imaging region in the TEM image to be processed, thereby greatly eliminating the interference of non-contour imaging regions. Then, the contour edge detection algorithm is used to search for edge contours in the initial contour imaging region, so as to obtain accurate and reliable contour information of the wafer under test in the TEM image to be processed. It is not constrained by the relative size difference and relative brightness difference of the contour, ensuring the accuracy of contour information extraction and providing reliable data for the analysis of semiconductor process quality. Attached Figure Description

[0046] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 A schematic flowchart illustrating the semiconductor processing contour information extraction method provided in this application embodiment;

[0048] Figure 2 This is a schematic diagram showing the position of the TEM image provided in the embodiments of this application in the layout diagram.

[0049] Figure 3 A schematic diagram showing the corrected position of the TEM image provided in the embodiment of this application in the layout diagram;

[0050] Figure 4 A schematic diagram of the average processing of the contour seed points of the overlapping candidate box provided in an embodiment of this application;

[0051] Figure 5 This is a structural block diagram of a semiconductor processing contour information extraction device provided in an embodiment of the present invention. Detailed Implementation

[0052] The core of this invention is to provide a method, apparatus, device, and computer-readable storage medium for extracting semiconductor processing contour information, which can accurately extract the contour information of the wafer under test in the TEM image to be processed, and provide reliable data for the analysis of semiconductor process quality.

[0053] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0054] like Figure 1 As shown, Figure 1 This is a schematic flowchart of a method for extracting semiconductor processing contour information provided in an embodiment of this application.

[0055] In one specific embodiment of this application, the method for extracting semiconductor processing contour information may include:

[0056] S1: Obtain the TEM image and design layout of the chip under test.

[0057] In this embodiment, the design layout refers to the layout of the structural shape of the wafer under test (DUT) designed before it is fabricated. In other words, the DUT is fabricated based on the design layout; therefore, apart from process-related errors, the structural shape of the DUT should be substantially the same as the design layout. The TEM image to be processed is the image obtained by scanning and capturing the DUT using a transmission electron microscope. Clearly, the imaging structure formed by the contour imaging in this TEM image should also be substantially consistent with the structural shape of the DUT; that is, there should be a one-to-one correspondence between the DUT, the TEM image, and the design layout.

[0058] S2: Search the design layout to determine the local layout corresponding to the TEM image to be processed.

[0059] It is understandable that a single scan of a transmission electron microscope can only capture a local area of ​​the wafer under test, not the entire wafer. Therefore, a single frame of the TEM image corresponds only to a local structure and a local area in the design layout of the wafer. Thus, this embodiment primarily focuses on extracting contour information from a single frame of the TEM image. For the entire wafer under test, contour information corresponding to each frame can be extracted sequentially using a similar method. By merging the contour information from each frame, the complete contour information of the entire wafer can be obtained.

[0060] Based on this, since there should be a one-to-one correspondence between the chip under test, the TEM image to be processed, and the design layout, it is obvious that the corresponding area of ​​the TEM image to be processed in the design layout can be searched and determined. The layout pattern of this area is also known as the local layout. Obviously, the edge contour of the TEM image to be processed should be roughly the same as the contour distribution position in the local layout. Therefore, the contour imaging area of ​​the TEM image to be processed can be effectively delineated based on the contour distribution position in the local layout.

[0061] Optionally, the process of determining the local layout of the TEM image to be processed corresponding to the actual design layout may include:

[0062] S21: Based on the center point of the imaging structure region on the wafer under test from which the TEM image to be processed is generated, determine the initial center position point of the center point of the TEM image to be processed in the design layout.

[0063] S22: Divide the initial local layout in the design layout with the initial center point as the center;

[0064] S23: Perform similarity calculations on the patterns of different regions in the TEM image to be processed and the initial local layout, and select the local layout with the highest similarity to the TEM image to be processed.

[0065] It is understood that in this embodiment, the TEM image to be processed is generated by scanning a local area of ​​the wafer under test using a transmission electron microscope. This local area is also the imaging structure region on the wafer under test from which the TEM image to be processed is generated. The position of this imaging structure region on the wafer under test can be determined based on the relative positional relationship between the transmission electron microscope and the wafer under test when the transmission electron microscope scans the wafer. Obviously, the center point of this imaging structure region is the imaging point in the TEM image to be processed, which is also the center point of the TEM image to be processed. The position point corresponding to the center point of this imaging structure region in the design layout can also be used as the initial center position point corresponding to the center point of the TEM image to be processed in the design layout.

[0066] An initial local layout can be defined based on this initial center point. Clearly, this initial local layout should at least include the layout portion corresponding to the imaging structure region on the wafer under test. In practical applications, the area of ​​this initial local layout can be at least twice the area of ​​the layout corresponding to the imaging structure region.

[0067] Taking a rectangular area of ​​a×b corresponding to the imaging structure region as an example, a 2a×2b area centered on the initial center point can be divided as the initial local area. In short, while ensuring that the area corresponding to the imaging structure region is included as much as possible, the area of ​​the initial local area should be kept as large as possible to avoid excessive computational load in the subsequent process.

[0068] As mentioned above, since both the TEM image to be processed and the design layout correspond to the same chip under test, there must be local layout patterns in the design layout that are roughly the same as those in the TEM image to be processed. Therefore, by performing similarity calculations on the TEM image to be processed and different regions of the initial local layout in sequence, the region with the highest similarity is obviously the local layout corresponding to the TEM image to be processed.

[0069] Further, optionally, the process of performing similarity calculations on different regions in the TEM image to be processed and the initial local layout may include:

[0070] The Canny edge extraction algorithm is used to perform edge extraction operations on the TEM image to be processed and the initial local layout to obtain the first edge image and the second edge image.

[0071] The similarity of different regions in the first edge map and the second edge map is calculated to obtain the local edge map with the highest similarity between the second edge map and the first edge map;

[0072] The local layout is defined as the region corresponding to the local edge map in the initial local layout.

[0073] In this embodiment, after performing edge extraction operations on the TEM image to be processed and the initial local layout to obtain the first edge image and the second edge image respectively, since the TEM image to be processed belongs to the image in the pixel coordinate system, while the initial local layout does not belong to the image in the pixel coordinate system, the transformation relationship between the TEM image to be processed and the initial local layout can be determined based on the transformation relationship between the TEM image to be processed and the design layout. The transformation relationship between the TEM image to be processed and the initial local layout is also the transformation relationship between the first edge image and the second edge image.

[0074] Based on this, the first edge image can be converted to be in the same coordinate system as the second edge image to obtain the transformed edge image corresponding to the first edge image. A sliding window is set according to the image border of the transformed edge image. The shape of the sliding window should be the same as the image border, and the size should be slightly larger than the image border (at least not smaller). The sliding window is slid on the second edge image to select different local regions and perform similarity calculation with the transformed edge image. Finally, the local region in the second edge image with the highest similarity to the transformed edge image is determined. The region determined in the second edge image is then mapped to the initial local layout, which is the local layout with the highest similarity to the TEM image to be processed.

[0075] S3: Based on the contour distribution position in the local map, determine the corresponding initial screening contour imaging area in the TEM image to be processed.

[0076] As described above, based on the correspondence between the chip under test, the TEM image to be processed, and the design layout, a mapping relationship between the TEM image to be tested and the design layout can be created; on this basis, the conversion relationship between each position point in the design layout and each pixel point in the TEM image to be processed can also be determined accordingly.

[0077] After determining the local layout corresponding to the TEM image to be processed in the design layout, the approximate area of ​​the processing structure on the wafer under test in the TEM image to be processed is determined based on the contour distribution position in the local layout, which is the initial screening contour imaging area.

[0078] Optionally, the process of determining the initial screening contour imaging region may include:

[0079] Based on the mapping relationship between the local layout and the TEM image to be processed, the contour edge lines in the local layout are transformed into the pixel coordinate system of the TEM image to be processed, and the contour edge pixel lines are obtained.

[0080] The initial contour imaging region is determined based on the area delineated by the contour edge pixel lines in the TEM image to be processed.

[0081] Understandably, in order to ensure that the contour imaging in the TEM image to be processed can be fully contained within the initial contour imaging area, the area after extending one or two pixels outward from the area enclosed by the contour edge pixel line in the TEM image to be processed can be used as the initial contour imaging area.

[0082] Clearly, this initial contour imaging region can largely eliminate the interference of the background region in the TEM image to be processed, providing the possibility for subsequent contour information extraction and ensuring the reliability of subsequent contour information extraction.

[0083] S4: Based on the pixel values ​​of each pixel in the initial screening contour imaging area, perform contour edge detection to obtain the contour information of the processing contour of the wafer under test in the TEM image to be processed.

[0084] After determining the initial screening contour imaging region in the TEM image to be processed, the interference of background pixels in the TEM image to extract contour information is eliminated to a certain extent. At this time, the SOBEL operator or other similar edge detection algorithms can be used to perform edge detection calculation based on the pixel values ​​of each pixel in the initial screening contour imaging region. Finally, accurate and reliable contour information of the processing structure of the wafer under test in the TEM image to be processed can be obtained.

[0085] In an optional embodiment of this application, the process of detecting contour information in the TEM image to be processed may include:

[0086] S41: Select several contour seed points in the initial contour imaging area;

[0087] S42: Using each contour seed point as the starting point for the search, perform SOBEL edge detection to obtain the gradient contour corresponding to each contour seed point.

[0088] S43: Perform Boolean merging on each gradient contour to obtain contour information.

[0089] It is understood that in this embodiment, the contour seed point refers to a pixel located within a contour block in the TEM image to be processed; and the contour block refers to the imaging block of the fabricated structure of the wafer under test in the TEM image to be processed. Obviously, selecting pixels within the contour block in the TEM image to be processed as contour seed points, and using these as the starting point for SOBEL edge detection, can further effectively eliminate interference from background pixels, which is beneficial to ensuring the accuracy and reliability of the final determined gradient contour. After determining the gradient contour based on each contour seed point, the gradient contours corresponding to each contour seed point are merged to obtain the contour information.

[0090] Based on the above discussion, in another optional embodiment of this application, the process of selecting and determining contour seed points in the initial screening imaging area may further include:

[0091] S411: An 8-neighbor sliding window is used to traverse the initial contour imaging area, and the center pixel of the window with the largest pixel value among the pixel values ​​of each pixel in the 8-neighbor sliding window is identified as the initial contour seed point.

[0092] S412: Merge adjacent seed points in the initial screening profile to use the merged seed points as profile seed points.

[0093] It is understandable that an 8-neighbor sliding window is a sliding window that can define 3×3 pixels. The pixel located at the center of the 8-neighbor sliding window is the center pixel of the window. It is determined whether the signal strength (i.e., pixel value) of the center pixel of the window is the largest relative to the signal strength of the 8 adjacent pixels. If so, the center pixel of the window is the initial screening contour seed point.

[0094] Building upon this, and further considering that some of the initial screening seed points determined based on the aforementioned 8-neighbor sliding window may be relatively concentrated, and that even if all these concentrated seed points are subjected to subsequent SOBEL edge detection operations, the detected gradient contour overlap rate will be relatively high, increasing the computational load, this embodiment further merges adjacent initial screening seed points; the remaining initial screening seed points after merging are used as the final contour seed points to participate in subsequent SOBEL edge detection operations.

[0095] It is understandable that the initial screening seed points that are adjacent to each other are, as the name suggests, the distance between them does not exceed a certain set distance threshold, and thus they are considered to be adjacent to each other as initial screening seed points.

[0096] In practical applications, there are multiple ways to identify and merge adjacent initial screening contour seed points. For example, the Euclidean distance between each initial screening contour seed point can be calculated based on the pixel coordinates of each initial screening contour seed point in the pixel coordinate system of the TEM image to be processed. A group of initial screening contour seed points whose distance between any two initial screening contour seed points is no greater than a set distance threshold can be taken as adjacent initial screening contour seed points. The same group of adjacent initial screening contour seed points can be merged into one. For example, the centroid pixel of the group of adjacent initial screening contour seed points can be taken as the merged initial screening contour seed point.

[0097] For example, clustering operations can be performed based on the pixel coordinate values ​​in the pixel coordinate system of each initial screening contour seed point, and the cluster radius can be set (which can be half of the distance threshold set above), and the cluster center of the same cluster can be used as the initial screening contour seed point after merging each initial screening contour seed point in that cluster.

[0098] In another optional embodiment of this application, the process of identifying and merging mutually adjacent initial screening contour seed points may further include:

[0099] S4121: For each seed point of the initial screening contour, draw a candidate box centered on the seed point of the initial screening contour.

[0100] S4122: Perform a merging ratio calculation on each candidate box, compare the calculated merging ratio with a set threshold, and select the initial screening contour seed points corresponding to candidate boxes with a merging ratio greater than the set threshold as mutually adjacent initial screening contour seed points.

[0101] S4123: Replace each adjacent initial screening contour seed point with the centroid pixel of at least two adjacent initial screening contour seed points to obtain contour seed points.

[0102] In this embodiment, candidate boxes are drawn for each initial screening contour seed point. Based on the merging ratio between candidate boxes, neighboring initial screening contour seed points are determined. Finally, the centroid pixel of each neighboring initial screening contour seed point, which is also the average position pixel, is used as the merged initial screening contour seed point to achieve non-maximum suppression of each initial screening contour seed point, and the contour seed point can be obtained in the end.

[0103] In summary, this application utilizes the design layout of the wafer under test to first preliminarily screen and determine the initial contour imaging region in the TEM image to be processed, thereby largely eliminating interference from non-contour imaging regions. Then, within this initial contour imaging region, a contour edge detection algorithm is used to search for edge contours, thus obtaining accurate and reliable contour information of the wafer under test in the TEM image to be processed. This is not constrained by differences in relative contour size and relative brightness, ensuring the accuracy of contour information extraction and providing reliable data for the analysis of semiconductor process quality.

[0104] In another optional embodiment of this application, the method for extracting semiconductor processing contour information may further include:

[0105] Step 1: Obtain the TEM image to be processed and the design layout. The initial image center coordinates of the center point of the TEM image to be processed in the layout coordinate system are... .

[0106] The TEM image to be processed is usually a grayscale image, corresponding to a sub-region of the global design layout. The design layout is stored in polygon format, reflecting the actual physical location of the process. However, the coordinates of the image center often fluctuate around the actual coordinates due to the physical limitations of the machine itself.

[0107] Step 2: Set an appropriate field of view size, using the initial image center coordinates in the design layout. Extend outwards from the center according to the field of view size to obtain the candidate area. Extract a local area of ​​the candidate area from the design layout and rasterize it to obtain the layout diagram.

[0108] like Figure 2As shown, the field of view size is a parameter to be adjusted, which can be understood as a loose estimate of the center coordinate jitter range. The size range is between the size of the image region corresponding to the TEM image in the design layout and the global range. Based on actual processing technology, the empirical value is roughly between 1µm and 3µm. In the layout coordinate system, the coordinate value of the upper left corner of the rasterized layout image is... satisfy ;in, These are the width and height dimensions of the field of view, respectively.

[0109] Step 3: Use the Canny edge extraction algorithm to extract edges from the TEM image and the rasterized Layout image to obtain the TEM_Edge image and the Layout_Edge image respectively.

[0110] The Canny edge detection algorithm allows you to set two adjustable parameters: high threshold and low threshold. Depending on the actual working conditions, you can choose to specify the parameters through the interface or to automatically calculate the parameters to deploy the operator. The automatic parameter calculation can be divided into calculation based on the statistical information of image pixel values, calculation based on the mean and standard deviation, and calculation based on the Otsu threshold, depending on the theory.

[0111] Step 4: Using the Layout_Edge graph as the global model and the TEM_Edge graph as the local model, perform a template matching operation (matchtemplate) to find the best matching position.

[0112] Template matching can be understood as using a sliding window of template size to traverse every position in the image, calculating the image similarity at the current position, and sorting the image similarities at each position. Let the global image (i.e., the Layout_Edge image) be I, the template image (i.e., the TEM_Edge image) be T, and the points in T be denoted as . The resulting image is R, and the points in R are denoted as . Image similarity calculation typically employs two methods depending on the image characteristics: calculating the normalized variance and calculating the normalized correlation coefficient. For images with significant area features, the normalized variance can be calculated using the following formula:

[0113] .

[0114] For images with clear edge features, a normalized correlation coefficient can be calculated using the following formula: .

[0115] Step 5: Calculate the corrected image center coordinates based on the obtained best matching position.

[0116] like Figure 3As shown, with the top left corner of the TEM_Edge image as the image anchor point, the coordinates of the matching point of this image anchor point in the Layout_Edge image in the layout coordinate system are denoted as... Based on the coordinates of the matching point, the center coordinates of the corrected image center in the layout diagram are determined as follows: The image width of the TEM image to be processed in the layout coordinate system is denoted as... Like height is recorded as Therefore, the coordinate transformation formula can be determined as follows:

[0117] .

[0118] Step 6: Based on the corrected image center coordinates, determine the local map within the image area, and transform the contour block region in the local map into the image coordinate system of the TEM image to be corrected, thereby obtaining the initial screening imaging area in the image coordinate system.

[0119] Based on the position of the image center coordinates of the corrected TEM image in the Layout image, the corresponding image region of the Layout image is cropped in the Layout image to obtain the local layout_In_Image; the coordinates of any point in the Layout image in the layout coordinate system can be denoted as... The coordinates of any point in the cropped Layout_In_Image, after transformation to the image coordinate system, are denoted as... In the image coordinate system, the size of each pixel in the TEM image under test is... Therefore, the coordinate transformation formula for any point in the local layout_In_Image to the image coordinate system can be determined as follows: .

[0120] Obviously, according to the above coordinate transformation formula, the coordinates of each point on the contour edge line corresponding to the contour block in the local layout_In_Image can be transformed from the layout coordinate system to the image coordinate system; the area enclosed by the contour edge line after transformation to the image coordinate system is the imaging area corresponding to the contour block in the TEM image to be tested, which is also the initial screening imaging area.

[0121] Step 7: Use an 8-neighbor sliding window to traverse the initial screening imaging area in the TEM image to be tested, and find the peak points within the 8-neighbor sliding window as seed points for the initial screening contour.

[0122] The window size should not be too large or too small. A window that is too large will significantly slow down the algorithm's detection speed, while a window that is too small will easily lead to too many local extrema. When the window center point ( When the signal strength of a point is the peak value within an 8-neighbor sliding window, that point is recorded as the initial screening profile seed point. ).

[0123] Step 8: Perform non-maximum suppression on the initial screening contour seed points, and perform average suppression on the initial screening contour seed points that are considered to overlap, to obtain the suppressed contour seed points.

[0124] Choose an appropriate candidate box size as ( Using the initial screening contour seed points generated in step seven as the center of the candidate box, generate contour candidate boxes. Then select an appropriate IOU threshold. If the IOU between two contour candidate boxes is greater than the IOU threshold, the two contour candidate boxes are considered to be overlapping candidate boxes.

[0125] like Figure 4 As shown, the Intersection over Union (IOU) ratio of two candidate contour boxes is calculated using the following formula. For two contour candidate boxes with an IOU greater than the merge ratio threshold (typically 0.8), they are considered overlapping candidate boxes and are placed in the suppression queue. After collecting all overlapping candidate boxes, several groups of overlapping candidate boxes are obtained, where the IOU of any two contour candidate boxes in each group is greater than the merge ratio threshold. The average is calculated for each group, and the result is recorded as the th group. The center point of the outline after averaging the overlapping candidate boxes is ( The number of candidate bounding boxes within a group is M, and its coordinate transformation formula is as follows: ;in, These are the coordinates of the initial contour seed points corresponding to the contour candidate boxes. Based on the above transformation formula, non-maximum suppression can be applied to each initial contour seed point corresponding to the overlapping candidate boxes to obtain the final contour seed points. For example... Figure 4 As shown, Figure 4 The image shows the contour center obtained by averaging the four initial contour seed points corresponding to the four overlapping candidate boxes. The center of the contour ( ), which can be used as the contour seed point to replace the four initial contour seed points.

[0126] Step 9: Use the SOBEL operator to calculate the signal intensity gradients in the X and Y directions of the TEM image to be tested, and obtain the TEM_X_GRAD image and TEM_Y_GRAD image.

[0127] A breadth-first search (BFS) is performed starting from each suppressed contour seed point. The termination condition is that the gradient of the candidate point in the X or Y direction is the peak value in its 4-neighborhood, or the distance of the candidate point outside the map is greater than a given threshold. This yields the gradient contour corresponding to each contour seed point.

[0128] The convolution kernel in the X direction is Pixels in the TEM image to be tested ( The signal strength is Then the contour gradient in the X direction is:

[0129] .

[0130] The convolution kernel in the Y direction is Pixels in the TEM image to be tested ( The signal strength is Then the contour gradient in the Y direction is:

[0131] .

[0132] Step 10: Summarize all the obtained gradient contours and perform a Boolean merging operation to obtain the final contour.

[0133] Compared to the traditional Block Scan algorithm, the implementation method in this embodiment has a significant advantage when there are large differences in contour brightness. The latter is difficult to adjust a single threshold to adapt to a large number of batches of images, while the former has less parameter tuning process and is more automated.

[0134] In practical applications, the error between the measured CD value and the true value of the contour at a given location can be analyzed to measure the quality of the contour extracted from the TEM image. As shown in Table 1 below, Table 1 is a comparison table of the contour measurement CD values ​​obtained by two different methods for the same given area in the TEM image.

[0135] Table 1:

[0136]

[0137] As can be seen from the comparison data in Table 1, the contour extraction method in this application embodiment can significantly improve the accuracy of CD measurement at key locations.

[0138] In addition, the EPE values ​​of the given location contours and design layouts are analyzed to measure the quality of the contours extracted from the TEM images. As shown in Table 2, multiple TEM images and their corresponding design layouts from a batch are taken. Table 2 is a comparison table of the contour EPE rms values ​​obtained by extracting contours using the Block Scan algorithm and the embodiments of this application, with the image as the smallest unit.

[0139] Table 2:

[0140]

[0141] As can be seen from the comparison data in Table 2, the contour extraction method in this application can significantly reduce EPE error.

[0142] The semiconductor processing contour information extraction device provided in the embodiments of the present invention will be described below. The semiconductor processing contour information extraction device described below and the semiconductor processing contour information extraction method described above can be referred to in correspondence.

[0143] Figure 5 This is a structural block diagram of a semiconductor processing contour information extraction device provided in an embodiment of the present invention, with reference to... Figure 5 The device for extracting semiconductor processing contour information may include:

[0144] Image acquisition module 100 is used to acquire the TEM image and design layout of the wafer under test;

[0145] Local search module 200 is used to search and determine the local layout corresponding to the TEM image to be processed in the design layout;

[0146] The preliminary screening contour module 300 is used to determine the corresponding preliminary screening contour imaging area in the TEM image to be processed based on the contour distribution position in the local map.

[0147] The contour detection module 400 is used to perform contour edge detection based on the pixel values ​​of each pixel in the initial screening contour imaging area to obtain the contour information of the processing contour of the wafer under test in the TEM image to be processed.

[0148] In an optional embodiment of this application, the local search module 200 is specifically used to determine the initial center position point of the center point of the TEM image to be processed in the design layout based on the center point of the imaging structure region on the wafer under test from which the TEM image to be processed is generated; to divide the design layout with the initial center position point as the center; to perform similarity calculation on the patterns of different regions of the TEM image to be processed and the initial local layout, and to filter out the local layout with the highest similarity to the TEM image to be processed.

[0149] In an optional embodiment of this application, the local search module 200 is specifically used to perform edge extraction operations on the TEM image to be processed and the initial local layout using the Canny edge extraction algorithm to obtain a first edge image and a second edge image; to calculate the similarity of different regions in the first edge image and the second edge image to obtain the local edge image with the highest similarity between the second edge image and the first edge image; and to use the layout of the region corresponding to the local edge image in the initial local layout as the local layout.

[0150] In an optional embodiment of this application, the initial contour screening module 300 is specifically used to convert the contour edge lines in the local layout to the pixel coordinate system of the TEM image to be processed according to the mapping relationship between the local layout and the TEM image to be processed, thereby obtaining contour edge pixel lines; and to determine the initial contour imaging area according to the area enclosed by the contour edge pixel lines in the TEM image to be processed.

[0151] In an optional embodiment of this application, the contour detection module 400 is specifically used to screen a number of contour seed points in the initial contour imaging area; to perform SOBEL edge detection operation with each of the contour seed points as the search starting point to obtain the gradient contour corresponding to each contour seed point; and to perform Boolean merging on each of the gradient contours to obtain the contour information.

[0152] In an optional embodiment of this application, the contour detection module 400 is specifically used to traverse the initial contour imaging area using an 8-neighbor sliding window, identify the window center pixel with the largest pixel value among the pixel values ​​of each pixel point in the 8-neighbor sliding window as the initial contour seed point; and merge the initial contour seed points that are adjacent to each other to use the merged initial contour seed points as contour seed points.

[0153] In an optional embodiment of this application, the contour detection module 400 is specifically used to delineate candidate boxes centered on each of the initial screening contour seed points; perform a merging ratio calculation on each of the candidate boxes, compare the calculated merging ratio with a set threshold, and identify the initial screening contour seed points corresponding to candidate boxes with merging ratios greater than the set threshold as mutually adjacent initial screening contour seed points; and replace each of the mutually adjacent initial screening contour seed points with the centroid pixels of at least two mutually adjacent initial screening contour seed points to obtain the contour seed points.

[0154] The semiconductor processing contour information extraction device of this embodiment is used to implement the aforementioned semiconductor processing contour information extraction method. Therefore, the specific implementation of the semiconductor processing contour information extraction device can be found in the embodiment section of the semiconductor processing contour information extraction method above. The specific implementation can be referred to the description of the corresponding embodiments, which will not be repeated here.

[0155] This application also provides an embodiment of a semiconductor processing contour information extraction device, which may include:

[0156] Memory, used to store computer programs;

[0157] A processor for executing the computer program to implement the steps of the semiconductor processing contour information extraction method as described in any of the preceding claims.

[0158] This application also provides a computer-readable storage medium storing a computer program that is executed to implement the steps of the semiconductor processing contour information extraction method as described in any of the preceding claims.

[0159] The computer-readable storage medium may include random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0160] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that the elements inherent in a process, method, article, or apparatus that includes a list of elements are included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Additionally, portions of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.

[0161] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A method for extracting semiconductor processing contour information, characterized in that, include: Obtain the TEM image and design layout of the chip under test; The local layout corresponding to the TEM image to be processed is determined by searching within the design layout. Based on the contour distribution position in the local map, determine the corresponding initial screening contour imaging area in the TEM image to be processed; Based on the pixel values ​​of each pixel in the initial screening contour imaging region, contour edge detection is performed to obtain the contour information of the processing contour of the wafer under test in the TEM image to be processed. Based on the contour distribution position in the local map, the corresponding initial screening contour imaging region in the TEM image to be processed is determined, including: Based on the mapping relationship between the local layout and the TEM image to be processed, the contour edge lines in the local layout are transformed into the pixel coordinate system of the TEM image to be processed to obtain the contour edge pixel lines. The initial screening contour imaging region is determined based on the region circled in the TEM image to be processed by the contour edge pixel line. Based on the pixel values ​​of each pixel in the initial screening contour imaging region, contour edge detection is performed to obtain the contour information of the processing contour of the wafer under test in the TEM image to be processed, including: Several contour seed points are selected in the initial contour imaging area. Using each of the contour seed points as the search starting point, SOBEL edge detection operation is performed to obtain the gradient contour corresponding to each contour seed point. Boolean merging is performed on each gradient contour to obtain the contour information; Several contour seed points are selected in the initial contour imaging region, including: An 8-neighbor sliding window is used to traverse the initial screening contour imaging area, and the center pixel of the window with the largest pixel value among all pixel values ​​in the 8-neighbor sliding window is identified as the initial screening contour seed point. The initial screening contour seed points that are adjacent to each other are merged, and the merged initial screening contour seed points are used as contour seed points.

2. The method for extracting semiconductor processing contour information as described in claim 1, characterized in that, Searching and determining the local layout corresponding to the TEM image to be processed within the design layout includes: Based on the center point of the imaging structure region on the wafer under test from which the TEM image to be processed is generated, the initial center position point of the center point of the TEM image to be processed is determined in the design layout. The initial local layout is divided in the design layout with the initial center position point as the center. The similarity calculation is performed on the patterns of different regions in the TEM image to be processed and the initial local layout, and the local layout with the highest similarity to the TEM image to be processed is selected.

3. The method for extracting semiconductor processing contour information as described in claim 2, characterized in that, The similarity calculation is performed on the patterns of different regions in the TEM image to be processed and the initial local layout image, and the local layout image with the highest similarity to the TEM image to be processed is selected, including: The Canny edge extraction algorithm is used to perform edge extraction operations on the TEM image to be processed and the initial local layout to obtain a first edge image and a second edge image. The similarity between different regions in the first edge map and the second edge map is calculated to obtain the local edge map with the highest similarity between the second edge map and the first edge map. The local layout is defined as the layout of the region corresponding to the local edge map in the initial local layout.

4. The method for extracting semiconductor processing contour information as described in any one of claims 1 to 3, characterized in that, The process of merging adjacent initial screening contour seed points to obtain the final contour seed points also includes: For each of the initial screening contour seed points, a candidate bounding box centered on the initial screening contour seed point is drawn. A merging ratio calculation is performed between each candidate box. The calculated merging ratio is compared with a set threshold. The initial screening contour seed points corresponding to candidate boxes with a merging ratio greater than the set threshold are mutually adjacent initial screening contour seed points. The contour seed points are obtained by replacing each of the adjacent initial screening contour seed points with the centroid pixels of at least two mutually adjacent initial screening contour seed points.

5. A device for extracting semiconductor processing contour information, characterized in that, include: The image acquisition module is used to obtain the TEM image and design layout of the chip under test; The local search module is used to search and determine the local layout corresponding to the TEM image to be processed in the design layout; The initial screening contour module is used to determine the corresponding initial screening contour imaging area in the TEM image to be processed based on the contour distribution position in the local map. The contour detection module is used to perform contour edge detection based on the pixel values ​​of each pixel in the initial screening contour imaging area, and obtain the contour information of the processing contour of the wafer under test in the TEM image to be processed. The initial screening contour module is specifically used to convert the contour edge lines in the local layout to the pixel coordinate system of the TEM image to be processed according to the mapping relationship between the local layout and the TEM image to be processed, thereby obtaining the contour edge pixel lines; and to determine the initial screening contour imaging area according to the area enclosed by the contour edge pixel lines in the TEM image to be processed. The contour detection module is specifically used to screen a number of contour seed points in the initial contour imaging area; to perform SOBEL edge detection operation with each of the contour seed points as the search starting point to obtain the gradient contour corresponding to each of the contour seed points; and to perform Boolean merging on each of the gradient contours to obtain the contour information. The contour detection module is further configured to use an 8-neighbor sliding window to traverse the initial screening contour imaging area, identify the window center pixel with the largest pixel value among the pixel values ​​of each pixel in the 8-neighbor sliding window as the initial screening contour seed point; and merge the initial screening contour seed points that are adjacent to each other to use the merged initial screening contour seed points as contour seed points.

6. A device for extracting semiconductor processing contour information, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the semiconductor processing contour information extraction method as described in any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that is executed to implement the steps of the semiconductor processing contour information extraction method as described in any one of claims 1 to 4.

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