Multi-path electric energy acquisition method and device based on dynamic compensation and isolation anti-interference

Abstract

The invention relates to the technical field of intelligent power grids, and particularly discloses a multipath electric energy acquisition method and device based on dynamic compensation and isolation anti-interference, and the method comprises the steps: carrying out the processing and control of electric energy data collected by a plurality of metering chips METER through a main control unit MCU; the state of an input power supply is monitored through a power supply management unit, and when abnormal power failure is detected, interruption is triggered and standby energy is provided for data storage; and sampling signals of the plurality of metering chips METER are collected through an anti-interference metering unit, and anti-interference processing is executed. By integrating the main control unit, the power management unit and the anti-interference metering unit, the core pain point of the existing low-voltage electric energy acquisition equipment is accurately solved: the anti-interference metering unit depends on multiple metering chips to be matched with the SPI communication isolation module and the interference suppression module, so that the problem that the number of sampling channels of the traditional equipment is limited is broken through to adapt to the multi-channel acquisition requirement; and electromagnetic interference and power supply noise can be effectively suppressed, and the stability of sampling signals is ensured.

Description

Technical Field

[0001] This invention relates to the field of smart grid technology, and in particular to a method and apparatus for multi-channel power acquisition based on dynamic compensation and isolation anti-interference. Background Technology

[0002] Against the backdrop of the rapid development of smart grid technology, the low-voltage power distribution link, as the core node of user-side power management, has an increasingly urgent need for real-time acquisition and high-precision metering of multiple power data. Current low-voltage power acquisition equipment must simultaneously meet the requirements of high-density sampling (adapting to multi-user, multi-circuit monitoring scenarios), stable operation in complex electromagnetic environments (resisting electromagnetic interference generated by switching operations and equipment start-ups / shutdowns within the power distribution system), and continuous power supply assurance (coping with grid outages, voltage fluctuations, and other anomalies). However, existing technologies generally suffer from a limited number of sampling channels, with a single device only supporting a few circuits, making it difficult to adapt to the multi-node, full-coverage acquisition needs of smart distribution networks. Furthermore, most devices lack targeted anti-interference design, and power supply noise and electromagnetic interference can easily lead to sampling signal distortion, directly affecting the accuracy of metering data and failing to provide reliable data support for power distribution management and fault diagnosis.

[0003] Furthermore, existing low-voltage power data acquisition equipment has significant shortcomings in terms of data integrity and security: on the one hand, when encountering abnormal power outages, the equipment often lacks efficient backup energy supply and data protection mechanisms, resulting in the loss of unstored metering data and affecting the continuity of electricity consumption statistics; on the other hand, as power data is a key information for user electricity consumption and grid dispatch, existing equipment often lacks hardware-level physical encryption modules, making it vulnerable to security risks such as unauthorized access and data tampering, and failing to meet the requirements for secure storage of power data. Summary of the Invention

[0004] This invention aims to at least partially solve one of the technical problems in related technologies. Therefore, the objective of this invention is to propose a multi-channel power acquisition method and device based on dynamic compensation and isolation anti-interference, to meet the reliability and security requirements of smart distribution networks for acquisition devices.

[0005] To achieve the above objectives, a first aspect of the present invention proposes a multi-channel power acquisition method based on dynamic compensation and isolation anti-interference, characterized in that the method includes the following steps: The main control unit processes and controls the electrical energy data collected by multiple metering chips. The power management unit monitors the input power status and triggers an interrupt to provide backup power for data saving when an abnormal power failure is detected. The sampling signals of the multiple metering chips are acquired by an anti-interference metering unit, and anti-interference processing is performed; wherein, the anti-interference processing includes: Signal isolation and drive control between the main control unit and each metering chip are achieved through an SPI communication isolation module. Electromagnetic interference and power supply noise are suppressed through an interference suppression module; The metering accuracy is dynamically calibrated based on ambient temperature and sampling error through the metering accuracy compensation and data redundancy module, and key metering data is backed up.

[0006] To achieve the above objectives, a second aspect of the present invention provides a multi-channel power acquisition device based on dynamic compensation and isolation anti-interference, the device comprising: Main control unit, power management unit, and anti-interference metering unit; The main control unit is used for processing power metering data and controlling and managing the power management unit and the anti-interference metering unit. The power management unit is used to monitor the power status and provide energy buffering in the event of an abnormal power outage; The anti-interference metering unit includes multiple metering chips, and an SPI communication isolation module, an interference suppression module, and a metering accuracy compensation and data redundancy module configured for each metering chip, used for collecting and processing electrical energy data to prevent interference.

[0007] To achieve the above objectives, a third aspect of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory. When the computer program is executed by the processor, it implements the above-described multi-channel power acquisition method based on dynamic compensation and isolation anti-interference.

[0008] The multi-channel power acquisition method and device based on dynamic compensation and isolation anti-interference in this invention, by integrating a main control unit, a power management unit, and an anti-interference metering unit, precisely addresses the core pain points of existing low-voltage power acquisition equipment: the anti-interference metering unit, relying on multiple metering chips combined with an SPI communication isolation module and an interference suppression module, not only overcomes the limitation of the number of sampling channels in traditional equipment to adapt to multi-channel acquisition needs, but also effectively suppresses electromagnetic interference and power supply noise, ensuring stable sampling signals; the power management unit and the abnormal power failure data protection module work together to quickly trigger an interrupt and provide backup energy when an abnormal power failure is detected, avoiding the loss of data. The main control unit's physical encryption and fault monitoring module achieves secure storage of power data through hardware-level encryption, preventing unauthorized access and data tampering risks. The metering accuracy compensation and data redundancy module, combined with dynamic gain adjustment of digital potentiometers and real-time calibration by temperature sensors, can effectively correct for environmental temperature and hardware sampling errors, maintaining the long-term metering accuracy of the equipment. At the same time, it uses non-volatile memory to back up key metering data, further ensuring data integrity. Overall, it significantly improves the reliability, security, and metering accuracy of low-voltage multi-channel power acquisition, fully meeting the high reliability, high security, and high precision operation requirements of smart distribution networks for acquisition devices. Attached Figure Description

[0009] Figure 1 This is a flowchart illustrating the multi-channel power acquisition method based on dynamic compensation and isolation anti-interference provided by the present invention. Figure 2 This is a schematic diagram of the structure of the multi-channel power acquisition device based on dynamic compensation and isolation anti-interference provided by the present invention; Figure 3 This is a schematic diagram of the circuit structure of the power management unit in the multi-channel power acquisition device based on dynamic compensation and isolation anti-interference provided by the present invention. Figure 4 This is a schematic diagram of the circuit structure of the abnormal power failure data protection module in the multi-channel power acquisition device based on dynamic compensation and isolation anti-interference provided by the present invention. Figure 5 This is a schematic diagram of the circuit structure of the physical encryption and fault monitoring module in the multi-channel power acquisition device based on dynamic compensation and isolation anti-interference provided by the present invention; Figure 6 This is a schematic diagram of the circuit structure of the SPI communication isolation module in the multi-channel power acquisition device based on dynamic compensation and isolation anti-interference provided by the present invention; Figure 7 This is a schematic diagram of the circuit structure of the interference suppression module in the multi-channel power acquisition device based on dynamic compensation and isolation anti-interference provided by the present invention; Figure 8It is a schematic circuit diagram of the measurement accuracy compensation and data redundancy module in the multi-channel power acquisition device based on dynamic compensation and isolation anti-interference provided by the present invention; Figure 9 It is a schematic structural diagram of the electronic device provided by the present invention. Specific embodiments

[0010] The embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, in which the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as a limitation of the present invention.

[0011] The multi-channel power acquisition method, device and electronic device based on dynamic compensation and isolation anti-interference according to the embodiments of the present invention will be described below with reference to the accompanying drawings. Embodiment

[0012] Figure 1 It is a schematic flowchart of the multi-channel power acquisition method based on dynamic compensation and isolation anti-interference according to an embodiment of the present invention. This method uses a system architecture of software and hardware collaboration to solve key technical problems such as easy data loss, poor anti-interference ability, measurement accuracy affected by the environment, and insufficient security during multi-channel power acquisition in a low-voltage distribution environment. The core of this method lies in the collaboration of three units: the main control unit is responsible for central control and data processing; the power management unit ensures the robustness and reliability of system power supply, especially in abnormal situations (such as power anomalies like power failure and voltage fluctuation); the anti-interference measurement unit is responsible for accurately and highly integrally collecting multi-channel power signals.

[0013] The specific implementation of this method will be described in detail step by step as follows: The first step: The main control unit processes and controls the power data collected by multiple metering chips.

[0014] The first step of this method is the core processing and control link of the system. The main control unit takes the microprocessor MCU as the core, and its role is far more than simple data aggregation. It undertakes the tasks of global scheduling, complex operations, and intelligent management.

[0015] The microprocessor MCU communicates with the metering chips METER in multiple anti-interference measurement units through the high-speed SPI (Serial Peripheral Interface) bus. It periodically polls or reads the original measurement data such as voltage, current, power, and energy from each metering chip METER through interrupts. Since it is multi-channel acquisition, the MCU needs to precisely control the communication timing with each channel of metering chips through the chip select signal CS to avoid bus conflicts, and this function is assisted by the SPI communication isolation module in the subsequent steps.

[0016] After reading the data, the MCU will perform a series of data processing tasks, including: 1. Data verification and integration: Perform CRC verification on the read raw data to ensure that no errors occur during data transmission, and then integrate the multiple data streams into a structured data packet.

[0017] 2. Numerical calculation and conversion: Based on the register data provided by the metering chip and the preset voltage and current transformer ratios, the actual electrical parameter values ​​are calculated.

[0018] 3. Logic Control: The MCU sends control commands to other units based on system status (such as power failure warning signals from the power management unit) and user configuration. For example, it sends a switching signal to the enable terminal of the first regulator LDO1 in the power management unit to control its output; and sends encryption or reset commands to the physical encryption and fault monitoring module.

[0019] Step 2: Monitor the input power status through the power management unit, and trigger an interrupt to provide backup power for data saving when an abnormal power failure is detected.

[0020] Robust power management is the cornerstone of ensuring data integrity. This method's power management process not only provides a stable voltage for daily operation but also possesses rapid response and buffering capabilities against abnormal power outages.

[0021] like Figure 3 As shown, during normal operation, the input power first passes through the self-resetting fuse F, providing overcurrent and short-circuit protection. Then, the power enters the Buck step-down chip U0, which efficiently reduces the higher input voltage to an intermediate voltage. This voltage is then further precisely regulated by the first regulator LDO1 to obtain a very clean 3.3V or 5V voltage, powering core components such as the MCU and encryption chip. Simultaneously, the supercapacitor C0 is charged from the output of the Buck chip through the second diode D2, acting like an energy reservoir, ready to unleash its power. The first voltage monitoring chip IC1 monitors the voltage across the supercapacitor C0 in real time.

[0022] When an abnormal power outage occurs, i.e., when the input power supply voltage suddenly drops, this method executes the following key sequence, the circuit logic of which can be found in [reference needed]. Figure 4 The circuit diagram of the abnormal power failure data protection module shown is as follows: 1. Voltage Comparison and Interrupt Trigger: A stable reference voltage Vref is connected to the non-inverting input of voltage comparator U1. The input power supply is divided by resistors R1 and R2 and then connected to the inverting input of voltage comparator U1. When the input power supply voltage is normal, the voltage at the inverting input is higher than Vref, and the comparator outputs a low level. When a power failure occurs and the input voltage drops below the threshold, the voltage at the inverting input is lower than Vref, and the output of voltage comparator U1 will momentarily jump to a high level. This high-level signal is directly sent to the MCU's first interrupt input pin INT-FAULT1, triggering a high-level interrupt, notifying the MCU to immediately stop the current task and prepare to execute the emergency data saving procedure.

[0023] 2. Backup Energy Release: The aforementioned high-level signal is simultaneously sent to the gate of the first MOSFET Q1, causing it to quickly turn on. After turning on, the energy stored in the first capacitor C1 (which has been pre-charged from the input power supply through the fourth resistor R4) is quickly released into the subsequent circuit through the third diode D3. The network composed of the fifth resistor R5 and the sixth resistor R6 is used to limit the discharge current and adjust the voltage level, forming a short-term, relatively stable backup power supply (second VCC power supply VCC2), providing energy assurance for critical chips such as the MCU and memory to continue operating for tens to hundreds of milliseconds after a complete power failure.

[0024] 3. Safety Reset: The second voltage monitoring chip IC2 continuously monitors the voltage across the first capacitor C1. When the energy is about to be depleted and the voltage drops to its reset threshold, IC2 sends a signal to the MCU's reset pin RESET, forcing the MCU to perform an orderly reset and preventing it from performing erroneous operations when the voltage is too low, which could lead to data corruption.

[0025] Through this series of monitoring-interruption-power-reset operations, this method provides the system with a valuable data retention window, fundamentally solving the problem of data loss caused by momentary power outages.

[0026] The third step involves acquiring the sampling signals from multiple metering chips through an anti-interference metering unit and performing anti-interference processing. This is the core of achieving high-precision acquisition. Anti-interference processing is not a single action, but a composite process completed collaboratively by three sub-modules, covering the entire process from communication and power supply to signal sampling.

[0027] Sub-step 1: Implement signal isolation and drive control between the main control unit and each metering chip through the SPI communication isolation module.

[0028] Sharing the SPI bus between multiple devices can easily lead to conflicts and interference. This method employs a hardware logic isolation scheme; its circuit implementation is detailed in the appendix. Figure 6 .

[0029] When the main control unit needs to send data to a metering chip (METER), the MCU first pulls down the corresponding chip select signal CS. This CS signal controls the conduction of the second transistor Q3 through the tenth resistor R10, thereby allowing the MCU's MOSI signal to be transmitted to the input of the tri-state buffer U2 through Q3. The latch U3 is used to lock the current CS signal state and control the output enable terminal of the tri-state buffer U2, ensuring that data can only be sent to the MOSI pin of the metering chip through U2 when the chip is selected.

[0030] When receiving data, the output pin signal of the metering chip is isolated by the fourth diode D4, and then smoothed by the RC filter network composed of the eleventh resistor R11 and the second capacitor C2 to eliminate glitches and interference. Finally, the clean signal is sent back to the MISO pin of the MCU.

[0031] D flip-flops (DFFs) utilize the synchronous triggering of the clock signal CLK in conjunction with the rising edge of the CS signal to generate precise timing control signals. This further ensures the stability of the tri-state buffer enable control and avoids timing race issues during multi-channel chip select signal switching. This method achieves physical isolation and timing synchronization between communication channels in hardware, greatly improving the reliability of multi-channel communication.

[0032] Sub-step 2: Suppress electromagnetic interference (EMI) and power supply noise through the interference suppression module.

[0033] A clean power supply is a prerequisite for accurate metering. This method equips each metering chip with an independent power supply noise filtering network; its circuit structure is detailed in the appendix. Figure 7 .

[0034] The power supply first passes through a dual π-type filter composed of the first inductor L1 and the second inductor L2 (combined with the third capacitor C3), effectively suppressing high-frequency noise from the power line. The filtered voltage is then input to the second regulator LDO2 for linear regulation, resulting in an extremely stable analog voltage supplied to the power input pin of the metering chip. At the output of LDO2, a fourth capacitor C4 and a fifth capacitor C5 are connected in parallel. The former is usually a ceramic capacitor used to filter out high-frequency noise, and the latter is usually an electrolytic capacitor used to provide transient response current to the load. The cooperation between the second regulator LDO2 and the output decoupling capacitors (fourth capacitor C4 and fifth capacitor C5) enables the metering chip to maintain high-precision and stable operation even when the power supply voltage fluctuates or the load changes abruptly. This provides it with a localized, low-impedance clean power supply, which isolates external interference to the maximum extent from the power supply head.

[0035] Sub-step 3: The measurement accuracy is dynamically calibrated based on ambient temperature and sampling error through the measurement accuracy compensation and data redundancy module, and key measurement data is backed up.

[0036] This is the ultimate guarantee for achieving long-term high precision and data security; its circuit implementation is detailed in the appendix. Figure 8 .

[0037] 1. Dynamic calibration of measurement accuracy: Gain Compensation: The sampled signal is first connected to the fixed terminal P0 of the digital potentiometer DPOT, and its sliding terminal output is grounded through the twelfth resistor R12, forming a programmable voltage divider. The MCU dynamically adjusts the resistance value of the digital potentiometer DPOT through digital control interfaces such as I²C or SPI, thereby fine-tuning the signal amplitude input to the analog input terminal of the metering chip METER and compensating for gain errors caused by resistor aging, line attenuation, or component variability.

[0038] Temperature Compensation: The TEMP temperature sensor monitors the ambient temperature inside the device in real time and transmits the analog voltage signal to the ADC channel of the MCU. The algorithm built into the MCU will find or calculate a compensation coefficient based on this temperature value to correct the raw data read by the metering chip and eliminate the impact of temperature drift on the metering accuracy.

[0039] In addition, the sixth capacitor C6 and the seventh capacitor C7 are connected in parallel at the power supply end of the metering chip to provide final local decoupling and ensure the power supply quality of the analog circuit section.

[0040] 2. Back up critical measurement data: The power-down detection chip U4 constantly compares the +5V power supply with the internal reference voltage. When an abnormal power drop is detected, its output immediately sends a signal to another interrupt input pin of the MCU.

[0041] Upon receiving this signal (potentially earlier than the power-off interrupt in step two), the MCU will immediately initiate an emergency data backup program, writing all key metering data and calibration parameters, including the currently processed power data, the register configuration parameters of the metering chip, the current resistance value of the digital potentiometer DPOT, and the temperature compensation coefficient, into the non-volatile second memory EEPROM2.

[0042] In this way, even if the system is completely powered off, this critical information will not be lost. When the system is powered on again, the MCU will first read this data from EEPROM2 and quickly restore the last working state, achieving seamless data continuity and maintaining measurement accuracy.

[0043] In summary, the method detailed in this embodiment organically integrates power management, data security, communication isolation, noise suppression, and dynamic compensation technologies into a unified whole through a sophisticated, interconnected process that combines hardware and software. It not only achieves basic multi-channel power data acquisition but also significantly improves the data integrity, metering accuracy, and system reliability of the acquisition device in complex electromagnetic environments, effectively addressing various industry pain points mentioned in the background section. Example

[0044] This embodiment details the specific hardware configuration of a multi-channel power data acquisition device based on dynamic compensation and isolation anti-interference. Through its unique hardware architecture and modular design, this device physically implements the aforementioned methods, aiming to provide a highly reliable, high-precision, and highly secure multi-channel power data acquisition solution for low-voltage power distribution systems.

[0045] The overall hardware architecture and signal flow of the device are as follows: Figure 2 As shown, its core consists of three main units: the main control unit, the power management unit, and the anti-interference metering unit. These three units are not simply stacked, but rather form an organic and coordinated whole through precise circuit design and logical connections.

[0046] 1. Main control unit The main control unit is responsible for executing complex data processing algorithms and coordinating the control of all other units. Its core is a microcontroller (MCU), such as a high-performance, low-power microcontroller based on the ARM Cortex-M core. This MCU has a sufficient number of I / O ports, multiple high-speed SPI interfaces, an ADC channel, and an interrupt controller to meet the needs of multi-channel data acquisition and real-time control. The MCU does not operate independently; its performance and reliability are greatly enhanced through two dedicated hardware modules: (1) Abnormal Power Loss Data Protection Module: This module exists as an independent hardware watchdog and energy buffer. For example... Figure 4 As shown, it consists of core components such as a voltage comparator U1, a first MOSFET Q1, a first capacitor C1, a third diode D3, and a second voltage monitoring chip IC2. These components are connected through a specific resistor network (R1-R6) to form a fast voltage monitoring and response circuit. The physical connections are as follows: the input power supply is divided by R1 and R2 and then fed into U1; the output of U1 simultaneously controls the interrupt pin of the MCU and the gate of Q1; the drain of Q1 is connected to the positive terminal of C1 through D3; the positive terminal of C1 simultaneously powers IC2, and the output of IC2 is connected to the reset pin of the MCU. This hardware circuit ensures that the hardware can react to power failure events immediately before software intervention.

[0047] (2) Physical encryption and fault monitoring module: This module provides hardware-level security for the device. For example... Figure 5 As shown, its core is a dedicated encryption chip, ENC, which communicates with a first memory, EEPROM1, and the MCU via the I²C bus. The SCL and SDA signal lines of the I²C bus are pulled up to a 3.3V power supply through resistors R7 (seventh resistor) and R8 (eighth resistor), respectively, ensuring communication stability. The clock of the encryption chip is provided by a crystal oscillator Y, ensuring precise timing of encryption operations. A key hardware control link is that a control pin CTRL of the MCU is connected to the base of the first transistor Q2 through resistor R9, and the collector of Q2 is directly connected to the reset pin RST of the encryption chip. This hardware design allows the MCU to directly force the encryption chip to reset via hardware circuitry when a security threat is detected, resulting in extremely fast response and high security.

[0048] 2. Power Management Unit The power management unit is responsible for processing the external input power into clean, stable multi-channel voltages and providing uninterrupted power supply for the entire system. Its specific circuit implementation is as follows: Figure 3 As shown.

[0049] The design of this unit embodies a multi-layered protection hardware concept. A self-resetting fuse F is first connected in series at the positive terminal of the input power supply, serving as the first line of hardware protection against overcurrent and short-circuit faults. Subsequently, the power supply enters the Buck step-down chip U0, which efficiently reduces it to an intermediate voltage. This intermediate voltage is divided into two paths: one path undergoes secondary stabilization via the first regulator LDO1, providing an extremely clean 3.3V operating voltage for the core chip. The enable pin of LDO1 is controlled by the MCU's GPIO pin, enabling software-managed energy-saving switching. The other path charges the supercapacitor C0 through the second diode D2. The second diode D2 plays a crucial unidirectional conduction role, preventing energy backflow into the supercapacitor when the main power supply fails. The hardware connection point of the first voltage monitoring chip IC1 is located at the positive terminal of the supercapacitor C0, and its reset output is directly coupled to the MCU's reset pin, thus forming an independent hardware monitoring loop to ensure a forced system reset in case of abnormal backup power supply voltage.

[0050] 3. Anti-interference metering unit The anti-interference metering unit is responsible for accurately capturing multiple power signals. This unit is not simply a parallel connection of multiple metering chips; instead, each metering chip is equipped with three complete sets of hardware protection, as shown in the structure below. Figure 2 The extension of the anti-interference measurement unit section is shown, with details corresponding to... Figure 6 , Figure 7 , Figure 8 .

[0051] SPI communication isolation module (circuit structure see) Figure 6 This module utilizes discrete logic chips to construct a hardware isolation channel. The second transistor Q3, tri-state buffer U2, latch U3, and D flip-flop DFF work together, using the chip select signal CS of the metering chip as the control signal, to achieve hardware-level isolation and selection of the SPI bus among multiple slave devices, completely avoiding data conflicts and bus contention.

[0052] Interference suppression module (circuit structure see) Figure 7 This module provides an independent purified power supply for each metering chip. The first inductor L1 and the second inductor L2, together with the third capacitor C3, form a π-type filter to first filter out high-frequency noise. Then, the second voltage regulator LDO2 performs linear voltage regulation, and the fourth capacitor C4 and the fifth capacitor C5 connected in parallel at its output are responsible for absorbing the instantaneous current fluctuations generated by the chip operation, ensuring that the voltage ripple supplied to the metering chip is minimal.

[0053] Measurement accuracy compensation and data redundancy module (circuit structure see...) Figure 8 This module forms the hardware foundation for accuracy and safety. The digital potentiometer DPOT, as a programmable analog front-end, has its sliding contact grounded via the twelfth resistor R12, allowing the MCU to dynamically adjust the signal amplitude input to the metering chip through a digital interface, achieving hardware-level gain calibration. The temperature sensor TEMP directly converts the ambient temperature physical quantity into an electrical signal for the MCU to acquire and use for software compensation. The positive input terminal IN+ of the power-down detection chip U4 is connected to a +5V power supply, and the negative input terminal IN- is connected to a reference voltage. Its output directly drives the MCU's interrupt pin; this hardware link ensures the highest priority for power-down warnings. All key parameters are ultimately stored in the non-volatile device secondary memory EEPROM2, achieving physical data persistence.

[0054] In summary, the device described in this embodiment materializes functional requirements through a series of specific and innovative hardware circuit designs. The various modules work together through clear physical connections, such as power lines, signal lines, interrupt lines, and reset lines, forming a physical entity capable of performing high-precision data acquisition, possessing strong anti-interference capabilities, and extremely high operational reliability. This provides an excellent hardware foundation for solving the technical challenges of low-voltage multi-channel power acquisition. Example

[0055] This embodiment is a further refinement and specification of Embodiment 2. It concretizes each sub-module of the main control unit, power management unit, and anti-interference metering unit into a hardware circuit composed of specific components connected in a specific topology, forming a full-link, hardware-level protection and optimization system from power input and signal acquisition to data processing. The device described in this embodiment is a physical entity with the highest reliability, safety, and metering accuracy.

[0056] 1. Specific hardware configuration of the main control unit The main control unit includes a microprocessor (MCU), an abnormal power failure data protection module, and a physical encryption and fault monitoring module.

[0057] The microprocessor (MCU) selected is a 32-bit ARM Cortex-M series chip with rich peripherals. This MCU has multiple SPI interfaces for connecting to multiple metering chips, sufficient ADC channels for acquiring temperature sensor signals, and multiple timers and interrupt controllers to meet the needs of real-time processing and multi-task scheduling. It is the logic control core and data convergence point of all hardware functional modules.

[0058] The specific circuit configuration of the abnormal power failure data protection module is as follows: Figure 4 As shown, it is a sophisticated analog-digital hybrid monitoring circuit, and its detailed connection relationships and working principle are as follows: Voltage Sampling and Comparison Section: The positive terminal VIN of the input power supply is connected through the first terminal of the first resistor R1. The second terminal of the first resistor R1 is connected to both the inverting input of voltage comparator U1 and the first terminal of the second resistor R2. The second terminal of the second resistor R2 is connected to the fourth ground terminal GND4. R1 and R2 form a voltage divider network, proportionally reducing the input power supply voltage before sending it to the comparator. The non-inverting input of voltage comparator U1 is connected to a stable reference voltage Vref, which can be generated by a precision reference voltage source chip. The output of U1 is pulled up to the first VCC power supply VCC1 through the third resistor R3.

[0059] Interrupt Triggering and Power Control Section: The output of U1 is connected to two key points: the first interrupt input pin INT-FAULT1 of the MCU, and the gate G of the first MOSFET Q1. The source S of the first MOSFET Q1 is connected to the second VCC power supply VCC2, and its drain D is connected to the first capacitor C1 through the third diode D3. The cathode of the third diode D3 is connected to the drain D of the first MOSFET Q1, and the anode of the third diode D3 is connected to the first terminal (positive terminal) of the first capacitor C1. The first terminal of the first capacitor C1 is also connected to the positive terminal VIN of the input power supply through the fourth resistor R4 to realize the pre-charge function; the negative terminal of the second terminal of C1 is connected to the sixth ground terminal GND6.

[0060] Discharge control and final reset section: Starting from the anode of the third diode D3, the fifth resistor R5 and the sixth resistor R6 are connected in series to the fifth ground terminal GND5. The function of the fifth resistor R5 and the sixth resistor R6 is to limit the discharge current and form a controllable sustaining voltage at the anode of D3. The power input terminal VCC of the second voltage monitoring chip IC2 is connected to the first terminal of the first capacitor C1 to monitor its voltage in real time. The ground terminal GND of IC2 is connected to the system common ground terminal, and its reset output terminal RESET is connected to the reset pin RESE of the MCU.

[0061] The specific circuit configuration of the physical encryption and fault monitoring module is as follows: Figure 5 As shown, its core is the construction of a secure hardware encryption environment: Encryption Core and Storage: The encryption chip ENC has its interrupt output pin INT-OUT connected to the MCU's other interrupt input pin INT. The ENC's serial clock pin SCL and serial data pin SDA are connected to corresponding pins of the first memory EEPROM1 via the I²C bus for storing keys and sensitive data. The SCL and SDA lines of the I²C bus are pulled up to the 3.3V power supply via resistors R7 (seventh resistor) and R8 (eighth resistor), respectively. The write protection pin WP of the first memory EEPROM1 is connected to the seventh ground terminal GND7, permanently disabling the write protection function; its write operations are entirely controlled by the encryption chip.

[0062] Clock and Reset Control: The output of crystal oscillator Y is connected to the external clock input pin CLKIN of the encryption chip ENC, providing it with a precise clock source. The ground terminal of Y is connected to the ninth ground terminal GND9. To enable active control of the encryption chip by the MCU, a general-purpose control pin CTRL of the MCU is connected to the base of the first transistor Q2 through the ninth resistor R9. The emitter of Q2 is connected to the eighth ground terminal GND8, and its collector is directly connected to the reset pin RST of the encryption chip ENC. When the MCU pulls the CTRL signal high, Q2 conducts, pulling the RST pin of ENC low, thus achieving a hardware forced reset.

[0063] 2. Specific hardware configuration of the power management unit The specific circuit configuration of the power management unit is as follows: Figure 3 As shown, it is a multi-level protection power supply system with backup capabilities: Input protection and step-down: The first terminal of the resettable fuse F is connected to the positive terminal of the external power supply, and the second terminal is connected to the input pin VIN of the Buck step-down chip U0. The ground pin GND of U0 is connected to the negative terminal of the power supply. U0 efficiently steps down the 24V input voltage to +5V.

[0064] Precise voltage regulation and backup power: The cathode of the first diode D1 is connected to the second terminal of the resettable fuse F, and its anode is connected to the first ground terminal GND1 to suppress voltage spikes at the input. The input terminal IN of the first voltage regulator LDO1 is connected to the output terminal of the Buck chip U0, and its output terminal OUT outputs a stable 3.3V to power the MCU, etc. The enable terminal EN of LDO1 is connected to an input / output pin GPIO of the MCU, which can be turned off by software to save energy. The positive terminal (first terminal) of the supercapacitor C0 is connected to the +5V output terminal of the Buck chip U0 through the anode of the second diode D2 (such as 1N5819); the cathode of D2 is connected to the positive terminal of C0 to prevent reverse discharge. The negative terminal (second terminal) of C0 is connected to the second ground terminal GND2.

[0065] Backup power monitoring: The power supply terminal VCC of the first voltage monitoring chip IC1 is connected to the positive terminal of the supercapacitor C0, its ground terminal GND is connected to the third ground terminal GND3, and its reset terminal RESET is connected to the MCU's reset pin RESET. IC1 continuously monitors the voltage on the supercapacitor, and once it falls below a threshold, such as 3.0V, it sends a reset signal to the MCU.

[0066] 3. Specific hardware configuration of the anti-interference measurement unit The anti-interference metering unit includes multiple metering chips (METER), and each METER is configured with the following three sub-modules: The circuit of the SPI communication isolation module is as follows: Figure 6 As shown, it is a hardware chip select and isolation network based on discrete logic devices: Transmission isolation: The emitter of the second transistor Q3 is connected to the signal output pin MOSI of the MCU, and its collector is connected to the data input terminal of the tri-state buffer U2; the base of Q3 is connected to the first chip select signal CS1 pin of the metering chip METER through the tenth resistor R10.

[0067] Buffering and Control: The data output terminal of the tri-state buffer U2 is connected to the MOSI input pin of the metering chip METER. The output enable terminal OE of U2 is connected to the output terminal Q of the latch U3. The input terminal D of the latch U3 is connected to the second chip select signal CS2 pin of the metering chip METER.

[0068] Receiver filtering and timing: The anode of the fourth diode D4 is connected to the output pin MISO of the metering chip METER, and its cathode is connected to the first terminal of the eleventh resistor R11. The second terminal of R11 is connected to the first terminal of the second capacitor C2, and the second terminal of C2 is connected to the tenth ground terminal GND10, forming an RC filter. The clock input terminal CLK of the D flip-flop DFF is connected to the third chip select signal CS3 pin of the metering chip, and its output terminal Q is connected back to the output enable terminal OE of the tri-state buffer U2, forming timing feedback.

[0069] The circuit of the interference suppression module is as follows: Figure 7 As shown, it is a multi-stage power supply filtering and voltage regulation circuit: π-type filter: The first terminal of the first inductor L1 is connected to the +5V power supply, and its second terminal is connected to the first terminal of the second inductor L2. The first terminal of the third capacitor C3 is connected to the junction of the first inductor L1 and the second inductor L2, and its second terminal is connected to the eleventh ground terminal GND11.

[0070] Linear regulation and decoupling: The input terminal IN of the second regulator LDO2 is connected to the second terminal of the second inductor L2, and its output terminal OUT is connected to the power input pin AVDD of the metering chip METER. A fourth capacitor C4 and a fifth capacitor C5 are connected in parallel between the output terminal of LDO2 and the twelfth ground terminal GND12.

[0071] The circuit of the measurement accuracy compensation and data redundancy module is as follows: Figure 8 As shown, it is key to achieving high precision and data security: Dynamic compensation: The first terminal P0 of the digital potentiometer DPOT is connected to the sampling signal from the voltage / current sampling circuit. The second terminal P1 of the DPOT is connected to the analog input terminal (VIP / VIN) of the metering chip METER. The sliding terminal of the DPOT is connected to the first terminal of the twelfth resistor R12, and the second terminal of R12 is connected to the thirteenth ground terminal GND13. The digital control interface of the DPOT, such as I²C's SCL / SDA, is connected to the corresponding communication interface pin of the MCU.

[0072] Temperature monitoring and local decoupling: The output of the temperature sensor TEMP is connected to the ADC channel of the MCU, and its input is connected to a 3.3V power supply. The sixth capacitor C6 and the seventh capacitor C7 are connected in parallel between the power supply terminal DVDD of the metering chip METER and the ground terminal.

[0073] Power-down detection and data storage: The positive input terminal IN+ of the power-down detection chip U4 is connected to a +5V power supply, and its negative input terminal IN- is connected to a stable reference voltage. The output terminal of U4 is connected to the interrupt input pin of the MCU, and its ground terminal is connected to the fourteenth ground terminal GND14. The second memory EEPROM2 is connected to the MCU via I²C or SPI bus and is used to store backup data.

[0074] In this embodiment, the device ensures that data is not lost due to power failure through an abnormal power-loss data protection module and a power management unit; ensures data security and integrity through a physical encryption and fault monitoring module; ensures the reliability of the data acquisition process through an SPI communication isolation module and an interference suppression module; and finally, ensures the long-term accuracy and recoverability of the measurement results through a metering accuracy compensation and data redundancy module. This complete hardware protection chain gives the device unparalleled advantages in complex low-voltage power distribution environments. Example

[0075] Corresponding to the above embodiments, the present invention also proposes an electronic device.

[0076] like Figure 9 The diagram shows a structural schematic of an electronic device according to the present invention. The electronic device 200 includes a processor 201 and a memory 203. The processor 201 and the memory 203 are connected, for example, via a bus 202. Optionally, the electronic device 200 may further include a transceiver 204. It should be noted that in practical applications, the transceiver 204 is not limited to one unit, and the structure of this electronic device 200 does not constitute a limitation on the embodiments of the present invention.

[0077] Processor 201 may be a CPU, a general-purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, transistor logic device, hardware component, or any combination thereof. It may implement or execute the various exemplary logic blocks, modules, and circuits described in connection with this disclosure. Processor 201 may also be a combination that implements computational functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0078] Bus 202 may include a path for transmitting information between the aforementioned components. Bus 202 may be a PCI bus or an EISA bus, etc. Bus 202 may be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 9 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0079] The memory 203 stores a computer program corresponding to the multi-channel power acquisition method based on dynamic compensation and isolation anti-interference in the above embodiments of the present invention. This computer program is executed by the processor 201. The processor 201 executes the computer program stored in the memory 203 to implement the content shown in the aforementioned method embodiments.

[0080] Among them, electronic devices 200 include, but are not limited to: mobile terminals such as laptops and tablets, as well as fixed terminals such as desktop computers. Figure 9The electronic device 200 shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0081] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, transmit, or transport programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, the computer-readable medium can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0082] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0083] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0084] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0085] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A multi-channel power acquisition method based on dynamic compensation and isolation anti-interference, characterized in that, The method includes the following steps: The main control unit processes and controls the electrical energy data collected by multiple metering chips. The power management unit monitors the input power status and triggers an interrupt to provide backup power for data saving when an abnormal power failure is detected. The sampling signals of the multiple metering chips are acquired by an anti-interference metering unit, and anti-interference processing is performed; wherein, the anti-interference processing includes: Signal isolation and drive control between the main control unit and each metering chip are achieved through an SPI communication isolation module. Electromagnetic interference and power supply noise are suppressed through an interference suppression module; The metering accuracy is dynamically calibrated based on ambient temperature and sampling error through the metering accuracy compensation and data redundancy module, and key metering data is backed up.

2. The method according to claim 1, characterized in that, The process of triggering an interrupt and providing backup power for data preservation upon detecting an abnormal power outage specifically includes: The input power supply voltage is compared with the reference voltage using a voltage comparator; When the input power supply voltage is lower than the reference voltage, the voltage comparator outputs a high-level interrupt signal to the first interrupt input pin of the main control unit; At the same time, the high-level interrupt signal turns on the first MOSFET, causing the pre-charged first capacitor to release the stored energy through the third diode, providing a short-term sustaining voltage for the main control unit; The voltage of the first capacitor is monitored by a second voltage monitoring chip, and a reset signal is sent to the reset pin of the main control unit when the voltage is lower than a set threshold.

3. The method according to claim 1 or 2, characterized in that, The method also includes steps for secure data storage and fault monitoring: The electricity metering data is encrypted using an encryption chip and then stored in the first memory. When the encryption chip detects unauthorized access, abnormal temperature, or voltage fluctuation, it sends an interrupt signal to the main control unit through its interrupt output pin. The main control unit controls the reset pin of the encryption chip via the control pin through the first transistor, thereby achieving a forced reset of the encryption chip.

4. The method according to claim 1, characterized in that, The dynamic calibration measurement accuracy specifically includes: The gain of the sampling signal input to the metering chip is adjusted by a digital potentiometer. The sliding terminal of the digital potentiometer is grounded through the twelfth resistor, and its digital control interface is controlled by the main control unit. The ambient temperature is monitored in real time by a temperature sensor, and the temperature signal is transmitted to the ADC channel of the main control unit for temperature compensation of the measurement results.

5. The method according to claim 1 or 4, characterized in that, The backup key metering data specifically includes: monitoring the system power supply voltage +5V through a power failure detection chip, and sending an interrupt signal to the main control unit when the voltage is abnormal; In response to the interrupt signal, the main control unit writes the current measurement data and calibration parameters into a non-volatile second memory.

6. A multi-channel power acquisition device based on dynamic compensation and isolation anti-interference for implementing the method of any one of claims 1-5, characterized in that, The device includes: a main control unit, a power management unit, and an anti-interference metering unit; The main control unit is used for processing power metering data and controlling and managing the power management unit and the anti-interference metering unit. The power management unit is used to monitor the power status and provide energy buffering in the event of an abnormal power outage; The anti-interference metering unit includes multiple metering chips, and an SPI communication isolation module, an interference suppression module, and a metering accuracy compensation and data redundancy module configured for each metering chip, used for collecting and processing electrical energy data to prevent interference.

7. The apparatus according to claim 6, characterized in that, The main control unit includes a microprocessor, an abnormal power failure data protection module, and a physical encryption and fault monitoring module. The abnormal power failure data protection module includes: a voltage comparator, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a first MOSFET, a third diode, and a second voltage monitoring chip; The physical encryption and fault monitoring module includes: an encryption chip, a first memory, a seventh resistor, an eighth resistor, a ninth resistor, a first transistor, and a crystal oscillator.

8. The apparatus according to claim 6, characterized in that, The power management unit includes: a Buck step-down chip, a first voltage regulator, a supercapacitor, a first diode, a second diode, a first voltage monitoring chip, and a resettable fuse; The self-resetting fuse is connected in series between the positive terminal of the input power supply and the input pin of the Buck step-down chip; The supercapacitor is connected to the output terminal of the Buck step-down chip via a second diode; The power supply terminal of the first voltage monitoring chip is connected to the positive terminal of the supercapacitor, and its reset output terminal is connected to the reset pin of the microprocessor of the main control unit.

9. The apparatus according to claim 6, characterized in that, The SPI communication isolation module includes: a second transistor, a tri-state buffer, a latch, a fourth diode, a tenth resistor, an eleventh resistor, a second capacitor, and a D flip-flop; The interference suppression module includes: a first inductor, a second inductor, a second voltage regulator, a third capacitor, a fourth capacitor, and a fifth capacitor; The metering accuracy compensation and data redundancy module includes: a digital potentiometer, a twelfth resistor, a temperature sensor, a sixth capacitor, a seventh capacitor, a second memory, and a power failure detection chip.

10. The apparatus according to claim 9, characterized in that, The first end of the digital potentiometer is connected to the sampling signal source, the second end is connected to the analog input terminal of the metering chip, and the sliding end is connected to the first end of the twelfth resistor. The positive input terminal of the power failure detection chip is connected to a +5V power supply, the negative input terminal is connected to a reference voltage, and the output terminal is connected to the interrupt input pin of the microprocessor of the main control unit.

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