Video stitching storage control method based on driving record camera system

Abstract

The invention relates to the technical field of vehicle-mounted image processing and storage, in particular to a video stitching storage control method based on a driving record camera system. The method comprises the following steps: acquiring an original video frame of a camera, adding a synchronization timestamp to the original video frame, recording angle values of a left rotating bracket and a right rotating bracket, and generating a time-space synchronization data packet; performing geometric correction on the original video frames of the left and right paths according to the rotation angle value in the space-time synchronization data packet to generate a standard view field frame set; and in a pre-developed memory virtual canvas, combining the front-path frame, the left-path standard frame and the right-path standard frame in the standard view field frame set according to a preset position to generate a synthesized main code stream frame. According to the invention, a traditional multi-file storage mode is replaced by two continuous large files and a cyclic coverage mechanism, so that the phenomenon of storage fragmentation is eliminated fundamentally, and the problems of the driving recording system in three dimensions of real-time performance, safety and reliability are effectively solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of vehicle-mounted image processing and storage technology, and in particular to a video splicing storage control method based on a driving record camera system. BACKGROUND

[0002] The traditional vehicle-mounted surround view system generally uses a high-performance GPU image fusion algorithm to process multiple video signals, resulting in an end-to-end delay of more than 300 ms from acquisition to display, which cannot meet the strict requirements of real-time during driving, greatly reducing the practical value of the system in emergency situations. The traditional system uses a mechanically fixed lens that cannot dynamically adjust the viewing angle with the vehicle turning, resulting in a high blind area of up to 25% in turning scenarios, causing key frames to be lost and posing a major safety hazard. The low storage efficiency caused by the independent storage mechanism of multiple videos results in up to 40% storage fragmentation after long-term use, which not only severely affects read and write speed but also significantly shortens the service life of the storage medium, increasing the risk of system failure.

[0003] In summary, the existing technology has problems of high processing delay, large blind area, and serious storage fragmentation, which need to be solved. SUMMARY

[0004] Therefore, it is necessary to provide a video splicing storage control method based on a driving record camera system to solve at least one of the above technical problems.

[0005] To achieve the above purpose, a video splicing storage control method based on a driving record camera system is applied to a driving record camera system, which includes four cameras and left and right rotating supports. The four cameras include a front camera, left and right cameras, and a rear camera. The left and right cameras are installed on the left and right rotating supports. The method includes the following steps: Step S1: Obtain the original video frames of the camera and add a synchronization timestamp to the original video frames. Record the angle values of the left and right rotating supports to generate a space-time synchronization data packet. Step S2: Perform geometric correction on the left and right original video frames according to the rotation angle values in the space-time synchronization data packet to generate a standard field of view frame set. Step S3: In a pre-created memory virtual canvas, combine the front frame, left standard frame, and right standard frame in the standard field of view frame set according to the preset position to generate a synthesized main stream frame. Step S4: Encode and compress the synthesized main stream frame, and decide whether to independently encode the rear original frame according to the existence state of the rear camera to generate a data stream unit to be written. Step S5: creating and maintaining a continuous data pool file and an index area on a preset storage medium, writing a data stream unit to be written into a corresponding data pool file according to the index area, and updating a persistent storage index.

[0006] The application controls four cameras to collect images simultaneously through high-precision synchronous clock signals, combines microsecond-level timestamp marking and accurate rotation angle recording, and solves the misalignment problem caused by the time difference of multiple video signals in the traditional scheme. The space-time synchronization data packet formed in this step provides strictly aligned original data for subsequent processing, eliminates the "ghost" and "fault" phenomena caused by time difference in traditional systems, and provides a basic condition for dynamic field of view adjustment with high-resolution recording (0.088°) of the angle sensor, greatly improving the environmental perception ability of the system when the vehicle turns. Based on the preset fisheye model parameters and the geometric correction processing of the real-time rotation angle, the high-visibility blind area of up to 25% generated by the traditional fixed lens when turning is effectively eliminated, and the blind area is reduced to within 5%. The use of lookup table and linear interpolation method significantly reduces the computational complexity, and the correction processing delay is controlled within milliseconds, while maintaining high-precision geometric transformation effect. The standard field of view frame set generated in this step lays the foundation for seamless splicing of three pictures, solving the problem of key information loss caused by fixed viewing angle in the traditional surround view system during vehicle turning. The physical coordinate mapping splicing method replaces the traditional GPU image fusion algorithm with direct memory block copy operation, reducing the splicing processing delay from more than 300ms to within 7ms, achieving efficient splicing with zero computing power consumption. The dynamically adjusted picture ratio mechanism intelligently allocates picture resources according to the vehicle speed and turning state, ensuring that the driver obtains the optimal field of view information in different scenarios. The brightness histogram adaptive enhancement technology solves the problem of uneven splicing picture caused by the difference in lighting conditions of different road sections, making the entire surround view picture visually consistent, and greatly improving the practicability of the system in complex lighting environments. The dual-encoder parallel processing architecture compresses the three spliced pictures and the rear independent picture in H.265 and H.264 formats respectively, reducing the bandwidth demand by about 50% while ensuring high picture quality. The intelligent encoding strategy dynamically adjusts the code rate allocation according to the connection state of the rear camera, avoiding resource waste. The hardware-accelerated encoding implementation controls the encoding delay within 30ms, combined with the previous steps, ensures that the total delay of the system is less than 100ms, meeting the strict requirements of real-time driving monitoring. The standardized data stream unit design simplifies the storage and playback process, improves the data recovery ability of the system in abnormal situations. The Format-Free pre-allocated index storage scheme completely solves the storage fragmentation problem caused by the traditional multi-file storage mode, reduces the fragmentation rate from more than 40% after 3 months in the traditional scheme to permanent 0%, significantly prolongs the service life of the storage medium and maintains long-term stable read / write performance. The B+ tree structure index and two-stage commit mechanism ensure data integrity and fast retrieval ability. The dual-SD card redundant storage and hot plug support provide high data security, even in the case of single card failure or replacement, zero data loss can be achieved.The stepped air duct heat dissipation and intelligent temperature management system enables the device to work stably in extreme environments, further enhancing the reliability and durability of the vehicle recording system.

[0007] Therefore, the application realizes the video splicing processing with zero algorithm power consumption by replacing the traditional GPU image fusion algorithm with "physical coordinate mapping"; at the same time, the turning blind area problem is solved by combining the ±15° rotating bracket with the dynamic distortion correction technology; and the Format-Free pre-allocation index storage scheme is introduced, so that the traditional multi-file storage mode is replaced by two continuous large files plus a cyclic coverage mechanism, which fundamentally eliminates the storage fragmentation phenomenon and effectively solves the core technical problems of the vehicle recording system in the three dimensions of real-time, safety and reliability. BRIEF DESCRIPTION OF DRAWINGS

[0008] Fig. 1 A step flowchart of a video splicing storage control method based on a vehicle recording camera system is provided. Fig. 2 A video processing flowchart of a vehicle-mounted three-way annular camera system in the application is provided.

[0009] The object implementation, functional features and advantages of the application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0010] The technical method of the application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the application.

[0011] In addition, the accompanying drawings are only schematic illustrations of the application, and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus repeated descriptions thereof will be omitted. Some block diagrams shown in the drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different network and / or processor methods and / or microcontroller methods.

[0012] It should be understood that, although the terms "first", "second" or the like can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the example embodiments. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0013] To achieve the above object, there is provided Figs. 1-2 The application provides a video splicing storage control method based on a driving record camera system, comprising the following steps: Step S1: obtaining original video frames of a camera, adding a synchronous timestamp to the original video frames, recording angle values of left and right rotating supports, and generating a space-time synchronous data packet; In the embodiment of the application, a 25Hz synchronous clock signal is sent to the four-way camera and the left and right rotating support control units through an I2C bus, the four-way camera simultaneously performs a frame collection operation, a front output has a resolution of 3840x2160, and the remaining three outputs have a resolution of 1920x1080. A main controller reads a current system time from a 64-bit hardware timer as a synchronous timestamp, writes the synchronous timestamp into a metadata area of each video frame, simultaneously reads angle data of a built-in AS5600 magnetic encoder of the left and right rotating supports through an SPI interface, and the angle resolution is 0.088°. Finally, the four-way original frames, the synchronous timestamp, and the rotating angle values are packaged into a space-time synchronous data packet, which contains a 128-byte metadata header and variable-length video data, so as to ensure the time and space consistency of the data.

[0014] Step S2: performing geometric correction on the original video frames of the left and right channels according to the rotating angle values in the space-time synchronous data packet, and generating a standard field of view frame set; In the embodiment of the application, the 1920x1080 resolution original frames of the left and right channels and the corresponding rotating angle values are extracted from the space-time synchronous data packet, an equidistant projection fisheye model parameter (focal length fx=962.5, fy=963.2, optical center coordinates cx=960, cy=540, radial distortion coefficient k1=-0.382, etc.) is accessed based on the equidistant projection fisheye model parameter, and a lookup table stored in a Flash is accessed. The lookup table covers a range of-25° to +25°, steps 0.5°, and a total of 101 angle gears. The system determines an accurate mapping matrix through linear interpolation, performs reverse geometric transformation by using a bilinear interpolation algorithm, corrects perspective distortion and trapezoidal distortion caused by lens rotation, and finally generates a standard field of view frame set containing the front original frame and the corrected left and right channel standard frames.

[0015] Step S3: In the pre-excavated memory virtual canvas, the front frame, the left standard frame and the right standard frame in the standard field of view frame set are combined according to the preset position to generate a synthesized main code stream frame; In the embodiment of the application, 18662400 bytes of continuous space are allocated in the DDR4 memory as a virtual canvas, corresponding to a 3840*3240 pixel YUV420 format image. The splicing operation is realized by three times of DMA transmission: the front frame data is copied to the upper half [0, 0] to [3840, 2160] area of the virtual canvas; the left standard frame is copied to the lower left part [0, 2160] to [1920, 3240] area; and the right standard frame is copied to the lower right part [1920, 2160] to [3840, 3240] area. The system automatically adjusts the splicing ratio according to the vehicle speed, adjusts the front picture height ratio at three threshold values of 35km / h, 70km / h and 100km / h, simultaneously dynamically expands the steering side picture width to 1.5 times according to the steering wheel angle, and applies adaptive contrast enhancement based on the brightness histogram to the spliced picture.

[0016] Step S4: The synthesized main code stream frame is encoded and compressed, and it is determined whether to independently encode the rear original frame according to the existence state of the rear camera to generate a data stream unit to be written; In the embodiment of the application, the rear camera connection state flag is read from the metadata header of the space-time synchronization data packet. When the rear camera is detected, two groups of independent hardware encoders are started: the first group is configured in H.265 / HEVC encoding mode (Main Profile, Level 5.1, 8Mbps code rate, CQP=26) to process the 3840*3240 main code stream frame; the second group is configured in H.264 / AVC encoding mode (High Profile, Level 4.2, 4Mbps code rate) to process the 1920*1080 rear original frame. When the rear camera is not detected, only the first group of encoders is started, and the code rate is increased to 10Mbps. After encoding, the system packs the compressed data and the metadata into a standardized data stream unit, including a 128-byte header and a variable-length data part.

[0017] Step S5: A continuous data pool file and an index area are created and maintained on a preset storage medium, the data stream unit to be written is written into the corresponding data pool file according to the index area, and the persistent storage index is updated; In the embodiment of the present application, two fixed-size continuous data pool files are created on the SD card: 29.5 GB MAIN_POOL.BIN and 14.5 GB REAR_POOL.BIN, and the first 4 MB area is divided into an index area and organized in a B+ tree structure. After receiving a data stream unit to be written, the system reads the current write position pointers P_main and P_rear, writes the data into the corresponding positions in the two pool files through a direct sector access command, and matches the physical sectors of the SD card using a 4 KB aligned block size. After writing is completed, the index information is updated and a two-phase commit is performed to ensure atomicity. When the pointers approach the end of the file, they are automatically rolled back to the starting position to form a circular coverage. The system integrates a dual-SD card redundant storage mechanism and a thermal management protection to achieve high-reliability storage with permanent zero fragmentation.

[0018] Preferably, step S1 comprises: sending a synchronous clock signal to the control units of the four-way camera and the left and right rotating supports; receiving video frames collected by the four-way camera at the same time and adding a uniform synchronous timestamp; reading the angle camera data built in the left and right rotating supports to obtain the rotation angle values; binding the synchronous video frames, the synchronous timestamp, and the rotation angle values to form a space-time synchronous data packet.

[0019] In this embodiment, the space-time synchronization data packet generation process is realized through a multi-stage synchronization clock distribution and data integration mechanism. The main controller first generates a 25Hz synchronization clock signal based on the internal 32.768kHz crystal oscillator after frequency multiplication by PLL and frequency division, with a clock accuracy of ±10ppm. This synchronization clock signal is sent to the front 4K camera module, left 1080P camera module, right 1080P camera module, rear 1080P camera module, and the STM32F103 control unit built-in in the left and right rotating brackets through the I2C bus. When the four-way camera receives the rising edge of the synchronization clock signal, it immediately triggers the CMOS image sensor to perform a complete frame acquisition operation. The front camera outputs a 3840x2160 resolution raw video frame, and the left and right rear cameras output a 1920x1080 resolution raw video frame. All video frames are transmitted to the main controller video input buffer through the MIPI CSI-2 interface. The main controller reads the current system time value from the internal 64-bit hardware timer, accurate to microseconds, and writes this time value as a synchronization timestamp to the 8-byte space at offset 16 bytes in each video frame metadata area. Synchronized with video acquisition is the rotation angle data acquisition. The 12-bit magnetic encoder AS5600 built-in in the left and right rotating brackets reports the current rotation angle to the STM32F103 control unit in real time through the SPI interface, with an angle resolution of 0.088°. The control unit converts the original 12-bit angle data to a signed floating-point number representation, with a range of -25.0° to +25.0°, and sends the angle data packet to the main controller through the CAN bus at a frequency of 100Hz. After receiving the angle data, the main controller aligns the time according to the synchronization timestamp, and matches the angle value closest to the video frame acquisition time with the corresponding video frame. Finally, the main controller encapsulates the front raw frame, left raw frame, right raw frame, rear raw frame (if connected), 64-bit synchronization timestamp, left rotation angle value, and right rotation angle value into a complete space-time synchronization data packet, using a fixed-length binary format with a total size of video data size plus 128-byte metadata header. The metadata header includes a 4-byte packet identifier 0xABCD1234, an 8-byte synchronization timestamp, the starting offset address of each video frame, the left and right rotation angle values, and a 16-byte CRC32 checksum to ensure data integrity. This space-time synchronization mechanism eliminates the inter-frame time difference problem of traditional multi-camera systems, achieving sub-millisecond acquisition synchronization accuracy.

[0020] Preferably, step S2 comprises: extracting the left and right raw frames and corresponding rotation angle values from the space-time synchronization data packet; obtaining vehicle driving parameters including vehicle steering angle, vehicle yaw angle, and vehicle lateral acceleration; dynamically tracking and controlling the rotation angles of the left and right rotating brackets according to the vehicle driving parameters to obtain the rotation angle values; Based on the preset lens internal parameter model and the rotation angle value, a preset lookup table is called, wherein the lens internal parameter model is a fisheye model or a wide-angle model, the range of the rotation angle value is ±15°, and the accuracy is ±0.5°; The original frames of the left and right paths are subjected to reverse geometric transformation to eliminate picture distortion and stretching caused by rotation. A standard field frame set is generated.

[0021] In the embodiment, the standard field frame set generation process first reads the left original frame starting offset address and the right original frame starting offset address from the metadata header of the space-time synchronization data packet, extracts 1920*1080 resolution YUV420 format original image data to the processing buffer, and reads the left rotation angle value and the right rotation angle value from the 24th byte and the 28th byte of the metadata header. The system reads the driving parameters provided by the vehicle ESP electronic stability system through the CAN bus at a frequency of 50 Hz, including the steering wheel steering angle (range ±720°, resolution 0.1°), vehicle yaw angle (range ±45°, resolution 0.01°) and lateral acceleration alat(range ±1.5g, resolution 0.001g).

[0022] Based on these parameters, the system performs dynamic rotation tracking control, and the calculation formula is: ; ; The calculation result is sent to the left and right STM32F103 rotating support control units through the CAN bus at a frequency of 100 Hz to perform precise angle adjustment, with an adjustment range limited within ±15° and an adjustment accuracy of ±0.5°. The lens intrinsic parameter model pre-calibrated by the system adopts an equidistant projection fisheye model, which is obtained by Zhang Zhengyou's calibration method and contains focal length fx=962.5 pixels, fy=963.2 pixels, optical center coordinates cx=960 pixels, cy=540 pixels, and radial distortion coefficients k1=-0.382, k2=0.147, k3=-0.029, and k4=0.005. Based on the lens intrinsic parameters and the rotating angle value, the system accesses the lookup table LUT stored in the Flash, which covers the range of-15° to +15° at a step of 0.5°, a total of 61 angle positions, and each position corresponds to a mapping matrix of 2073600 bytes, recording the mapping relationship of the target pixel to the source pixel. The processing unit determines the two closest angle positions according to the current rotating angle by linear interpolation, for example, when the left side angle is-12.3°, the mapping matrices of-12.5° and-12.0° positions are extracted, and the accurate mapping matrix is obtained by fusing them with a weight of 0.6:0.4. The reverse geometric transformation adopts a bilinear interpolation algorithm, traverses each pixel coordinate (u, v) of the target image, finds the corresponding source image coordinates (x, y) through the mapping matrix, extracts the pixel values of the four integer coordinates around (x, y) in the source image, and calculates the brightness and chroma values of the target pixel. In the transformation, for the coordinates outside the boundary of the source image, a mirror filling strategy is adopted to map the coordinates exceeding the boundary back to the effective area according to the boundary symmetry. After the reverse geometric transformation, the perspective distortion and trapezoidal distortion caused by the lens rotation in the left and right images are completely corrected, generating a standard 1920x1080 rectangular picture. Finally, the processing unit combines and packages the unprocessed 3840x2160 front road original frame, the corrected 1920x1080 left standard frame, and the 1920x1080 right standard frame into a standard field of view frame set, adopts a continuous memory layout, and the total size is 12441600 bytes, of which the first 8294400 bytes store the front road frame data, the next 2073600 bytes store the left standard frame data, and the last 2073600 bytes store the right standard frame data. The frame set header contains 32 bytes of description information, recording the resolution, format, and offset position of each frame.

[0023] Preferably, the rotating angles of the left rotating support and the right rotating support are dynamically rotated and tracked according to the vehicle driving parameters, including: When the vehicle steering angle is greater than 10° and the duration exceeds 0.3 seconds, the rotating support on the steering side is immediately controlled to rotate outward at a speed of 10° per second until it reaches a maximum of 20°, wherein the rotating direction is consistent with the direction of the steering angle, i.e., the right support rotates outward when turning right, and the left support rotates outward when turning left; When the vehicle yaw rate is greater than 30° / s and the duration exceeds 0.2 seconds, immediately control the two sides of the rotating support to increase the rotation angle by 5° outward respectively; if the yaw rate continues to increase, the rotation angle can be cumulatively increased, and the maximum is not more than 15°; When the vehicle lateral acceleration is greater than 2 m / s² and the duration exceeds 0.5 seconds, immediately control the two sides of the rotating support to increase the rotation angle by 3° outward respectively to cope with the temporary expansion of the blind area when the vehicle slides or changes lanes urgently; when the direction of lateral acceleration changes, the rotating support adjusts the rotation direction accordingly; When the above trigger parameters return to the preset normal range and remain stable for more than 1 second, the rotating support slowly returns to the initial angle at a speed of 5° per second.

[0024] In this embodiment, the dynamic tracking control of the camera rotating support is realized based on a multi-level trigger mechanism and a priority algorithm. The system receives the vehicle steering angle, yaw rate and lateral acceleration signals through the CAN bus, with a sampling frequency of 100 Hz. For the vehicle steering angle parameter, the main controller compares the current steering angle value with the 10° threshold value in real time, and maintains a timer to record the duration of the threshold value. When the absolute value of the steering angle is greater than 10° and the duration timer reaches 300 ms, the steering response mechanism is triggered, and the controller immediately sends a rotating instruction to the rotating support STM32F103 control unit on the steering side, specifying an angular velocity of 10° / s in the same direction as the vehicle steering. When turning right, the right support is controlled to rotate outward (in the direction of the right side of the vehicle), and when turning left, the left support is controlled to rotate outward (in the direction of the left side of the vehicle). During the rotation process, the current angle is fed back in real time through the AS5600 magnetic encoder, and the rotation stops when it reaches 20°. For the yaw rate parameter, the system sets a separate trigger timer, and when the absolute value of the yaw rate exceeds 30° / s and lasts for more than 200 ms, it sends an incremental rotating instruction to the rotating supports on both sides, specifying that both sides should increase by 5° of rotation angle outward at the same time. The system records the time when the yaw rate continuously exceeds the threshold value through an integrator, and every time 0.5 seconds is added, the rotation angle of both sides is increased by 5° respectively, but the cumulative increase is set to an upper limit of 15°. For the lateral acceleration parameter, the system maintains an independent 500 ms duration timer, and when the absolute value of the lateral acceleration exceeds 2 m / s² and lasts for more than 500 ms, the lateral control algorithm is triggered, and an instruction to increase the rotation angle of both sides by 3° is sent to the rotating supports. The system records the direction of the lateral acceleration, and when the direction changes (the sign is reversed), it immediately recalculates and sends a new rotating direction instruction to ensure that the rotating direction of the support always matches the direction of the lateral force. The system implements a priority processing mechanism for multiple conditions triggered at the same time, and when multiple trigger conditions are met at the same time, the maximum value strategy is adopted, that is, the maximum value of the rotation angle calculated by each condition is taken as the final execution angle. After the trigger condition is over, the system starts a stability timer, and when all trigger parameters (steering angle, yaw rate, lateral acceleration) fall back to the normal range (steering angle < 5°, yaw rate < 15° / s, lateral acceleration < 1 m / s²) and last stably for more than 1000 ms, the system sends a return instruction to the rotating supports on both sides, specifying a return angular velocity of 5° / s, gradually returning to the 0° initial position. The return process uses an exponential smoothing algorithm, and the angle change follows the formula where is the time constant, set to 0.8 s, ensuring smooth and jitter-free return process. The entire dynamic tracking control process provides closed-loop feedback with ±0.088° accuracy through the left and right AS5600 magnetic encoders, ensuring accurate and rapid control of the rotation angle.

[0025] Preferably, step S3 comprises: A virtual canvas with a size of 3840x3240 pixels is pre-opened in the memory; The front road frame data of 3840x2160 is directly copied to the upper half of the virtual canvas, with the coordinate range being [0, 0] to [3840, 2160]; The left standard frame data of 1920x1080 is directly copied to the lower left part of the virtual canvas, with the coordinate range being [0, 2160] to [1920, 3240]; The right standard frame data of 1920x1080 is directly copied to the lower right part of the virtual canvas, with the coordinate range being [1920, 2160] to [3840, 3240]; The splicing is completed through a direct memory block copy operation to generate a synthesized main stream frame; the synthesized main stream frame is optimized according to the rotation angles of the left and right rotating supports, and the optimization process includes: During the adjustment of the left and right rotating supports, the display area of the corresponding side view in the synthesized main stream frame is expanded to 1.5 times of the original, improving the display priority of the side view; when the display area is expanded, a smooth image scaling algorithm is used to avoid abrupt changes in the picture; When the rotating supports return to the initial angle, the display area of the side view is synchronously restored to the original proportion.

[0026] In this embodiment, the generation of the synthetic main stream frame is realized by memory space optimization and dynamic area adjustment mechanism. The system first allocates a continuous memory space in the DDR4 memory as a virtual canvas through the malloc function, and the memory block size is 18662400 bytes, which corresponds to the storage demand of a 3840x3240 pixel YUV420 format image. The memory address is aligned according to 16 bytes to optimize the DMA transmission efficiency. The memory layout of the virtual canvas adopts a flat format, the first 12441600 bytes store the Y component, the next 3110400 bytes store the U component, and the last 3110400 bytes store the V component. The splicing operation executes three independent memory block transmission tasks through the DMA controller of the ARM processor. The first DMA transmission directly copies the front frame data of the standard field frame set to the virtual canvas, transmits 8294400 bytes of front Y component data to the starting position of the Y plane of the virtual canvas, transmits 2073600 bytes of front U component data to the starting position of the U plane of the virtual canvas, and transmits 2073600 bytes of front V component data to the starting position of the V plane of the virtual canvas, covering the upper area of the virtual canvas coordinates [0, 0] to [3840, 2160]. The second DMA transmission processes the left standard frame data, the Y component data is transmitted by row, each row has 1920 bytes, a total of 1080 rows, and the target address is the starting position of the 2160th row of the Y plane of the virtual canvas. The U and V components are transmitted in the same way but each row has 960 bytes and a total of 540 rows, and are written into the corresponding positions of the U plane and the V plane of the virtual canvas respectively, completing the filling of the lower left area of the virtual canvas coordinates [0, 2160] to [1920, 3240]. The third DMA transmission processes the right standard frame data, the Y component is transmitted by row, and the target address is the 1920th byte of each row of the Y plane of the virtual canvas. By setting the DMA target address step parameter to 3840 bytes and the source address step to 1920 bytes, the right image is accurately placed on the right side of the virtual canvas, and the filling of the lower right area of the coordinates [1920, 2160] to [3840, 3240] is completed. The system performs dynamic display optimization according to the rotation angle value of the left and right rotating supports. When it is detected that the absolute value of the angle of the left rotating support is greater than 5°, the system reconfigures the DMA transmission parameters, adjusts the left picture display area width from 1920 pixels to 2880 pixels, and the right picture is correspondingly reduced to 960 pixels, and the total width of the two remains unchanged at 3840 pixels. The expansion operation is realized by modifying the DMA source address step value. When the left side is expanded, the source data step value is set to 1920x2 / 3=1280 bytes, realizing 1.5 times horizontal stretching; when the right side is reduced, the source data step value is set to 1920x2=3840 bytes, realizing 0.5 times horizontal compression. The expansion process adopts a cubic spline interpolation algorithm, and the interpolation kernel is [-1, 8, 0, -8, 1] / 8, which ensures smooth transition of the picture edge.Similarly, when the absolute value of the right rotation bracket angle is greater than 5°, the system expands the right picture to 2880 pixels and shrinks the left picture to 960 pixels. During the angle change, the system calculates the expansion ratio coefficient k = 0.5 + angle value / 10 in real time, ranging from [0.5, 1.5], to achieve smooth changes in picture width with angle. When the rotation bracket angle returns to the range of ±2° and stabilizes for 300 ms, the system restores the side view picture display ratio to the original 1:1 state, and uses a cosine transition function to calculate the intermediate frame ratio during the recovery process to ensure no visual discontinuity. The entire stitching and optimization process is completed through a GPU accelerated computing unit, with a single frame processing delay controlled within 7 ms, meeting the real-time processing requirements of 25 fps.

[0027] Especially important is that step S3 also includes: Automatically adjusting the stitching ratio according to vehicle driving parameters, increasing the front picture proportion to provide a wider field of view when driving at high speed; Applying adaptive contrast enhancement based on brightness histogram to the stitched picture to obtain the final stitched picture, balancing the brightness of the three pictures under different lighting conditions.

[0028] In this embodiment, the automatic adjustment of the splicing ratio and the picture brightness equalization are realized through real-time parameter acquisition and image processing algorithm. The system acquires the speed signal on the vehicle CAN bus at a frequency of 10 Hz in real time through the vehicle-mounted OBD interface, and obtains the accurate speed value after analysis. The system sets three key speed thresholds: 35 km / h, 70 km / h and 100 km / h, corresponding to four splicing ratio gears. When the speed is lower than 35 km / h, the height ratio of the front road picture to the left and right road pictures is maintained at 2:1, the front road height is 2160 pixels, and the left and right road heights are each 1080 pixels; when the speed reaches 35 km / h but is lower than 70 km / h, the system re-divides the virtual canvas, adjusts the front road picture height to 2376 pixels, and the left and right road heights to each 864 pixels, with a height ratio of 2.75:1; when the speed reaches 70 km / h but is lower than 100 km / h, the front road picture height is adjusted to 2592 pixels, and the left and right road heights to each 648 pixels, with a height ratio of 4:1; when the speed reaches or exceeds 100 km / h, the front road picture height is further expanded to 2700 pixels, and the left and right road heights to each 540 pixels, with a height ratio of 5:1. Each time the splicing ratio is adjusted, the system recalculates the DMA transmission parameters and performs memory reorganization. The vertical expansion of the front road picture uses a bicubic interpolation algorithm, with a kernel function of [1,-9,36,46,-9,1] / 64, to ensure smooth transition in the vertical direction. To address the problem of uneven picture brightness under different lighting conditions, the system performs adaptive contrast enhancement processing based on a histogram. First, the brightness histograms of the front road, left road and right road regions are calculated respectively, and the 256-level grayscale distribution of the Y component in each region is counted. An 8x8 pixel block sampling method is used, with a total of 60x34=2040 sampling blocks in the front road region and 30x17=510 sampling blocks in the left and right road regions. According to the histogram information, the system calculates the average brightness values Ymean_front, Ymean_left and Ymean_right and the standard deviations Ystd_front, Ystd_left and Ystd_right of the three regions. The average brightness of the three regions is normalized to the middle value 128, and the brightness correction coefficients Kfront=128 / Ymean_front, Kleft=128 / Ymean_left and Kright=128 / Ymean_right are calculated. For regions with large brightness variance (Ystd<40 or Ystd>80), the system additionally applies a contrast stretching algorithm with stretching coefficients Sfront=64 / Ystd_front, Sleft=64 / Ystd_left and Sright=64 / Ystd_right, and maps each pixel point through the formula The system also performs gradual fusion of the region boundaries, setting a 32-pixel-wide transition band at the region junction, and calculating the fused pixel value using a linear weight function w(x)=x / 32 (x is the number of pixels from the boundary). The whole brightness equalization processing is performed on the NEON parallel processing unit of the ARM processor, 16 pixel points are processed simultaneously through the 128-bit SIMD instruction set, and the time consumption of single frame processing is controlled within 5 ms. The joint optimization of speed adaptation and brightness equalization ensures the visual consistency of the spliced picture in various driving environments and improves the recognition degree of the key area.

[0029] Preferably, step S4 comprises: checking whether there is data of the rear camera in the space-time synchronization data packet; when the rear camera is detected, starting two parallel encoders, the first encoder compresses the synthesized main stream frame of 3840x3240 according to the H.264 / H.265 standard, and the second encoder independently compresses the rear original frame of 1920x1080; when the rear camera is not detected, only the first encoder is started to compress the synthesized main stream frame; packaging the compressed data block and the meta information required for decoding to generate a data stream unit to be written.

[0030] In this embodiment, the video encoding and data packaging process is implemented through hardware-accelerated encoders and structured data organization. The system first reads the camera connection status flag from the 8th byte of the metadata header of the spatiotemporal synchronization data packet. The 3rd bit of this flag indicates the connection status of the rear camera. A value of 1 indicates that the rear camera is connected and working normally, and a value of 0 indicates that the rear camera is not connected or is malfunctioning. When the rear camera connection status flag is detected as 1, the system activates two independent hardware encoders built into the main SoC chip. The first encoder is configured in H.265 / HEVC encoding mode, with Profile set to Main Profile, Level set to 5.1, target bitrate set to 8Mbps, keyframe interval set to 50 frames, B-frame count set to 2, encoding speed priority set to 4, and input source being the synthesized 3840×3240 main bitstream frame, input format set to YUV420, and color space set to BT.709. The second encoder is simultaneously configured in H.264 / AVC encoding mode, with Profile set to High Profile, Level set to 4.2, target bitrate set to 4Mbps, keyframe interval set to 25 frames, B-frame count set to 0, encoding speed priority set to 5, and input source being the 1920×1080 rear original frame from the spatiotemporal synchronization data packet, input format set to YUV420, and color space set to BT.709. The two encoders employ a hardware-level parallel processing architecture, reading source video data from system memory through independent DMA channels. Encoding processing is completed in a dedicated ASIC module, ensuring no interference and minimizing main CPU resource consumption. When the rear camera connection status flag is detected as 0, the system activates only the first encoder, performing H.265 / HEVC encoding on the synthesized main stream frame. The encoding parameters are the same as described above, but the target bitrate is increased to 10Mbps to ensure image quality. In both cases, the encoder uses Constant Quantization (CQP) encoding mode, with the quantization parameter QP set to 26, the chroma component quantization parameter offset set to -2, and adaptive quantization technology and deblocking filter enabled. After encoding, the system packages the compressed video data stream and metadata into standardized data stream units. These data stream units use a custom binary format, containing a 128-byte header and a variable-length data portion. The header contains the following information: a 4-byte magic number (0x5A4B3C2D), an 8-byte timestamp, a 4-byte main stream data length, a 4-byte downstream stream data length (0 if not connected), a 2-byte video width, a 2-byte video height, a 1-byte encoding format identifier (1 for H.264, 2 for H.265), a 1-byte frame type (I / P / B), a 4-byte sequence number, a 32-byte reserved area, and a 32-byte MD5 checksum. The data is arranged in the order of main stream first, then downstream stream, with each stream segment beginning with a 4-byte length field.The complete data stream unit is transmitted to the write buffer of the storage controller through the DMA channel, and waits for subsequent storage operation. The whole encoding and packaging process is completed on the hardware acceleration unit of the main SoC chip, and the processing delay is controlled within 30 ms.

[0031] Preferably, step S5 comprises: Two continuous data pool files are created on the storage medium, one for the main stream and one for the auxiliary stream, and an index area is established at the head of the data pool file; According to the current write position pointer recorded in the index area, the main stream data block and the auxiliary stream data block are appended to the end of the corresponding data pool file respectively; The pointer position in the index area is updated; When the data pool in the data pool file is full, the pointer automatically rolls back to the starting position of the data pool file, and the oldest data is overwritten from the beginning, forming a cyclic coverage mechanism.

[0032] In this embodiment, the Format-Free storage mechanism is implemented by pre-allocating continuous data pools and efficient index structures. When initializing the SD card, the system performs a file system pre-allocation operation to create two fixed-size continuous data pool files on the SD card. The main stream data pool file is named "MAIN_POOL.BIN" and is set to 29.5 GB in size. The rear stream data pool file is named "REAR_POOL.BIN" and is set to 14.5 GB in size. A total of 44 GB of space is occupied, and the remaining space is reserved for system files and index backups. The data pool file is forced to use the continuous physical sectors of the SD card during creation. After clearing the target area by sending the TRIM command, sequential writing is performed to ensure physical continuity. The first 4 MB region of each data pool file is divided into an index area, and the remaining space is a data area. The index area uses a B+ tree structure and contains the following key fields: file header identifier 0xF5E4D3C2, current write position pointer P_main and P_rear, cyclic flag cyclic_flag, earliest data timestamp T_earliest, latest data timestamp T_latest, total data block count block_count, emergency event marker table, and complete index table. Each entry in the index table occupies 32 bytes and contains an 8-byte timestamp, a 4-byte data block start position, a 4-byte data block length, a 4-byte checksum, a 4-byte frame type marker, and an 8-byte reserved field. The entries are sorted by timestamp. When receiving a data stream unit to be written, the storage controller first reads the current write position pointers P_main and P_rear from the index area. Then, by using the direct sector access command, the main stream data block is written from the system memory directly into the MAIN_POOL.BIN data area at an offset of P_main with a length of L_main bytes. If there is a rear stream data block, it is written into the REAR_POOL.BIN data area at an offset of P_rear with a length of L_rear bytes. The write operation uses direct IO to bypass the operating system cache and uses a 4 KB aligned block size to match the physical sectors of the SD card, maximizing write efficiency. After writing the data, the storage controller immediately updates the information in the index area: P_main is updated to (P_main+L_main), P_rear is updated to (P_rear+L_rear), and a new entry is added to the index table to record the timestamp, position, length, and other information of the current data block. The T_latest field is also updated. The update of the index area uses a transaction mechanism to ensure atomicity. The updated content is first written to the log area, and then the actual index area is modified.When P_main is about to exceed the end of MAIN_POOL.BIN data area (less than 10MB from the end), the storage controller resets P_main to 4MB (end position of index area) and sets cyclic_flag to 1, indicating that the data has started to be overwritten in a loop; the processing of P_rear uses the same mechanism. During the loop overwriting process, the storage controller dynamically maintains T_earliest information by comparing the current write position with the earliest data position in the index table, and automatically deletes the index entries of the overwritten data. To prevent accidental power failure from causing damage to the index area, the system backs up the complete index area to the reserved area of the SD card every 5 minutes, and performs a forced index synchronization operation before shutdown. The entire storage mechanism completely eliminates file fragmentation through the three core technologies of pre-allocation, direct access, and loop overwriting, achieving continuous high-speed write performance, with a write speed of 45MB / s and a fragmentation rate of 0.

[0033] Especially important is that the method further includes a dual-SD card redundancy storage step, wherein the dual-SD card redundancy storage step includes: configuring two parallel SD card slots in the storage medium, each slot supporting hot plug function; establishing and maintaining real-time data mirroring relationship between the two SD cards; during data writing, writing the same data stream to the two SD cards simultaneously through parallel redundancy circuit; real-time monitoring of the writing state and health status of each SD card; when detecting that any SD card has a writing error or is removed, automatically redirecting the data stream to the other SD card, and recording the event in the system log; when the removed SD card is reinserted or replaced with a new card, the system automatically performs data synchronization operation to copy the latest data on the main SD card to the secondary SD card, ensuring data consistency between the two cards; through the redundancy mechanism, achieving storage reliability with no data loss during hot plug.

[0034] In this embodiment, the dual-SD card redundant storage mechanism is implemented through a hardware-level RAID1 architecture and intelligent hot plug detection. Two completely independent SD card slots, SD1 and SD2, are integrated on the system motherboard, each equipped with a separate power supply circuit, clock signal line, and data bus interface, and configured in UHS-II high-speed mode with a theoretical transfer speed of 104 MB / s. The two SD card slots are connected to the main controller through the FD1935DX hot plug controller, which has a plug detection response time of 10 μs and provides independent power supply isolation protection. The system implements independent control of the two-way SD card power supply based on the TPS54424 dual-channel power management chip from Texas Instruments, providing overcurrent protection and voltage monitoring functions. Data mirroring is achieved through the hardware-level RAID1 controller NUC980, which is located between the main CPU and the SD card and presents a single storage device to the CPU, performing data replication operations internally. When the system performs a storage operation, the data stream unit to be written is first transmitted to the 16 MB buffer of the RAID1 controller, and then written to SD1 and SD2 through two independent DMA engines, each with independent transmission parameters but identical data content. The RAID1 controller simultaneously monitors the response time, error rate, and write completion status of the two SD cards, performing an SD card health check every 1 second by sending a CMD13 command to obtain the status register value and temperature information. The system divides the health status into four levels: normal (temperature < 65℃, error rate < 0.001%), warning (temperature 65℃~75℃, error rate 0.001%~0.01%), danger (temperature 75℃~85℃, error rate 0.01%~0.1%), and failure (temperature > 85℃, error rate > 0.1% or write timeout). When SD1 or SD2 enters a failure state or is physically removed (detected through GPIO pin level change), the RAID1 controller immediately marks the card as offline, stops sending data to it, and only maintains write operations on the other normal card, while sending a status change interrupt signal to the main controller through the I2C bus, which records the current timestamp and fault card slot number in the system log. When the faulty card is replaced or reinserted, the hot plug controller detects the insertion event and sends a card slot ready signal to the RAID1 controller. The RAID1 controller performs four initialization operations: first, sends CMD0 to reset the SD card; second, sends CMD8 to check voltage matching; third, sends ACMD41 to activate the SD card; and fourth, reads the CID and CSD registers to obtain card information. After initialization, the system performs three-phase data synchronization: the first phase compares the timestamp information in the index area of the two cards to determine the synchronization starting point; the second phase copies the index area and data area content from the primary card to the secondary card in 32 MB units; and the third phase verifies the CRC32 checksum of the copied data.After synchronization is completed, the two cards re-enter the mirroring state, and the RAID1 controller resumes the double-card parallel writing mode. The entire resynchronization process is performed in the background, which does not affect the writing operation of new data, realizes hot plug zero data loss, and even if any SD card is pulled out again during the synchronization process, the data integrity can still be ensured.

[0035] Preferably, updating the persistent storage index comprises: recording the starting position and the ending position of the main code stream and the post road code stream in the respective data pool; updating the timestamp information of each video segment; adjusting the current writing pointer position; setting a loop coverage state flag to indicate the progress and state of data coverage.

[0036] In this embodiment, the index update process achieves data consistency management with the B+ tree structure through a two-phase commit protocol. After completing the data write operation, the system immediately executes the index update process, first constructing an index update transaction record in memory, which contains a 32-byte header and a variable-length data section. The header contains a 4-byte transaction identifier 0x7B6A5C4D, an 8-byte timestamp, a 4-byte transaction sequence number, a 4-byte transaction type code (1 for normal writing, 2 for cycle point switching, and 3 for emergency event marking), a 4-byte checksum, and an 8-byte reserved field. The data section accurately records the position information of this write: the start position P_main_start (offset relative to the data pool file header, in bytes) of the main stream data block, the end position P_main_end, the start position P_rear_start of the rear stream, the end position P_rear_end, the length of the main stream data block L_main, the length of the rear stream L_rear, the video segment start timestamp T_start, and the end timestamp T_end (using Unix timestamp format, accurate to milliseconds). The controller first writes the transaction record to the transaction log area at offset 0x2000 in the SD card index area, and after writing is complete, it ensures that the data is physically written to disk through the fsync function, and then updates the active index table in the index area. The index table uses a B+ tree structure, and the leaf nodes store video segment records, each record occupying 64 bytes, sorted by timestamp, containing the aforementioned position and length information, as well as additional 4-byte frame type markers (distinguishing I / P / B frames), 4-byte quality scores (range 0-100), and 16-byte metadata pointers. During the update process, the controller calculates the position where the new record should be inserted, adjusts the B+ tree structure to maintain balance through left or right rotation operations, and updates the meta information in the index header, including the total number of records (increased by 1), the latest data timestamp (set to T_end), and the current write pointer (P_main updated to P_main_end, P_rear updated to P_rear_end). For the cycle coverage mechanism, the controller additionally maintains a 32-byte cycle state record, which contains a 4-byte cycle flag (0 for not cycling, 1 for having started cycling), an 8-byte cycle start time, a 4-byte cycle counter (records the number of completed cycles), an 8-byte earliest valid data timestamp, and an 8-byte earliest valid data position. When it is detected that P_main_end is less than 10MB from the end of the data area, the controller creates a special transaction record with type code 2, resets P_main to 4MB (the end position of the index area), increments the cycle counter value, and updates the cycle flag to 1; at the same time, it scans the index table, deletes all old records that will be overwritten by the new round of writing, maintains the integrity of the index structure by rebuilding the lower nodes of the B+ tree, and updates the earliest valid data timestamp field.The whole index updating process adopts the principle of atomic operation, and any step failure triggers the rollback mechanism to recover to the state before updating through log recording, ensuring the integrity and consistency of the index data, and even in the case of power failure, it can be recovered through the transaction log.

[0037] Preferably, before step S1 is performed, it further comprises: detecting the intensity of ambient light; When the intensity of ambient light is lower than the preset light threshold, the dual-band infrared light source integrated with the left and right cameras is activated, and the dual-band infrared light source includes two wavelengths of 850nm and 940nm; adjusting the exposure parameters and gain value of the camera; collecting video frames in night mode as original video frames.

[0038] In this embodiment, the night mode activation process is achieved through light sensing and multi-wavelength infrared light supplement technology. The system integrates a BH1750FVI ambient light sensor on the left camera module, with a measurement range of 1-65535 lux and an accuracy of ±20%. The sensor reports the current ambient light intensity value to the main controller once per second through the I2C bus. The main controller compares the received light intensity value with the preset night mode trigger threshold of 50 lux. When the sampling value is continuously below the threshold for 5 times, the system activates the night mode workflow. The night mode first starts the dual-band infrared light source array distributed in a ring around the left and right cameras by outputting a high-level signal through GPIO. The array is composed of 12 850nm wavelength infrared LEDs and 12 940nm wavelength infrared LEDs arranged alternately. The infrared light emitted by the 850nm wavelength LED is invisible to the human eye but has good night vision effect, with a maximum radiant power of 120mW / sr and an irradiation distance of 22 meters. The 940nm wavelength LED is completely invisible but has strong fog penetration ability, with a maximum radiant power of 90mW / sr and an irradiation distance of 15 meters. The system controls the power ratio of the two types of LEDs through PWM modulation according to the current ambient temperature. When the temperature is below 5°C, the 850nm:940nm power ratio is 7:3. When the temperature is between 5°C and 25°C, the ratio is 6:4. When the temperature is above 25°C, the ratio is 5:5, ensuring the best night vision effect under different weather conditions. At the same time of starting the infrared light supplement, the system reconfigures the exposure parameters of the camera, extending the exposure time of the CMOS sensor from 1 / 60s in daytime mode to 1 / 15s, increasing the analog gain value from the baseline value of 1 to 16, and increasing the digital gain from 1 to 4. The system also switches the image signal processing (ISP) chip to night processing mode, enabling the 3DNR time domain noise reduction algorithm with a noise reduction intensity of 8 (range 0-10), and applying a contrast stretching algorithm to compress the dynamic range of the original image from 10bit to 8bit, and the black level to 16 (range 0-255). The system disables the automatic white balance function, fixes the color temperature at 3200K, and electrically switches the infrared filter to a transparent mode that allows infrared spectrum to pass through. After completing the above configuration, the system collects four-way camera output night mode video frames through the MIPI CSI-2 interface, and these video frames are used as the original video frames in the night environment, entering the subsequent synchronous spatiotemporal data packet generation process.

[0039] Preferably, the heat management and data protection step further comprises, after step S5: monitoring the temperature of the storage medium in real time; when the temperature exceeds the heat dissipation activation threshold, starting a stepped air duct heat dissipation system with an opening rate of 62%; when the temperature exceeds the storage switching threshold, automatically allocating the data stream unit to be written to a preset standby storage medium.

[0040] In this embodiment, the thermal management and data protection mechanism is realized through multi-level temperature monitoring and emergency storage transfer. The system integrates a DS18B20 digital temperature sensor near each SD card slot, with a measurement accuracy of ±0.5℃ and a range of -55℃ to +125℃. The temperature sampling value is reported to the main controller every 5 seconds through the 1-Wire bus. The temperature sampling value is filtered through a five-point sliding average algorithm to obtain a stable real-time temperature value T_current. The system presets two key temperature thresholds: the fan activation threshold T_fan = 52℃ and the storage switching threshold T_switch = 68℃. When T_current first exceeds T_fan, the main controller sends a start command to the fan control chip EMC2301 through the I2C bus to activate the built-in step-type air duct cooling system. This cooling system consists of three layers: the outermost layer is a honeycomb metal mesh with an opening rate of 62%, an opening diameter of 1.2mm, a thickness of 0.8mm, and a material of anodized aluminum; the middle layer is a three-section step-type air duct, with the air duct height gradually decreasing from 6mm at the entrance to 3mm at the exit, forming a Venturi effect to accelerate airflow; the inner layer is a copper heat conduction plate that directly contacts the SD card, with a thickness of 1.5mm and a surface coated with 0.2mm thick phase change heat conduction material. The fan uses Delta's ultra-thin model KDB04105HB, with a thickness of 4.5mm, a maximum air volume of 6.5CFM, and a maximum static pressure of 2.8mmH2O. The fan speed is dynamically adjusted according to the temperature, using a PID control algorithm: RPM = 2000 + K_p × (T_current - T_fan) + K_i × ∫(T_current - T_fan)dt + K_d × d(T_current - T_fan) / dt, where the proportional coefficient K_p = 100, the integral coefficient K_i = 20, and the differential coefficient K_d = 5. When T_current drops to T_fan - 3℃, i.e., below 49℃ for 15 seconds, the system reduces the fan speed to 30% standby state. When T_current exceeds T_switch, the system immediately triggers the storage protection mechanism, creating a storage switching transaction that includes the following operation sequence: first, pause the current SD card write operation and save the data in the buffer to the emergency cache area of the LPDDR4 memory; then send an activation command to the built-in 8GB eMMC storage chip to wake it up from low power consumption state; then redirect the write pointer to the eMMC storage, and all subsequent data flow units to be written are allocated to the eMMC; at the same time, the system increases the fan speed to 100% and displays the temperature warning symbol on the LED indicator screen. The eMMC storage uses a ring buffer structure with a size of 6GB, enough to store about 20 minutes of video data.When T_current falls to T_switch-10℃, i.e. below 58℃ for 30 seconds, the system performs a data rollback operation: suspends writing, transfers all data in the eMMC back to the SD card in chronological order, resumes writing on the SD card after completion, and re-sets the eMMC to the standby state.

[0041] Therefore, from any point of view, the embodiments should be considered as exemplary and non-limiting, the scope of the application being defined by the appended claims and not by the above description, therefore all variations falling within the meaning and the scope of the equivalent elements of the application file are intended to be included in the application.

[0042] The foregoing is considered as merely illustrative of the principles of the application, and the application is to be regarded as not limited to such embodiments, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A video stitching and storage control method based on a vehicle dashcam system, characterized in that, The method is applied to a vehicle recording camera system, which includes four cameras and left and right rotating brackets respectively mounted on the left and right sides of the vehicle. The four cameras include a front camera, a left camera, a right camera, and a rear camera. The left and right cameras are respectively mounted on the left and right rotating brackets. The method includes the following steps: Step S1: Obtain the original video frames from the camera, add a synchronization timestamp to the original video frames, record the angle values ​​of the left and right rotating brackets, and generate a spatiotemporal synchronization data packet; Step S2: Perform geometric correction of the original video frames of the left and right channels based on the rotation angle values ​​in the spatiotemporal synchronization data packet to generate a standard field of view frame set; Step S3: In the pre-allocated memory virtual canvas, combine the front frame, left standard frame and right standard frame in the standard field of view frame set according to the preset positions to generate the synthesized main bitstream frame. Step S4: Encode and compress the synthesized main stream frame, and decide whether to independently encode the original rear frame based on the presence status of the rear camera to generate a data stream unit to be written. Step S5: Create and maintain continuous data pool files and index areas on the preset storage medium, write the data stream units to be written to the corresponding data pool files according to the index areas, and update the persistent storage index.

2. The video stitching and storage control method based on a vehicle recording camera system according to claim 1, characterized in that, Step S1 includes: Send a synchronization clock signal to the control units of the four cameras and the left and right rotating brackets; Receive video frames captured simultaneously from four cameras and add a unified synchronization timestamp; Read the angle camera data built into the left and right rotating brackets to obtain the rotation angle value; Synchronize video frames, synchronization timestamps, and rotation angle values ​​to form a spatiotemporal synchronization data packet.

3. The video stitching and storage control method based on a vehicle recording camera system according to claim 1, characterized in that, Step S2 includes: Extract the original frames and corresponding rotation angle values ​​of the left and right paths from the spatiotemporal synchronization data packets; Obtain vehicle driving parameters, including vehicle steering angle, vehicle yaw angle, and vehicle lateral acceleration; perform dynamic rotation tracking control on the rotation angles of the left and right rotating supports based on the vehicle driving parameters to obtain the rotation angle values; Based on the preset lens intrinsic parameter model and rotation angle value, a preset lookup table is called, where the lens intrinsic parameter model is either a fisheye model or a wide-angle model, and the rotation angle value ranges from ±15° with an accuracy of ±0.5°. Perform reverse geometric transformation on the original frames of the left and right channels to eliminate image distortion and stretching caused by rotation; Generate a rectangular image with a standardized viewpoint to form a standard field of view frame set.

4. The video stitching and storage control method based on a vehicle recording camera system according to claim 3, characterized in that, Dynamic rotation tracking control is performed on the rotation angles of the left and right rotating supports based on vehicle driving parameters, including: When the vehicle's steering angle is greater than 10° and lasts for more than 0.3 seconds, immediately control the rotating bracket on the steering side to rotate outward at a speed of 10° per second until it reaches a maximum of 20°. The direction of rotation is the same as the direction of the steering angle, that is, when turning right, the right bracket rotates outward, and when turning left, the left bracket rotates outward. When the vehicle's yaw rate is greater than 30° / s and lasts for more than 0.2 seconds, immediately control both rotating supports to increase their rotation angle outward by 5° simultaneously; if the yaw rate continues to increase, the rotation angle can be increased cumulatively, up to a maximum of 15°. When the vehicle's lateral acceleration exceeds 2 m / s² and lasts for more than 0.5 seconds, immediately control the rotating brackets on both sides to increase their rotation angle outward by 3° each to cope with the temporary expansion of the blind spot when the vehicle sideslips or makes an emergency lane change; when the direction of lateral acceleration changes, the rotating brackets adjust their rotation direction accordingly. When the aforementioned trigger parameters return to the preset normal range and remain stable for more than 1 second, the rotating bracket slowly returns to the initial angle at a speed of 5° per second.

5. The video stitching and storage control method based on a vehicle recording camera system according to claim 1, characterized in that, The standard field-of-view frame set includes front-path frame data, left-path standard frame data, and right-path standard frame data. Step S3 includes: A virtual canvas with a size of 3840×3240 pixels is pre-allocated in memory; Copy the 3840×2160 front-path frame data directly to the upper half of the virtual canvas, with coordinates ranging from [0,0] to [3840,2160]. Copy the 1920×1080 left-side standard frame data directly to the lower left part of the virtual canvas, with coordinates ranging from [0,2160] to [1920,3240]. Copy the 1920×1080 right-side standard frame data directly to the lower right part of the virtual canvas, with coordinates ranging from [1920,2160] to [3840,3240]. The splicing is completed through direct memory block copying operations to generate the synthesized main bitstream frame; the synthesized main bitstream frame is optimized according to the rotation angles of the left and right rotating supports, and the optimization process includes: During the adjustment of the left and right rotating brackets, the display area of ​​the corresponding side view in the synthesized main stream frame is expanded to 1.5 times the original size to improve the display priority of the side view; when expanding the display area, a smooth image scaling algorithm is used to avoid abrupt changes in the image. When the rotating bracket returns to its initial angle, the side view display area synchronously restores to its original proportions.

6. The video stitching and storage control method based on a vehicle recording camera system according to claim 1, characterized in that, Step S4 includes: Check if the spatiotemporal synchronization data packet contains data from the rear camera; When the presence of a rear camera is detected, two parallel encoders are started. The first encoder compresses the synthesized main stream frame of 3840×3240 according to the H.264 / H.265 standard, and the second encoder independently compresses the original rear frame of 1920×1080. When no rear camera is detected, only the first encoder is activated to compress the synthesized main stream frame; The compressed data block is packaged with the metadata required for decoding to generate a data stream unit to be written.

7. The video stitching and storage control method based on a vehicle recording camera system according to claim 1, characterized in that, Step S5 includes: Create two consecutive data pool files on the storage medium, one for the main bitstream and one for the downstream bitstream, and build an index area at the beginning of the data pool files; Based on the current write position pointer recorded in the index area, the main stream data block and the subsequent stream data block are appended to the end of the corresponding data pool file respectively; Update the pointer position in the index area; When the data pool file is full, the pointer automatically rolls back to the beginning of the data pool file and starts overwriting the oldest data from the beginning, forming a circular overwrite mechanism.

8. The video stitching and storage control method based on a vehicle recording camera system according to claim 7, characterized in that, Updating persistent storage indexes includes: Record the start and end positions of the main stream and subsequent streams in their respective data pools; Update the timestamp information for each video segment; Adjust the current write pointer position; Set a loop overwrite status flag to indicate the progress and status of data overwrite.

9. The video stitching and storage control method based on a vehicle recording camera system according to claim 1, characterized in that, Before step S1 is executed, the following also applies: Detect ambient light intensity; When the ambient light intensity is lower than the preset light threshold, the dual-band infrared light source integrated in the left and right cameras is activated. The dual-band infrared light source includes two wavelengths: 850nm and 940nm. Adjust the camera's exposure parameters and gain value; Video frames captured in night mode are used as raw video frames.

10. The video stitching and storage control method based on a vehicle recording camera system according to claim 1, characterized in that, Following step S5, a thermal management and data protection step is included, which comprises: Real-time monitoring of the temperature of the storage medium; When the temperature exceeds the heat dissipation activation threshold, the stepped air duct heat dissipation system is activated. The heat dissipation system has an opening rate of 62%. When the temperature exceeds the storage switching threshold, the data stream unit to be written is automatically allocated to the preset backup storage medium.

Images