Semiconductor device, preparation method thereof and power device
By improving the fabrication method of the shielding gate structure, a three-layer dielectric structure and a polycrystalline silicon shielding gate are used as the blocking layer, which solves the problem of insufficient blocking ability of the blocking layer, improves the yield of semiconductor devices, and simplifies the fabrication process.
Patent Information
- Application Number
- CN202511616908.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-05
- Publication Date
- 2026-02-06
Smart Images
Figure CN121487286A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and a power device. Background Technology
[0002] Shielded Gate Trench FETs (SGT FETs) offer optimized high-voltage, high-speed, and low-loss performance for power MOSFETs and are widely used in high-efficiency, high-frequency power conversion applications.
[0003] In the fabrication of shielded field-effect transistors, plasma implantation is typically used to form doped regions in the substrate. However, the barrier layer used in this process often lacks sufficient blocking power, allowing dopant elements to penetrate the barrier layer and remain doped in areas previously shielded, thus reducing the yield of the semiconductor device. Summary of the Invention
[0004] In view of the above problems, this application provides a semiconductor device and its fabrication method, as well as a power device, which can improve the blocking ability of the blocking structure and thus improve the yield of the semiconductor device.
[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions:
[0006] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor device, comprising:
[0007] A substrate is provided, the substrate comprising adjacent cell regions and terminal regions;
[0008] A dielectric material layer is formed on the substrate, and the substrate and the dielectric material layer are patterned to form a gate trench in the substrate, and the remaining dielectric material layer constitutes a first dielectric layer.
[0009] A shielding gate structure is formed within the gate trench. Along the extension direction of the gate trench, the shielding gate structure includes a first shielding gate structure and a second shielding gate structure interconnected. The first shielding gate structure is located within the cell region, and the top surface of the first shielding gate structure is lower than the top surface of the substrate and forms a filling region with the substrate. The second shielding gate structure is located in the terminal region, and the shielding gate of the second shielding gate structure extends outside the gate trench and covers the terminal region. The shielding gate covering the terminal region forms an initial barrier layer, and the stacked first dielectric layer and the initial barrier layer constitute an initial barrier structure.
[0010] An insulating layer and a gate structure are formed in the filled region;
[0011] The initial blocking structure is partially removed, and the remaining initial blocking structure constitutes the blocking structure.
[0012] Using the gate and the barrier structure as masks, the exposed substrate is doped to form a first doped region and a second doped region.
[0013] In one possible implementation, the step of forming a shielding gate structure within the gate trench includes:
[0014] A first gate dielectric layer is formed on at least the inner wall of the gate trench;
[0015] A shielding gate material layer is formed within the area enclosed by the first gate dielectric layer. The shielding gate material layer extends beyond the gate trench and covers the top surface of the first dielectric layer.
[0016] A second mask layer is formed, which covers the substrate located in the terminal region;
[0017] Using the second mask layer as a mask, at least a portion of the shielding gate material layer located within the cell region is removed, the shielding gate material layer located within the gate trench is retained to form a shielding gate, and the shielding gate material layer located on the terminal region is retained to form an initial blocking layer.
[0018] In one possible implementation, the first gate dielectric layer includes a first sub-gate dielectric layer and a second sub-gate dielectric layer stacked together, the first sub-gate dielectric layer covering the inner wall of the gate trench;
[0019] The step of removing part of the shielding grid material layer further includes:
[0020] A portion of the second sub-gate dielectric layer is removed so that the top surface of the remaining second sub-gate dielectric layer is lower than the shielding gate.
[0021] In one possible implementation, the step of forming a stacked insulating layer and a gate within the filled region includes:
[0022] A deposition process is performed to form an insulating material layer within the filled area, the insulating material layer extending beyond the filled area and capping the top surface of the first dielectric layer and the initial barrier structure;
[0023] A third mask layer is formed to cover the initial blocking structure located in the terminal area;
[0024] Using the third mask layer as a mask, a portion of the insulating material layer and the first dielectric layer and the first sub-gate dielectric layer located in the cell region are removed to retain a portion of the insulating material layer located on top of the shielding gate to form the insulating layer;
[0025] A thermal oxidation process is performed to form a second gate dielectric layer on the exposed surface of the substrate and the top surface of the initial barrier structure, the second gate dielectric layer being connected to the retained first gate dielectric layer;
[0026] A gate is formed within the region enclosed by the second gate dielectric layer.
[0027] In one possible implementation, the step of removing part of the initial blocking structure includes:
[0028] A fourth mask layer is formed, which covers the cell region and part of the initial blocking structure;
[0029] Using the fourth mask layer as a mask, a portion of the initial blocking structure is removed to form the blocking structure.
[0030] In one possible implementation, the step of doping the exposed substrate using the gate and the barrier structure as masks to form a first doped region and a second doped region further includes:
[0031] A plasma implantation process is performed to dope the exposed substrate to form a first initial doped region and a second initial doped region;
[0032] A push-in activation process is performed to expand the first initial doped region and the second initial doped region to form a first doped region and a second doped region, wherein the first doped region is located in the cell region and the second doped region is located in the terminal region.
[0033] In one possible implementation, after performing the push-well activation process, the fabrication method further includes:
[0034] A fifth mask layer is formed, which covers the second doped region;
[0035] A plasma implantation process is performed to form a third doped region in the first doped region, wherein the conductivity type of the first doped region and the conductivity type of the third doped region are different.
[0036] In one possible implementation, after the step of forming the third doped region, the fabrication method further includes:
[0037] A first conductive plug, a second conductive plug, a third conductive plug, a fourth conductive plug, and a fifth conductive plug are formed; wherein, the first conductive plug is electrically connected to the gate located in the cell region; the second conductive plug is electrically connected to the first doped region; the third conductive plug is electrically connected to the shielding gate located in the terminal region; the fourth conductive plug is electrically connected to the substrate located in the terminal region; and the fifth conductive plug is electrically connected to the second doped region.
[0038] Secondly, embodiments of this application provide a semiconductor device, which is fabricated by the semiconductor device fabrication method described in the first aspect, and the semiconductor device includes:
[0039] A substrate having cellular regions and terminal regions;
[0040] A shielding grid structure, comprising a first shielding grid structure and a second shielding grid structure connected to each other, wherein the first shielding grid structure is located within the cell region and the top surface of the first shielding grid structure is lower than the top surface of the substrate, and the second shielding grid structure is located in the terminal region and the top surface of the second shielding grid structure is flush with the top surface of the substrate.
[0041] An insulating layer is disposed on the first shielding grid structure;
[0042] A gate structure, wherein the gate structure is disposed on the insulating layer;
[0043] A blocking structure is disposed on the terminal area, and the blocking structure includes a first dielectric layer and a blocking layer stacked together, wherein the blocking layer is fabricated simultaneously with the shielding grid of the shielding grid structure;
[0044] A first doped region and a second doped region, wherein the first doped region is located within the cell region and is used to form a transistor with the gate structure, and the second doped region is located in the terminal region and is used to form a diode with the adjacent substrate.
[0045] Thirdly, embodiments of this application provide a power device, including the semiconductor device described in the second aspect.
[0046] In the semiconductor devices and their fabrication methods and power devices provided in this application, the step of forming the shielding gate structure is improved. During the etching process of the shielding gate, the shielding gate covering the terminal region is retained as a barrier layer, so that the barrier structure includes a first dielectric layer and a barrier layer, and the first dielectric layer is a three-layer structure. This greatly enhances the barrier capability of the barrier structure. Simultaneously, the shielding gate is typically made of polysilicon, which is a heavily doped material, further enhancing the barrier capability. When the gate and barrier structure are used as masks to form the first doped region and the second doped region, doping of the substrate shielded by the barrier structure can be avoided, improving the yield of the semiconductor device.
[0047] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that the semiconductor devices and their preparation methods and power devices provided by the embodiments of this application can solve, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific embodiments. Attached Figure Description
[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0049] Figure 1 A process flow diagram of the method for fabricating a semiconductor device provided in the embodiments of this application;
[0050] Figure 2 A schematic diagram illustrating the formation of a dielectric material layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0051] Figure 3 A schematic diagram of the patterned dielectric material layer in the method for fabricating a semiconductor device provided in the embodiments of this application;
[0052] Figure 4 This is a schematic diagram of the patterned substrate in the method for fabricating a semiconductor device provided in the embodiments of this application;
[0053] Figure 5 A schematic diagram of the formation of the first gate dielectric layer in the method for fabricating the semiconductor device provided in the embodiments of this application;
[0054] Figure 6 A schematic diagram illustrating the formation of a shielding gate material layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0055] Figure 7 A schematic diagram illustrating the removal of a portion of the shielding gate material layer in the fabrication method of the semiconductor device provided in this application embodiment;
[0056] Figure 8 A schematic diagram illustrating the formation of a second mask layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0057] Figure 9 This is a schematic diagram of forming a shielding gate in a method for fabricating a semiconductor device provided in an embodiment of this application;
[0058] Figure 10 A schematic diagram illustrating the removal of a portion of the second sub-gate dielectric layer in the fabrication method of the semiconductor device provided in this application embodiment;
[0059] Figure 11 A schematic diagram illustrating the formation of an insulating material layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0060] Figure 12 A schematic diagram of the removal of a portion of the insulating material layer in the fabrication method of the semiconductor device provided in this application embodiment. Figure 1 ;
[0061] Figure 13 A schematic diagram of the removal of a portion of the insulating material layer in the fabrication method of the semiconductor device provided in this application embodiment. Figure 2 ;
[0062] Figure 14 A schematic diagram of the removal of a portion of the insulating material layer in the fabrication method of the semiconductor device provided in this application embodiment. Figure 3 ;
[0063] Figure 15 A schematic diagram of the removal of a portion of the insulating material layer in the fabrication method of the semiconductor device provided in this application embodiment. Figure 4 ;
[0064] Figure 16 This is a schematic diagram illustrating the formation of an insulating layer in a method for fabricating a semiconductor device according to an embodiment of this application.
[0065] Figure 17 A schematic diagram of the formation of the second gate dielectric layer in the method for fabricating the semiconductor device provided in the embodiments of this application;
[0066] Figure 18 This is a schematic diagram illustrating the formation of a gate material layer in a method for fabricating a semiconductor device according to an embodiment of this application.
[0067] Figure 19 This is a schematic diagram of the formation of a gate in a method for fabricating a semiconductor device provided in an embodiment of this application;
[0068] Figure 20 A schematic diagram illustrating the formation of a fourth mask layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0069] Figure 21 This is a schematic diagram illustrating the formation of a barrier structure in a method for fabricating a semiconductor device according to an embodiment of this application.
[0070] Figure 22 This is a schematic diagram illustrating the formation of an initial doped region in the fabrication method of the semiconductor device provided in this application embodiment;
[0071] Figure 23 This is a schematic diagram illustrating the formation of a doped region in a method for fabricating a semiconductor device according to an embodiment of this application.
[0072] Figure 24 This is a schematic diagram illustrating the formation of a third doped region in a method for fabricating a semiconductor device according to an embodiment of this application.
[0073] Figure 25 A schematic diagram illustrating the formation of a third dielectric layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0074] Figure 26 A schematic diagram illustrating the formation of a sixth mask layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0075] Figure 27 A schematic diagram of the patterned third dielectric layer in the method for fabricating a semiconductor device provided in the embodiments of this application;
[0076] Figure 28 A schematic diagram illustrating the continued formation of etched holes in the fabrication method of the semiconductor device provided in this application embodiment;
[0077] Figure 29 This is a schematic diagram illustrating the formation of a heavily doped region in a method for fabricating a semiconductor device according to an embodiment of this application.
[0078] Figure 30 A schematic diagram of the formation of contact plugs in the method for fabricating a semiconductor device provided in this application embodiment. Figure 1 ;
[0079] Figure 31 A schematic diagram of the formation of contact plugs in the method for fabricating a semiconductor device provided in this application embodiment. Figure 2 ;
[0080] Figure 32 This is a schematic diagram of the formation of an interconnect layer in a method for fabricating a semiconductor device provided in an embodiment of this application.
[0081] Explanation of reference numerals in the attached figures:
[0082] 10: Substrate; 11: Cell region; 12: Termination region; 13: Gate trench; 14: Fill region; 15: First doped region; 151: First initial doped region; 16: Second doped region; 161: Second initial doped region;
[0083] 20: First dielectric layer; 21: First sub-dielectric layer; 22: Second sub-dielectric layer; 23: Third sub-dielectric layer; 24: Dielectric material layer; 241: First dielectric material layer; 242: Second dielectric material layer; 243: Third dielectric material layer;
[0084] 31: First mask layer; 32: Second mask layer; 33: Third mask layer; 34: Fourth mask layer; 35: Fifth mask layer; 36: Sixth mask layer; 361: Opening;
[0085] 40: First gate dielectric layer; 41: First sub-gate dielectric layer; 42: Second sub-gate dielectric layer;
[0086] 50: Shielding gate; 51: Shielding gate material layer;
[0087] 60: Barrier structure; 61: Initial barrier structure; 62: Initial barrier layer; 63: Barrier layer;
[0088] 70: Insulating layer; 71: Insulating material layer;
[0089] 80: Second gate dielectric layer;
[0090] 90: Gate; 91: Gate material layer;
[0091] 100: Second dielectric layer;
[0092] 111: First etched hole; 112: Second etched hole; 113: Third etched hole; 114: Fourth etched hole; 115: Fifth etched hole;
[0093] 120: Heavily doped region;
[0094] 131: First conductive plug; 132: Second conductive plug; 133: Third conductive plug; 134: Fourth conductive plug; 135: Fifth conductive plug;
[0095] 140: Interconnect block. Detailed Implementation
[0096] In related technologies, the barrier layer used in the manufacturing process of semiconductor devices is usually a single silicon nitride layer or a silicon nitride layer and a silicon oxide layer. This makes the barrier layer's barrier ability insufficient, which in turn allows dopant elements to penetrate the barrier layer and have dopant elements in the areas blocked by the barrier layer, thus reducing the yield of semiconductor devices.
[0097] To address the aforementioned technical problems, this application provides a semiconductor device and its fabrication method, as well as a power device. By improving the step of forming the shielding gate structure, the shielding gate covering the terminal region is retained as a barrier layer during the etching process of the shielding gate. This results in the barrier structure comprising a first dielectric layer and a barrier layer, with the first dielectric layer being a three-layer structure, significantly enhancing the barrier's blocking capability. Simultaneously, the shielding gate is typically made of polycrystalline silicon, a heavily doped material, which further enhances the barrier's blocking capability. When the gate and barrier structure are used as masks to form the first and second doped regions, doping of the substrate shielded by the barrier structure can be avoided, improving the yield of the semiconductor device.
[0098] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0099] Please refer to Figure 1 This application provides a method for fabricating a semiconductor device, comprising the following steps:
[0100] Step S100: Provide a substrate, which includes adjacent cell regions and terminal regions.
[0101] The substrate 10 serves as a support component for the semiconductor device, supporting other components disposed thereon. The substrate 10 can be made of a semiconductor material, which can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbide compounds. It should be noted that the substrate 10 can be a single-layer structure or a multilayer structure. For example, the substrate 10 includes a substrate and an epitaxial layer disposed on the substrate.
[0102] The substrate 10 includes adjacent cell regions 11 and terminal regions 12. Cell regions 11 are the main functional regions in a semiconductor device, typically containing multiple repeating unit structures or cells. Terminal regions 12 are areas located around cell regions 11, typically used to support and protect the normal operation of cell regions 11.
[0103] Step S200: A dielectric material layer is formed on the substrate, and the substrate and the dielectric material layer are patterned to form a gate trench in the substrate, and the remaining dielectric material layer constitutes the first dielectric layer.
[0104] Please refer to Figure 2A dielectric material layer 24 is formed on the substrate 10. It should be noted that the dielectric material layer 24 can be a single film layer or a stacked structure, so that the first dielectric layer 20 formed subsequently is also a stacked structure.
[0105] For example, please refer to the appendix. Figure 2 The dielectric material layer 24 has a stacked structure, and each film layer of the dielectric material layer 24 can be prepared by deposition process or other methods. For example, the material of the first dielectric material layer 241 includes silicon oxide. The first dielectric material layer 241 can be formed on the substrate 10 by thermal oxidation, which ensures that the first dielectric material layer 241 has high purity and quality, and makes the top surface of the first dielectric material layer 241 as flat as possible, improving the interface flatness of the first dielectric material layer 241.
[0106] Subsequently, a second dielectric material layer 242 and a third dielectric material layer 243 are formed on the first dielectric material layer 241 using a deposition process. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In this embodiment, the second dielectric material layer 242 is made of silicon nitride, and the third dielectric material layer 243 is made of silicon oxide.
[0107] In this embodiment, the thickness of the first dielectric material layer 241 is 300 Å to 500 Å; the thickness of the second dielectric material layer 242 is 1000 Å to 1500 Å; and the thickness of the third dielectric material layer 243 is 2000 Å to 2500 Å.
[0108] Please refer to Figure 3 A first mask layer 31 with a mask pattern is formed on the dielectric material layer 24. Then, using the first mask layer 31 as a mask, the dielectric material layer 24 and the substrate 10 are etched to form a gate trench 13 within the substrate 10. The remaining dielectric material layer 24 constitutes the first dielectric layer 20, which includes a first sub-dielectric layer 21, a second sub-dielectric layer 22, and a third sub-dielectric layer 23 stacked together. In this embodiment, the depth of the gate trench 13 is 3.3 μm, and the critical dimension CD of the gate trench 13 is 1.0 μm.
[0109] It should be noted that the extension direction of the gate trench 13 can be tilted relative to the horizontal direction, and Figure 3The cross-sectional lines can be parallel to the horizontal direction to allow multiple gate trenches to be displayed on the cross-sectional view. Part of the gate trench 13 is located within the cell region, and part is located within the termination region. Figure 3 For example, from left to right, sections of the first and second gate trenches in cell region 11 and sections of the third gate trench in terminal region 12 are cut out.
[0110] Please continue to refer to the following: Figure 4 A cleaning process is performed to remove the first mask layer 31.
[0111] Step S300: A shielding gate structure is formed within the gate trench. Along the extension direction of the gate trench, the shielding gate structure includes a first shielding gate structure and a second shielding gate structure interconnected. The first shielding gate structure is located within the cell region, and its top surface is lower than the top surface of the substrate, forming a filling region with the substrate. The second shielding gate structure is located in the termination region, and its shielding gate extends outside the gate trench and covers the termination region. The shielding gate covering the termination region forms an initial barrier layer, and the stacked first dielectric layer and the initial barrier layer constitute the initial barrier structure. Its structure can be referenced... Figures 5 to 10 .
[0112] Step S400: An insulating layer and a gate structure are stacked within the filled region. The structure can be referenced from [reference needed]. Figures 11 to 20 .
[0113] Step S500: Remove part of the initial blocking structure; the remaining initial blocking structure constitutes the blocking structure. Its structure can be referenced... Figure 21 .
[0114] Step S600: Using the gate and barrier structures as masks, the exposed substrate is doped to form a first doped region and a second doped region.
[0115] The barrier structure in this embodiment includes a first dielectric layer and a barrier layer, and the first dielectric layer is a three-layer structure, which greatly improves the barrier capability of the barrier structure. At the same time, the shielding gate is usually polysilicon, which is a heavily doped material, and can further enhance the barrier capability of the barrier structure. When the gate and barrier structure are used as masks to form the first doped region and the second doped region, doping of the substrate shielded by the barrier structure can be avoided, thus improving the yield of semiconductor devices.
[0116] In one possible implementation, the step of forming the shielding gate structure in the gate trench further includes:
[0117] Please refer to Figure 5A first gate dielectric layer 40 is formed at least on the inner wall of the gate trench 13. It should be noted that the first gate dielectric layer 40 can be a single film layer or a composite film layer. For example, a first sub-gate dielectric layer 41 can be formed on the inner wall of the gate trench 13 by thermal oxidation. The material of the first sub-gate dielectric layer 41 is the same as that of the first sub-dielectric layer 21, which is silicon oxide. Then, a deposition process is performed to form a second sub-gate dielectric layer 42 on the surface of the first sub-gate dielectric layer 41. The second sub-gate dielectric layer 42 can be located only within the gate trench 13, or it can extend to the gate trench 13 and cover the top surface of the first dielectric layer 20.
[0118] In this embodiment, the thermal oxidation process can be performed at a temperature of 1150°C, and the thickness of the first sub-gate dielectric layer 41 is 1500 Å. The thickness of the second sub-gate dielectric layer 42 is 1800 Å. Subsequently, the formed semiconductor device is subjected to a heat treatment process at 1100°C for 30 minutes to improve the quality of the first gate dielectric layer 40.
[0119] Please refer to Figure 6 A shielding gate material layer 51 is formed within the area enclosed by the first gate dielectric layer 40. The shielding gate material layer 51 extends beyond the gate trench 13 and covers the top surface of the first dielectric layer 20. The shielding gate material layer 51 is made of polysilicon.
[0120] Next, please refer to Figure 7 The shielding grid material layer 51 is further thinned by chemical mechanical polishing (CMP) to reduce its thickness.
[0121] Please refer to Figure 8 A second mask layer is formed, which covers the substrate located in the terminal region. Alternatively, the second mask layer 32 covers the shielding gate material layer 51 located in the gate trench of the terminal region, which is the shielding gate material layer 51 located outside the gate trench.
[0122] Please refer to Figure 9 Using the second mask layer 32 as a mask, at least a portion of the shielding gate material layer 51 located in the cell region 11 is removed, so that the shielding gate material layer 51 located in the gate trench 13 forms the shielding gate 50, and the shielding gate material layer 51 located on the terminal region 12 forms the initial blocking layer 62.
[0123] It should be noted that when the first gate dielectric layer 40 includes a first sub-gate dielectric layer 41 and a second sub-gate dielectric layer 42 stacked together, the first sub-gate dielectric layer 41 covers the inner wall of the gate trench 13.
[0124] The steps of removing part of the shielding barrier material layer also include:
[0125] Please refer to Figure 10 Furthermore, using the second mask layer 32 as a mask, a portion of the second sub-gate dielectric layer 42 is removed so that the top surface of the remaining second sub-gate dielectric layer 42 is lower than the shielding gate 50.
[0126] The second mask layer 32 can then be removed through a cleaning process.
[0127] Please refer to Figures 11 to 16 The step of forming a stacked insulating layer and a gate within the filled region includes:
[0128] Please refer to Figure 11 A deposition process is performed to form an insulating material layer 71 within the filled region 14. The insulating material layer 71 extends beyond the filled region 14 and covers the top surface of the first dielectric layer 20 and the initial barrier structure 61. The insulating material layer 71 is made of silicon oxide.
[0129] Next, please refer to Figure 12 The thickness of the insulating material layer 71 is partially removed by chemical mechanical polishing (CMP) to ensure that the remaining structure has a flat surface. It should be noted that during the polishing process, the initial barrier layer 62 in the initial barrier structure 61 can be used as a barrier layer to improve the accuracy of the chemical mechanical polishing process.
[0130] Next, please refer to Figure 13 This forms a third mask layer 33 that covers the initial blocking structure 61 located in the terminal region 12.
[0131] Please refer to Figures 14 to 16 Using the third mask layer 33 as a mask, a portion of the insulating material layer 71, as well as the first dielectric layer 20 and the first sub-gate dielectric layer 41 located in the cell region, are removed to retain a portion of the insulating material layer 71 located on top of the shielding gate 50, thereby forming the insulating layer 70.
[0132] It's important to understand that this step can be completed in three steps. For an example, please refer to... Figure 14 Using the third mask layer 33 as a mask, the insulating material layer 71 exposed on the top surface of the first dielectric layer 20 is removed. In this way, using the first dielectric layer 20 as an etching stop layer can improve the etching accuracy.
[0133] Please refer to Figure 15 The third mask layer 33 is used as a mask, and the first sub-dielectric layer 21 is used as an etch stop layer to remove the exposed second sub-dielectric layer 22 of the first dielectric layer 20.
[0134] Please refer to Figure 16 Continuing with the third mask layer 33 as a mask, the first sub-dielectric layer 21 of the exposed first dielectric layer 20, as well as the first sub-gate dielectric layer 41 and part of the insulating material layer 71 exposed in the gate trench 13, are removed, so that the remaining insulating material layer 71 constitutes the insulating layer 70. Furthermore, the first gate dielectric layer 40 enclosing the shielding gate 50 and the shielding gate 50 constitute the shielding gate structure.
[0135] Please refer to Figure 17 A thermal oxidation process is performed to form a second gate dielectric layer 80 on the surface of the exposed substrate 10 and the top surface of the initial barrier structure 61, wherein the second gate dielectric layer 80 is connected to the retained first gate dielectric layer 40. The formation process of the second gate dielectric layer 80 can be a thermal oxidation process. In this step, the temperature of the thermal oxidation process can be 1150°C, and the thickness of the second gate dielectric layer 80 is 500 Å.
[0136] Please refer to Figure 18 and Figure 19 A gate 90 is formed in the area enclosed by the second gate dielectric layer 80, and the gate 90 and the second gate dielectric layer 80 constitute a gate structure.
[0137] For details, please refer to Figure 18 A gate material layer 91 is formed within the area enclosed by the second gate dielectric layer 80 through a deposition process. The gate material layer 91 also covers the top surface of the initial barrier structure 61. The gate material layer 91 is made of polysilicon.
[0138] Then, using the second gate dielectric layer 80 as an etch stop layer, a portion of the gate material layer 91 is etched, and the gate material layer 91 remaining in the gate trench 13 constitutes the gate 90.
[0139] In one possible implementation, the step of removing part of the initial blocking structure includes:
[0140] Please refer to Figure 20 This forms a fourth mask layer 34, which covers the cell region 11 and part of the initial blocking structure 61.
[0141] Please refer to Figure 21 Using the fourth mask layer 34 as a mask, a portion of the initial blocking structure 61 is removed to form the blocking structure 60.
[0142] In one possible implementation, the step of doping the exposed substrate using the gate and barrier structures as masks to form the first and second doped regions further includes:
[0143] Please refer to Figure 22 Using the gate 90 and the barrier structure 60 as masks, the exposed substrate 10 is doped to form a first initial doped region 151 and a second initial doped region 161.
[0144] Please refer to Figure 23 The push-well activation process is performed to expand the first initial doped region 151 and the second initial doped region 161 to form the first doped region 15 and the second doped region 16, wherein the first doped region 15 is located in the cell region 11, the second doped region 16 is located in the terminal region 12, and extends below the barrier structure 60.
[0145] For example, by performing heat treatment on the semiconductor device described above to expand the first initial doped region 151 and the second initial doped region 161, it is helpful to form a deeper initial doped region, thereby improving the electrical performance of the semiconductor device. Furthermore, it can promote the diffusion of dopant ions, making the doping concentration within the doped region more uniform, which helps to improve the performance stability and consistency of the semiconductor device. The temperature in the heat treatment is 1050°C, and the treatment time is 60 minutes.
[0146] Please refer to Figure 24 In some embodiments, the method for fabricating the semiconductor device further includes:
[0147] A fifth mask layer 35 is formed, which covers the second doped region 16.
[0148] A plasma implantation process is performed to form a third doped region 17 within the first doped region 15. The conductivity types of the first doped region 15 and the third doped region 17 are different. For example, the conductivity type of the first doped region 15 is N-type, and the conductivity type of the third doped region 17 is P-type.
[0149] by Figure 24 Taking the structure shown as an example, the drain region of the semiconductor device provided in this embodiment is located on the back side of the substrate. In this case, the third doped region 17 constitutes the source region of the transistor, and the first doped region 15 constitutes the channel region of the transistor. When a voltage is applied to the gate 90, the first doped region 15 undergoes inversion to enable the transistor to conduct.
[0150] In one possible implementation, after the step of forming the third doped region, the method for fabricating the semiconductor device further includes:
[0151] A first conductive plug, a second conductive plug, a third conductive plug, a fourth conductive plug, and a fifth conductive plug are formed. The first conductive plug is electrically connected to the gate of the cell region; the second conductive plug is electrically connected to the first doped region; the third conductive plug is electrically connected to the shielding gate located in the termination region; the fourth conductive plug is electrically connected to the substrate located in the termination region; and the fifth conductive plug is electrically connected to the second doped region. Please refer to the following structure. Figures 25 to 32 .
[0152] Please refer to Figure 25 A second dielectric layer 100 is formed, which covers the barrier structure 60 and the exposed second gate dielectric layer 80 and gate 90.
[0153] Please refer to Figure 26 A sixth mask layer 36 is formed on the second dielectric layer 100, and the sixth mask layer 36 is patterned to form a plurality of openings 361 within the sixth mask layer 36.
[0154] Please refer to Figure 27 An etching process is performed, using the sixth mask layer 36 as a mask, to remove the second dielectric layer 100 and the blocking structure 60 exposed within the opening 361, thereby forming multiple etched holes. It should be understood that the number of etched holes can be set according to the number of devices in the substrate 10.
[0155] For example, the plurality of etched holes include a first etched hole 111, a second etched hole 112, a third etched hole 113, a fourth etched hole 114, and a fifth etched hole 115. The first etched hole 111 exposes the top surface of the gate 90, the second etched hole 112 exposes the top surface of the third doped region 17, the third etched hole 113 exposes the top surface of the barrier structure 60, the fourth etched hole 114 exposes the top surface of the second sub-dielectric layer in the barrier structure 60, and the fifth etched hole 115 exposes the top surface of the second doped region 16.
[0156] Please refer to Figure 28 The etching continues along the first etch hole 111, the second etch hole 112, the third etch hole 113, the fourth etch hole 114 and the fifth etch hole 115, such that the bottom of the first etch hole 111 extends into the gate 90, the bottom of the second etch hole 112 extends into the first doped region 15, the bottom of the third etch hole 113 extends into the shield gate 50, the fourth etch hole 114 exposes the top surface of the substrate 10, and the bottom of the fifth etch hole 115 extends into the second doped region 16.
[0157] It should be noted that the conductive plug formed later is electrically connected to the corresponding device. In order to reduce the contact resistance between the two, the preparation method provided in this embodiment further includes: forming a heavily doped region 120, which is disposed at the end of the conductive plug facing the substrate 10.
[0158] For example, please refer to Figure 29 Except for the fourth etched via 114, the exposed areas of the remaining etched vias are heavily doped using a plasma doping process to form a heavily doped region 120. This configuration reduces the contact resistance between the conductive plug and the corresponding device, which helps improve current transmission efficiency and reduce power loss. It also improves the overall performance of the semiconductor device, including switching speed, signal transmission speed, and current drive capability.
[0159] Please refer to the attached document. Figure 30 and Figure 31 Conductive plugs are formed within each etched hole using a deposition process. These conductive plugs include a first conductive plug 131, a second conductive plug 132, a third conductive plug 133, a fourth conductive plug 134, and a fifth conductive plug 135. The first conductive plug 131 is electrically connected to the gate 90, the second conductive plug 132 is electrically connected to the first doped region 15, the third conductive plug 133 is electrically connected to the shielding gate 50, the fourth conductive plug 134 is electrically connected to the substrate 10, and the fifth conductive plug 135 is electrically connected to the second doped region 16. A diode is formed between the second doped region 16 and the substrate 10.
[0160] Please refer to Figure 32 After the conductive plug is formed, an interconnect layer is also required. The interconnect layer includes multiple interconnect blocks 140 that are insulated from each other. Each interconnect block is used to electrically connect with the corresponding conductive plug so as to facilitate connection with the external circuit.
[0161] As can be clearly seen from the above embodiments, six photomasks are used in the fabrication process of semiconductor devices. Compared with the approximately ten photomasks required in related technologies, this greatly reduces the frequency of photomask usage, thereby simplifying the semiconductor device fabrication process and reducing the fabrication cost.
[0162] This application also provides a semiconductor device, which is prepared by the semiconductor device preparation method described in any of the above embodiments.
[0163] Please refer to Figure 32 Semiconductor devices include:
[0164] The substrate 10 has a cell region 11 and a terminal region 12.
[0165] The shielding gate structure includes a first shielding gate structure and a second shielding gate structure that are interconnected. The first shielding gate structure is located within the cell region 11, and its top surface is lower than the top surface of the substrate 10. The second shielding gate structure is located in the terminal region 12, and its top surface is flush with the top surface of the substrate 10. The first gate dielectric layer 40 and the shielding gate 50 together constitute the shielding gate structure.
[0166] Insulating layer 70 is disposed on the first shielding grid structure.
[0167] A gate structure is disposed on an insulating layer 70. The second gate dielectric layer 80 and the gate 90 constitute the gate structure.
[0168] The barrier structure 60 is disposed on the terminal area 12, and the barrier structure 60 includes a first dielectric layer 20 and a barrier layer 63 stacked together. The barrier layer 63 is prepared synchronously with the shielding grid of the shielding grid structure.
[0169] A first doped region 15 and a second doped region 16 are located within a cell region 11 and are used to form a transistor with a gate structure. The second doped region 16 is located in a terminal region and is used to form a diode with an adjacent substrate.
[0170] Given that the semiconductor device provided in this application includes a barrier structure, and the barrier layer of the barrier structure and the shielding gate of the shielding gate structure are fabricated simultaneously, it is unnecessary to re-form a mask, thus reducing the number of masks. Furthermore, the first dielectric layer is a three-layer structure, which greatly enhances the barrier capability of the barrier structure. Meanwhile, the shielding gate is typically made of polysilicon, a heavily doped material, which further enhances the barrier capability of the barrier structure. When the gate and barrier structure are used as masks to form the first and second doped regions, doping of the substrate shielded by the barrier structure can be avoided, improving the yield of the semiconductor device.
[0171] This application also provides a power device, including the semiconductor device described in any of the above embodiments. The power device provided in this application can be applied to discrete devices, AC-DC converters, or temperature sensors.
[0172] It should be noted that the beneficial effects of the power device provided in this application embodiment are the same as the beneficial effects of the semiconductor device provided in the above embodiment, and will not be elaborated further in this embodiment.
[0173] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0174] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., mentioned in the specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.
[0175] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate comprising adjacent cell regions and terminal regions; A dielectric material layer is formed on the substrate, and the substrate and the dielectric material layer are patterned to form a gate trench in the substrate, and the remaining dielectric material layer constitutes a first dielectric layer. A shielding gate structure is formed within the gate trench. Along the extension direction of the gate trench, the shielding gate structure includes a first shielding gate structure and a second shielding gate structure interconnected. The first shielding gate structure is located within the cell region, and the top surface of the first shielding gate structure is lower than the top surface of the substrate and forms a filling region with the substrate. The second shielding gate structure is located in the terminal region, and the shielding gate of the second shielding gate structure extends outside the gate trench and covers the terminal region. The shielding gate covering the terminal region forms an initial barrier layer, and the stacked first dielectric layer and the initial barrier layer constitute an initial barrier structure. An insulating layer and a gate structure are formed in the filled region; The initial blocking structure is partially removed, and the remaining initial blocking structure constitutes the blocking structure. Using the gate and the barrier structure as masks, the exposed substrate is doped to form a first doped region and a second doped region.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The steps of forming a shielding gate structure within the gate trench include: A first gate dielectric layer is formed on at least the inner wall of the gate trench; A shielding gate material layer is formed within the area enclosed by the first gate dielectric layer. The shielding gate material layer extends beyond the gate trench and covers the top surface of the first dielectric layer. A second mask layer is formed, which covers the substrate located in the terminal region; Using the second mask layer as a mask, at least a portion of the shielding gate material layer located within the cell region is removed, the shielding gate material layer located within the gate trench is retained to form a shielding gate, and the shielding gate material layer located on the terminal region is retained to form an initial blocking layer.
3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The first gate dielectric layer includes a first sub-gate dielectric layer and a second sub-gate dielectric layer stacked together, wherein the first sub-gate dielectric layer covers the inner wall of the gate trench; The step of removing part of the shielding grid material layer further includes: A portion of the second sub-gate dielectric layer is removed so that the top surface of the remaining second sub-gate dielectric layer is lower than the shielding gate.
4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The step of forming a stacked insulating layer and a gate within the filled region includes: A deposition process is performed to form an insulating material layer within the filled area, the insulating material layer extending beyond the filled area and capping the top surface of the first dielectric layer and the initial barrier structure; A third mask layer is formed to cover the initial blocking structure located in the terminal area; Using the third mask layer as a mask, a portion of the insulating material layer and the first dielectric layer and the first sub-gate dielectric layer located in the cell region are removed to retain a portion of the insulating material layer located on top of the shielding gate to form the insulating layer; A thermal oxidation process is performed to form a second gate dielectric layer on the exposed surface of the substrate and the top surface of the initial barrier structure, the second gate dielectric layer being connected to the retained first gate dielectric layer; A gate is formed within the region enclosed by the second gate dielectric layer.
5. The method for fabricating a semiconductor device according to any one of claims 1-4, characterized in that, The steps of removing part of the initial blocking structure include: A fourth mask layer is formed, which covers the cell region and part of the initial blocking structure; Using the fourth mask layer as a mask, a portion of the initial blocking structure is removed to form the blocking structure.
6. The method for fabricating a semiconductor device according to any one of claims 1-4, characterized in that, The step of doping the exposed substrate using the gate and the barrier structure as masks to form a first doped region and a second doped region further includes: A plasma implantation process is performed to dope the exposed substrate to form a first initial doped region and a second initial doped region; A push-in activation process is performed to expand the first initial doped region and the second initial doped region to form a first doped region and a second doped region, wherein the first doped region is located in the cell region and the second doped region is located in the terminal region.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, After performing the push-in activation process, the preparation method further includes: A fifth mask layer is formed, which covers the second doped region; A plasma implantation process is performed to form a third doped region in the first doped region, wherein the conductivity type of the first doped region and the conductivity type of the third doped region are different.
8. The method for fabricating a semiconductor device according to claim 7, characterized in that, After the step of forming the third doped region, the preparation method further includes: A first conductive plug, a second conductive plug, a third conductive plug, a fourth conductive plug, and a fifth conductive plug are formed; wherein, the first conductive plug is electrically connected to the gate located in the cell region; the second conductive plug is electrically connected to the first doped region; the third conductive plug is electrically connected to the shielding gate located in the terminal region; the fourth conductive plug is electrically connected to the substrate located in the terminal region; and the fifth conductive plug is electrically connected to the second doped region.
9. A semiconductor device, characterized in that, The semiconductor device is prepared by the method for preparing a semiconductor device according to any one of claims 1-8, and the semiconductor device comprises: A substrate having cellular regions and terminal regions; A shielding grid structure, comprising a first shielding grid structure and a second shielding grid structure connected to each other, wherein the first shielding grid structure is located within the cell region and the top surface of the first shielding grid structure is lower than the top surface of the substrate, and the second shielding grid structure is located in the terminal region and the top surface of the second shielding grid structure is flush with the top surface of the substrate. An insulating layer is disposed on the first shielding grid structure; A gate structure, wherein the gate structure is disposed on the insulating layer; A blocking structure is disposed on the terminal area, and the blocking structure includes a first dielectric layer and a blocking layer stacked together, wherein the blocking layer is fabricated simultaneously with the shielding grid of the shielding grid structure; A first doped region and a second doped region, wherein the first doped region is located within the cell region and is used to form a transistor with the gate structure, and the second doped region is located in the terminal region and is used to form a diode with the adjacent substrate.
10. A power device, characterized in that, Includes the semiconductor device as described in claim 9.