Superjunction component with improved edge sealing

Abstract

A semiconductor device comprises a semiconductor body, which includes a main face, a back face, and an outer edge face; a superjunction structure, which includes multiple superjunction columns alternating along a lateral direction of the semiconductor body in a conductivity type; an active region, which includes multiple transistor cells; and a peripheral region, which laterally separates the active region from the outer edge face, wherein the peripheral region is free of the transistor cells;wherein the superjunction structure comprises a first cell region and a second cell region, wherein the superjunction columns in the second cell region have a lower dopant concentration than the superjunction columns in the first cell region, wherein the first cell region is arranged within a central part of the active region, and wherein the second cell region overlaps at least partially with an outer part of the active region adjacent to the peripheral region.

Description

BACKGROUND Power semiconductor devices conduct high load currents and withstand high reverse voltages. Superjunction devices are power semiconductor devices that comprise a superjunction structure with oppositely doped columns formed in a drift zone, electrically connected in series to controllable device channels. When a reverse voltage is applied to a superjunction device, a lateral electric field increases and clears the mobile charge carriers along the vertical pn junctions between the oppositely doped columns. A space charge begins to expand perpendicular to the direction of on-state load current flow. At a relatively low reverse voltage, the mobile charge carriers are completely expelled from the superjunction structure. As the reverse voltage is further increased, the depleted superjunction structure acts as a quasi-intrinsic layer, and the vertical electric field increases.The breakdown voltage is decoupled from the dopant concentrations in the superjunction structure, allowing for comparatively high dopant concentrations. Therefore, superjunction devices typically combine very low on-resistance with high blocking capability. The more precisely the dopant concentrations of the oppositely doped columns are matched, the higher the efficiency of the superjunction structure with respect to blocking capability and semiconductor volume. There is a need to improve superjunction components. SUMMARY One embodiment of a semiconductor device comprises: a semiconductor body having a main face, a back face, and an outer perimeter extending between the main face and the back face; a superjunction structure having multiple superjunction columns alternating along a lateral direction of the semiconductor body in a conductivity type; an active region having multiple transistor cells, each transistor cell configured to control a vertical current flowing through one of the superjunction columns; and a peripheral region separating the active region laterally from the outer perimeter, the peripheral region being free of transistor cells;wherein the superjunction structure comprises a first cell region and a second cell region, wherein the superjunction columns in the second cell region have a lower dopant concentration than the superjunction columns in the first cell region, wherein the first cell region is arranged within a central part of the active region, and wherein the second cell region overlaps at least partially with an outer part of the active region adjacent to the peripheral region. One embodiment of a semiconductor device comprises: a semiconductor body having a main face, a back face, and an outer perimeter extending between the main face and the back face; a superjunction structure having multiple superjunction columns alternating along a lateral direction of the semiconductor body in a conductivity type; an active region having multiple transistor cells, each transistor cell configured to control a vertical current flowing through one of the superjunction columns; a peripheral region separating the active region laterally from the outer perimeter, the peripheral region being free of transistor cells;and a groove formed in the main surface of the semiconductor body in the peripheral region, the groove being filled with a dielectric material, wherein the width of an inner section of the peripheral region is less than or equal to twice the cell pitch of the superjunction structure, the cell pitch being a separation distance between immediately adjacent superjunction columns of the same doping type in the superjunction structure, and the width of the inner section of the peripheral region being a lateral distance from the center of a gate trench of an outermost transistor cell of the active region to a lower corner of the groove. BRIEF DESCRIPTION OF THE DRAWINGS The elements of the drawings are not necessarily to scale with each other. Identical reference numerals denote corresponding similar parts. The features of the various embodiments shown can be combined, provided they are not mutually exclusive. Embodiments are illustrated in the drawings and are described in detail in the following description. Fig. 1 illustrates a superjunction semiconductor device from a cross-sectional perspective according to one embodiment. Fig. 2, which includes Figs. 2A and 2B, illustrates a superjunction semiconductor device from a top-down perspective according to one embodiment. Fig. 3 illustrates dopant concentration profiles of superjunction semiconductor devices according to embodiments. Fig. 4 illustrates a detailed cross-sectional view of an inner section of the peripheral region of a superjunction semiconductor device according to one embodiment. DETAILED DESCRIPTION Embodiments of a superjunction power semiconductor device are disclosed herein. The semiconductor device has a superjunction structure formed by superjunction columns alternating along a lateral direction of a semiconductor body of a conductivity type. The power semiconductor device comprises an active region and a peripheral region that laterally separates the active region from an outer edge of the semiconductor body. The active region has multiple transistor cells configured to control a vertical load current flowing through the semiconductor body. The peripheral region is free of transistor cells and is designed to relax the electric field that builds up in the semiconductor body, thereby ensuring that no breakdown occurs near the outer edge of the semiconductor body.Advantageously, the embodiments disclosed herein reduce the size of the peripheral area relative to the active area without impairing the voltage blocking capability of the device. Thus, a larger proportion of the chip area is dedicated to the transistor cells. Consequently, a higher current-carrying capacity can be achieved for a given chip size while maintaining the voltage blocking capability. Figure 1 discloses a semiconductor device 100 according to one embodiment. The semiconductor device 100 is formed in a semiconductor body 102. The semiconductor body 102 can be made of a single-crystal semiconductor material such as silicon (Si), silicon carbide (SiC), germanium (Ge), a silicon-germanium crystal (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), etc. The semiconductor body 102 has a main surface 104, a back surface 106, and an outer edge 108 extending between the main surface 104 and the back surface 106. The main surface 104 can be at least approximately planar and can have coplanar surface sections. The back surface 106 can also be at least approximately planar and can have coplanar surface sections parallel to the main surface 104. A minimum distance between the main and back surfaces 104, 106 is chosen such that a specified voltage-blocking capability of the semiconductor device 100 is achieved. The outer edge 108 is a lateral surface connecting the main and back surfaces 104, 106. The outer edge 108 can, for example, be perpendicular to the main and back surfaces 104, 106. The semiconductor body 102 has a superjunction structure. Examples of devices with superjunction structures and corresponding techniques for fabricating devices with superjunction structures are disclosed in U.S. Patent 10,084,038B2, U.S. Patent 10,468,479B2, and U.S. Patent 11,211,483, the contents of each document being incorporated herein by reference. The superjunction structure has several superjunction columns 110 that alternate along a lateral direction of the semiconductor body 102 in a conductivity type. In particular, the superjunction structure has columns 112 of a first conductivity type and columns 114 of a second conductivity type opposite to the conductivity type of the columns 112 of the first conductivity type, which are arranged alternately with each other along the lateral direction of the semiconductor body 102.At least in the active transistor region, the net dopant concentration of the superjunction columns 110 is chosen to be high, so that the contribution of the drift region to the on-resistance of the device can be kept low. For example, a net dopant concentration of the superjunction columns 110 in the active transistor region can be in the range of 1E15 dopant atoms / cm3 to 1E18 dopant atoms / cm3. Furthermore, the net dopant concentration of the columns 112 of the first conductivity type can be substantially equal to the net dopant concentration of the adjacent columns 114 of the second conductivity type, e.g., within 20%, within 10%, within 5%, to maintain the compensation principle. The following discussion refers to superjunction unit cells.These superjunction unit cells correspond to pairs of superjunction columns 110 that are directly adjacent to each other and form a pn junction, i.e., a column 112 of the first conductivity type adjacent to a column 114 of the second conductivity type. The superjunction structure consists of several superjunction unit cells arranged in a pattern. These superjunction unit cells can be formed according to a regular pitch. The superjunction structure can be produced in various ways. For example, the superjunction structure can be produced by a multi-epi / multi-implantation process in which multiple epitaxial layers are grown, dopants are implanted into the surfaces of the epitaxial layers, and the process is repeated. Alternatively, the superjunction structure can be produced by creating a thick epitaxial sublayer, creating trenches in the thick epitaxial sublayer, and, for example,This can be achieved by implanting dopants through the side walls of the trenches or by depositing doped layers in the trenches. The semiconductor body 102 has an active region 116. The active region 116 has several transistor cells. The transistor cells are configured to control a vertical load current flowing between the main surface 104 and the back surface 106. The transistor cells can be configured, for example, as MOSFET cells or IGBT cells. Each transistor cell has a gate electrode 118. As shown, the gate electrode 118 can be arranged within a trench. Alternatively, the gate electrode 118 can be a planar electrode arranged on a surface of the semiconductor body 102. Each transistor cell has a source / emitter region 120 of a first conductivity type (e.g. n-type) (see Fig. 4) located on the main surface 104, and a body region 122 of a second conductivity type (e.g. p-type) (see Fig. 4) located between the source / emitter regions 120 and the back surface 106 of the semiconductor body 102.The body regions 122 can be created by a single doped layer fabricated in the main surface 104, with the source / emitter regions 120 corresponding to localized implantations within the single doped layer. The semiconductor body 102 has a drain / collector region 124 on the back surface 106 of the semiconductor body 102. The drain / collector region 124 can be provided by a highly doped layer of a first conductivity type in the case of a MOSFET or a highly doped layer of a second conductivity type in the case of an IGBT. In a generally known manner, each gate electrode 118 controls a current flowing from the source / emitter regions to the drain / collector of the device.The columns 112 of the first conductivity type form the drift region of the device, such that the transistor current flows through these superjunction columns 110 in the on-state of the device, and these superjunction columns 110 maintain a voltage potential in the off-state of the device. The columns 114 of the second conductivity type allow for higher doping of the columns 112 of the first conductivity type by compensating for the charges present in these superjunction columns 110, thereby reducing the on-resistance of the device while maintaining the reverse voltage in the off-state. At an outer boundary of the active region 116, the outermost column 114 of the second conductivity type, which is connected to the source regions, is actively conductive in both directions and thus accepts a vertical forward and reverse current of the semiconductor device 100. The semiconductor body 102 has a peripheral region 126. The peripheral region 126 separates the active region 116 laterally from the outer edge 108. That is, the peripheral region 126 is located between the active transistor cells and the chip edge. According to one embodiment, from a top-down perspective of the semiconductor body 102, the peripheral region 126 forms a closed ring that completely surrounds the active region 116. That is, the peripheral region 126 forms a complete buffer that separates the active transistor cells from the chip edge in every direction. The peripheral region 126 is free of transistor cells. That is, the peripheral region 126 refers to a section of the semiconductor body 102 that does not include any controllable structures for controlling a load current flowing between the main surface 104 and the back surface 106 of the semiconductor body 102.The outermost transistor cell of the active region 116 forms a boundary with the peripheral region 126. As explained in more detail below, the superjunction structure can extend into the peripheral region 126. However, the superjunction unit cells of the peripheral region 126 differ from the superjunction unit cells of the active region 116 in that no gate structure and / or source / emitter region is formed above them, and thus no current of the active transistor device flows through these superjunction unit cells. Therefore, the boundary between the active region 116 and the peripheral region 126 is located at the interface between the outermost superjunction unit cell of the active region 116, which forms the drift structure of an active transistor device, and the innermost superjunction unit cell of the peripheral region 126, which does not form part of an active transistor device. The peripheral region 126 features edge termination structures designed to improve the voltage-blocking capability of the device by preventing large equipotential gradients from occurring near the outer edge face 108 of the semiconductor body 102. In particular, the superjunction structure can extend into the peripheral region 126, and the doping concentration can be graded downwards towards the outer edge face 108 in a manner described in more detail below. Additionally, the peripheral region 126 can include a field-plate electrode 128 located on the main face 104 of the semiconductor body 102, a so-called junction termination extension (JTE) region 130 bridging multiple superjunction columns 110, and an intrinsically or very lightly doped outer region 132 located between the superjunction structure and the outer edge face 108 of the semiconductor body 102.The depicted peripheral region 126 represents only one exemplary edge termination configuration. The concepts disclosed herein, and in particular the superjunction structure doping and the width of the inner section of the peripheral region 126, are applicable to a variety of different edge termination configurations, including one of the edge termination configurations discussed in the aforementioned patent documents. The superjunction structure is formed with a first cell region 134 and a second cell region 136. The first cell region 134 is located within a central part of the active region 116. That is, the first cell region 134 refers to a group of superjunction unit cells that are completely contained within the active region 116. Thus, each of the superjunction unit cells from the first cell region 134 forms one of the transistor cells. The second cell region 136 overlaps at least partially with an outer part of the active region 116 that borders the peripheral region 126. That is, the second cell region 136 includes at least one of the superjunction unit cells at the outer edge of the active region 116, which forms one of the transistor cells. The second cell region 136 may also extend into the peripheral region 126.Thus, the second cell region 136 comprises both superjunction unit cells from the outer part of the active region 116 and superjunction unit cells that do not form part of an active transistor device. In general, the number of superjunction unit cells from the second cell region 136 that overlap with the active region 116 cannot exceed 20, 15, 10, 5, 3, etc. Expressed as percentages, the overlap between the second cell region 136 and the active region 116 cannot exceed 10%, 5%, or 1% of the total area of ​​the active region 116. The superjunction structure is designed such that the superjunction columns 110 in the second cell region 136 have a lower dopant concentration than the superjunction columns 110 in the first cell region 134. In this context, the dopant concentration of the superjunction columns 110 refers to an average dopant concentration in the respective superjunction column 110. This dopant concentration can be expressed as a dopant concentration integrated from top to bottom within the respective superjunction column 110.In a configuration where the superjunction columns 110 in the second cell region 136 have a lower dopant concentration than the superjunction columns 110 in the first cell region 134, the mean dopant concentration of each of the superjunction columns 110 in the first cell region 134 is at or above a first amount, and the mean dopant concentration of each of the superjunction columns 110 in the second cell region 136 is not higher than a second amount, which is below the first amount. According to one embodiment, the dopant concentration of each of the superjunction unit cells in the first cell region 134 is substantially the same.This means that each of the columns 112 of the first conductivity type is nominally doped to have the same concentration, each of the columns 114 of the second conductivity type is nominally doped to have the same concentration, and any difference in dopant concentration between the columns 112 of the first conductivity type and the columns 114 of the second conductivity type is kept below a predefined threshold to maintain charge compensation, e.g., within ±10%, ±5%, etc. In a more specific embodiment, the columns 112 of the first conductivity type and the columns 114 of the second conductivity type of each unit cell have the same dopant concentration.In the second cell region 136, the superjunction unit cells are configured such that at least one of the columns 112 of the first conductivity type and one of the columns 114 of the second conductivity type has a lower dopant concentration than the counterpart superjunction columns 110 from the first cell region 134. Consequently, the superjunction unit cell from the second cell region 136, which overlaps with the active region 116, consists of at least one superjunction unit cell with at least one superjunction column that is less densely doped than its counterpart superjunction columns 110 from the first cell region 134. According to one embodiment, the superjunction structure is configured such that the dopant concentration in the superjunction columns 110 in the second cell region 136 decreases laterally away from the active region 116 and towards the outer edge 108. This decrease can occur according to a variety of different schemes or patterns. In one embodiment, the dopant concentration of each of the superjunction columns 110 in the second cell region 136 decreases laterally towards the outer edge 108 relative to a directly adjacent superjunction column. That is, the decrease in dopant concentration occurs on a column-by-column basis.For example, an outermost superjunction column 110 from the first cell region 134 can have a first dopant concentration, an innermost superjunction column 110 from the second cell region 136, adjacent to the outermost superjunction column 110 from the first cell region 134, can have a second dopant concentration that is lower than the first dopant concentration, a subsequent superjunction column 110 from the second cell region 136, adjacent to the innermost superjunction column 110 from the second cell region 136, can have a third dopant concentration that is lower than the second dopant concentration, and so on. According to one embodiment, in the second cell region 136, the dopant concentration of each superjunction unit cell decreases in the lateral direction towards the outer edge 108 relative to a directly laterally adjacent superjunction unit cell.This means that the decrease in dopant concentration occurs on a unit-cell-by-unit-cell basis. For example, an outermost of the superjunction unit cells from the first cell region 134 can be configured such that each superjunction column is doped with a first dopant concentration, an innermost of the superjunction unit cells from the second cell region 136 can be configured such that each superjunction column is doped with a second dopant concentration that is lower than the first dopant concentration, a subsequent set of superjunction unit cells from the second cell region 136 can be configured such that each superjunction column 110 is doped with a third dopant concentration that is lower than the second dopant concentration, and so on.According to another embodiment, in the section of the second cell region 136 that overlaps with the active region 116, the dopant concentration of each superjunction unit cell decreases relative to the directly laterally adjacent superjunction unit cell in the lateral direction towards the outer edge 108. This decrease can occur over five or fewer of the superjunction unit cells, three or fewer of the superjunction unit cells, and so on. Subsequently, the dopant concentration of each superjunction unit cell within the peripheral region 126 can remain substantially constant, e.g., within approximately 10% of each other in the lateral direction towards the outer edge 108. Separately or in combination, the dopant concentration of the superjunction columns 110 in the peripheral region 126 is configured to maintain a constant lateral electric field.This means that the dopant concentration of the superjunction columns 110 is equal or essentially equal between laterally adjacent superjunction columns 110, so that the lateral electric field between the two remains constant. Meanwhile, the vertical dopant profile of the superjunction columns 110 can vary, for example, by increasing towards a vertical center of the device. However, the vertically stepped profile can remain constant across laterally adjacent superjunction columns 110 to maintain a constant lateral electric field. More generally, any scheme or pattern that gradually decreases the dopant concentration of the superjunction columns 110 can be used. The change in dopant concentration can follow a linear function or more complex functions. A superjunction structure with the graded dopant profile described above can be realized by employing dopant techniques that modify the dopant dose used to fabricate the superjunction columns 110 along the lateral direction. More precisely, as explained above, the superjunction structure can be fabricated by a multi-epi / multi-implantation process. In this case, the patterned masks fabricated on each of the epitaxial layers can have differently sized openings in a lateral direction towards the outer edge 108 of the semiconductor body 102. The superjunction columns 110 in the first cell region 134 can be fabricated using mask openings that are large to the extent permitted by lithography, thus enabling the maximum implantation dose.The size of these openings can be gradually reduced as the implantation mask approaches the outer edge face 108 of the semiconductor body 102, and can approach or reach the minimum opening size of the mask, thereby reducing the implantation dose when the superjunction columns 110 are located in these regions. If the superjunction columns 110 are produced by implanting dopants through the sidewalls of the trenches or by depositing doped layers in the trenches, similar masking techniques can be employed to modify the amounts of dopants implanted into the semiconductor material in a lateral direction towards the outer edge face 108 of the semiconductor body 102. By configuring the superjunction structure such that it has superjunction columns 110 in the outer edge of the active region 116 with a lower dopant concentration than the superjunction columns 110 in the remaining central part of the active region 116, an advantageous reduction in chip area is possible while maintaining the nominal voltage. More precisely, the configuration of the superjunction structure in which the dopant concentration of the superjunction columns 110 decreases in the lateral direction towards the outer edge 108 reduces the gradient of the electric field and increases the effective breakdown voltage in the outer edge region of the chip. The decreasing dopant concentration of the superjunction columns 110 must occur gradually over many superjunction columns 110 so that directly adjacent superjunction columns 110 remain in a relatively compensated arrangement, i.e., the superjunction principle is maintained.By initiating a reduction in the dopant concentration within the active region 116, the number of superjunction unit cells required in the peripheral region to achieve the necessary field formation for a given breakdown strength is reduced. As a result, the size of the edge termination can be reduced, and consequently, the ratio between the active region 116 and the peripheral region 126 can be increased while maintaining a given voltage blocking capability. This results in a larger proportion of the chip area being dedicated to active transistor cells, leading to a favorable current carrying capacity per chip size. Figure 2 shows a top view of the superjunction semiconductor device 100 according to one embodiment. Figures 2A and 2B show the layout of the superjunction columns 110 at one corner of the semiconductor body 102. Similar arrangements can be provided at any other corner of the semiconductor body 102. As shown in Figure 2A, the width of the superjunction columns 110 can change as they approach the outer edge 108. In the X direction of Figure 2A, the width of the superjunction columns 110 can decrease as they approach the outer edge 108. For example, the width of the superjunction columns 110 can decrease from about 1.3 µm - 1.5 µm to about 0.7 µm - 0.9 µm and / or by about 30% - 50% in the X-direction. In the Y-direction of Fig. 2A, the width of the superjunction columns 110 gradually tapers as the superjunction columns 110 approach the outer edge 108.Figure 2A illustrates regions 137 with equal doping levels. These regions represent the relative dopant concentration of the superjunction columns 110. Thus, the region 137 with equal doping levels within a center of the semiconductor body 102 corresponds to the region where the superjunction columns 110 are most highly doped, followed by an outer region 137 with equal doping levels where the dopant concentration of the superjunction columns 110 is reduced. As shown, the region 137 with equal doping levels can be configured as closed rings surrounding the active region 116. Figure 2B shows a possible geometry of the regions 137 with equal doping levels at a corner of the semiconductor body 102.As shown in the figure, the regions 137 with the same dopant level can be arranged with linear rows and columns perpendicular to the rows, with gradual transitions between the rows and columns at the corner of the semiconductor body 102. Alternatively, the regions 137 with the same dopant level can have other types of gradual transitions, such as radial or curved transitions. This can be used to achieve charge reduction near the corner of the semiconductor body. Figure 3 shows a graph illustrating the dopant concentrations of two different superjunction semiconductor devices. Curve 201 shows a dopant profile of one superjunction semiconductor device, where the dopant concentration decreases in the superjunction columns 110 at the outer edge of the active region 116. Curve 203 shows a dopant profile of one superjunction semiconductor device 100, where the decrease in dopant concentration occurs only in the superjunction columns 110 located outside the active region 116. The local peaks in each curve correspond to the dopant concentrations observed in the columns 112 of the first conductivity type or the columns 114 of the second conductivity type.As can be seen, the device represented by curve 201 contains far fewer superjunction columns 110 in the peripheral region 126 than the device represented by curve 203, resulting in a larger proportional proportion of the chip being dedicated to the active transistor area. Advantageously, due to the earlier reduction of the dopant concentrations within the active region 116, a similar edge termination effect is achieved, and the two devices can have a comparable voltage rating. Figure 4 shows a detailed cross-sectional view of a superjunction semiconductor device 100 according to one embodiment. The semiconductor device 100 of Figure 4 is a superjunction device with multiple superjunction columns 110 alternating along a lateral direction of the semiconductor body 102 in a conductivity type. The superjunction structure can be configured to have a second cell region 136 that overlaps with an outer part of the active region 116 and has superjunction columns 110 with a lower dopant concentration than the superjunction columns 110 in the first cell region 134, as described above with reference to Figure 1. The semiconductor device 100 has a groove 142 formed in the main surface 104 of the semiconductor body 102. This groove 142 is formed in the peripheral region 126 and can extend to the outer edge 108 (as shown in Fig. 1) of the semiconductor body 102. The groove 142 is filled with a dielectric material. For example, the groove 142 can be filled with a thermally grown oxide or nitride, e.g., SiO₂, SiN, SiOXNY, etc. The semiconductor device 100 has a body contact region 144 that extends from the main surface 104 into the semiconductor body 102 and is located between the active region 116 and the groove 142. The body contact area 144 is an area of ​​a second conductivity type (e.g. p-type) that establishes contact with the columns 114 of the second conductivity type from the peripheral area 126.The semiconductor device 100 has a body contact 146, which is formed on the main surface 104 of the semiconductor body 102 and is in low-resistance contact with the body contact area 144. This body contact 146 can, for example, be connected to a source / emitter potential. The semiconductor device 100 is configured such that the width W1 of an inner section of the peripheral region 126 is less than or equal to twice the cell pitch CP of the superjunction structure. The inner section refers to a portion of the peripheral region 126 that accommodates non-transistor superjunction unit cells, i.e., superjunction unit columns that do not form part of active transistors closest to the active region 116. Instead, these superjunction unit cells form part of a structure that dissipates charge carriers of the second conductivity type during a switching operation through the body contact 146. The inner section of the peripheral region 126 extends from the center of the gate trench of an outermost transistor cell of the active region 116 to a lower corner of the slot 142.The cell pitch CP refers to a separation distance between immediately adjacent superjunction columns 110 of the same doping type in the superjunction structure. Thus, each of the columns 112 of the first conductivity type is separated from immediately adjacent columns 112 of the first conductivity type by an amount equal to twice the cell pitch CP. According to one embodiment, the width W1 of the inner section of the peripheral region 126 can be between one and two times the cell pitch CP of the superjunction structure. In particular, the width W1 of the inner section of the peripheral region 126 is approximately 1.5 times the cell pitch CP of the superjunction structure. From a top-down perspective, the groove 142 can form a rounded transition at a corner of a semiconductor device 100 in a similar manner to the region 137 described above with reference to Fig. 2, with the same doping level. According to one embodiment, from a top-down perspective of the semiconductor device, the radius of the groove 142, i.e., the radius of the rounded transition, is between one and two times the cell pitch CP of the superjunction structure. In particular, the radius of the groove 142 is In a superjunction structure, very high current densities are generated in the peripheral region during each switching operation due to the high output charge from the peripheral region. In particular, the secondary conductance current (e.g., hole current) must flow from the peripheral region 126 to the outermost body contact 146 on the surface. This is problematic. On the one hand, the high current density always causes high ohmic power dissipation, which reduces the switching efficiency of the transistor. On the other hand, a high current density creates a high voltage drop, which can control a parasitic NPN bipolar transistor between the source / emitter, body, and drain / collector. This can create a latch-up state, which must be avoided because it can damage the transistor under certain operating conditions. In a superjunction power semiconductor device 100 with the narrow separation distance between the active region 116 and the slot 142, as described above, the aforementioned parasitic NPN transistor can be designed to be more robust, since the distance between the source / emitter end and the body contact 146 can be chosen to be smaller. The body contact region 144 can have a higher dopant concentration, so that the effective base-emitter voltage is lower at the same current. Due to modern lithography techniques, charge reduction within the active cell region, as described above, can be carried out and can be more pronounced in the peripheral region 126, resulting in a device with a significantly lower output charge in the peripheral region 126. Furthermore, the width of the outer body contact 146 can advantageously be made smaller.According to one embodiment, the width of the body contact 146 in contact with the body contact area 144 of the inner section of the peripheral region 126 is the same as that of each of the inner body contacts used in the active transistor cells. That is, the body contact hole 146 can be manufactured at the minimum size corresponding to the contact hole used in the active region 116. The source / collector implant can be omitted from the outermost gate-trough sidewall to improve the robustness of the parasitic NPN transistor. Although the present revelation is not limited to this, the following numbered examples illustrate one or more aspects of the revelation. Example 1. A semiconductor device comprising: a semiconductor body having a main face, a back face, and an outer edge extending between the main face and the back face; a superjunction structure having multiple superjunction columns alternating along a lateral direction of the semiconductor body in a conductivity type; an active region having multiple transistor cells, each of the transistor cells configured to control a vertical current flowing through one of the superjunction columns;and a peripheral region that laterally separates the active region from the outer edge, wherein the peripheral region is free of the transistor cells, wherein the superjunction structure comprises a first cell region and a second cell region, wherein the first cell region is arranged within a central part of the active region, and wherein the second cell region overlaps at least partially with an outer part of the active region adjacent to the peripheral region, and wherein the superjunction columns in the second cell region have a lower dopant concentration than the superjunction columns in the first cell region. Example 2. Semiconductor device according to Example 1, wherein the superjunction structure has several superjunction unit cells formed by adjacent pairs of the superjunction columns, and wherein the second cell region has at least one of the superjunction unit cells that overlaps with the active region. Example 3. Semiconductor device according to Example 2, wherein the second cell region has no more than three of the superjunction unit cells that overlap with the active region. Example 4. Semiconductor device according to Example 2, wherein in the first cell region the dopant concentration of each of the superjunction unit cells is essentially the same. Example 5. Semiconductor device according to Example 1, wherein in the second cell region the dopant concentration of each of the superjunction columns decreases in the lateral direction towards the outer edge relative to a directly laterally adjacent superjunction column. Example 6. Semiconductor device according to Example 1, wherein the second cell region consists of several of the superjunction unit cells, and wherein in the second cell region a dopant concentration of each superjunction unit cell decreases in the lateral direction towards the outer edge relative to a directly laterally adjacent superjunction unit cell. Example 7. Semiconductor device according to Example 1, wherein the second cell region overlaps with the peripheral region. Example 8. Semiconductor device according to Example 7, wherein in the second cell region the dopant concentration of each of the superjunction columns decreases in the lateral direction towards the outer edge relative to a directly laterally adjacent superjunction column. Example 9. Semiconductor device according to Example 1, wherein, from a top-down perspective of the semiconductor body, a dopant concentration of the superjunction columns is defined by regions with the same dopant level, and wherein the regions with the same dopant level form a closed ring that completely surrounds the active region. Example 10. Semiconductor device according to Example 9, wherein, from the top-down perspective of the semiconductor body, each of the regions with the same doping level within the active region forms corners perpendicular to each other. Example 11. Semiconductor device according to Example 1, wherein at an outer boundary of the active region an outermost column of the second conductivity type is actively conductive in both directions. Example 12. Semiconductor device according to Example 1, wherein in the peripheral region the superjunction columns are arranged such that they maintain a constant lateral electric field. Example 13. Semiconductor device according to Example 1, wherein the peripheral region has an intrinsically or very lightly doped outer region located between the superjunction structure and the outer edge of the semiconductor body. Example 14. Semiconductor device comprising: a semiconductor body having a main face, a back face, and an outer perimeter extending between the main face and the back face; a superjunction structure having multiple superjunction columns alternating along a lateral direction of the semiconductor body in a conductivity type; an active region having multiple transistor cells, each of the transistor cells configured to control a vertical current flowing through one of the superjunction columns; a peripheral region separating the active region laterally from the outer perimeter, the peripheral region being free of transistor cells;and a groove formed in the main surface of the semiconductor body in the peripheral region, the groove being filled with a dielectric material, wherein the width of an inner section of the peripheral region is less than or equal to twice the cell pitch of the superjunction structure, the cell pitch being a separation distance between immediately adjacent superjunction columns of the same doping type in the superjunction structure, and the width of the inner section of the peripheral region being a lateral distance from the center of a gate trench of an outermost transistor cell of the active region to a lower corner of the groove. Example 15. Semiconductor device according to Example 14, wherein the width of the inner section of the peripheral region is between one and two times the cell pitch of the superjunction structure. Example 16. Semiconductor device according to Example 14, wherein the inner section of the peripheral region has a body contact region extending from the main surface between the outermost of the superjunction columns of the active region and the lower corner of the groove, wherein the body contact region is a highly doped region of a second conductivity type. Example 17. Semiconductor device according to Example 16, wherein the semiconductor device has several inner body contacts within the active region and a first outer body contact located adjacent to the outermost of the superjunction columns, wherein the first outer body contact forms a low-resistance connection with the body contact region and wherein a width of the first outer body contact is equal to a width of each of the inner body contacts. Example 18. Semiconductor device according to Example 17, wherein a transistor cell of the outermost of the superjunction columns has only one source region which is located on an inside of the transistor cell opposite the peripheral region. Example 19. Semiconductor device according to Example 17, wherein the superjunction structure has a first cell region and a second cell region, wherein the superjunction columns in the second cell region have a lower dopant concentration than the superjunction columns in the first cell region, wherein the first cell region is arranged within a central part of the active region, wherein the second cell region overlaps at least partially with an outer part of the active region adjacent to the peripheral region. Example 20. Semiconductor device according to Example 19, wherein in the second cell region a dopant concentration of each of the superjunction columns decreases in a lateral direction towards the outer edge relative to a directly laterally adjacent superjunction column. Example 21. Semiconductor device according to Example 20, wherein the second cell region overlaps with the inner section of the peripheral region. Example 22. Semiconductor device according to Example 14, wherein, from a top-down perspective, the slot has a radius, and wherein the radius is less than or equal to twice the cell pitch of the superjunction structure. The present description refers to a "first" and a "second" conductivity type of dopants with which semiconductor regions are doped. The first conductivity type can be n-type and the second conductivity type can be p-type, or vice versa. As is generally known, depending on the doping type or the polarity of the source and drain regions, insulated-gate field-effect transistors (IGFETs), such as metal-oxide-semiconductor field-effect transistors (MOSFETs), can be n-channel or p-channel MOSFETs. For example, in an n-channel MOSFET, the source and drain regions are doped with n-type dopants. In a p-channel MOSFET, the source and drain regions are doped with p-type dopants. As is clearly understood, in the context of this description, the doping types can be reversed.When a specific current path is described using directional language, this description should be understood to indicate only the path and not the polarity of the current flow, i.e., whether the current flows from source to drain or vice versa. The figures may include polarity-sensitive components, such as diodes. As is clear, the specific arrangement of these polarity-sensitive components is given as an example and can be reversed to achieve the described functionality, depending on whether the first conductivity type signifies an n-type or a p-type. Spatially relative terms such as "below," "under," "lower," "above," "upper," and the like are used to simplify the description and to explain the positioning of one element relative to another. These terms are intended to encompass different orientations of the structural element in addition to those shown in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe different elements, areas, sections, etc., and are not intended to be restrictive. The same terms refer to the same elements throughout the description. As used herein, the terms "have," "contain," "include," and the like are open terms that indicate the presence of the specified elements or features but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include both the plural and the singular unless the context clearly indicates otherwise. Considering the above range of variations and applications, it is understood that the present invention is neither limited by the foregoing description nor by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents. QUOTES INCLUDED IN THE DESCRIPTION This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature US 10,084,038B2

[0009] US 10,468,479B2

[0009] US 11,211,483

[0009]

Claims

Semiconductor device comprising: a semiconductor body (102) having a main face (104), a back face (106) and an outer edge (108) extending between the main face (104) and the back face (106); a superjunction structure comprising multiple superjunction columns (110) alternating along a lateral direction of the semiconductor body (102) in a conductivity type; an active region (116) comprising multiple transistor cells, each transistor cell configured to control a vertical current flowing through one of the superjunction columns (110);and a peripheral region (126) that laterally separates the active region (116) from the outer edge (108), wherein the peripheral region (126) is free of the transistor cells, wherein the superjunction structure has a first cell region (134) and a second cell region (136), wherein the first cell region (134) is arranged within a central part of the active region (116), and wherein the second cell region (136) overlaps at least partially with an outer part of the active region (116) that borders the peripheral region (126), and wherein the superjunction columns (110) in the second cell region (136) have a lower dopant concentration than the superjunction columns (110) in the first cell region (134). Semiconductor device according to claim 1, wherein the superjunction structure comprises several superjunction unit cells formed by adjacent pairs of the superjunction columns (110), and wherein the second cell region (136) comprises at least one of the superjunction unit cells that overlaps with the active region (116). Semiconductor device according to claim 2, wherein the second cell region (136) has no more than three of the superjunction unit cells that overlap with the active region (116). Semiconductor device according to claim 2 or 3, wherein in the first cell region (134) the dopant concentration of each of the superjunction unit cells is substantially the same. Semiconductor device according to one of claims 1 to 4, wherein in the second cell region (136) a dopant concentration of each of the superjunction columns (110) decreases relative to a directly laterally adjacent superjunction column in the lateral direction towards the outer edge (108). Semiconductor device according to one of claims 1 to 4, wherein the second cell region (136) consists of several of the superjunction unit cells, and wherein in the second cell region (136) a dopant concentration of each superjunction unit cell relative to a directly laterally adjacent superjunction unit cell decreases in the lateral direction towards the outer edge (108). Semiconductor device according to one of claims 1 to 6, wherein the second cell region (136) overlaps with the peripheral region (126). Semiconductor device according to claim 7, wherein in the second cell region (136) a dopant concentration of each of the superjunction columns (110) decreases relative to a directly laterally adjacent superjunction column in the lateral direction towards the outer edge (108). Semiconductor device according to one of claims 1 to 8, wherein, from a top-view perspective of the semiconductor body (102), a dopant concentration of the superjunction columns (110) is defined by regions (137) with the same dopant level, and wherein the regions (137) with the same dopant level form a closed ring that completely surrounds the active region (116). Semiconductor device according to claim 9, wherein, from the top view perspective of the semiconductor body (102), each of the regions (137) with the same doping level within the active region (116) forms corners perpendicular to each other. Semiconductor device according to one of claims 1 to 10, wherein at an outer boundary of the active region (116) an outermost column of the second conductivity type is actively conductive in both directions. Semiconductor device according to one of claims 1 to 11, wherein in the peripheral region (126) the superjunction columns (110) are arranged such that they maintain a constant lateral electric field. Semiconductor device according to one of claims 1 to 12, wherein the peripheral region (126) has an intrinsically or very lightly doped outer region arranged between the superjunction structure and the outer edge (108) of the semiconductor body (102). Semiconductor device comprising: a semiconductor body (102) having a main face (104), a back face (104, 106) and an outer edge face (108) extending between the main face (104) and the back face (104, 106); a superjunction structure comprising multiple superjunction columns (110) alternating along a lateral direction of the semiconductor body (102) in a conductivity type; an active region (116) comprising multiple transistor cells, each of the transistor cells configured to control a vertical current flowing through one of the superjunction columns (110); a peripheral region (126) that laterally separates the active region (116) from the outer edge face (108), the peripheral region (126) being free of the transistor cells;and a groove (142) formed in the main surface (104) of the semiconductor body (102) in the peripheral region (126), wherein the groove (142) is filled with a dielectric material, wherein a width of an inner section of the peripheral region (126) is less than or equal to twice a cell pitch of the superjunction structure, wherein the cell pitch is a separation distance between immediately adjacent superjunction columns (110) of the same doping type in the superjunction structure, and wherein the width of the inner section of the peripheral region (126) is a lateral distance from a center of a gate trench of an outermost transistor cell of the active region (116) to a lower corner of the groove (142). Semiconductor device according to claim 14, wherein the width of the inner section of the peripheral region (126) is between one and two times the cell pitch of the superjunction structure. Semiconductor device according to claim 14 or 15, wherein the inner section of the peripheral region (126) has a body contact region (144) extending from the main surface (104) between the outermost of the superjunction columns (110) of the active region (116) and the lower corner of the groove (142), wherein the body contact region (144) is a highly doped region of a second conductivity type. Semiconductor device according to claim 16, wherein the semiconductor device has several inner body contacts within the active region (116) and a first outer body contact which is arranged adjacent to the outermost of the superjunction columns (110), wherein the first outer body contact forms a low-resistance connection with the body contact region (144) and wherein a width of the first outer body contact is equal to a width of each of the inner body contacts. Semiconductor device according to claim 17, wherein a transistor cell of the outermost of the superjunction columns (110) has only one source region which is arranged on an inside of the transistor cell opposite the peripheral region (126). Semiconductor device according to claim 17 or 18, wherein the superjunction structure comprises a first cell region (134) and a second cell region (136), wherein the superjunction columns (110) in the second cell region (136) have a lower dopant concentration than the superjunction columns (110) in the first cell region (134), wherein the first cell region (134) is arranged within a central part of the active region (116), wherein the second cell region (136) overlaps at least partially with an outer part of the active region (116) adjacent to the peripheral region (126). Semiconductor device according to claim 19, wherein in the second cell region (136) a dopant concentration of each of the superjunction columns (110) decreases relative to a directly laterally adjacent superjunction column in a lateral direction towards the outer edge (108). Semiconductor device according to claim 20, wherein the second cell region (136) overlaps with the inner section of the peripheral region (126). Semiconductor device according to one of claims 14 to 21, wherein, from a top view perspective, the groove (142) has a radius, and wherein the radius is less than or equal to twice the cell pitch of the superjunction structure.

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