A semiconductor structure and a method of fabricating the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a cell region and a terminal region. The preparation method comprises the following steps: providing a substrate; forming an epitaxial layer on one side of the substrate; forming a plurality of spaced shielding regions in the epitaxial layer of the cell region; forming a first hard mask layer on the side of the epitaxial layer away from the substrate, wherein the first hard mask layer in the cell region is provided with a plurality of first openings, and the gap between the first opening in the substrate and the adjacent shielding region in the orthogonal projection of the substrate is overlapped in the orthogonal projection of the substrate; based on the first opening, sequentially forming a junction field effect transistor region well region and a source region in the epitaxial layer of the cell region; forming a second opening in the first opening, and the orthogonal projection of the second opening in the substrate is smaller than the orthogonal projection of the first opening in the substrate; and forming a groove in the epitaxial layer based on the second opening. The semiconductor structure and the preparation method thereof can significantly reduce the number of mask uses, simplify the process flow and reduce the manufacturing cost.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) have become an important development direction for next-generation power semiconductor devices due to their advantages such as high breakdown voltage, large on-current, fast switching speed, low power loss, and good high-temperature stability. Among them, trench-type silicon carbide MOSFETs have attracted widespread attention in high-power, high-frequency applications due to their smaller on-resistance and parasitic capacitance.

[0003] However, compared to silicon-based devices, silicon carbide substrates and epitaxial materials are more expensive, making SiC MOSFETs significantly more expensive than silicon-based devices of the same voltage level, thus limiting their market competitiveness in large-scale applications. Besides material costs, the complexity of the manufacturing process is also a crucial factor affecting cost.

[0004] In the existing technology, the fabrication of trench silicon carbide MOSFETs usually requires multiple ion implantation and trench etching processes. Each functional region, such as the shielding region, JFET (junction field effect) region, well region, source region, etc., as well as the trench structure, is often patterned using different masks. This results in a large number of masks, complex process steps, and high wafer fabrication costs, which is not conducive to reducing the overall manufacturing cost of the device.

[0005] Therefore, how to effectively reduce the manufacturing cost of trench silicon carbide MOSFETs by optimizing the process flow, reducing the number of masks used, and simplifying the manufacturing steps while ensuring device performance has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problems of large number of masks, complex process steps, and high manufacturing costs in existing technologies.

[0007] To achieve the above objectives, this application provides a method for fabricating a semiconductor structure, the semiconductor structure comprising a cell region and a terminal region, the fabrication method comprising the following steps:

[0008] Provide a substrate of the first conductivity type:

[0009] An epitaxial layer of a first conductivity type is formed on one side of the substrate;

[0010] A plurality of spaced-apart shielding regions of the second conductivity type are formed within the epitaxial layer of the cell region;

[0011] A first hard mask layer is formed on the side of the epitaxial layer away from the substrate, wherein the first hard mask layer located in the cell region is provided with a plurality of first openings, and the orthographic projection of the first opening on the substrate overlaps with the gap between the adjacent shielding regions on the orthographic projection of the substrate.

[0012] Based on the first opening, a junction field-effect transistor region of the first conductivity type, a well region of the second conductivity type, and a source region of the first conductivity type are sequentially formed in the epitaxial layer of the cell region.

[0013] A second opening is formed within the first opening, wherein the orthographic projection of the second opening onto the substrate is smaller than the orthographic projection of the first opening onto the substrate.

[0014] A trench is formed in the epitaxial layer based on the second opening.

[0015] In one embodiment, the step of sequentially forming a junction field-effect transistor region of a first conductivity type, a well region of a second conductivity type, and a source region of a first conductivity type within the epitaxial layer of the cell region based on the first opening includes:

[0016] Based on the first opening, ion implantation of a first conductivity type is performed in the epitaxial layer to form the junction field-effect transistor region;

[0017] Based on the first opening, ion implantation of a second conductivity type is performed in the junction field-effect transistor region to form the well region;

[0018] Based on the first opening, ion implantation of a first conductivity type is performed on the surface of the well region to form the source region.

[0019] In one embodiment, prior to performing ion implantation of a first conductivity type within the surface layer of the well region based on the first opening to form the source region, the method further includes:

[0020] A sacrificial oxide layer is formed on the side of the epitaxial layer away from the substrate, the sacrificial oxide layer covering the bottom of the first hard mask layer and the first opening;

[0021] The step of implanting ions of a first conductivity type into the surface layer of the well region based on the first opening to form the source region further includes:

[0022] The source region is formed on the surface of the well region based on the sacrificial oxide layer.

[0023] In one embodiment, forming a second opening within the first opening includes:

[0024] An etching buffer layer is formed to cover the sacrificial oxide layer and fill the first opening, the etching buffer layer having a groove located within the first opening;

[0025] Remove the sacrificial oxide layer and the etching buffer layer outside the first opening and at the bottom of the groove to form the second opening.

[0026] In one embodiment, after forming the trench in the epitaxial layer based on the second opening, the method further includes:

[0027] Remove the sacrificial oxide layer, the etching buffer layer, and the first hard mask layer.

[0028] In one embodiment, forming a first hard mask layer on the side of the epitaxial layer away from the substrate includes:

[0029] A first hard mask material layer is formed on the side of the epitaxial layer away from the substrate in the cell region and the terminal region;

[0030] The first hard mask material layer located in the cell region is patterned so that the orthographic projection of the patterned first hard mask material layer on the substrate overlaps with the orthographic projection of the shielding area on the substrate, and a plurality of first openings are formed in the first hard mask layer located in the cell region, thereby forming the first hard mask layer.

[0031] In one embodiment, forming a plurality of spaced-apart shielding regions of a second conductivity type within the epitaxial layer of the cell region includes:

[0032] A second hard mask is formed on the side of the epitaxial layer away from the substrate, and the second hard mask has a plurality of third openings;

[0033] Based on the third opening, ion implantation of the second conductivity type is performed on the epitaxial layer to form a plurality of spaced shielding regions in the epitaxial layer;

[0034] Remove the second hard mask layer.

[0035] In one embodiment, forming a second hard mask on the side of the epitaxial layer away from the substrate includes:

[0036] A second hard mask material layer is formed on the side of the epitaxial layer away from the substrate in the cell region and the terminal region;

[0037] The second hard mask material layer located in the cell region is patterned so that a plurality of the third openings are formed in the patterned second hard mask material layer, thereby forming the second hard mask layer.

[0038] In one embodiment, in the thickness direction of the substrate, the depth of the trench is not greater than the depth of the junction field-effect transistor region and not less than the depth of the well region, and the depth of the junction field-effect transistor region is not greater than the depth of the shielding region.

[0039] This application also provides a semiconductor structure, which is prepared by the semiconductor structure preparation method described in any of the above embodiments.

[0040] The aforementioned semiconductor structure and its fabrication method have the following beneficial effects: By forming a first hard mask layer on the side of the epitaxial layer away from the substrate, the first hard mask layer has multiple first openings in the cell region, and the orthographic projection of the first opening onto the substrate overlaps with the orthographic projection of the gap between two adjacent shielding regions onto the substrate; based on the first openings, a junction field-effect transistor region, a well region, and a source region are sequentially formed in the epitaxial layer of the cell region; a second opening is formed within the first opening, and the orthographic projection of the second opening onto the substrate is smaller than the orthographic projection of the first opening onto the substrate; based on the second opening, a trench is formed in the epitaxial layer. That is, by forming the junction field-effect transistor region, well region, source region, and trench based on a single first hard mask layer, the number of masks used is significantly reduced, the process flow is simplified, the number of photolithography alignments is reduced, and manufacturing costs are lowered, while ensuring the relative positional accuracy between functional regions and improving the consistency and reliability of the device structure. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0043] Figure 2 This is a schematic cross-sectional view of the structure obtained after forming an epitaxial layer in a semiconductor structure fabrication method provided in one embodiment.

[0044] Figure 3 This is a schematic cross-sectional view of the structure obtained after forming the second hard mask layer in a semiconductor structure fabrication method provided in one embodiment.

[0045] Figure 4 This is a schematic cross-sectional view of the structure obtained after forming a shielding region in a semiconductor structure fabrication method provided in one embodiment.

[0046] Figure 5 This is a schematic cross-sectional view of the structure obtained after forming the first hard mask layer in a semiconductor structure fabrication method provided in one embodiment.

[0047] Figure 6 This is a schematic cross-sectional view of the structure obtained after forming the junction field-effect transistor region and the well region in a semiconductor structure fabrication method provided in one embodiment.

[0048] Figure 7 This is a schematic cross-sectional view of the structure obtained after forming a sacrificial oxide layer in a semiconductor structure fabrication method provided in one embodiment.

[0049] Figure 8 This is a schematic cross-sectional view of the structure obtained after forming the source region in a semiconductor structure fabrication method provided in one embodiment.

[0050] Figure 9 This is a schematic cross-sectional view of the structure obtained after forming an etching buffer layer in a semiconductor structure fabrication method provided in one embodiment.

[0051] Figure 10 This is a schematic cross-sectional view of the structure obtained after forming the second opening in a semiconductor structure fabrication method provided in one embodiment.

[0052] Figure 11 This is a schematic cross-sectional view of the structure obtained after forming a trench in a semiconductor structure fabrication method provided in one embodiment.

[0053] Figure 12 This is a schematic cross-sectional view of the structure obtained after removing the first hard mask layer, the functional oxide layer and the etching buffer layer in a semiconductor structure fabrication method provided in one embodiment.

[0054] Explanation of reference numerals in the attached figures:

[0055] 1-Substrate, 11-Epipolar layer, 2-Shielding region, 3-First hard mask layer, 31-First opening, 32-Second opening, 4-Junction field-effect transistor region, 5-Well region, 6-Source region, 7-Trench, 8-Sacrificial oxide layer, 9-Etching buffer layer, 91-Groove, 10-Second hard mask layer, 101-Third opening, 100-Cell region, 200-Termination region. Detailed Implementation

[0056] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0058] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0059] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0060] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0061] Please see Figure 1 This application provides a method for fabricating a semiconductor structure, the semiconductor structure including a cell region 100 and a terminal region 200, the fabrication method including the following steps:

[0062] Step S1: Provide a substrate 1 of a first conductivity type;

[0063] Step S2: Form an epitaxial layer 11 of the first conductivity type on one side of the substrate 1;

[0064] Step S3: A plurality of spaced shielding regions 2 of the second conductivity type are formed in the epitaxial layer 11 of the cell region 100;

[0065] Step S4: A first hard mask layer 3 is formed on the side of the epitaxial layer 11 away from the substrate 1. The first hard mask layer 3 has a plurality of first openings 31 in the cell region 100. The orthographic projection of the first opening 31 on the substrate 1 overlaps with the orthographic projection of the gap between two adjacent shielding regions 2 on the substrate 1.

[0066] Step S5: Based on the first opening 31, a junction field-effect transistor region (JFET region) of the first conductivity type, a well region of the second conductivity type, and a source region of the first conductivity type are sequentially formed in the epitaxial layer 11 of the cell region 100.

[0067] Step S6: A second opening 32 is formed in the first opening 31, and the orthographic projection of the second opening 32 on the substrate 1 is smaller than the orthographic projection of the first opening 31 on the substrate 1.

[0068] Step S7: Based on the second opening 32, a trench 7 is formed in the epitaxial layer 11.

[0069] In the above example, a first hard mask layer 3 is formed on the side of the epitaxial layer 11 away from the substrate 1. The first hard mask layer 3 has multiple first openings 31 in the cell region 100. The orthographic projection of the first opening 31 on the substrate 1 overlaps with the orthographic projection of the gap between two adjacent shielding regions 2 on the substrate 1. Based on the first openings 31, a junction field-effect transistor region 4, a well region 5, and a source region 6 are sequentially formed in the epitaxial layer 11 of the cell region 100. A second opening 32 is formed in the first openings 31. The orthographic projection of the second opening 32 on the substrate 1 is smaller than the orthographic projection of the first opening 31 on the substrate 1. Based on the second opening 32, a trench 7 is formed in the epitaxial layer 11. That is, the junction field-effect transistor region 4, the well region 5, the source region 6, and the trench 7 are formed based on a single first hard mask layer 3, which significantly reduces the number of masks used, simplifies the process flow, reduces the number of photolithography alignments and manufacturing costs, while ensuring the relative positional accuracy between the functional regions and improving the consistency and reliability of the device structure.

[0070] Specifically, please refer to Figure 2 Steps S1 to S2 are performed to provide a substrate 1 of a first conductivity type; an epitaxial layer 11 of the first conductivity type is formed on one side of the substrate 1.

[0071] In this application, the semiconductor structure includes a cell region 100 and a termination region 200. Generally, the cell region 100 and the termination region 200 can be divided in the design of the device layout or before epitaxial growth to form power element units and termination structures, respectively.

[0072] For example, the material of substrate 1 may include silicon carbide (SiC), silicon (Si), etc. Substrate 1 is used to support the growth of epitaxial layer and form device structure. The size of substrate 1 can be selected according to the actual device power level and application requirements, and is not limited here.

[0073] In one embodiment, such as Figure 2 As shown, the method for forming the epitaxial layer 11 includes epitaxy, chemical vapor deposition (CVD) or other suitable methods. The epitaxial layer 11 is used to provide an active layer structure for a semiconductor device. The material of the epitaxial layer 11 may be the same as or different from that of the substrate 1 to meet device performance requirements.

[0074] Specifically, please refer to Figures 3 to 4 Step S3 is executed to form a plurality of spaced shielding regions 2 of the second conductivity type within the epitaxial layer 11 of the cell region 100.

[0075] In one embodiment, such as Figures 3 to 4 As shown, a plurality of second-conductivity shielding regions 2 are formed at intervals within the epitaxial layer 11 of the cell region 100, including:

[0076] A second hard mask layer 10 is formed on the side of the epitaxial layer 11 away from the substrate 1, and a plurality of third openings 101 are provided in the second hard mask layer 10;

[0077] Exemplarily, a second hard mask layer 10 is formed on the side of the epitaxial layer 11 away from the substrate 1, including:

[0078] A second hard mask material layer (not shown) is formed on the side of the epitaxial layer 11 away from the substrate 1. The method for forming the second hard mask material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods. The material of the second hard mask material layer may include polysilicon, silicon nitride or other suitable materials.

[0079] The second hard mask material layer is patterned to obtain the third opening 101, wherein the patterning of the second hard mask material layer includes:

[0080] A second photoresist layer (not shown) is formed on the side of the second hard mask material layer away from the substrate 1.

[0081] The second photoresist layer is patterned to obtain a second patterned photoresist layer;

[0082] Based on the second patterned photoresist layer, the second hard mask material layer of the cell region 100 is etched; the method for etching the second hard mask material layer includes dry etching, wet etching or other suitable methods, and the third opening 101 is the injection region of the shielding region 2.

[0083] Based on the third opening 101, ion implantation of the second conductivity type is performed on the epitaxial layer 11 to form a plurality of spaced shielding regions 2 in the epitaxial layer 11. The shielding regions 2 are heavily doped regions, and the doping depth and doping concentration of the shielding regions 2 can be selected according to the actual situation. The shielding regions 2 are used to improve the device's breakdown voltage and conduction performance.

[0084] In one embodiment, after performing ion implantation of a second conductivity type on the epitaxial layer 11 based on the third opening 101 to form a plurality of spaced-apart shielding regions 2 in the epitaxial layer 11, the method further includes:

[0085] Remove the second hard mask layer 10 by means of dry etching, wet etching, chemical mechanical polishing or other suitable methods.

[0086] Specifically, please refer to Figure 5 In step S4, a first hard mask layer 3 is formed on the side of the epitaxial layer 11 away from the substrate 1. The first hard mask layer 3 has a plurality of first openings 31 in the cell region 100. The orthographic projection of the first opening 31 on the substrate 1 overlaps with the orthographic projection of the gap between two adjacent shielding regions 2 on the substrate 1.

[0087] In one embodiment, such as Figure 5 As shown, a first hard mask layer 3 is formed on the side of the epitaxial layer 11 away from the substrate 1, comprising:

[0088] A first hard mask material layer (not shown) is formed on the side of the epitaxial layer 11 away from the substrate 1 in the cell region 100 and the terminal region 200. The method for forming the first hard mask material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods. The material of the first hard mask material layer may include polysilicon, silicon nitride or other suitable materials.

[0089] The first hard mask material layer of the cell region 100 is patterned so that the orthographic projection of the patterned first hard mask material layer on the substrate 1 overlaps with the orthographic projection of the shielding region 2, thereby forming the first hard mask layer 3, and a plurality of first openings 31 are formed in the first hard mask layer 3 of the cell region 100.

[0090] The first hard mask material layer of cell region 100 is patterned, including:

[0091] A first photoresist layer (not shown) is formed on the side of the first hard mask material layer away from the substrate 1.

[0092] The first photoresist layer is patterned to obtain the first patterned photoresist layer;

[0093] Based on the first patterned photoresist layer, the first hard mask material layer of the cell region 100 is etched; the method for etching the first hard mask material layer includes dry etching, wet etching or other suitable methods, and the first opening 31 is the implantation region of JFET region 4, well region 5 and source region 6.

[0094] Specifically, please refer to Figures 6 to 8 In step S5, based on the first opening 31, a junction field-effect transistor region 4 of the first conductivity type, a well region 5 of the second conductivity type, and a source region 6 of the first conductivity type are sequentially formed in the epitaxial layer 11 of the cell region 100.

[0095] In one embodiment, such as Figures 6 to 8 As shown, based on the first opening 31, a junction field-effect transistor region (JFET region) of the first conductivity type, a well region of the second conductivity type, and a source region of the first conductivity type are sequentially formed in the epitaxial layer 11 of the cell region 100, including:

[0096] Based on the first opening 31, ion implantation of the first conductivity type is performed in the epitaxial layer 11 to form JFET region 4; wherein, the implantation depth and doping concentration can be selected according to the actual situation and are not limited here. JFET region 4 is of medium doping type. JFET region 4 is used to form conductive channels between adjacent well regions 5 and adjust the on-resistance of the device.

[0097] Based on the first opening 31, ion implantation of the second conductivity type is performed in the JFET region 4 to form the well region 5; the implantation depth and doping concentration can be selected according to the actual situation and are not limited here. The well region 5 is of medium doping type and is used to form the channel region together with the source region 6.

[0098] Based on the first opening 31, ion implantation of the first conductivity type is performed in the surface layer of the well region 5 to form the source region 6; the implantation depth and doping concentration can be selected according to the actual situation and are not limited here. The source region 6 is heavily doped and is used as the current input terminal of the device.

[0099] In one embodiment, such as Figure 7 As shown, prior to ion implantation of a first conductivity type within the surface layer of the well region 5 based on the first opening 31 to form the source region 6, the process further includes:

[0100] A sacrificial oxide layer 8 is formed on the side of the epitaxial layer 11 away from the substrate 1, and the sacrificial oxide layer 8 also covers the first hard mask layer 3; the method of forming the sacrificial oxide layer 8 includes thermal oxidation, chemical vapor deposition or other suitable methods, and the material of the sacrificial oxide layer 8 may include silicon oxide or other suitable materials;

[0101] Furthermore, based on the first opening 31, ion implantation of a first conductivity type is performed within the surface layer of the well region 5 to form the source region 6, and the method further includes:

[0102] Based on the sacrificial oxide layer 8, the source region 6 is formed on the surface of the well region 5. By setting the sacrificial oxide layer 8, it serves two purposes: firstly, it regulates the ion implantation energy distribution, reduces implantation damage, and precisely controls the junction depth and doping profile of the source region 6; secondly, it acts as a process buffer layer, functionally decoupling the source region 6 implantation process from the subsequent trench 7 etching process under the same mask conditions. This ensures the surface quality of the source region 6 and the pattern accuracy of the trench 7, allowing multiple implantation processes and trench etching processes to share the same hard mask, thereby reducing the number of masks, simplifying the process flow, and lowering manufacturing costs.

[0103] It should be noted that during the process of ion implantation to form JFET region 4, well region 5, and source region 6, the first hard mask layer 3 is required to cover the terminal region 200 to prevent undesired doping in the terminal region 200 from affecting the breakdown voltage characteristics of the device.

[0104] The first conductivity type and the second conductivity type are opposite conductivity types. When the first conductivity type is N-type, the second conductivity type is P-type, and when the second conductivity type is N-type, the first conductivity type is P-type. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0105] Specifically, please refer to Figures 9 to 10 Step S6 is executed to form a second opening 32 within the first opening 31. The orthographic projection of the second opening 32 onto the substrate 1 is smaller than the orthographic projection of the first opening 31 onto the substrate 1.

[0106] In one embodiment, such as Figures 9 to 10 As shown, a second opening 32 is formed within the first opening 31, including:

[0107] An etching buffer layer 9 is formed to cover the sacrificial oxide layer 8 and fill the first opening 31. The etching buffer layer 9 has a groove 91 located within the first opening 31. The material of the etching buffer layer 9 may include silicon oxide, silicon nitride, or other suitable materials. The method for forming the etching buffer layer 9 may include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0108] The sacrificial oxide layer 8 and the etching buffer layer 9 outside the first opening 31 and at the bottom of the groove 91 are removed to form a second opening 32. The second opening 32 is formed in the sacrificial oxide layer 8 and the etching buffer layer 9 that are removed and located in the first opening 31. The second opening 32 penetrates the sacrificial oxide layer 8 and the etching buffer layer 9 located in the first opening 31 to expose the epitaxial layer 11. The second opening 32 is the formation area of ​​the trench 7.

[0109] By superimposing a sacrificial oxide layer 8 and an etching buffer layer 9 within the first opening 31 and then etching to shrink the opening size, the first hard mask layer 3 is shared during the etching process of forming the junction field-effect transistor region JFET region 4, well region 5, source region 6, and trench 7. This reduces the number of masks used, simplifies the process flow, and effectively reduces the manufacturing cost of the device.

[0110] Specifically, please refer to Figures 11 to 12 Step S7 is executed, and a trench 7 is formed in the epitaxial layer 11 based on the second opening 32.

[0111] In one embodiment, such as Figure 11 As shown, the trench 7 can be formed by dry etching, wet etching, or other suitable methods.

[0112] In one embodiment, in the direction perpendicular to the substrate 1, the depth of the trench 7 is not greater than the depth of the JFET region 4 and not less than the depth of the well region 5, and the depth of the JFET region 4 is not greater than the depth of the shielding region 2, so that the trench 7 is located at an appropriate position between the well region 5 and the junction field-effect transistor region JFET region 4, thereby ensuring that the trench gate device channel formation position is accurately controllable, while avoiding the trench 7 being too deep and affecting the device breakdown voltage performance, or too shallow and affecting the channel control capability.

[0113] The trench 7 is used to form the trench gate structure. Therefore, the trench 7 is located between two adjacent shielding regions 2. By precisely controlling the depth of the trench 7, the trench 7 is formed without damaging the shielding region 2, thereby ensuring the shielding performance of the shielding region 2 on the gate structure in the trench 7, and ensuring the electric field modulation capability and withstand voltage performance of the device.

[0114] In one embodiment, such as Figure 12 As shown, after forming the trench 7 in the epitaxial layer 11 based on the second opening 32, the method further includes:

[0115] The sacrificial oxide layer 8, the etching buffer layer 9, and the first hard mask layer 3 are removed. The methods for removing the sacrificial oxide layer 8, the etching buffer layer 9, and the first hard mask layer 3 include dry etching, wet etching, chemical mechanical polishing, or other suitable methods to expose the trench 7 and provide a clean process interface for subsequent formation of the trench gate structure.

[0116] In one embodiment, please refer to... Figure 12 This application also provides a semiconductor structure, which is prepared by the above-described semiconductor structure preparation method. The semiconductor structure includes a cell region 100 and a terminal region 200, comprising: a substrate 1 of a first conductivity type, an epitaxial layer 11 of a first conductivity type, a plurality of spaced shielding regions 2 of a second conductivity type, a junction field-effect transistor (JFET) region 4 of a first conductivity type, a well region 5 of a second conductivity type, a source region 6 of a first conductivity type, and a trench 7, wherein the epitaxial layer 11 is located on one side of the substrate 1; the plurality of spaced shielding regions 2 of the second conductivity type are located within the epitaxial layer 11 of the cell region 100;

[0117] In the thickness direction of substrate 1, JFET region 4, well region 5 and source region 6 are sequentially disposed in the epitaxial layer 11 of cell region 100 and located between two adjacent shielding regions 2. Specifically, JFET region 4 is located in epitaxial layer 11, well region 5 is located in JFET region 4, and source region 6 is located on the surface of well region 5. Trench 7 is located between two adjacent shielding regions 2, and the depth of trench 7 is not greater than the depth of JFET region 4 and not less than the depth of well region 5. The depth of JFET region 4 is not greater than the depth of shielding region 2.

[0118] The aforementioned semiconductor structure, based on the sharing of the same hard mask to form the junction field-effect transistor region 4, well region 5, source region 6 and trench 7, reduces the number of masks used, simplifies the process flow, significantly reduces manufacturing costs, and enhances the industrial competitiveness of silicon carbide power devices.

[0119] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0120] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0121] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0122] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The semiconductor structure includes a cell region and a terminal region, and the fabrication method includes the following steps: Provide a substrate of the first conductivity type: An epitaxial layer of a first conductivity type is formed on one side of the substrate; A plurality of spaced-apart shielding regions of the second conductivity type are formed within the epitaxial layer of the cell region; A first hard mask layer is formed on the side of the epitaxial layer away from the substrate, wherein the first hard mask layer located in the cell region is provided with a plurality of first openings, and the orthographic projection of the first opening on the substrate overlaps with the gap between the adjacent shielding regions on the orthographic projection of the substrate. Based on the first opening, a junction field-effect transistor region of the first conductivity type, a well region of the second conductivity type, and a source region of the first conductivity type are sequentially formed in the epitaxial layer of the cell region. A second opening is formed within the first opening, wherein the orthographic projection of the second opening onto the substrate is smaller than the orthographic projection of the first opening onto the substrate. A trench is formed in the epitaxial layer based on the second opening.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The method of sequentially forming a junction field-effect transistor region of a first conductivity type, a well region of a second conductivity type, and a source region of a first conductivity type within the epitaxial layer of the cell region based on the first opening includes: Based on the first opening, ion implantation of a first conductivity type is performed in the epitaxial layer to form the junction field-effect transistor region; Based on the first opening, ion implantation of a second conductivity type is performed in the junction field-effect transistor region to form the well region; Based on the first opening, ion implantation of a first conductivity type is performed on the surface of the well region to form the source region.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, Before performing ion implantation of a first conductivity type within the surface layer of the well region based on the first opening to form the source region, the method further includes: A sacrificial oxide layer is formed on the side of the epitaxial layer away from the substrate, the sacrificial oxide layer covering the bottom of the first hard mask layer and the first opening; The step of implanting ions of a first conductivity type into the surface layer of the well region based on the first opening to form the source region further includes: The source region is formed on the surface of the well region based on the sacrificial oxide layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The process of forming a second opening within the first opening includes: An etching buffer layer is formed to cover the sacrificial oxide layer and fill the first opening, the etching buffer layer having a groove located within the first opening; Remove the sacrificial oxide layer and the etching buffer layer outside the first opening and at the bottom of the groove to form the second opening.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, After forming a trench in the epitaxial layer based on the second opening, the method further includes: Remove the sacrificial oxide layer, the etching buffer layer, and the first hard mask layer.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a first hard mask layer on the side of the epitaxial layer away from the substrate includes: A first hard mask material layer is formed on the side of the epitaxial layer away from the substrate in the cell region and the terminal region; The first hard mask material layer located in the cell region is patterned so that the orthographic projection of the patterned first hard mask material layer on the substrate overlaps with the orthographic projection of the shielding area on the substrate, and a plurality of first openings are formed in the first hard mask layer located in the cell region, thereby forming the first hard mask layer.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a plurality of spaced-apart shielding regions of the second conductivity type within the epitaxial layer of the cell region includes: A second hard mask is formed on the side of the epitaxial layer away from the substrate, and the second hard mask has a plurality of third openings; Based on the third opening, ion implantation of the second conductivity type is performed on the epitaxial layer to form a plurality of spaced shielding regions in the epitaxial layer; Remove the second hard mask layer.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The step of forming a second hard mask on the side of the epitaxial layer away from the substrate includes: A second hard mask material layer is formed on the side of the epitaxial layer away from the substrate in the cell region and the terminal region; The second hard mask material layer located in the cell region is patterned so that a plurality of the third openings are formed in the patterned second hard mask material layer, thereby forming the second hard mask layer.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that, In the thickness direction of the substrate, the depth of the trench is not greater than the depth of the junction field-effect transistor region and not less than the depth of the well region, and the depth of the junction field-effect transistor region is not greater than the depth of the shielding region.

10. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the semiconductor structure preparation method as described in any one of claims 1 to 9.

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