Semiconductor structure and preparation method thereof

By using a single hard mask layer to form the junction field-effect transistor region, well region, source region, and trench in the fabrication of trench silicon carbide MOSFETs, the problems of large mask quantity and complex process are solved, manufacturing costs are reduced, and device consistency and reliability are improved.

CN122121201APending Publication Date: 2026-05-29GUANGDONG XINYUENENG SEMICON CO LTD
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Patent Information

Application Number
CN202610194873.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-02-11
Publication Date
2026-05-29

AI Technical Summary

Technical Problem

In the existing technology, the fabrication process of trench silicon carbide MOSFETs is complex and involves a large number of masks, resulting in high manufacturing costs and affecting their market competitiveness in large-scale applications.

Method used

Multiple first openings are formed on the side of the epitaxial layer away from the substrate using a single first hard mask layer. Based on these openings, a junction field-effect transistor region, a well region, and a source region are sequentially formed in the cell region. A trench is formed through a second opening, which simplifies the process flow and reduces the number of masks used.

Benefits of technology

It significantly reduces the number of masks used, simplifies the process flow, reduces the number of photolithography alignments and manufacturing costs, while ensuring the relative positional accuracy between functional areas and improving the consistency and reliability of the device structure.

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Abstract

The invention relates to a semiconductor structure and a preparation method thereof, the semiconductor structure comprises a cellular region and a terminal region, and the preparation method comprises the following steps: providing a substrate: forming an epitaxial layer on one side of the substrate; forming a plurality of shielding regions arranged at intervals in the epitaxial layer of the cellular region; a first hard mask layer is formed on the side, away from the substrate, of the epitaxial layer, the first hard mask layer located in the cellular area is provided with a plurality of first openings, and the orthographic projection of the first openings on the substrate is overlapped with the orthographic projection of gaps between the adjacent shielding areas on the substrate; based on the first opening, sequentially forming a junction field effect transistor well region and a source region in the epitaxial layer of the cellular region; forming a second opening in the first opening, wherein the orthographic projection of the second opening on the substrate is smaller than the orthographic projection of the first opening on the substrate; and forming a groove in the epitaxial layer based on the second opening. According to the semiconductor structure and the preparation method thereof, the use number of masks is remarkably reduced, the technological process is simplified, and the manufacturing cost is reduced.
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