Semiconductor devices and their fabrication methods

Abstract

This application discloses a semiconductor device and its fabrication method. The semiconductor device includes: a substrate comprising a cell region and a peripheral region; multiple bit lines located on the cell region; multiple gate structures located on the peripheral region; a first dielectric layer located between adjacent gate structures; multiple interconnects located within the first dielectric layer and connected to the substrate; multiple memory node contact structures located between adjacent bit lines; multiple capacitor structures located on the memory node contact structures; a hard mask layer covering the top surface of the interconnects; and a second dielectric layer comprising a first portion above the hard mask layer and a second portion above the memory node contact structures, wherein the vertices of the first portion and the second portion of the second dielectric layer are located at different horizontal heights. Using the above semiconductor device, the technical effect of improving semiconductor device performance is achieved without increasing process time and process cost.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of volatile memory. A DRAM device typically includes a memory region consisting of an array of memory cells and a peripheral region consisting of control circuitry. The control circuitry in the peripheral region can address each memory cell in the memory region through a complex number of column word lines and a complex number of row bit lines, and is electrically connected to each memory cell to perform data reading, writing, or erasing.

[0003] In current semiconductor manufacturing, memory cells and peripheral circuits are formed simultaneously using the same manufacturing process, which typically includes patterning. How to ensure device performance while forming memory cells and peripheral circuits through multiple processes such as patterning is a problem that urgently needs to be solved in the current technology. Summary of the Invention

[0004] This application provides a semiconductor device and its fabrication method to solve the problem in related technologies of how to ensure device performance while forming memory cells and peripheral circuits through multiple processes such as patterning.

[0005] According to one aspect of this application, a semiconductor device is provided, comprising: a substrate including a cell region and a peripheral region; a plurality of bit lines located on the cell region; a plurality of gate structures located on the peripheral region; a first dielectric layer located between adjacent gate structures; a plurality of interconnects located within the first dielectric layer and connected to the substrate; a plurality of memory node contact structures located between adjacent bit lines; a plurality of capacitor structures located on the memory node contact structures; a hard mask layer covering the top surface of the interconnects; and a second dielectric layer including a first portion located above the hard mask layer and a second portion located above the memory node contact structures, wherein the vertices of the first portion and the second portion of the second dielectric layer are located at different horizontal heights.

[0006] According to another aspect of this application, a semiconductor device is provided, comprising: a substrate including a cell region and a peripheral region; a plurality of bit lines located on the cell region; a plurality of gate structures located on the peripheral region; a first dielectric layer located between adjacent gate structures; a plurality of interconnects located within the first dielectric layer and connected to the substrate; a plurality of memory node contact structures located between adjacent bit lines; a plurality of capacitor structures located on the memory node contact structures; a hard mask layer covering the top surface of the interconnects; and a second dielectric layer covering the hard mask layer and directly contacting the top surface of the interconnects and the sidewalls of the capacitor structures.

[0007] Optionally, the vertex of the first portion of the second dielectric layer is higher than the vertex of the second portion.

[0008] Optionally, the vertices of the hard mask layer are higher than the vertices of the second portion of the second dielectric layer.

[0009] Optionally, the hard mask layer includes a first sub-mask covering the connector and a second sub-mask covering the storage node contact structure, wherein the vertices of the first sub-mask are higher than the vertices of the second sub-mask.

[0010] Alternatively, the hard mask layer is completely isolated from the top surface of the storage node contact structure.

[0011] Optionally, the semiconductor device further includes a third dielectric layer located above the gate structure and between adjacent interconnects, with the apex of the third dielectric layer lower than the apex of the hard mask layer.

[0012] Alternatively, the hard mask layer may directly contact the top surface of the connector and the sidewalls of the capacitor structure.

[0013] According to another aspect of this application, a method for fabricating a semiconductor device is also provided, comprising: providing a substrate, the substrate including a cell region and a peripheral region; forming a plurality of bit lines on the cell region, forming a plurality of gate structures on the peripheral region, and forming a first dielectric layer between adjacent gate structures; forming a plurality of interconnects located within the first dielectric layer; forming a plurality of memory node contact structures located between adjacent bit lines; forming a hard mask layer covering the top surface of the interconnects; forming a second dielectric layer and a capacitor structure, the capacitor structure being located on the memory node contact structure, the second dielectric layer covering the hard mask layer, wherein the second dielectric layer includes a first portion located above the hard mask layer and a second portion located above the memory node contact structure, the vertices of the first portion and the second portion of the second dielectric layer being located at different horizontal heights.

[0014] Optionally, the fabrication method further includes: forming a conductive material covering the bit line and gate structure; forming a patterned hard mask on the surface of the conductive material; partially removing the conductive material to form an electrical connector and a memory node contact structure; and completely removing the patterned hard mask located on the memory node contact structure to form a hard mask layer covering the top surface of the connector.

[0015] Optionally, the fabrication method further includes: forming a conductive material covering the bit line and gate structure; forming a patterned hard mask on the surface of the conductive material; partially removing the conductive material to form an electrical connector and a memory node contact structure; partially removing the patterned hard mask to form a first sub-mask covering the connector and a second sub-mask covering the memory node contact structure, wherein the vertex of the first sub-mask is higher than the vertex of the second sub-mask.

[0016] Optionally, the fabrication method further includes: forming a third dielectric layer such that the third dielectric layer is located above the gate structure and between adjacent interconnects.

[0017] According to this application, a semiconductor device includes a substrate and bit lines, a gate structure, a first dielectric layer, a connector, a hard mask layer, a second dielectric layer, a memory node contact structure, and a capacitor structure located on the substrate. Since the hard mask layer covers the top surface of the connector, and the second dielectric layer includes a first portion above the hard mask layer and a second portion above the memory node contact structure, the vertices of the first and second portions of the second dielectric layer are at different horizontal heights. The hard mask layer is formed from residual hard mask material during the formation of the connector. During the formation of the connector, the hard mask layer... Mask material is deposited simultaneously in the memory region and the surrounding region. Grooves are formed in the surrounding region through patterning and etching processes to space out multiple connectors. Grooves are also formed in the memory region at the same time. Due to the difference in materials, the depth of the grooves formed in the memory region will be greater than the depth of the grooves in the surrounding region. If the depth of the grooves in the memory region is too large, it may be over-etched to the bit line, causing a short circuit. However, in the embodiments of this application, by leaving hard mask material on the surface of the second connector, the depth of the grooves formed in the memory region can be avoided to be too large, thereby avoiding the risk of over-etching and improving the reliability of the device. Attached Figure Description

[0018] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0019] Figure 1 This is a partial cross-sectional schematic diagram of a semiconductor device according to an embodiment of this application;

[0020] Figure 2This is a cross-sectional schematic diagram of a first connector and a second connector in a semiconductor device according to an embodiment of this application;

[0021] Figure 3 This is a partial cross-sectional schematic diagram of another semiconductor device provided according to an embodiment of this application;

[0022] Figure 4 This is a process flow diagram of a semiconductor device fabrication method provided according to an embodiment of this application;

[0023] Figure 5 This is a partial cross-sectional schematic diagram of the substrate after bit lines and gate structures are formed on the substrate in a method for fabricating a semiconductor device according to an embodiment of this application.

[0024] Figure 6 Is Figure 5 A partial cross-sectional schematic diagram of the substrate after the contact hole is formed in the gate structure is shown in the figure;

[0025] Figure 7 Is Figure 6 The diagram shows a partial cross-sectional view of the substrate after the deposition of conductive material and mask material on the substrate.

[0026] Figure 8 Yes Figure 7 The diagram shows a partial cross-sectional view of the substrate after the mask material has been etched to form connectors and a hard mask layer.

[0027] Figure 9 Yes Figure 8 The diagram shows a partial cross-sectional view of the substrate after the connector is covered with dielectric material;

[0028] Figure 10 It is etching Figure 9 The diagram shows a partial cross-sectional view of the dielectric material substrate.

[0029] Figure 11 It is Figure 10 The diagram shows a partial cross-sectional view of the substrate after the formation of the second and third dielectric layers by the dielectric material.

[0030] The above figures include the following reference numerals:

[0031] 10. Substrate; 210. Gate structure; 211. First semiconductor layer; 212. First metal layer; 213. First patterned mask; 220. Bit line; 221. Second semiconductor layer; 222. Second metal layer; 223. Second patterned mask; 30. Barrier layer; 410. First sidewall; 411. First insulating layer; 412. Second insulating layer; 413. Third insulating layer; 420. Second sidewall; 421. Fourth insulating layer; 422. Fifth insulating layer; 423. Sixth insulating layer; 50. Shallow trench isolation junction Structure; 610, contact opening; 620, memory node contact opening; 70, semiconductor structure; 80, connector; 801, first connector; 802, second connector; 810, memory node contact structure; 820, contact pad; 821, conductive material; 811, first connection portion; 812, second connection portion; 90, hard mask layer; 910, mask material; 100, first dielectric layer; 101, dielectric material; 120, second dielectric layer; 130, capacitor structure; 140, support layer; 150, wire. Detailed Implementation

[0032] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0033] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0035] According to embodiments of this application, a semiconductor device is provided. Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application.

[0036] like Figure 1 As shown, the semiconductor device includes a substrate 10, a plurality of bit lines 220, a plurality of gate structures 210, a first dielectric layer 100, a plurality of connectors 80, a plurality of memory node contact structures 810, a plurality of capacitor structures 130, a hard mask layer 90, and a second dielectric layer 120, wherein: the substrate 10 includes a cell region and a peripheral region; the plurality of bit lines 220 are located on the cell region; the plurality of gate structures 210 are located on the peripheral region; the first dielectric layer 100 is located between adjacent gate structures 210; the plurality of connectors 80 are located within the first dielectric layer 100 and connected to the substrate; the plurality of memory node contact structures 810 are located between adjacent bit lines 220; the plurality of capacitor structures 130 are located on the memory node contact structures 810; the hard mask layer 90 covers the top surface of the connectors; the second dielectric layer 120 includes a first portion located above the hard mask layer 90 and a second portion located above the memory node contact structures 810, the vertices of the first portion and the second portion of the second dielectric layer 120 being located at different horizontal heights.

[0037] In the semiconductor devices described in the embodiments of this application, such as Figure 1 As shown, since the hard mask layer 90 covers the top surface of the connector 80, and the second dielectric layer includes a first part above the hard mask layer 90 and a second part above the memory node contact structure, the vertices of the first part and the second part of the second dielectric layer 120 are at different horizontal heights. The hard mask layer 90 is formed by residual hard mask material during the formation of the connector 80. During the formation of the connector 80, the hard mask material is deposited simultaneously in the memory region and the surrounding region. Grooves are formed in the surrounding region through patterning and etching processes to space out multiple connectors 80. Grooves are also formed synchronously in the memory region. Due to the difference in materials, the depth of the grooves formed in the memory region is much greater than the depth of the grooves in the surrounding region. If the depth of the grooves in the memory region is too large, it may be over-etched to the bit line 220, causing a short circuit. In this embodiment, by leaving hard mask material on the surface of the second connector 802, the depth of the grooves formed by etching in the memory region can be avoided, thereby avoiding the risk of over-etching and improving device reliability.

[0038] Furthermore, the aforementioned hard mask layer 90 can be formed by leaving hard mask material on the top surface of the aforementioned connector 80 during the semiconductor device fabrication process, while the memory node contact structure 810 and the connector 80 are formed using a patterning process. This eliminates the need for additional process steps, thereby achieving the technical effect of improving the performance of semiconductor devices without increasing process time and process cost.

[0039] In the semiconductor devices described in the embodiments of this application, such as Figure 1As shown, the semiconductor structure includes a substrate 10, on which a peripheral region B and a memory region A are defined.

[0040] The substrate 10 may have a shallow trench isolation structure (STI) 50 formed therein to define multiple active regions of memory cells in the memory region A of the substrate 10, and multiple active regions of semiconductor devices in the peripheral region B of the substrate 10. The substrate 10 may be a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, etc., and the embodiments of this application do not specifically limit it.

[0041] The aforementioned peripheral region B may be provided with peripheral circuitry for controlling the operation and input / output of memory cells in memory region A. For example, it may include drivers, buffers, amplifiers, and decoders. Peripheral region B may also include circuitry for repairing faulty memory cells, such as fuse circuits; however, this embodiment does not impose specific limitations. Memory region A may contain an array of memory cells, such as DRAM cells. According to embodiments of the present invention, the semiconductor devices of the peripheral circuitry in peripheral region B and the DRAM cells in memory region A are fabricated on substrate 10 using the same manufacturing process.

[0042] In the semiconductor devices described in the embodiments of this application, such as Figure 1 As shown, multiple bit lines 220 can be spaced apart along the x-direction on the memory region A, and multiple gate structures 210 can be spaced apart along the x-direction on the peripheral region B. The multiple gate structures 210 formed on the peripheral region B and the multiple bit lines 220 formed on the memory region A can be fabricated using the same process steps. For example, a semiconductor material layer, a metal material layer, and a hard mask material layer are sequentially formed on the peripheral region B and the memory region A of the substrate 10. The hard mask material layer is then patterned to obtain a patterned mask. The metal material layer and the semiconductor material layer are then etched sequentially using the patterned mask as a mask to transfer the pattern of the patterned hard mask material into the semiconductor material layer, thereby obtaining the gate structures 210 and bit lines 220.

[0043] The gate structure 210 may include a first semiconductor layer 211, a first metal layer 212, and a first patterned mask 213 stacked sequentially in a direction away from the substrate 10. The bit line 220 may include a second semiconductor layer 221, a second metal layer 222, and a second patterned mask 223 stacked sequentially in a direction away from the substrate 10. The materials of the first semiconductor layer 211 and the second semiconductor layer 221 may include polysilicon. The materials of the first metal layer 212 and the second metal layer 222 may include low resistivity metal materials such as aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), and titanium-aluminum alloy (TiAl). The materials of the first patterned mask 213 and the second patterned mask 223 may include any one or more of silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN), and may also include other dielectric materials. The embodiments of this application do not specifically limit the types of materials mentioned above.

[0044] It should be noted that a gate oxide layer (not shown in the figure) may also be disposed between the substrate 10 and the first semiconductor layer 211 of the gate structure 210. The material of the gate oxide layer may be silicon oxide (SiO2).

[0045] In the semiconductor devices described in the embodiments of this application, such as Figure 1 As shown, the first dielectric layer 100 is located between adjacent gate structures 210. The semiconductor device described in this embodiment may further include a barrier layer 30 located on the gate structure 210 and the first dielectric layer 100. The materials of the first dielectric layer 100 and the barrier layer 30 may include any one or more of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN), and may also include other types of dielectric materials. This embodiment does not specifically limit the materials used.

[0046] like Figure 1 As shown, the semiconductor device described in this embodiment may further include first sidewalls 410 located on both sides of the gate structure 210. Exemplarily, the first sidewalls 410 include a first insulating layer 411, a second insulating layer 412, and a third insulating layer 413 that sequentially cover the sidewalls of the gate structure 210 from the inside out.

[0047] like Figure 1 As shown, the semiconductor device described in this application embodiment may further include a second sidewall 420 located on both sides of the bit line 220. Exemplarily, the second sidewall 420 includes a fourth insulating layer 421, a fifth insulating layer 422, and a sixth insulating layer 423 that sequentially cover the sidewalls of the bit line 220 and the barrier layer 30 from the inside out.

[0048] The first sidewall 410 and the second sidewall 420 can be prepared by the same process steps, and the material of each insulating layer in the first sidewall 410 and the second sidewall 420 can be conventional insulating materials in the prior art, such as silicon oxide (SiO2). This application embodiment does not make specific limitations.

[0049] In the semiconductor devices described in the embodiments of this application, such as Figure 2 As shown, the connector 80 may include a plurality of first connectors 801 and at least one second connector 802. Each connector 80 includes a first connection portion 811 and a second connection portion 812. The first connection portion 811 is located between at least one gate structure 210 and an adjacent first dielectric layer 100. The second connection portion 812 is located on the side of the first connection portion 811 facing away from the substrate 10. The surface of the second connection portion 812 facing away from the first connection portion 811 is a first surface. The material of the connector 80 may include a metal, such as tungsten (W).

[0050] In the semiconductor devices described in the embodiments of this application, such as Figure 1 As shown, multiple memory node contact structures 810 are located between adjacent bit lines 220. Each memory node contact structure 810 includes a semiconductor structure 70 located between adjacent bit lines 220 and contact pads 820 located on the semiconductor structure 70. The semiconductor structure 70 may be made of polysilicon, and the contact pads 820 may be made of a metal, such as tungsten (W). For example, the semiconductor structure 70 fills the bottom of the memory node contact opening 620 between adjacent bit lines 220, a portion of the contact pads 820 fills the top of the semiconductor structure 70, and another portion of the contact pads 820 is located outside the memory node contact opening, covering a portion of the top surface of the bit line.

[0051] In the semiconductor devices described in the embodiments of this application, such as Figure 1 As shown, the second dielectric layer 120 includes a first portion located above the hard mask layer 90 and a second portion located above the memory node contact structure 810. The vertices of the first portion and the second portion of the second dielectric layer 120 are located at different horizontal heights. The hard mask layer 90 can be formed by leaving hard mask material on the top surface of the connector while removing the hard mask material on the top surface of the memory node contact structure 810 during the patterning process in the semiconductor device fabrication process. The material of the second dielectric layer 120 can include any one or more of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN), and may also include other types of dielectric materials. This application embodiment does not specifically limit the materials.

[0052] In some optional embodiments of this application, such as Figure 1As shown, the second dielectric layer 120 includes a first portion located above the hard mask layer and a second portion located above the memory node contact structure 810, with the vertex of the first portion higher than the vertex of the second portion. Hard mask material is simultaneously deposited in memory region A and peripheral region B, followed by sequential patterning and etching processes to form grooves in peripheral region B. Multiple connectors 80 are spaced apart by these grooves. Grooves are also simultaneously etched in memory region A. Due to material differences, the depth of the grooves formed in memory region A is greater than the depth of the grooves in peripheral region B. If the depth of the grooves in memory region A is too large, over-etching to the bit line 220 may cause a short circuit. In this embodiment, by leaving hard mask material on the surface of the second connector 802, the depth of the grooves etched in memory region A can be avoided from being too large, thereby avoiding the risk of over-etching and improving device reliability.

[0053] For example, such as Figure 1 As shown, the plurality of connectors 80 include a first connector 801 and a second connector 802. The top surface dimension of the second connector 802 is larger than that of the first connector 801. A hard mask layer 90 is located on the top surface of the second connector 802. The bottom surface dimension of the hard mask layer 90 in contact with the top surface of the second connector 802 is W3, and the height of the hard mask layer 90 is H3. Specifically, the hard mask layer 90 is formed in the semiconductor device fabrication process by using a patterning process to form the memory node contact structure 810 and the connectors 80, while at least some hard mask material remains on the top surface of the second connector 802. At this time, the hard mask material on the top surface of the second connector 802 and the top surface of the memory node contact structure 810 can be removed.

[0054] In another example, such as Figure 1 As shown, the hard mask layer 90 is also located on the top surface of the contact pad 820 in at least one memory node contact structure 810. The bottom surface dimension of the hard mask layer 90 in contact with the top surface of the contact pad 820 is W1, and the height of the hard mask layer 90 is H1. Specifically, in the semiconductor device fabrication process, while the memory node contact structure 810 and the connector 80 are formed by patterning, hard mask material remains on the top surface of the second connector 802 and the top surface of at least one memory node contact structure 810, while the hard mask material on the top surface of the first connector 801 and the top surfaces of the remaining memory node contact structures 810 is removed.

[0055] In another example, such as Figure 1As shown, the hard mask layer 90 is also located on the top surface of the first connector 801. The bottom surface dimension of the hard mask layer 90 in contact with the top surface of the first connector 801 is W2, and the height of the hard mask layer 90 is H2. In the semiconductor device fabrication process, while the memory node contact structure 810 and the connector 80 are formed by patterning, in addition to the hard mask material remaining on the top surface of the first connector 801 and the top surface of at least one memory node contact structure 810, the top surface of at least one second connector 802 also has hard mask material remaining. The remaining hard mask material forms the hard mask layer 90. Since the top surface dimension of the second connector 802 is larger than the top surface dimension of the first connector 801, the dimension of the hard mask layer 90 on the top surface of the second connector 802 is larger than the dimension of the hard mask layer 90 on the top surface of the first connector 801. The bottom surface dimension of the hard mask layer 90 in contact with the top surface of the second connector 802 is larger than the bottom surface dimension of the hard mask layer 90 in contact with the top surface of the first connector 801, and the height of the hard mask layer 90 on the top surface of the second connector 802 is also greater than the height of the hard mask layer 90 on the top surface of the first connector 801.

[0056] In some optional embodiments of this application, such as Figure 1 As shown, the hard mask layer 90 includes a first sub-mask covering the connector 80 and a second sub-mask covering the memory node contact structure 810. The vertex of the first sub-mask is higher than the vertex of the second sub-mask. The first sub-mask is disposed on the top surface of at least one connector 80, and the second sub-mask is disposed on the top surface of at least one memory node contact structure 810. The first and second sub-masks may be formed by leaving hard mask material on the top surface of the connector 80 during the semiconductor device fabrication process, while the memory node contact structure 810 and the connector 80 are formed using a patterning process.

[0057] In some optional embodiments of this application, the hard mask layer is completely isolated from the top surface of the memory node contact structure. In this case, the hard mask layer is formed by removing the hard mask material from the top surface of the memory node contact structure during the patterning process in the semiconductor device fabrication process, while leaving hard mask material on the top surface of at least one connector.

[0058] like Figure 3 As shown, the hard mask layer 90 can also directly contact the top surface of the storage node contact structure 810 and the sidewall of the capacitor structure 130. After the wires 150 (first connector 801 and second connector 802) are connected above the connector 80, the hard mask layer 90 contacts the sidewall of the wires 150.

[0059] In the semiconductor devices described in the embodiments of this application, such as Figure 1 and Figure 3As shown, multiple capacitor structures 130 are located on the storage node contact structure 810, and each capacitor structure 130 is connected to at least one adjacent capacitor structure 130 through the support layer 140.

[0060] The aforementioned multiple capacitor structures 130 are spaced apart above the substrate 10 and are connected one-to-one with the contact pads 820 in the storage node contact structure 810.

[0061] According to embodiments of this application, a semiconductor device is also provided, such as... Figure 3 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application.

[0062] like Figure 3 As shown, the semiconductor device includes a substrate 10, a plurality of bit lines 220, a plurality of gate structures 210, a first dielectric layer 100, a plurality of connectors 80, a plurality of memory node contact structures 810, a plurality of capacitor structures 130, a hard mask layer 90, and a second dielectric layer 120, wherein: the substrate 10 includes a cell region and a peripheral region; the plurality of bit lines 220 are located on the cell region; the plurality of gate structures 210 are located on the peripheral region; the first dielectric layer 100 is located between adjacent gate structures 210; the plurality of connectors 80 are located within the first dielectric layer 100 and connected to the substrate; the plurality of memory node contact structures 810 are located between adjacent bit lines 220; the plurality of capacitor structures 130 are located on the memory node contact structures 810; the hard mask layer 90 covers the top surface of the connectors; and the second dielectric layer 120 covers the hard mask layer 90 and directly contacts the top surface of the connectors 80 and the sidewalls of the capacitor structures 130.

[0063] In the semiconductor devices described in the embodiments of this application, such as Figure 3 As shown, the hard mask layer 90 can be formed in the semiconductor device fabrication process by removing the hard mask material on the top surface of the memory node contact structure 810 during the patterning process, while leaving hard mask material on the top surface of the aforementioned connector. Specifically, the hard mask material is deposited simultaneously in the memory region A and the peripheral region B, and the patterning process and etching process are performed sequentially to form grooves in the peripheral region B to space out multiple connectors 80. Grooves are also simultaneously etched in the memory region A. Due to the difference in materials, the depth of the grooves formed in the memory region A will be greater than the depth of the grooves in the peripheral region B. If the depth of the grooves in the memory region A is large, it may be over-etched to the bit line 220, causing a short circuit. However, in this embodiment, by leaving hard mask material on the surface of the second connector 802, the depth of the grooves formed by etching in the memory region A can be avoided to be too large, thereby avoiding the risk of over-etching and improving device reliability.

[0064] In the semiconductor device described in the embodiments of this application, the positional relationship and materials of the substrate 10, bit line 220, gate structure 210, first dielectric layer 100, connector 80, memory node contact structure 810, capacitor structure 130 and hard mask layer 90 can be the same as those of the semiconductor device provided in the previous embodiments, and will not be repeated in the embodiments of this application.

[0065] According to embodiments of this application, a method for fabricating a semiconductor device is also provided. Figure 4 This is a process flow diagram of a method for fabricating a semiconductor device according to an embodiment of this application.

[0066] like Figures 4 to 11 As shown, the method for fabricating this semiconductor device includes the following steps:

[0067] A substrate 10 is provided, which includes a cell region and a peripheral region:

[0068] Multiple bit lines 220 are formed on the cell region, multiple gate structures 210 are formed on the peripheral region, and a first dielectric layer 100 is formed between adjacent gate structures 210.

[0069] Multiple connectors 80 are formed within the first dielectric layer 100;

[0070] Multiple memory node contact structures 810 are formed between adjacent bit lines 220;

[0071] A hard mask layer 90 is formed covering the top surface of the connector 80;

[0072] A second dielectric layer 120 and a capacitor structure 130 are formed. The capacitor structure 130 is located on the memory node contact structure 810. The second dielectric layer 120 covers the hard mask layer 90. The second dielectric layer 120 includes a first portion located above the hard mask layer 90 and a second portion located above the memory node contact structure 810. The vertices of the first portion and the second portion of the second dielectric layer 120 are located at different horizontal heights.

[0073] In the semiconductor device fabrication method described in this application embodiment, since a hard mask layer 90 is formed covering the top surface of the connector 80, and the second dielectric layer includes a first portion located above the hard mask layer 90 and a second portion located above the memory node contact structure, the vertices of the first portion and the second portion of the second dielectric layer 120 are located at different horizontal heights. The hard mask layer 90 is formed from residual hard mask material during the formation of the connector 80. During the formation of the connector 80, the hard mask material is simultaneously deposited in the memory region A and the peripheral region B. Patterning and etching processes form grooves in the peripheral region B to space out multiple connectors 80. Grooves are also formed simultaneously in the memory region A. Due to material differences, the depth of the grooves formed in the memory region A is greater than the depth of the grooves in the peripheral region B. If the depth of the grooves in the memory region A is too large, it may over-etch to the bit line 220, causing a short circuit. However, in this embodiment, by leaving a hard mask material on the surface of the second connector 802, the depth of the grooves formed in the memory region A can be avoided from being too large, thereby avoiding the risk of over-etching and improving device reliability.

[0074] Furthermore, the aforementioned hard mask layer 90 can be formed by leaving hard mask material on the top surface of the aforementioned connector 80 during the semiconductor device fabrication process, while the memory node contact structure 810 and the connector 80 are formed using a patterning process. This eliminates the need for additional process steps, thereby achieving the technical effect of improving the performance of semiconductor devices without increasing process time and process cost.

[0075] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0076] First, such as Figure 5 As shown, a substrate 10 is provided, which includes a cell region and a peripheral region.

[0077] The substrate 10 mentioned above can be a semiconductor substrate such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate. This application does not specifically limit the specific substrate.

[0078] In some alternative implementations, a shallow trench isolation structure (STI) 50 is formed in the substrate 10 to define multiple active regions of memory cells in the memory region A of the substrate 10, and multiple active regions of semiconductor devices in the peripheral region B of the substrate 10.

[0079] After providing substrate 10, as Figure 5As shown, multiple bit lines 220 are formed on the cell region, multiple gate structures 210 are formed on the peripheral region, and a first dielectric layer 100 is formed between adjacent gate structures 210.

[0080] In some alternative implementations, such as Figure 5 As shown, multiple gate structures 210 located on the peripheral region B and multiple bit lines 220 located on the memory region A are formed through the same process steps. Exemplarily, a semiconductor material layer, a metal material layer, and a hard mask material layer are sequentially formed on the peripheral region B and the memory region A of the substrate 10. The hard mask material layer is then patterned to obtain a patterned mask. The metal material layer and the semiconductor material layer are then etched sequentially using the patterned mask as a mask to transfer the pattern of the patterned hard mask into the semiconductor material layer, thereby obtaining the gate structures 210 and bit lines 220.

[0081] The gate structure 210 may include a first semiconductor layer 211, a first metal layer 212, and a first patterned mask 213 stacked sequentially in a direction away from the substrate 10. The bit line 220 may include a second semiconductor layer 221, a second metal layer 222, and a second patterned mask 223 stacked sequentially in a direction away from the substrate 10. The materials of the first semiconductor layer 211 and the second semiconductor layer 221 may include polysilicon. The materials of the first metal layer 212 and the second metal layer 222 may include low resistivity metal materials such as aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), and titanium-aluminum alloy (TiAl). The materials of the first patterned mask 213 and the second patterned mask 223 may include any one or more of silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN), and may also include other dielectric materials. The embodiments of this application do not specifically limit the types of materials mentioned above.

[0082] It should be noted that before the step of forming the gate structure 210, a gate oxide layer (not shown in the figure) may be formed on the substrate 10 so that the gate oxide layer is located between the substrate 10 and the semiconductor portion 22 of the gate structure 210. The material of the gate oxide layer may be silicon oxide (SiO2).

[0083] After the step of forming the gate structure 210, as Figure 5 As shown, a first dielectric layer 100 is formed between adjacent gate structures 210. After the step of forming the first dielectric layer 100, as... Figure 5As shown, the fabrication method provided in this application embodiment may further include: forming a barrier layer 30 located on the gate structure 210 and the first dielectric layer 100. The materials of the first dielectric layer 100 and the barrier layer 30 may include any one or more of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN), and may also include other types of dielectric materials, which are not specifically limited in this application embodiment.

[0084] like Figure 5 As shown, the fabrication method provided in this application embodiment may further include: forming a first sidewall 410 located on both sides of the gate structure 210; and forming a second sidewall 420 located on both sides of the bit line 220.

[0085] For example, the first sidewall 410 includes a first insulating layer 411, a second insulating layer 412 and a third insulating layer 413 that sequentially cover the sidewall of the gate structure 210 from the inside out, and the second sidewall 420 includes a fourth insulating layer 421, a fifth insulating layer 422 and a sixth insulating layer 423 that sequentially cover the sidewall of the bit line 220 and the barrier layer 30 from the inside out.

[0086] The first sidewall 410 and the second sidewall 420 can be prepared by the same process steps, and the material of each insulating layer in the first sidewall 410 and the second sidewall 420 can be conventional insulating materials in the prior art, such as silicon oxide (SiO2). This application embodiment does not make specific limitations.

[0087] After the step of forming the first dielectric layer 100, as Figure 6 and Figure 7 As shown, a plurality of connectors 80 are formed within the first dielectric layer 100.

[0088] In some alternative implementations, the step of forming the connector 80 includes: as follows Figure 6 As shown, contact openings 610 are formed on both sides of at least one gate structure 210, and the contact openings 610 extend from both sides of the gate structure 210 into the substrate 10; as Figure 7 As shown, conductive material 821 is deposited on substrate 10 so that a portion of the conductive material 821 fills the contact opening 610 to form a shape as shown. Figure 2 As shown, the first connection portion 811, the remaining conductive material 821 forms a conductive layer on the side of the gate structure 210 and the first dielectric layer 100 facing away from the substrate 10; as Figure 8 and Figure 9 As shown, a mask material 910 is deposited on the surface of the conductive layer, and the mask material is used to form a patterned mask. Then, the conductive layer is etched through the patterned mask to form the conductive layer as shown. Figure 2The second connecting part 812 shown provides the first connecting member 801 and the second connecting member 802.

[0089] In the above optional implementations, such as Figure 6 As shown, while forming the contact opening 610, a memory node contact opening 620 located between adjacent bit lines 220 can also be formed, such as... Figure 7 As shown, conductive material 821 can be deposited simultaneously in peripheral region B and memory region A. A portion of the conductive material 821 deposited in peripheral region B fills the contact opening 610, and a portion of the conductive material 821 deposited in memory region A fills the memory node contact opening 620, as shown. Figure 8 As shown, the mask material 910 deposited on the surface of the conductive layer also covers the surface of the conductive material 821 in the memory region A. After the mask material is formed into a patterned hard mask, the conductive material 821 is etched through the patterned hard mask located in the memory region A to form a contact pad 820.

[0090] In some alternative implementations, a conductive material covering the bit lines and gate structure is first formed, a patterned hard mask is formed on the surface of the conductive material, the conductive material is then partially removed to form the connector and memory node contact structure, and then the patterned hard mask on the memory node contact structure is completely removed to form a hard mask layer covering the top surface of the connector.

[0091] In the above optional embodiments, while completely removing the hard mask material on the top surface of the memory node contact structure in the patterning process, a portion of the hard mask material remains on the top surface of the connector to form a hard mask layer. This avoids the depth of the grooves formed by etching in memory region A, thereby avoiding the risk of over-etching and improving device reliability.

[0092] In other alternative implementations, such as Figure 7 and Figure 8 As shown, a conductive material 821 is formed covering the bit line 220 and the gate structure 210; a patterned hard mask is formed on the surface of the conductive material 821; the conductive material 821 is partially removed to form a connector 80 and a memory node contact structure 810; the patterned hard mask is partially removed to form a first sub-mask covering the connector 80 and a second sub-mask covering the memory node contact structure 810, wherein the vertex of the first sub-mask is higher than the vertex of the second sub-mask.

[0093] In the above optional embodiments, a first sub-mask is disposed on the top surface of at least one connector 80, and a second sub-mask is disposed on the top surface of at least one memory node contact structure 810. The first and second sub-masks can be formed by leaving hard mask material on the top surface of the connector 80 during the semiconductor device fabrication process, while the memory node contact structure 810 and the connector 80 are formed using a patterning process. After the patterning process, an etching process is performed to form grooves in the peripheral region B, through which multiple connectors 80 are spaced. Grooves are also simultaneously etched in the memory region A. Due to the difference in materials, the depth of the grooves formed in the memory region A will be greater than the depth of the grooves in the peripheral region B. If the depth of the grooves in the memory region A is large, it may cause over-etching to the bit line 220, resulting in a short circuit. By making the height of the hard mask material remaining on the top surface of the connector 80 greater than the height of the hard mask material remaining on the top surface of the memory node contact structure 810, the depth of the grooves formed by etching in the memory region A can be avoided to be too large, thereby avoiding the risk of over-etching and improving device reliability.

[0094] After the steps of forming the connector 80 and the storage node contact structure 810, as Figure 9 As shown, the fabrication method provided in this application embodiment may further include: depositing a dielectric material 101 on the substrate 10 to cover the connector 80, the memory node contact structure 810, and the hard mask layer 90, and filling the spaces between adjacent memory node contact structures 810 and adjacent connectors 80, such as... Figure 10 As shown, the portion of the dielectric material 101 covering the connector 80, the storage node contact structure 810, and the hard mask layer 90 is removed.

[0095] After the step of forming dielectric material 101, as Figure 11 As shown, a second dielectric layer 120 is formed. The second dielectric layer 120 includes a first portion located above the hard mask layer 90 and a second portion located above the memory node contact structure 810. The vertices of the first portion and the second portion of the second dielectric layer 120 are located at different horizontal heights, which can avoid the excessive depth of the grooves formed by etching in the memory region A, thereby avoiding the risk of over-etching and improving device reliability.

[0096] Furthermore, the aforementioned hard mask layer 90 can be formed by leaving hard mask material on the top surface of the aforementioned connector 80 during the semiconductor device fabrication process, while the memory node contact structure 810 and the connector 80 are formed using a patterning process. This eliminates the need for additional process steps, thereby achieving the technical effect of improving the performance of semiconductor devices without increasing process time and process cost.

[0097] After the step of forming the second dielectric layer 120, as Figure 1 As shown, a capacitor structure 130 is formed, which is located on the storage node contact structure 810.

[0098] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0099] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes the cell region and the peripheral region; Multiple bit lines are located on the cell region; Multiple gate structures are located on the peripheral region; A first dielectric layer is located between adjacent gate structures; Multiple connectors are located within the first dielectric layer and connected to the substrate, with the dielectric material isolating adjacent connectors. Multiple memory node contact structures are located between adjacent bit lines, and the dielectric material isolates the adjacent memory node contact structures. Multiple capacitor structures are located on the storage node contact structure and are in direct contact with the storage node contact structure; A hard mask layer is located on the top surface of the connector; A second dielectric layer covers the dielectric material, the connector, and the hard mask layer, wherein the portion of the second dielectric layer on the hard mask layer has the highest vertex.

2. The semiconductor device according to claim 1, characterized in that, The hard mask layer includes a first sub-mask covering the connector and a second sub-mask covering the storage node contact structure, wherein the vertices of the first sub-mask are higher than the vertices of the second sub-mask.

3. The semiconductor device according to claim 1, characterized in that, The hard mask layer is completely isolated from the top surface of the storage node contact structure.

4. The semiconductor device according to claim 1, characterized in that, It also includes a third dielectric layer located above the gate structure and between adjacent connectors, with the vertex of the third dielectric layer lower than the vertex of the hard mask layer.

5. The semiconductor device according to claim 1, characterized in that, The hard mask layer is in direct contact with the top surface of the connector and the sidewall of the capacitor structure.

6. A semiconductor device, characterized in that, include: The substrate includes the cell region and the peripheral region; Multiple bit lines are located on the cell region; Multiple gate structures are located on the peripheral region; A first dielectric layer is located between adjacent gate structures; Multiple connectors are located within the first dielectric layer and connected to the substrate, with the dielectric material isolating adjacent connectors. Multiple memory node contact structures are located between adjacent bit lines, and the dielectric material isolates the adjacent memory node contact structures. Multiple capacitor structures are located on the storage node contact structure and are in direct contact with the storage node contact structure; A hard mask layer is located on the top surface of the connector; A second dielectric layer covers the dielectric material, the connector, and the hard mask layer, and directly contacts the top surface of the connector and the sidewalls of the capacitor structure, wherein the portion of the second dielectric layer on the hard mask layer has the highest vertex.

7. The semiconductor device according to claim 6, characterized in that, The hard mask layer includes a first sub-mask covering the connector and a second sub-mask covering the storage node contact structure, wherein the vertices of the first sub-mask are higher than the vertices of the second sub-mask.

8. The semiconductor device according to claim 6, characterized in that, The hard mask layer is completely isolated from the top surface of the storage node contact structure.

9. The semiconductor device according to claim 6, characterized in that, It also includes a third dielectric layer located above the gate structure and between adjacent connectors, with the vertex of the third dielectric layer lower than the vertex of the hard mask layer.

10. The semiconductor device according to claim 7, characterized in that, The hard mask layer is in direct contact with the top surface of the connector and the sidewall of the capacitor structure.

11. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate comprising a cell region and a peripheral region: Multiple bit lines are formed on the cell region, multiple gate structures are formed on the peripheral region, and a first dielectric layer is formed between adjacent gate structures. Multiple connectors are formed within the first dielectric layer, and the dielectric material isolates adjacent connectors. Multiple memory node contact structures are formed between adjacent bit lines, and the dielectric material isolates the adjacent memory node contact structures. A hard mask layer is formed on the top surface of the connector; A second dielectric layer and a capacitor structure are formed, the capacitor structure being located on the memory node contact structure and in direct contact with the memory node contact structure. The second dielectric layer covers the dielectric material, the connector, and the hard mask layer, wherein the portion of the second dielectric layer on the hard mask layer has the highest vertex.

12. The preparation method according to claim 11, characterized in that, Also includes: A conductive material is formed covering the bit lines and the gate structure; A patterned hard mask is formed on the surface of the conductive material; Partial removal of conductive material to form the contact structure between the connector and the storage node; The patterned hard mask located on the storage node contact structure is completely removed to form a hard mask layer covering the top surface of the connector.

13. The preparation method according to claim 11, characterized in that, Also includes: A conductive material is formed covering the bit lines and the gate structure; A patterned hard mask is formed on the surface of the conductive material; Partial removal of conductive material to form the contact structure between the connector and the storage node; Partial removal of the patterned hard mask forms a first sub-mask covering the connector and a second sub-mask covering the storage node contact structure, wherein the vertices of the first sub-mask are higher than the vertices of the second sub-mask.

14. The preparation method according to any one of claims 11 to 13, characterized in that, Also includes: A third dielectric layer is formed such that it is located above the gate structure and between the adjacent connector.

15. A semiconductor device, characterized in that, include: The substrate includes the cell region and the peripheral region; Multiple bit lines are located on the cell region; Multiple gate structures are located on the peripheral region; A first dielectric layer is located between adjacent gate structures; Multiple connectors are located within the first dielectric layer and connected to the substrate; Multiple storage node contact structures are located between adjacent bit lines; Multiple capacitor structures are in direct contact with the top surface of the storage node contact structure; A hard mask layer is located on the top surface of the connector; The second dielectric layer includes a first portion located above the hard mask layer and a second portion located between the storage node contact structure and the first portion of the second dielectric layer, wherein the vertex of the first portion of the second dielectric layer is higher than the vertex of the second portion.

16. The semiconductor device according to claim 15, characterized in that, The apex of the hard mask layer is higher than the apex of the second portion of the second dielectric layer.

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