Wafer acceptance test method for identifying abnormal dies based on spatial correlation

Abstract

The application discloses a wafer acceptance test abnormal wafer grain identification method based on spatial correlation, and the method specifically comprises the following steps: (1) determining a first test point with missing electrical parameters in wafer acceptance test, and filling the missing electrical parameters of the first test point based on wafer spatial correlation; (2) grouping electrical parameter characteristics, screening key electrical parameter characteristics in each group of electrical parameter characteristics, and identifying abnormal test points based on the key electrical parameter characteristics in each group; and (3) detecting the abnormal type of the abnormal test points, wherein the abnormal type includes test escape or transition test. The missing electrical data is filled based on wafer spatial correlation, the nonlinear relationship between parameters is mined through feature grouping driven by mutual information, and then a self-encoder model is constructed to capture abnormal test points; and artificial neural network is used to realize fine-grained classification of abnormal wafer grains.

Description

Technical Field

[0001] This invention belongs to the field of wafer acceptance testing technology, and more specifically, this invention relates to a method for identifying abnormal grains in wafer acceptance testing based on spatial correlation. Background Technology

[0002] As integrated circuits (ICs) modernize towards higher performance and lower power consumption, the demand for precision and complexity in chip manufacturing processes continues to increase. In the development of modern industries, to meet market chip demands, miniaturization processes are used to continuously reduce transistor size, thereby improving chip integration and performance. With the continuous increase in chip manufacturing precision, the increased sensitivity to process fluctuations and the increase in the number of lithography layers lead to a significant increase in defect density during wafer manufacturing, directly threatening chip yield. Statistics show that a 1% decrease in yield in advanced processes can increase the cost per wafer by millions of dollars; therefore, improving wafer testing quality is becoming a significant challenge in the chip industry.

[0003] The semiconductor manufacturing process is mainly divided into three stages: design, manufacturing, and packaging / testing. In the design stage, engineers use hardware description languages, layout design, and circuit logic to design the required functions and circuit patterns. In the manufacturing stage, raw material supplier A first processes high-purity silicon raw materials through melting, single-crystal growth, and dicing to prepare single-crystal silicon wafers. The FAB (Fabrication, Assembly, and Packaging) plant then uses deposition, photolithography, and etching processes according to the circuit structure designed in the design stage to build complete circuits on the silicon wafers, forming integrated wafers. In the packaging / testing stage, qualified chips are diced and packaged, and then undergo final electrical testing (FT) to complete the semiconductor device manufacturing process, ensuring that the chips ultimately flowing into the market meet the performance, power consumption, and reliability requirements of the corresponding chip manufacturers. Wafer testing, as a core quality control step before wafer dicing, mainly uses tungsten or other alloy probes in automated test equipment (ATE) to test the manufactured wafers, including wafer acceptance test (WAT) and chip probing (CP). Wafer acceptance testing precisely aligns with the test structure contact points in the dicing slots, applies voltage / current signals, and tests the electrical parameters of the dies, generating a wafer acceptance test dataset. Wafer probe testing tests the functional pads of the dies on the wafer. Considering the actual chip functional testing requirements, each die is inspected, resulting in a wafer yield distribution map. Through WAT and CP, the die test quality can be monitored in a timely manner, allowing test results to be fed back to the manufacturer in real time for root cause analysis.

[0004] WAT (Wafer Test Acquisition) testing, as the first step in wafer testing and the first stage of all electrical tests, acquires a dataset of electrical / physical parameters corresponding to specific test structures on the wafer to determine whether they meet specifications. Some parameters in WAT testing are prone to anomalies; therefore, pre-processing the WAT test dataset can improve semiconductor manufacturing efficiency, reduce testing resource consumption and cycle time, and enable timely detection of test defects.

[0005] The testing quality of WAT electrical parameters directly affects the screening efficiency of subsequent wafer-level testing. Therefore, improving WAT testing quality is an urgent problem to be solved. Currently, the main factors affecting test quality are test escape and overtesting. Test escape refers to defective dies that should have been rejected by WAT passing the test due to missed detection, flowing into subsequent stages, leading to potential failure risks and increased costs. Overtesting refers to some good dies being misjudged as defective and scrapped due to overly strict test thresholds, resulting in yield loss and wasted testing resources. Therefore, how to balance test escape and overtesting when identifying abnormal dies is the key to improving test quality. Traditional methods for analyzing wafer acceptance test (WAT) data mainly rely on statistical process control (SPC), expert experience, and manual diagnosis. These methods are no longer sufficient to meet the needs of modern testing for complex defect patterns and high-dimensional nonlinear data. Summary of the Invention

[0006] This invention provides a method for identifying anomalous grains in wafer acceptance testing based on spatial correlation, aiming to improve at least one of the above-mentioned problems.

[0007] This invention is implemented as follows: a method for identifying abnormal grains in wafer acceptance testing based on spatial correlation, the method being as follows:

[0008] (1) Identify the first test point in the wafer acceptance test where electrical parameters are missing, and fill in the missing electrical parameters of the first test point based on wafer space correlation;

[0009] (2) Group the electrical parameter features, filter the key electrical parameter features in each group, and identify abnormal test points based on the key electrical parameter features in each group;

[0010] (3) The abnormality type of the test point that detects the abnormality. The abnormality types include test escape or overtest.

[0011] Furthermore, the specific method for filling in the missing electrical parameters at the first test point is as follows:

[0012] (11) Based on the distribution of the first test point on the standard radius, the wafer is divided into three regions: the wafer edge region, the wafer middle region, and the wafer center region.

[0013] (12) Calculate the standardized radius of each first test point and determine the area where each first test point is located;

[0014] (13) Take neighborhood sampling points in the area where each first test point is located, determine the interpolation weight based on the distance between the first test point and each neighborhood sampling point, and use the weighted average of the electrical parameters of each neighborhood sampling point as the missing electrical parameters of the corresponding first test point.

[0015] Furthermore, the electrical parameters of the i first test points The specific calculation formula is as follows:

[0016] ;

[0017] ;

[0018] ;

[0019] in, This represents the difference weight of the j-th neighboring sampling points of the i-th first test point. This represents the electrical parameters of the j-th neighboring sampling point of the i-th first test point. Indicates the number of neighboring sampling points. This represents the Euclidean distance between the i-th first test point and its j-th neighboring sample points. This is the distance attenuation coefficient. This represents the position coordinates of the j-th neighboring sampling point of the i-th first test point;

[0020] Number of neighboring sampling points in different regions and distance attenuation coefficient different.

[0021] Furthermore, the process for obtaining key electrical parameter characteristics is as follows:

[0022] (21) Treat each electrical parameter as an electrical parameter feature, group different electrical parameter features with the same unit into the same group, calculate the mutual information between each electrical parameter feature in the group, and form the mutual information matrix M for each group;

[0023] (22) Determine the key electrical parameters in the corresponding group of electrical parameter characteristics based on the mutual information matrix M.

[0024] Furthermore, the specific method for obtaining the key electrical parameters of the mutual information matrix M is as follows:

[0025] (221) Calculate the centrality score of each electrical parameter feature within the group. The centrality score of an electrical parameter feature is the sum of the mutual information between the electrical parameter feature and all other electrical parameter features within the group.

[0026] (222) The average of the centrality scores of all electrical parameter features within a group is used as the threshold, and electrical parameter features with centrality scores higher than the threshold are included in the candidate electrical parameter feature set;

[0027] (223) Extract the mutual information submatrix M_sub that contains only the candidate electrical parameter features from the mutual information matrix M corresponding to the electrical parameter features of this group;

[0028] (224) Convert the mutual information submatrix M_sub into the distance matrix D, and divide the candidate electrical parameters into two clusters based on the distance threshold;

[0029] (225) Detect the number of candidate electrical parameter features in two clusters. For clusters where the number of candidate electrical parameter features is less than the set number min_size, retain all candidate electrical parameter features in the corresponding cluster coarse as key electrical parameter features. For clusters where the number of candidate electrical parameter features is less than the set number min_size, retain the candidate electrical parameter feature with the highest centrality score in the corresponding cluster coarse as key electrical parameter feature.

[0030] Furthermore, the clustering method based on distance thresholds is as follows:

[0031] In the distance matrix D, those whose distance is greater than the distance threshold 1-t are grouped into one cluster, and those whose distance is less than the distance threshold 1-t are grouped into another cluster.

[0032] Furthermore, the specific method for identifying abnormal test points based on the key electrical parameter characteristics in each group is as follows:

[0033] The vectors corresponding to the key electrical parameter features of each group are standardized and input into the stacked autoencoder. The stacked autoencoder outputs the vectors corresponding to the key electrical parameter features reconstructed in the corresponding group. Test points with large reconstruction errors are identified as abnormal test points.

[0034] Furthermore, the reconstruction error at each test point The specific calculation formula is as follows:

[0035] ;

[0036] in, This represents the mean of the centrality scores of all key electrical parameters within group g. , Indicates the first The vector corresponding to the key electrical parameter features of the group. The first reconstructed for stacked autoencoders The vector corresponding to the key electrical parameters of the group.

[0037] Furthermore, the vectors corresponding to the key electrical parameter features of the abnormal test points are input into the ANN model, and the ANN model outputs the abnormality type of the abnormal test points.

[0038] Missing electrical data is filled in based on wafer spatial correlation, and nonlinear relationships between parameters are mined through feature grouping driven by mutual information. In this way, an autoencoder model is constructed to capture abnormal test points; and an artificial neural network is used to achieve fine-grained classification of abnormal grains. Attached Figure Description

[0039] Figure 1 A flowchart illustrating the method for identifying abnormal grains in wafer acceptance testing based on spatial correlation, provided in an embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram of the wafer parameter distribution provided in an embodiment of the present invention;

[0041] Figure 3 RMSE and R provided for embodiments of the present invention 2 The comparison results are shown in the figure, where (a) is the root mean square error (RMSE) and (b) is the correlation coefficient (R). 2 ;

[0042] Figure 4 An adaptive electrical parameter feature selection diagram provided in an embodiment of the present invention;

[0043] Figure 5 A set of electrical parameter feature curves provided for embodiments of the present invention;

[0044] Figure 6 A schematic diagram illustrating the screening of key electrical parameter features provided in embodiments of the present invention;

[0045] Figure 7 This is a schematic diagram of anomaly detection point identification based on key electrical parameter features and reconstructed key electrical parameter features provided in an embodiment of the present invention;

[0046] Figure 8 The test escape rate (TER) and overtest rate (OVR) trade-off curve provided in the embodiments of the present invention. Detailed Implementation

[0047] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, so as to help those skilled in the art to have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention.

[0048] Figure 1 A flowchart of an abnormal grain identification method for wafer acceptance testing based on spatial correlation provided in an embodiment of the present invention is shown below:

[0049] (1) Identify the first test point in the wafer acceptance test (WAT) where electrical parameters are missing, and fill in the missing electrical parameters based on wafer space correlation;

[0050] As a preliminary step in wafer testing, WAT (Wafer Equipment Testing) may encounter missing electrical parameter datasets during the ATE (Electrical Parameter Testing) process due to various factors such as hardware failures, software issues, wafer defects, and environmental interference. Common methods to address this issue include directly deleting missing data or filling in missing data with neighboring parameters. While deleting the corresponding data row effectively reduces potentially erroneous data, it compromises the overall integrity of the dataset, hindering comprehensive wafer performance analysis. Another common approach to handling missing data is to use the median or mean of neighboring parameters to replace missing values, thus completing the electrical parameter dataset and reducing the impact of outliers.

[0051] The surface of wafers manufactured in semiconductor factories is not a uniform medium. Due to the physical and chemical effects introduced during the manufacturing process, spatially dependent structures are naturally introduced on the surface of the silicon wafer. This results in spatial correlations between features, parameters, or defects at different locations on the wafer (e.g., within-wafer, between-wafer, and lot-level statistics).

[0052] This invention focuses on the first test point in a wafer acceptance test dataset where electrical parameters are missing. Using the location coordinates of the first test point with electrical parameters as input, the invention binarizes this first test point to form a wafer parameter distribution map. In the wafer parameter distribution map, test points with electrical parameters are white against a black background. Figure 2 As can be seen, the first test point in the central region of the wafer is significantly sparser than that in the edge region. Wafer edge detection is more prone to electrical data loss. Therefore, using gradient layered data filling is more consistent with the actual spatial distribution of wafer parameters.

[0053] In this embodiment of the invention, the method for filling in the missing electrical parameters at the first test point is as follows:

[0054] (11) Based on the distribution of the first test point on the standard radius, the wafer is divided into three regions: the wafer edge region, the wafer middle region, and the wafer center region. The wafer edge region is far from the wafer center, the wafer center region includes the wafer center, and the wafer middle region is located between the wafer center region and the wafer edge region.

[0055] On a real dataset, the distribution of the first test point along the standard radius was statistically analyzed. Two standard radius thresholds, 0.8 and 0.3, were selected. The percentage of the first test points in three regions out of the total number of first test points was calculated. The percentage of standard radii r greater than 0.8 was 33.61%, the percentage of standard radii r less than 0.3 was 9.38%, and the percentage of standard radii r between 0.3 and 0.8 was 57.01%. The standardized radius was then... The region is the edge region of the wafer, with a normalized radius. The region is the middle area of ​​the wafer. The central region of the wafer.

[0056] (12) Calculate the standardized radius of each first test point and determine the area where each first test point is located;

[0057] In this embodiment of the invention, the standard radius of the i-th first test point is calculated based on formula (1). Formula (1) is as follows:

[0058] (1)

[0059] in, Where is the radius of the wafer. This indicates the coordinates of the wafer center. This represents the position coordinates of the i-th first test point.

[0060] (13) Take neighborhood sampling points in the area where each first test point is located, determine the interpolation weight based on the distance between the first test point and each neighborhood sampling point, and use the weighted average of the electrical parameters of each neighborhood sampling point as the electrical parameters of the corresponding first test point.

[0061] The smaller the distance between the first test point to be interpolated and the neighboring sampling points, the more similar the two points are, and the greater the interpolation weight. Distance weighting preserves the spatial gradient characteristics of the parameters, avoids smoothing effects, and ensures data integrity. The electrical parameters of the i first test points are calculated based on formulas (2) to (4). The formula is as follows:

[0062] (2)

[0063] in, This represents the difference weight of the j-th neighboring sampling points of the i-th first test point. This represents the electrical parameters of the j-th neighboring sampling point of the i-th first test point. This indicates the number of neighboring sampling points.

[0064] In this embodiment of the invention, the difference weight The specific calculation formula is as follows:

[0065] (3)

[0066] in, This represents the Euclidean distance between the i-th first test point and its j-th neighboring sample points. The distance decay coefficient controls the rate at which the weights decay with distance, where distance... The specific calculation formula is as follows:

[0067] (4)

[0068] in, This represents the position coordinates of the j-th neighboring sampling point of the i-th first test point.

[0069] (2) Group the electrical parameter features corresponding to each electrical parameter, screen the key electrical parameter features in each group, and identify abnormal test points based on the key electrical parameter features of each group. One test point generally corresponds to one grain.

[0070] In this embodiment of the invention, the process of obtaining key electrical parameter characteristics is as follows:

[0071] (21) Treat each electrical parameter as an electrical parameter feature, group different electrical parameter features with the same unit into the same group, calculate the mutual information between each electrical parameter feature in the group, and form the mutual information matrix M for each group;

[0072] With the miniaturization and increasing complexity of chips, the number of WAT feature parameters has increased significantly. Furthermore, some electrical parameters need to exhibit similar characteristic relationships, such as high / low frequency clock signal items and input / output power supply test items. Therefore, this invention, by practically classifying physically meaningful parameter features and placing similar features into corresponding groups, can effectively reduce the time cost of seeking interrelated feature relationships, thereby improving the flexibility and maintainability of classification. For similar semiconductor products, as test items increase, new parameter features are added to the corresponding groups, facilitating the flexible expansion of semiconductor test items. WAT parameters not only contain linear correlations but also complex nonlinear interactions, collectively forming a multi-faceted relationship network affecting chip performance. Therefore, it is necessary to introduce a method that can comprehensively capture complex linear and nonlinear patterns and more easily analyze the intrinsic relationships between parameters to achieve a more accurate grasp of parameter characteristics.

[0073] After parameter grouping for wafer acceptance testing, to overcome the challenges of high dimensionality and drastic fluctuations in electrical parameter characteristic data, maximum-minimum standardization is first used to linearly scale each electrical parameter to the [0,1] interval, unifying dimensions and orders of magnitude and balancing the weight of each parameter in subsequent analysis. After feature grouping the normalized wafer electrical test data, mutual information (MI) is used to measure the correlation of parameters within a group. MI can effectively capture the complex statistical dependencies between high-dimensional, nonlinear, and drastically fluctuating electrical parameters, is unaffected by dimensions, has strong interpretability, and is relatively robust to outliers. It is also suitable for the large sample data commonly found in wafer acceptance testing.

[0074] In this embodiment of the invention, the mutual information between the m-th electrical parameter and the n-th electrical parameter within the group... The specific calculation formula is as follows:

[0075] (5)

[0076] in, This represents the m-th and n-th electrical parameters within the same group. , They represent electrical parameters respectively entropy, Indicate electrical parameters and electrical parameters The joint entropy.

[0077] (22) Determine the key electrical parameters in the corresponding group of electrical parameter characteristics based on the mutual information matrix M;

[0078] In this embodiment of the invention, the method for obtaining key electrical parameters is as follows:

[0079] (221) Calculate the centrality score of each electrical parameter characteristic within the group. Centrality score is a characteristic of electrical parameters The sum of mutual information between the electrical parameters and characteristics of the group and all other electrical parameters.

[0080] If electrical parameter characteristics Features that are strongly correlated with many electrical parameters within a group indicate a stronger "centrality".

[0081] (222) The average of the centrality scores of all electrical parameter features within a group is used as the threshold, and electrical parameter features with centrality scores higher than the threshold are included in the candidate electrical parameter feature set;

[0082] (223) Extract the mutual information submatrix M_sub that contains only the candidate electrical parameter features from the mutual information matrix M corresponding to the electrical parameter features of this group;

[0083] (224) Convert the mutual information submatrix M_sub into the distance matrix D, and divide the candidate electrical parameters into two clusters based on the distance threshold;

[0084] Since the candidate electrical parameter feature set may contain a large number of redundant (i.e., highly correlated) candidate electrical parameter features, further simplification is required. First, a mutual information submatrix M_sub containing only the candidate features is extracted from the mutual information matrix M (keeping only the rows and columns corresponding to the candidate electrical parameter features in the feature set). The mutual information submatrix M_sub can intuitively reflect the correlation between candidate features. To adapt to the clustering algorithm's requirement for "distance" (features with strong correlation should have small distances), the mutual information submatrix M_sub is converted into a distance matrix D, with the conversion method being D = 1 - M_sub (the larger the mutual information, the smaller the distance). Subsequently, clustering is performed based on the distance matrix D, using a distance threshold 1-t to divide the clustering results. Distances greater than 1-t are assigned to one cluster (high feature redundancy), and distances less than 1-t are assigned to another cluster (low feature redundancy).

[0085] (225) Detect the number of candidate electrical parameter features in two clusters. For clusters where the number of candidate electrical parameter features is less than the set number min_size, it indicates that the number of features in the cluster is small and the redundancy is not significant. All candidate electrical parameter features in the corresponding cluster are retained as key electrical parameter features. For clusters where the number of candidate electrical parameter features is less than the set number min_size, it indicates that there are a large number of redundant candidate electrical parameter features in the cluster. The candidate electrical parameter feature with the highest centrality score in the corresponding cluster is retained as key electrical parameter features, thereby removing other redundant candidate electrical parameter features.

[0086] (23) Stack the autoencoders to reconstruct the vectors corresponding to the key electrical parameter features in each group of electrical parameter features, and identify the test points with large reconstruction errors as abnormal test points;

[0087] In this embodiment of the invention, the method for identifying abnormal test points based on key electrical parameter characteristics is as follows:

[0088] The vectors corresponding to the key electrical parameter features of each group are standardized and input into the stacked autoencoder. The stacked autoencoder outputs the vectors corresponding to the key electrical parameter features reconstructed for each group. Test points with large reconstruction errors are identified as abnormal test points.

[0089] The vectors corresponding to the key electrical parameter features are standardized to eliminate the influence of dimensions. The mutual information value calculated in the feature grouping stage is used as the reconstruction loss weight to enhance the anomaly sensitivity of high mutual information feature groups. The specific formula for calculating the reconstruction error of each test point is as follows:

[0090] (6)

[0091] in, This represents the mean centrality score of all critical electrical parameters within group g, where G represents the number of groups. Indicates the first The vector corresponding to the key electrical parameter features of the group. The first reconstructed for stacked autoencoders The vector corresponding to the key electrical parameters of the group.

[0092] True outliers often reflect potential structural defects or complex defect patterns. By strengthening the anomalous response of key feature groups through a mutual information weighting mechanism, it is more robust to interference from weakly correlated features compared to traditional autoencoders.

[0093] (3) The abnormality type of the test point that detects the abnormality. The abnormality types include test escape or overtest.

[0094] These dies are more prone to potential failures during the use of the chips they are assigned to. Therefore, classifying these potentially abnormal dies is crucial for improving the quality of wafer acceptance testing. This invention uses an artificial neural network (ANN) to finely determine each abnormal test point. In the WAT scenario, key parameters affecting die yield (such as leakage current and high-frequency clock) often exhibit complex nonlinear relationships. Removing all abnormal dies can effectively reduce potential safety risks, but it leads to a high overall yield loss, impacting actual costs. Retaining all abnormal dies can reduce the scrap rate of good products, but it may affect the potential risks of subsequent chips, raising questions about product reliability and quality. ANN can effectively capture the implicit correlation patterns between these parameters, which are difficult to describe with explicit rules, by learning from massive amounts of historical test data. This allows for a more accurate determination of whether a die marked as "abnormal" by the autoencoder is a true defective product or an acceptable marginal good product.

[0095] This system accurately distinguishes abnormal test points in wafer testing, classifying them into two categories: test escape (genuine defects) and over-testing (acceptable marginal good products), and optimizes each category independently. An artificial neural network model is trained based on labeled historical wafer test data. To address the class imbalance problem in the data, a class-based weight balancing strategy is adopted to reduce the dominant influence of the majority class on the model training results. Simultaneously, a Dropout layer is introduced after key layers (such as fully connected layers) of the neural network to effectively suppress overfitting and improve its generalization ability. Compared to traditional rule-based methods based on static thresholds (which struggle to capture complex relationships between parameters), the ANN model can learn non-linear patterns in the data and output the probability of each die belonging to a category. Based on this probability output, dies can be dynamically and effectively classified into normal, test escape, or over-testing categories. Accurate classification based on probability is crucial, enabling independent analysis and optimization of decision strategies for test escape rate and over-testing rate, rather than treating all abnormal dies as a single category.

[0096] Based on the probabilities output by the ANN, a dynamic decision threshold mechanism is employed to systematically adjust classification probabilities, exploring the trade-off between test escape rate and overtest rate. Increasing the probability value leads to more good products being misclassified as defective (increased overtest rate), increasing yield loss, but reducing test escape risk. Conversely, decreasing the probability value reduces misclassification of good products (decreased overtest rate), reducing yield loss, but increasing test escape risk. To optimize testing decisions, we quantify the test escape cost and overtest cost under different test values, constructing a total cost function. The ultimate goal is to find the trade-off data point between test escape and overtest by selecting the optimal probability value, thereby maximizing overall yield, while satisfying the constraint of an acceptable level of test escape risk.

[0097] To verify the proposed spatial correlation-based wafer acceptance test quality optimization method, experiments were conducted on a TensorFlow 2.13.0 environment and an RTX 3090 hardware platform. The wafer acceptance test dataset was obtained from Anhui Chaoyuan Semiconductor Co., Ltd., and this dataset records the results of the Automated Test Equipment (ATE) stopping testing upon the first failure. The effectiveness of the proposed method was verified on the empirical WAT dataset obtained during wafer testing. The Adam optimizer (learning rate 0.001) was used, and the training, test, and validation sets were divided in a 70:15:15 ratio.

[0098] Following the principle of stopping immediately upon first failure, the wafer acceptance test dataset containing missing data was divided into three regions according to grain standardization. Simultaneously, an 8:2 stratified data extraction method was selected, and 20% of the data was extracted from each stratum for cross-validation testing. Furthermore, this invention compares with commonly used methods for imputing missing data in wafer acceptance test datasets, using the 3*3 neighborhood median and mean, respectively. The proposed inverse distance weighted algorithm is used to impute the hidden data, and then the original data is compared with the three imputed data sets. Multiple experiments are conducted to verify its effectiveness in comparing the root mean square error (RMSE) and correlation coefficient (R²) of the wafer acceptance test dataset after using the above method to complete the dataset. 2 Experimental results. Among them, the root mean square error quantifies the deviation between the predicted and actual values, and the correlation coefficient (R²) 2 This is used to measure how well a model fits the data. Among them... Indicates the number of points to be measured. This is the actual value at that point. These are the predicted values ​​obtained using the fill method. It is the mean of the actual values. This is verified by checking RMSE and R... 2 The experimental results of these three methods on different quantitative features were compared to identify the superior data imputation method.

[0099] In the wafer center region, k=15 and the distance attenuation coefficient p=1; in the middle region, k=10 and p=2; and in the edge region, k=5 and p=3. Due to the strong process uniformity and gentle spatial gradient changes in the wafer center region, the correlation between neighboring points is high. A larger neighborhood range allows for the inclusion of more sampling points in the calculation. Combined with a smaller power parameter, sampling points at greater distances also receive relatively significant weights. The wafer edge region is significantly affected by boundary effects, exhibiting drastic spatial gradient changes and low correlation with the center region. A smaller neighborhood range strictly limits the number of sampling points participating in the interpolation, ensuring that only the nearest and most relevant points are used. Simultaneously, a larger power parameter ensures that only very close neighbors contribute significantly to the interpolation points. In the middle region, the uniformity and gradient changes fall between the two. Therefore, a moderate neighborhood range and a standard power parameter are used to strike a balance between noise suppression and local feature preservation, adapting to its transitional characteristics. The IDW algorithm proposed in this paper explicitly quantifies the similarity strength of neighboring points through distance decay weights and innovatively combines wafer spatial differentiation partitioning to achieve dynamic and accurate modeling of spatial correlation. This enables the IDW algorithm to more accurately match the spatial characteristics and data quality requirements of different locations on the wafer, thereby optimizing the overall performance of missing data filling.

[0100] Experimental results Figure 3 This demonstrates that, with an increasing number of features, the proposed region-adaptive IDW algorithm... Both were significantly lower than the 3×3 neighborhood median method and the mean method, and The values ​​are all significantly higher than those of the two commonly used methods. Among the 277 electrical features used in this dataset, While the value tends towards 1 with increasing features, the other two methods approach stable constant values, indicating that IDW has higher accuracy and predictive ability when filling missing data in wafer testing. Its robustness and superiority are particularly evident when dealing with high-dimensional, complex wafer data, providing stronger assurance for data integrity and analytical reliability in the wafer manufacturing process. In contrast, methods using simple statistical neighborhood filling, while easy to operate, severely neglect complex spatial dependency structures, leading to significant biases in high-dimensional, complex data.

[0101] After populating the WAT dataset, the original dataset was divided into 14 feature groups (such as IO characteristics, power supply characteristics, etc.) based on the physical meaning of the electrical parameters. Using an adaptive feature selection algorithm, the mutual information matrix of the internal parameters was calculated for each group, and key features were extracted: first, parameters with higher-than-average mutual information scores (i.e., the sum of mutual information with all features within the group) were selected to form a candidate set; then, strongly correlated features were merged through hierarchical clustering driven by mutual information distance, and representative features were dynamically selected based on cluster size—small clusters retained all features, while large clusters selected the key features with the highest cluster centrality. In the validation phase, covariance trace analysis and PCA reconstruction error comparison were used to quantitatively evaluate the ability of the key feature set to retain information about the original data structure.

[0102] One set of adaptive electrical parameter feature selections indicates that, as Figure 4 By considering the mutual information relationships within groups and constructing a feature centrality distribution, the centrality scores and average values ​​of all features within the corresponding groups are calculated. Seven features all exceed the group average; therefore, the first seven are selected as the candidate feature set, i.e., those with centrality scores higher than the average are used to represent the entire classification. When verifying the relationship between key features and the overall feature set, such as... Figure 5 As we can see from the curves, using the candidate feature set (blue dashed line) achieves a higher cumulative variance contribution rate with fewer principal components compared to the full feature set (pink curve). The candidate feature set rapidly accumulates most of the variance in the first few principal components, demonstrating its advantages in data compression and information preservation. This verifies the effectiveness of the feature selection algorithm in extracting the most representative features while reducing model complexity. Furthermore, considering feature parameter redundancy, it's clear from the graph that this method further reduces redundancy when selecting key features (red dashed line). The key feature set processed by adaptive feature selection shows a significant quality improvement compared to the original feature set.

[0103] For the dataset used in this experiment, we divided all features of the dataset into 14 feature groups based on their physical meaning for the experiment. Using an adaptive key feature selection algorithm, key features were extracted from the original feature set, significantly reducing the number of features. This invention reduced the original total of 277 electrical features to 160 after mutual information redundancy processing. Further clustering and key feature selection reduced this to 136. This process not only simplified the model but also improved data processing efficiency. In all test cases, the number of features was reduced, indicating that the feature selection algorithm effectively removed redundant information while retaining features crucial to model performance, providing a more concise and efficient feature set for subsequent data analysis and model construction. Figure 6 As shown.

[0104] In calculating the reconstruction error, the reconstruction error for each feature is weighted according to its importance. This autoencoder consists of a symmetric encoder and decoder, where the encoder contains three fully connected layers, and the decoder symmetrically reconstructs the input data. The model aims to minimize the mean squared error (MSE). To visually demonstrate the reconstruction effect, we have plotted a comparison of feature reconstructions, such as... Figure 7 As shown in the figure, the locations of outliers are marked. Simultaneously, the distribution of outliers is illustrated using a reconstruction error distribution map. This anomaly detection method effectively captures complex anomaly patterns in the key feature space, providing supervisory signals for subsequent artificial neural network prediction of test escape and overtesting risks. In the experimental figures, we can see that the reconstruction error of key features is significantly amplified, the mutual information weighting strategy effectively highlights the anomalies of highly important features, and the long-tailed distribution of reconstruction errors clearly marks the locations of outliers. Furthermore, our experimental results show that the method of seeking mutual information through multi-parameter features can consider the interrelationships between parameters, thus finding more latent defect grains and more anomaly data compared to traditional single-parameter data processing methods. This paper also compares this method with traditional methods for testing anomalous grains.

[0105] Based on an anomaly dataset identified using a multi-feature parameter joint autoencoder, this study aims to utilize an artificial neural network (ANN) to further refine the classification of anomalous grains within this dataset. The experiment, grounded in the aforementioned anomalous data, first labels the grain samples, clearly distinguishing between "normal grains" and "defective grains." The "abnormal grains," due to their inherent characteristics, constitute the core object of our modeling. We construct and train an artificial neural network model specifically designed to differentiate between normal and defective grains. The dataset is divided into training, testing, and validation sets in a 70%:15%:15% ratio. Using a specific ANN architecture, the model outputs a predicted probability that each grain belongs to the defect category. To achieve the final classification of the initial anomalous grain set, we introduce a crucial decision threshold based on the model's output anomaly probability. Establishing this threshold requires a trade-off between the risk of test escape (missing defect detection) and the cost of overtesting (false positives for normal detection). By applying this threshold, the originally identified anomalous grains can be further subdivided into more specific categories.

[0106] The experimental results for a single feature group show the trade-off curve between the designed Test Escape Rate (TER) and Overtest Rate (OVR). Simultaneously, the parameter values ​​of all features within this feature group were normalized to the [0,1] interval. Based on the aforementioned test threshold, the TER and OVR curves dynamically change with adjustments to the threshold. Furthermore, by comparing the calculated Abnormal Grain Proportion with the overall data, it was found that this proportion changes with the threshold used for binary decision-making. Figure 8 Experimental curves show that we achieved superior results at a specific quantization threshold. This approach significantly reduces testing costs while maintaining test quality. Experimental results show that the average test escape rate for this group is 0.0612%, and the overtest rate is 0.298%.

[0107] With the increasing complexity and stringent specifications of integrated circuits, optimizing chip testing quality has become a key challenge. This research focuses on the primary electrical testing stage of wafer testing—Wafer Acceptance Testing (WAT)—and improves overall testing quality through data processing and defective die detection technologies. In high-dimensional WAT parameter feature processing, approximately 50.9% feature dimensionality reduction was achieved, significantly reducing the computational and cost overhead of subsequent testing. Simultaneously, the application of Artificial Neural Networks (ANNs) for accurate classification of abnormal dies became a core means of improving testing quality. This solution effectively balances the needs of testing quality (yield assurance) and cost control, significantly reducing unnecessary testing costs while ensuring testing quality.

[0108] The present invention has been described by way of example. Obviously, the specific implementation of the present invention is not limited to the above-described manner. Any non-substantial improvements made using the inventive concept and technical solution of the present invention, or the direct application of the inventive concept and technical solution of the present invention to other occasions without modification, are all within the protection scope of the present invention.

Claims

1. A method for identifying anomalous grains in wafer acceptance testing based on spatial correlation, characterized in that, The method is as follows: (1) Identify the first test point in the wafer acceptance test where electrical parameters are missing, and fill in the missing electrical parameters of the first test point based on wafer space correlation; (2) Group the electrical parameter features, filter the key electrical parameter features in each group, and identify abnormal test points based on the key electrical parameter features in each group; (3) The anomaly type of the test point that detects anomalies, including test escape or overtesting; The specific method for filling in the missing electrical parameters at the first test point is as follows: (11) Based on the distribution of the first test point on the standard radius, the wafer is divided into three regions: the wafer edge region, the wafer middle region, and the wafer center region. (12) Calculate the standardized radius of each first test point and determine the area where each first test point is located; (13) Take neighborhood sampling points in the area where each first test point is located, determine the interpolation weight based on the distance between the first test point and each neighborhood sampling point, and use the weighted average of the electrical parameters of each neighborhood sampling point as the missing electrical parameters of the corresponding first test point; The specific process for obtaining key electrical parameter characteristics is as follows: (21) Treat each electrical parameter as an electrical parameter feature, group different electrical parameter features with the same unit into the same group, calculate the mutual information between each electrical parameter feature in the group, and form the mutual information matrix M for each group; (22) Determine the key electrical parameters in the corresponding group of electrical parameter characteristics based on the mutual information matrix M; The specific methods for obtaining the key electrical parameters of the mutual information matrix M are as follows: (221) Calculate the centrality score of each electrical parameter feature within the group. The centrality score of an electrical parameter feature is the sum of the mutual information between the electrical parameter feature and all other electrical parameter features within the group. (222) The average of the centrality scores of all electrical parameter features within a group is used as the threshold, and electrical parameter features with centrality scores higher than the threshold are included in the candidate electrical parameter feature set; (223) Extract the mutual information submatrix M_sub containing only the candidate electrical parameter features from the mutual information matrix M corresponding to the electrical parameter features of this group; (224) Convert the mutual information submatrix M_sub into the distance matrix D, and divide the candidate electrical parameter features into two clusters based on the distance threshold; (225) Detect the number of candidate electrical parameter features in two clusters. For clusters where the number of candidate electrical parameter features is less than the set number min_size, retain all candidate electrical parameter features in the corresponding cluster as key electrical parameter features. For clusters where the number of candidate electrical parameter features is less than the set number min_size, retain the candidate electrical parameter feature with the highest centrality score in the corresponding cluster as key electrical parameter features.

2. The method for identifying anomalous grains in wafer acceptance testing based on spatial correlation as described in claim 1, characterized in that, Electrical parameters of i first test points The specific calculation formula is as follows: ； ； ； in, This represents the difference weight of the j-th neighboring sampling points of the i-th first test point. This represents the electrical parameters of the j-th neighboring sampling point of the i-th first test point. Indicates the number of neighboring sampling points. This represents the Euclidean distance between the i-th first test point and its j-th neighboring sample points. This is the distance attenuation coefficient. This represents the position coordinates of the j-th neighboring sampling point of the i-th first test point. This represents the position coordinates of the i-th first test point; Number of neighboring sampling points in different regions and distance attenuation coefficient different.

3. The method for identifying anomalous grains in wafer acceptance testing based on spatial correlation as described in claim 1, characterized in that, The clustering method based on distance thresholds is as follows: In the distance matrix D, those whose distance is greater than the distance threshold 1-t are grouped into one cluster, and those whose distance is less than the distance threshold 1-t are grouped into another cluster.

4. The method for identifying anomalous grains in wafer acceptance testing based on spatial correlation as described in claim 1, characterized in that, The specific method for identifying abnormal test points based on the key electrical parameter characteristics in each group is as follows: The vectors corresponding to the key electrical parameter features of each group are standardized and input into the stacked autoencoder. The stacked autoencoder outputs the vectors corresponding to the key electrical parameter features reconstructed in the corresponding group. Test points with large reconstruction errors are identified as abnormal test points.

5. The method for identifying abnormal grains in wafer acceptance testing based on spatial correlation as described in claim 4, characterized in that, Reconstruction error at each test point The specific calculation formula is as follows: ； in, This represents the mean of the centrality scores of all key electrical parameters within group g. Indicates the number of groups. Indicates the first The vector corresponding to the key electrical parameter features of the group. The first step represents the reconstruction of the stacked autoencoder. The vector corresponding to the key electrical parameters of the group.

6. The method for identifying anomalous grains in wafer acceptance testing based on spatial correlation as described in claim 1, characterized in that, The vectors corresponding to the key electrical parameter features of the abnormal test points are input into the ANN model, and the ANN model outputs the abnormality type of the abnormal test points.

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