A method for automatic discovery and dynamic address assignment of 485 bus devices

Abstract

The application relates to the technical field of address allocation, in particular to a 485 bus equipment automatic discovery and dynamic address allocation method, wherein a host verifies a broadcast address and transmits an instruction to a bus, a slave time-delay response is captured to establish a response queue, intensive signals are analyzed and conflict fragments are stripped, a sampling generation rhythm map is dynamically adjusted, an address instruction is issued according to sequencing, the slave checks and updates and returns a feedback, the host collects and generates an allocation table, signal drift is monitored and timing parameters are adjusted, a response period is reconfigured, a synchronization state is updated and record is completed. According to the application, a mapping mechanism based on broadcast response timing is established, stable node differentiation is obtained through multi-dimensional signal analysis, independent extraction and sequence self-checking are realized through differentiated allocation and dynamic sampling, an adaptive communication structure is constructed, pairing and rhythm coordination are uniformly identified in address allocation, self-organizing capability is significantly improved, concurrent conflict is reduced and precision is improved, and communication consistency and efficient automatic addressing in a dynamic environment are ensured.

Description

Technical Field

[0001] This invention relates to the field of address allocation technology, and in particular to a method for automatic discovery and dynamic address allocation of 485 bus devices. Background Technology

[0002] Address allocation technology encompasses the process of configuring and managing unique addresses for various device nodes in a communication network. Its core components include address application, address detection, address conflict resolution, and unique address confirmation. This technology is typically applied in multi-node bus communication systems. By establishing address identification mechanisms at the physical and communication protocol layers, it achieves unique identification and orderly communication for device nodes within the network. In RS-485 communication systems, to ensure normal communication, each terminal device needs to maintain a unique, non-repeating address. Currently, most RS-485 terminal devices rely on manual address allocation, and their initial addresses are often uniform at the factory. When the number of terminals is large, addresses must be configured for each device individually, ensuring non-repeating addresses. This method relies on manual operation, is inefficient, and prone to errors.

[0003] The automatic discovery and dynamic address allocation method for RS485 bus devices refers to a technical solution for multi-node devices using RS485 bus communication structure. It provides a solution that can automatically detect the existence of the device when it is powered on or connected to the bus, and complete the unique address allocation without manual settings. It mainly covers technical aspects such as bus signal polling detection, device response information capture, device identification code comparison and address generation rule setting. By configuring a query mechanism on the communication host and setting response logic on the slave, the automatic identification and address registration of newly connected devices can be achieved, thereby completing the dynamic address allocation process of the device at the system level.

[0004] Existing technologies rely on fixed broadcasts and manual verification in node address management, lacking the ability to dynamically analyze differences in node responses and signal distribution characteristics. When multiple nodes respond to broadcasts simultaneously, the host struggles to distinguish the corresponding node based on signal arrival patterns, easily leading to overlapping responses and disordered allocation. The address detection process lacks self-calibration and time mapping mechanisms, resulting in frequent problems such as disordered response order and unclear node identification. When devices are frequently connected or the communication environment is complex, the system is prone to address drift and timing misalignment, reducing communication stability and increasing the time consumption for reconfiguration and troubleshooting, thus limiting the automation and real-time configuration capabilities under multi-node bus structures. Summary of the Invention

[0005] To address the technical problems existing in the prior art, this invention provides a method for automatic discovery and dynamic address allocation of 485 bus devices. The technical solution is as follows:

[0006] An automatic discovery and dynamic address allocation method for 485 bus devices includes the following steps:

[0007] S1: Obtain the host broadcast request and verify the validity of the broadcast address, write it to the send buffer and increment the request number, set the signal type and confirm that the port is idle, send the task to the 485 bus and record the result, and generate the host broadcast signal record table.

[0008] S2: According to the instruction transmission timing in the host broadcast signal record table, the host switches to the listening mode, each slave node parses the broadcast number and generates a differentiated delay before sending a response, the host parses the identification code and verifies the timing, establishes a response queue and organizes the time period information, and generates a node response time distribution table.

[0009] S3: Based on the distribution range and time domain characteristics of the response signal in the node response time distribution table, select the dense response period, perform timing and waveform detection on the slave response signal, identify and separate conflict response segments, dynamically adjust the sampling frequency to extract independent data, and generate a node response rhythm mapping table.

[0010] S4: Based on the slave node identification code and response timing parameters in the node response rhythm mapping table, establish an addressing sequence and bind the slave node's identification code and allocation number, issue address commands in sequence, the slave verifies and updates its local address and sends an acknowledgment, and generates a device dynamic address allocation table.

[0011] As a further embodiment of the present invention, the host broadcast signal recording table includes broadcast number information, broadcast address parameters, signal transmission status, transmission stability data, and recording time identifier; the node response time distribution table includes node response interval, response signal timing parameters, node identification number, response strength index, and time domain distribution characteristics; the node response rhythm mapping table includes node rhythm parameters, signal waveform characteristics, sampling frequency setting, time domain change law, and response synchronization characteristics; and the device dynamic address allocation table includes node identification information, dynamic address number, allocation order parameters, address binding relationship, and acknowledgment data.

[0012] As a further aspect of the present invention, the step of obtaining S1 is as follows:

[0013] S101: Obtain the broadcast request information from the host sender, extract the fixed broadcast address, perform byte-by-byte verification and comparison on the address field, match the verified address segment with the number field in the control register, and after confirming a successful match, write the matching data into the send buffer and mark the write status. At the same time, record the current request number index and generate the address write index sequence.

[0014] S102: Write the index sequence according to the address, call the signal type register bit in the control unit, set the transmission flag to a high level, detect the occupancy status of the communication port and compare it with the port occupancy reference value. After determining that the port is idle, start the transmission task, push the broadcast instruction data in the buffer to the 485 bus interface in byte order, record the stable changes of the output signal level, and obtain the stable range of the output signal.

[0015] S103: Based on the stable range of the output signal, call the broadcast number sequence in the transmission record buffer, compare the number order with the transmission completion flag, filter out the completed broadcast number data, sort them in ascending order by number and write them into the broadcast record area, establish the correspondence between the number index and the timestamp, and generate the host broadcast signal record table.

[0016] As a further aspect of the present invention, the step of obtaining S2 is as follows:

[0017] S201: Obtain instruction transmission timing data from the host broadcast signal record table, switch the host to monitoring mode, continuously monitor the 485 bus feedback signal, identify the frequency band of signal level change and calculate its duration, register the signal band data within the stable period with the instruction number time node, establish the correspondence sequence between signal and number, and generate the feedback signal time interval.

[0018] S202: Based on the feedback signal time interval, each slave node parses the received broadcast number and extracts the identification information. Using the difference between the identification number and the broadcast number as a benchmark, the internal timing circuit is triggered to form the response delay period of each node. The time difference is calculated for the delay period of all nodes, and the node pairs with adjacent delay times are selected and the relative timing interval is recorded to obtain the node response delay interval.

[0019] S203: Based on the node response delay interval, the host captures the response signal returned by the slave, performs a matching comparison between the identification code in the response signal and the broadcast request number, calculates the arrival distance of the successfully matched signals, arranges them in ascending order of arrival distance to form a response sequence, and summarizes and records the start and end time data of each response according to the node identification code to generate a node response time distribution table.

[0020] As a further aspect of the present invention, the step of obtaining S3 is as follows:

[0021] S301: Obtain the distribution range and time-domain characteristic data of the response signal in the node response time distribution table. The host filters the time intervals in which the response signals arrive densely. It compares the arrival time of each response signal in the interval with the average time interval to determine the concentration of signal arrival and extracts the start and end time nodes of the dense segment to generate the boundary interval of the key time period.

[0022] S302: Based on the boundary interval of key time period, the host calls the recorded response signal sequence of slave node, compares the waveforms of the response signal samples in the interval according to the sampling order, judges the overlapping or conflicting areas according to the waveform amplitude change and sampling interval, strips the detected overlapping bands and rearranges the response signal order to obtain the node independent response sample group;

[0023] S303: Based on the independent response sample group of the nodes, the host detects the amplitude change trend of the response signal in the time domain, compares the waveform continuity between adjacent samples, calculates the interval ratio and time allocation difference between signals, adjusts the sampling frequency and interval, recalibrates the response start and end sequence corresponding to each slave node, and generates a node response rhythm mapping table.

[0024] As a further aspect of the present invention, the step of obtaining S4 is as follows:

[0025] S401: Obtain the slave node identification code and corresponding response timing parameters from the node response rhythm mapping table. The host sorts all identification codes according to the response time sequence, extracts the start and end time of each node's response and calculates the time interval, arranges the time interval data in ascending order to form an address sequence index, and binds it to the identification code to generate an address sequence index set.

[0026] S402: Based on the address sequence index set, the host generates an allocation number for each slave node, combines the allocation number with the corresponding identification code to form an address instruction unit, verifies the continuity of all instruction unit sequence numbers and corrects the number spacing, writes the instruction units into the communication task buffer according to the address sequence order, and generates an address instruction sorting set.

[0027] S403: Based on the address instruction sorting set, the host sends instructions sequentially in the communication channel. After receiving the instructions, the slave compares the instruction identification information with the local identification code and records the matching result. When the comparison values ​​match, the local address is updated and an acknowledgment signal is returned. The host records the node information and summarizes the acknowledgment sequence according to the order of the acknowledgment signals to generate a device dynamic address allocation table.

[0028] As a further aspect of the present invention, the method further includes:

[0029] S5: Based on the dynamic address, allocation order and corresponding communication timing parameters of the slave nodes in the device dynamic address allocation table, monitor the address confirmation signals returned by each slave node, compare the arrival order of the receipts and correct the response drift, perform timing position adjustment for slave nodes that are detected to have response offset or time drift, recalibrate the communication rhythm parameters of the slave nodes and update the synchronization status, and generate a node address synchronization status table.

[0030] The node address synchronization status table includes the node dynamic address, communication timing parameters, synchronization offset, rhythm correction parameters, and status record information.

[0031] As a further aspect of the present invention, the step of obtaining S5 is as follows:

[0032] S501: Obtain the dynamic address, allocation order and communication timing parameters of the slave nodes in the device dynamic address allocation table. The host monitors the address confirmation signal returned by each slave node, compares the arrival time of the confirmation signal with the corresponding communication timing reference value, calculates the acknowledgment offset of each node and marks the data segments that exceed the time threshold. The offset results obtained from the comparison are sorted by node number to generate the node response offset sequence.

[0033] S502: Based on the node response offset sequence, the host reads the corresponding communication timing parameters of the slave node with response offset, calculates the time drift and compares it with the set timing reference interval, determines the offset direction and magnitude, adjusts the timing position of the node in the addressing sequence, reorders the adjustment results to form a corrected communication rhythm record, and obtains the node communication rhythm matrix.

[0034] S503: Based on the node communication rhythm matrix, the host identifies the matching relationship between the dynamic address of each slave node and the corresponding response time period, performs synchronization status determination on the updated rhythm parameters, extracts the timing synchronization flag of each slave and summarizes it to the control terminal, establishes a synchronization status index and records it in the terminal status buffer, and generates a node address synchronization status table.

[0035] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0036] In this invention, by establishing a node information extraction and rhythm mapping mechanism based on broadcast response timing, the host can obtain stable node response differentiation results under multi-dimensional analysis of signal distribution patterns and waveform characteristics. By utilizing differentiated time allocation strategies and dynamic sampling adjustment methods, independent extraction and sequence self-correction of node response data are achieved, forming an adaptively updatable communication order structure. In the process of address allocation and synchronization, the system achieves the unification of node identification, time-domain pairing, and rhythm coordination, significantly improving self-organization capability and communication stability, reducing response congestion and signal conflicts when multiple nodes are concurrent, improving allocation accuracy and response reliability, and enabling the system to maintain continuous communication consistency and efficient automatic addressing performance under dynamic node changes and address reconstruction conditions. Attached Figure Description

[0037] Figure 1 This is a flowchart of the method of the present invention;

[0038] Figure 2 This is a flowchart illustrating the process of obtaining the host broadcast signal record table of the present invention.

[0039] Figure 3 This is a flowchart illustrating the process of obtaining the node response time distribution table in this invention.

[0040] Figure 4 This is a flowchart illustrating the process of obtaining the node response rhythm mapping table in this invention.

[0041] Figure 5 This is a flowchart illustrating the process of obtaining the dynamic address allocation table for the device in this invention.

[0042] Figure 6 This is a flowchart illustrating the process of obtaining the node address synchronization status table in this invention. Detailed Implementation

[0043] The technical solution of the present invention will now be described with reference to the accompanying drawings.

[0044] In embodiments of the present invention, words such as "exemplarily," "for example," etc., are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" in the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present the concept in a concrete manner. Furthermore, in embodiments of the present invention, the meaning expressed by "and / or" can be both, or either one.

[0045] In the embodiments of this invention, the terms "image" and "picture" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, they convey the same meaning. Similarly, the terms "of," "corresponding (relevant)," and "corresponding" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, they convey the same meaning.

[0046] In this embodiment of the invention, sometimes a subscript such as W1 may be written in a non-subscript form such as W1. When the difference is not emphasized, the meaning they express is the same.

[0047] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0048] Please see Figure 1 This invention provides a technical solution: an automatic discovery and dynamic address allocation method for 485 bus devices, comprising the following steps:

[0049] S1: Obtain the broadcast request information from the host transmitter, extract the fixed broadcast address, verify the validity of the address field, write the address data into the transmission buffer and record the writing status, increment the request number sequentially and load it into the control register, set the signal type and activate the transmission flag in the control unit, detect the occupancy status of the communication port and confirm that it is idle, start the transmission task to transmit the buffer instructions to the 485 bus interface one by one, detect the stability of the output signal level and record the transmission results, organize and archive the transmitted broadcast instruction numbers, and generate the host broadcast signal record table.

[0050] S2: According to the instruction transmission timing in the host broadcast signal record table, the host switches to listening mode and monitors the 485 bus feedback signal. Each slave node parses the received broadcast number and extracts its own identification information. Based on the identification number, it triggers the internal timing circuit to generate differentiated response waiting time. After the delay ends, the response data frame is sent to the 485 bus in sequence. The host captures the response signal returned by the slave node, parses the identification code in the response signal, and performs timing verification on the response signal in combination with the instruction transmission timing. The identification code is associated and matched with the broadcast request number. A response queue is established according to the order of arrival of the response signals. The response time period information of each slave node is recorded and classified, and a node response time distribution table is generated.

[0051] S3: Based on the distribution range and time-domain characteristics of the response signals in the node response time distribution table, the host selects the time interval with dense arrival of response signals as the key analysis period, calls the recorded slave node response signal sequence, performs time sequence detection on the response signal samples in the key analysis period, compares the changing trend of the response signal waveform and the sampling order, identifies and removes overlapping or conflicting response segments, performs coherence verification on the differences of response signals of different slave nodes, dynamically adjusts the sampling frequency and interval according to the detected time-domain characteristics, re-extracts the independent response data of each slave node, updates the signal sorting and matching relationship, and generates a node response rhythm mapping table;

[0052] S4: Based on the slave node identification code and corresponding response timing parameters in the node response rhythm mapping table, the host extracts all identified slave node information, establishes an addressing sequence according to the order of slave node response times, binds the identification information of each slave node with the newly generated allocation number to form an address instruction set, and sends address instructions one by one in the communication channel according to the addressing sequence. After receiving the instruction, the slave compares the identification information in the instruction with the identification code stored locally to confirm consistency. After the verification is successful, the slave updates the local address and returns an address confirmation receipt. The host records the receipt order and result of each slave node, collects all receipt information to generate an allocation list, and generates a device dynamic address allocation table.

[0053] S5: Based on the slave node dynamic address, allocation order, and corresponding communication timing parameters in the device dynamic address allocation table, the host monitors the address confirmation signals returned by each slave node, compares the arrival order of the acknowledgments according to the allocation order and the predetermined communication timing parameters, performs timing position adjustment on slave nodes that are detected to have response offset or time drift, recalibrates the communication rhythm parameters of the slave nodes, so that the dynamic address of the slave node is rematched with the response time period. After the adjustment is completed, the host updates the synchronization status of each slave node and records it to the control terminal, generating a node address synchronization status table.

[0054] The host broadcast signal record table includes broadcast number information, broadcast address parameters, signal transmission status, transmission stability data, and recording time identifier. The node response time distribution table includes node response interval, response signal timing parameters, node identification number, response strength index, and time domain distribution characteristics. The node response rhythm mapping table includes node rhythm parameters, signal waveform characteristics, sampling frequency settings, time domain variation patterns, and response synchronization characteristics. The device dynamic address allocation table includes node identification information, dynamic address number, allocation order parameters, address binding relationship, and acknowledgment data. The node address synchronization status table includes node dynamic address, communication timing parameters, synchronization offset, rhythm correction parameters, and status record information.

[0055] Please see Figure 2 The steps to obtain S1 are as follows:

[0056] S101: Obtain the broadcast request information from the host sender, extract the fixed broadcast address, perform byte-by-byte verification and comparison on the address field, match the verified address segment with the number field in the control register, and after confirming a successful match, write the matching data into the send buffer and mark the write status. At the same time, record the current request number index and generate the address write index sequence.

[0057] Upon receiving a broadcast request from the host, the host uses the Direct Memory Access (DMA) controller to read a 64-byte data frame starting at address 0x2000 from memory. The host performs a pointer offset operation to read the two-byte fields at offsets 0x02 and 0x03 as the address to be verified. The standard broadcast address parameter is set to 0xFFFF. The host then calls the Arithmetic Logic Unit (ALU) to perform a bitwise XOR operation between the extracted address to be verified and the standard broadcast address parameter. If the result is 0x0000, the address field is considered valid; otherwise, it is considered an illegal request, triggering an interrupt, writing an exception code to the error log register, and terminating the current process. When the address is valid, the host immediately reads the number field register at address 0x4004 in the control register area to obtain the current memory address. The request number value stored, for example, 0x0A, is compared with the sequence number byte in the broadcast request header. If the two values ​​are equal, the sequence number is confirmed to be matched successfully. The host starts the direct memory access transmission channel and copies the data frame starting at address 0x2000 byte by byte to the transmit buffer starting at address 0x6000. After each byte is copied, a binary value of 1 is written to the corresponding bit in the status register 0x6040 to mark the write status, until all 64 bytes are transmitted. The host reads the current request number value 0x0A and converts it into a hexadecimal index value. This index value is stored at the tail position of the address write index sequence. For example, if the index sequence currently contains [0x08, 0x09], the updated sequence will be [0x08, 0x09, 0x0A], and the address write index sequence is generated.

[0058] S102: Write the index sequence according to the address, call the signal type register bit in the control unit, set the transmission flag to a high level, detect the occupancy status of the communication port and compare it with the port occupancy reference value. After determining that the port is idle, start the transmission task, push the broadcast instruction data in the buffer to the 485 bus interface in byte order, record the stable changes of the output signal level, and obtain the stable range of the output signal.

[0059] The host writes an index sequence based on the address. It reads the latest added index value, 0x0A, from the sequence and uses this index value to address the General Purpose Input / Output (GPIO) configuration register. It then locates the register bit for the transmit enable pin (DE / RE) of the RS-485 transceiver (such as the MAX485 chip) and writes a high-level logic value (1) to this register bit, putting the transceiver into transmit mode. The host continuously acquires the voltage values ​​of the communication port lines A and B through the differential signal conditioning circuit and high-precision analog-to-digital converter (ADC) connected to bus A and B. and The sampling period was set to 10 microseconds, and five consecutive sampling periods were collected. The absolute value of the differential voltage in each period was calculated. The port occupancy reference value is set to 0.2 volts. This reference value is based on the difference (±200mV) between the receive threshold voltage of logic 0 and logic 1 in the RS-485 standard. If the absolute value of the differential voltage for five consecutive cycles is less than 0.2 volts, the communication port is considered idle. If a voltage greater than 0.2 volts is detected in any cycle, the bus is considered busy, and a random backoff algorithm is executed to wait and retry. After determining that the port is idle, the host activates the Universal Asynchronous Receiver / Transmitter (UART), sets the baud rate to 9600bps, and allocates 0x6000 bytes to the transmit buffer. The instruction data is pushed into the transmit shift register byte by byte according to the frame format of start bit, data bit, parity bit, and stop bit. During the data push process, the host continuously monitors the voltage level of the transmit pin and records the moment when the level jumps from low level to high level and remains high for more than one byte transmission cycle as the starting stable point. The moment when the level returns to the idle state after the data is sent is recorded as the ending stable point. For example, the starting stable point is the clock counter value of 1000 and the ending stable point is the clock counter value of 5000, thereby defining the stable range of the output signal.

[0060] S103: Based on the stable range of the output signal, call the broadcast number sequence in the transmission record buffer, compare the number order with the transmission completion flag, filter out the completed broadcast number data, sort them in ascending order by number and write them into the broadcast record area, establish the correspondence between the number index and the timestamp, and generate the host broadcast signal record table.

[0061] Based on the stable range of the output signal, the host calls the transmission record buffer array residing in random access memory (RAM). This array contains multiple sets of structured data, each set containing a broadcast number, a transmission completion flag, and a transmission end timestamp. The host iterates through this array, extracts the transmission end timestamp of each set of data, and performs a numerical range determination between the output signal stable range [1000, 5000]. Records whose timestamp values ​​fall within this range are selected, for example, the record numbered 0x0A with a transmission completion flag of 1. The host then performs a bubble sort on the selected records. The algorithm compares the broadcast numbers of adjacent records. If the number of the previous record is greater than that of the next record, they are swapped to arrange the unordered records into an ascending sequence. The host allocates a broadcast record area in non-volatile memory (such as EEPROM or Flash), writes the sorted broadcast number 0x0A to the first address of the record area, and reads the timer count value driven by the internal high-frequency crystal oscillator corresponding to this transmission as a timestamp. A key-value mapping relationship is established between the number 0x0A and the timestamp value. This mapping relationship is written into the data table structure row by row to generate the host broadcast signal record table.

[0062] Please see Figure 3 The steps to obtain S2 are as follows:

[0063] S201: Obtain instruction transmission timing data from the host broadcast signal record table, switch the host to monitoring mode, continuously monitor the 485 bus feedback signal, identify the frequency band of signal level change and calculate its duration, register the signal band data within the stable period with the instruction number time node, establish the correspondence sequence between signal and number, and generate the feedback signal time interval.

[0064] The host retrieves the instruction transmission timing data from the host broadcast signal record table. The host reads the broadcast end timestamp stored in the record table; for example, the recorded timestamp value is... At the microsecond level, the direction register of the microprocessor's general-purpose input / output port is switched from output mode to input mode, a timer is started to count, and the sampling frequency is set to 1MHz. The host continuously samples the differential voltage of ports A and B of the 485 bus through a differential probe circuit, storing the sampled values ​​in a circular buffer. The host executes edge detection logic to calculate the difference between the voltage values ​​of two adjacent sampling points. If the absolute value of the difference between three consecutive sampling points is greater than the preset logic threshold voltage of 200mV, a signal level change is detected, and this moment is recorded as the signal start point. Continue sampling until the absolute value of the difference between three consecutive sampling points is less than 50mV, and record this moment as the signal termination point. Calculate the difference between the two. As a duration, for example, if the starting point is measured to be 10500 microseconds, the ending point to be 10600 microseconds, and the duration to be 100 microseconds, the stable period baseline value is set to one complete byte transmission time for a baud rate of 9600bps;

[0065] The baseline value is set as follows In microseconds, the host computer compares the calculated duration with the stable period reference value. If the duration deviation is within... Within the range, then extract the to If the waveform data within a range deviates beyond the acceptable range, it is considered noise interference and the sampled segment is discarded. For valid segments, the host computer reads the instruction number and corresponding timestamp from the broadcast signal record table again, and sets the signal start point... With broadcast end timestamp Perform a difference operation. If the difference is within the preset timeout window of 500 milliseconds, then establish a key-value association between the memory address pointer of the signal waveform data segment and the instruction number 0x0A in the index table, and store them sequentially into the linked list structure in chronological order to generate the feedback signal time interval.

[0066] S202: Based on the feedback signal time interval, each slave node parses the received broadcast number and extracts the identification information. Using the difference between the identification number and the broadcast number as a benchmark, the internal timing circuit is triggered to form the response delay period of each node. The time difference is calculated for the delay period of all nodes, and the node pairs with adjacent delay times are selected and the relative timing interval is recorded to obtain the node response delay interval.

[0067] Based on the feedback signal time interval, each slave node reads the broadcast data frame through the bus receiver (Transceiver) and decodes it to obtain the broadcast number value. (For example, 0x0A, which is decimal 10) and the hardware identification number stored in the local ROM. (For example, slave A is 12 and slave B is 15), the slave microcontroller performs a subtraction operation. Calculate the difference between the identification number and the broadcast number. The difference is 2 for slave A and 5 for slave B. Then, call the preset time slice coefficient.

[0068] Milliseconds, the period for calculating response latency Slave A calculates 20 milliseconds, slave B calculates 50 milliseconds, and the slave node starts its internal hardware timer to load the data. The countdown begins, and the host computer simulates and calculates the theoretical latency values ​​for all potential nodes in the network, generating a set of latency values. In milliseconds, the host sorts the values ​​in the set and calculates the difference between adjacent values. Filter out For node pairs with a delay less than the minimum safe interval (e.g., set to 5 milliseconds), assuming there is a slave C with a calculation delay of 22 milliseconds, then the difference between slave A and slave C is 2 milliseconds, which is less than 5 milliseconds. The host records the node pair (slave A, slave C) and its relative timing interval of 2 milliseconds into the conflict warning register and sets the conflict flag to trigger time slot reallocation in subsequent steps. If there is no interval less than 5 milliseconds, the theoretical delay start and end points of each node are recorded. For example, the interval for slave A is [20, 30] milliseconds, and the interval for slave B is [50, 60] milliseconds, thus obtaining the node response delay interval.

[0069] S203: Based on the node response delay interval, the host captures the response signal returned by the slave, performs a matching comparison between the identification code in the response signal and the broadcast request number, calculates the arrival distance of the successfully matched signals, arranges them in ascending order of arrival distance to form a response sequence, and summarizes and records the start and end time data of each response according to the node identification code to generate a node response time distribution table.

[0070] Based on the node response delay interval, after the host captures the actual response data packet sent by the slave on the bus interface, it directly reads the source address field in the packet header as the identification code. For example, if the host captures a response signal with the identification code 0x0C (i.e., slave A), it uses the InputCaptureUnit to latch the arrival time of the signal's frame header. (e.g., 10025 milliseconds), read the end time of transmission corresponding to the broadcast request number. (e.g., 10000 milliseconds), perform subtraction. The arrival interval of a successfully matched signal is calculated to be 25 milliseconds. The host repeats the above calculation for multiple captured slave response signals, obtaining a series of arrival interval values, for example... In milliseconds, the host calls the quicksort algorithm to sort the set of values ​​in ascending order and updates it to... Milliseconds, corresponding to the identification code sequence is The host creates a structure array in memory, indexed by the identification code 0x0C, and writes the response start time. and the end time calculated based on the data frame length (ByteCount × 10 bits / baud rate) The complete response time records of each node are summarized, and a node response time distribution table is generated.

[0071] Please see Figure 4 The steps to obtain S3 are as follows:

[0072] S301: Obtain the distribution range and time-domain characteristic data of the response signal in the node response time distribution table. The host filters the time intervals in which the response signals arrive densely. It compares the arrival time of each response signal in the interval with the average time interval to determine the concentration of signal arrival and extracts the start and end time nodes of the dense segment to generate the boundary interval of the key time period.

[0073] The host retrieves the response signal distribution range and time-domain characteristic data from the node response time distribution table, reads the recorded time distribution table from memory, and extracts the response start time of all records. For example, extracting time series millisecond;

[0074] The host computer sets the sliding window size to The monitoring window moves within milliseconds, with a step size of 5 milliseconds, and counts the number of response signals falling into each window within the total monitoring period. If a certain window contains If the window contains a dense candidate region, then mark the window as a candidate dense region. If a signal falls within the interval [20,40] milliseconds, it is marked as a sparse region and skipped in subsequent processing to save computing power; for example, if three signals (25,28,30) fall within the interval [20,40] milliseconds, the host calculates the time difference between adjacent signals in the candidate dense region. To obtain the set of differences Milliseconds, the average time interval for calculation (Where k is the number of signals), the average interval is calculated to be 2.5 milliseconds. The density judgment benchmark is set to twice the single-byte transmission time (approximately 2 milliseconds). The host will calculate the arrival time difference of each response signal. Compared with the benchmark value, if If the signal arrival concentration is less than or equal to the baseline value, it is determined that the signal arrival concentration is high. The host extracts the first signal start time (25ms) of the continuous signal sequence that meets this condition as the starting point of the dense section. Extract the end time of the last signal (assuming the signal duration is 10ms, then it is 30+10=40ms) as the termination point. Generate boundary intervals for key time periods.

[0075] S302: Based on the boundary interval of key time period, the host calls the recorded response signal sequence of slave node, compares the waveforms of the response signal samples in the interval according to the sampling order, judges the overlapping or conflicting areas according to the waveform amplitude change and sampling interval, strips the detected overlapping bands and rearranges the response signal order to obtain the node independent response sample group;

[0076] Based on the key time period boundary interval, the host retrieves all original waveform data packets corresponding to the timestamp from the slave node response signal sequence buffer pool according to the interval range [25, 40] milliseconds. The host then reads the digitized waveform point set within this segment at a sampling rate of 1MHz. Perform a point-by-point scan on the waveform point set and calculate the rate of change of amplitude between adjacent sampling points. The collision detection threshold is set to 1.5 times the standard logic level transition slope (based on the bus capacitor charging and discharging characteristics). When a collision is detected... When the threshold is exceeded and the duration is less than half a bit cycle (approximately 52 microseconds), it is determined that there is signal superposition or phase conflict at that location. The host marks the index range of all waveform segments where conflicts occur, such as indices [500, 600] and [1200, 1300]. A digital filter algorithm (such as a finite impulse response filter, FIR) is called to zero out the abnormal waveform data within the marked range or to perform interpolation smoothing to remove overlapping bands and retain the complete data frames that are not disturbed. The host reads the frame header synchronization byte of each processed data frame, parses its corresponding slave identification code, and if a data frame with a certain identification code is found to be incomplete (length less than 64 bytes), it is discarded and the retransmission request flag is set, retaining the complete response data frame. According to the order of detection of the data frame header, the retained signals are renumbered and sorted. For example, if the original order is A, B, C (B and C overlap), after processing, it is confirmed to be A, B (C is discarded or retransmitted), thus obtaining the node independent response sample group.

[0077] S303: Based on the node independent response sample group, the host detects the amplitude change trend of the response signal in the time domain, compares the waveform continuity between adjacent samples, calculates the interval ratio and time allocation difference between signals, adjusts the sampling frequency and interval, recalibrates the response start and end sequence corresponding to each slave node, and generates a node response rhythm mapping table.

[0078] Based on the node-independent response sample groups, the host reads the waveform data retained in each sample group and calculates the average amplitude of the signal within the bit period. ,like If the voltage deviation from the standard voltage (3.3V or 5V) exceeds 10%, the signal is determined to have attenuation or interference. The host computer calculates the time interval between the end point and the start point of two adjacent independent samples. For example, if sample A ends at 35ms and sample B begins at 38ms, then Set the ideal protection interval to 5ms and calculate the interval ratio. ;

[0079] Calculate the time allocation difference ,because The host triggers an adjustment command from the sampling controller (ADCSamplingControlRegister) to increase the sampling frequency of the analog-to-digital converter from 1MHz to 2MHz to improve the time-domain resolution and shorten the start interval of subsequent sampling cycles. Value (2ms), if If the original sampling parameters remain unchanged, the host will re-measure the rising edge time of each slave node signal based on the adjusted sampling parameters, and use this as the new response start sequence. The host will write each slave identification code (e.g., ID=12) into the mapping table with the corrected response start time (e.g., 38ms) and end time (e.g., 48ms) to generate the node response rhythm mapping table.

[0080] Please see Figure 5 The steps to obtain S4 are as follows:

[0081] S401: Obtain the slave node identification code and corresponding response timing parameters from the node response rhythm mapping table. The host sorts all identification codes according to the response time sequence, extracts the start and end time of each node's response and calculates the time interval, arranges the time interval data in ascending order to form an address sequence index, and binds it to the identification code to generate an address sequence index set.

[0082] The host obtains the slave node identification code and corresponding response timing parameters from the node response timing mapping table. The host reads N sets of data from the mapping table (e.g., N=3, records are {ID:12,Start:38ms,End:48ms}, {ID:15,Start:25ms,End:35ms}, {ID:18,Start:52ms,End:62ms}). The host performs a sorting operation, reordering these three sets of data in ascending order based on the magnitude of the Start value of the response start time. The sorted result is {ID:15,25ms}, {ID:12,38ms}, {ID:18,52ms}. The host iterates through the sorted list and extracts the start time of each set of data. End time of the previous set of data (Set the first data reference point to 0), calculate the time interval. The interval sequence is obtained as follows: , , The host then performs another numerical comparison on the calculated interval sequence and rearranges the index order according to the interval value from smallest to largest (i.e., index 2 corresponds to 3ms and is ranked first, index 3 corresponds to 4ms and is ranked second, and index 1 corresponds to 25ms and is ranked third). The host establishes a pointer binding relationship between the sorted index positions and the original identification codes. For example, index 2 points to ID:12, index 3 points to ID:18, and index 1 points to ID:15. These binding relationships are stored sequentially into the lookup table structure in RAM to generate the address sequence index set.

[0083] S402: Based on the address sequence index set, the host generates an allocation number for each slave node, combines the allocation number with the corresponding identification code to form an address instruction unit, verifies the continuity of all instruction unit sequence numbers and corrects the number spacing, writes the instruction units into the communication task buffer according to the address sequence order, and generates an address instruction sorting set.

[0084] Based on the address sequence index set, the host starts an address generation counter, initially set to 0x01. It reads the bound identification codes sequentially according to the index set order. It reads the first ID: 12, assigns the current counter value of 0x01 as its new communication address, and increments the counter to 0x02. It then reads the second ID: 18, assigns address 0x02, and so on, until all indices have been traversed. The host then concatenates the assigned address (e.g., 0x01) with the corresponding identification code (e.g., ID: 12) into a 6-byte instruction unit (containing a start character, opcode, identification code, new address, and checksum). (Checksum), the host checks the new address field of all generated instruction units, calculates the difference between adjacent addresses. If the difference is always equal to 1, the sequence number continuity check is passed. If there is a gap in the sequence number with a difference greater than 1, the rollback mechanism is triggered to reset the counter to 0x01 and re-execute the allocation process. After the correction is correct, the host writes the generated instruction units into the first-in-first-out (FIFO) communication task buffer one by one according to the addressing sequence (i.e., first ID:12, then ID:18, and finally ID:15). A task priority mark is attached to the header of each instruction unit to generate an address instruction sorting set.

[0085] S403: According to the address instruction sorting set, the host sends instructions in sequence in the communication channel. After receiving the instructions, the slave compares the instruction identification information with the local identification code and records the matching result. When the comparison value is consistent, the local address is updated and an acknowledgment signal is returned. The host records the node information and summarizes the acknowledgment sequence according to the order of the acknowledgment signals to generate a device dynamic address allocation table.

[0086] According to the address instruction sequence set, the host reads the first instruction (address 0x01 for ID:12) from the head of the communication task buffer queue and sends the instruction frame through the 485 bus driver. The slave node receives the bus data and performs a bitwise XOR comparison between the identification code field in the instruction frame and the hardware ID in the local read-only memory. If the XOR result is all 0, it is determined to be a match. The slave immediately writes the new address 0x01 from the instruction into the local EEPROM address configuration area and sends a single-byte acknowledgment (ACK0x06) containing the new address to the bus. The host starts a receive timer to record the moment the ACK signal is received. If an acknowledgment is received within the timeout threshold of 200ms, the source address information in the acknowledgment (which should be 0x01 at this time) is read and compared with the target address in the sending record. After confirming that there is no error, the host writes the node's identification code, the newly allocated address 0x01, and the acknowledgment reception time into a row of the data table. If no acknowledgment is received within 200ms or the address comparison is incorrect, the node is recorded as "allocation failed" and the retransmission mechanism is triggered to continue sending the next instruction until the buffer is cleared. The host then summarizes all the record data and generates the device dynamic address allocation table.

[0087] Please see Figure 6 The steps to obtain S5 are as follows:

[0088] S501: Obtain the dynamic address, allocation order and communication timing parameters of the slave nodes in the device dynamic address allocation table. The host monitors the address confirmation signal returned by each slave node, compares the arrival time of the confirmation signal with the corresponding communication timing reference value, calculates the acknowledgment offset of each node and marks the data segments that exceed the time threshold. The offset results obtained from the comparison are sorted by node number to generate the node response offset sequence.

[0089] The master node retrieves the slave node's dynamic address, allocation order, and communication timing parameters from the device's dynamic address allocation table, and extracts the theoretical response arrival time recorded in the table. (For example, node 0x01 is 100ms, node 0x02 is 120ms), the host captures the address acknowledgment signal (ACK frame) returned by each slave node in real time, and records its actual arrival time using the input capture unit (ICU). (For example, node 0x01 actually lasts 102ms, and node 0x02 actually lasts 125ms), the host performs a subtraction operation. Calculate the receipt offset, obtaining the offset of node 0x01 + 2ms and the offset of node 0x02 + 5ms. Set the maximum allowable deviation threshold as follows. (Based on the cumulative error tolerance setting for a single baud rate period), the host will calculate The host compares the values ​​with the threshold. For node 0x02, if the offset is 5ms greater than 3ms, the host marks it as "abnormal delay". For node 0x01, if the offset is 2ms less than 3ms, the host marks it as "normal". For nodes marked as "normal", the host directly retains their current timing parameters without further correction. The host iterates through all marked node data, sorts them in ascending order according to the value of the slave dynamic address (0x01, 0x02, ...), and fills the corresponding offset values ​​(+2ms, +5ms, ...) and status flags (normal, abnormal) into the linear list structure to generate the node response offset sequence.

[0090] S502: Based on the node response offset sequence, the host reads the corresponding communication timing parameters of the slave node with response offset, calculates the time drift and compares it with the set timing reference interval, determines the offset direction and magnitude, adjusts the timing position of the node in the addressing sequence, reorders the adjustment results to form a corrected communication rhythm record, and obtains the node communication rhythm matrix.

[0091] Based on the node response offset sequence, the host retrieves node entries marked as "abnormal" (e.g., node 0x02, offset +5ms), reads the node's preset communication time slot parameters in the allocation table (e.g., time slot length 20ms, guard interval 5ms), and calculates the time drift. That is, 5ms, the drift correction reference interval is set to [3ms, 10ms], and the host determines... If a node falls within this interval and its offset sign is positive (lagging), the host determines that the node's response is too slow. The host then invokes a timing adjustment algorithm to add a compensation value to the node's waiting time slot in the addressing sequence. The allocated time slot length is adjusted from 20ms to 26ms. Here, the coefficient 1.2 is a preset proportional-integral (PI) adjustment gain used to eliminate steady-state errors. If the offset sign is negative (leading), the pre-delay is increased. The host updates the theoretical response time of the node and its subsequent nodes based on the adjusted time slot parameters. For example, after node 0x02 is adjusted, the theoretical time of the subsequent node 0x03 is delayed from 140ms to 146ms. The host reorders the timing parameters of all nodes after the correction and writes the adjusted start and end times into a two-dimensional array to obtain the node communication rhythm matrix.

[0092] S503: Based on the node communication rhythm matrix, the host identifies the matching relationship between the dynamic address of each slave node and the corresponding response time period, performs synchronization status determination on the updated rhythm parameters, extracts the timing synchronization flag of each slave and summarizes it to the control terminal, establishes a synchronization status index and records it in the terminal status buffer, and generates a node address synchronization status table.

[0093] According to the node communication rhythm matrix, the host reads the dynamic address (e.g., 0x02) and the corrected response time period (e.g., [126ms, 152ms]) corresponding to each row in the matrix, and sends a "timing synchronization" command packet to each slave. This command packet contains the adjusted time slot length and offset compensation value. After receiving and applying the new parameters, the slave returns a "synchronization complete" signal. The host receives this signal and parses the status bit. If the status bit is 0xAA (indicating that the clock has been calibrated), the host extracts the status code and compares it with the preset synchronization success code in memory. If they are equal, the synchronization status flag is set to "synchronized (1)"; otherwise, it is set to "not synchronized (0)". If three consecutive synchronization attempts return "not synchronized", the host reports an error to the system. The host uses the dynamic addresses (0x01, 0x02, 0x03...) of all slaves as index keys, uses the corresponding synchronization status flags (1, 1, 0...) as values, constructs a hash mapping table, and uploads the data stream of the mapping table to the display buffer of the host computer control terminal through a serial interface (such as USB or UART) to generate a node address synchronization status table.

[0094] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for automatic discovery and dynamic address assignment of 485 bus devices, characterized in that, The method comprises the following steps: S1: obtaining a host broadcast request and checking the validity of the broadcast address, writing into a sending buffer and incrementing the request number, setting the signal type and confirming the port idle, sending the task to the 485 bus and recording the result, generating a host broadcast signal record table; S2: according to the instruction transmission time sequence in the host broadcast signal record table, the host switches the listening mode, each slave node analyzes the broadcast number and generates a differentiated delay before sending a response, the host analyzes the identification code and checks the time sequence, establishes a response queue and arranges the time period information, and generates a node response time distribution table; S3: according to the response signal distribution interval and time domain characteristics in the node response time distribution table, the response dense period is selected, the time sequence and waveform of the slave response signal are detected, the conflict response segment is identified and stripped, the sampling frequency is dynamically adjusted to extract independent data, and a node response rhythm mapping table is generated; S4: according to the slave node identification code and response time sequence parameters in the node response rhythm mapping table, an addressing sequence is established, and the identification code and allocation number of the slave node are bound, and the address instruction is sequentially issued, the slave node checks and updates the local address and returns the receipt, and a device dynamic address allocation table is generated.

2. The method for automatic discovery and dynamic address assignment of 485 bus devices according to claim 1, characterized in that: The host broadcast signal record table includes broadcast number information, broadcast address parameters, signal sending state, transmission stability data and record time identifier, the node response time distribution table includes node response interval, response signal time sequence parameter, node identification number, response intensity index and time domain distribution characteristics, the node response rhythm mapping table includes node rhythm parameter, signal waveform characteristics, sampling frequency setting, time domain variation law and response synchronization characteristics, and the device dynamic address allocation table includes node identification information, dynamic address number, allocation sequence parameter, address binding relationship and confirmation receipt data.

3. The method for automatic discovery and dynamic address assignment of 485 bus devices as claimed in claim 1 wherein: The acquisition step of S1 is: S101: obtaining the broadcast request information of the host sending end, extracting the fixed broadcast address, performing byte-by-byte comparison and verification on the address field, performing sequence number matching between the verified address segment and the number field in the control register area, confirming the matching success, writing the matching data into the sending buffer and marking the writing state, recording the current request number index at the same time, and generating an address writing index sequence; S102: according to the address writing index sequence, calling the signal type register bit in the control unit, setting the sending identifier to high level state, detecting the occupation state of the communication port and comparing with the port occupation reference value, judging that the port is idle, starting the sending task, pushing the broadcast instruction data in the buffer to the 485 bus interface in byte order, recording the stable change of the output signal level, and obtaining the output signal stable interval; S103: based on the output signal stable interval, calling the broadcast number sequence in the transmission record buffer, comparing the number sequence and the transmission completion flag bit, screening out the completed broadcast number data, arranging in ascending order after writing into the broadcast record area, establishing the correspondence between the number index and the time stamp, and generating a host broadcast signal record table.

4. The method for automatic discovery and dynamic address assignment of 485 bus devices as claimed in claim 1 wherein: The acquisition step of S2 is: S201: Obtain instruction transmission timing data in the host broadcast signal record table, the host switches to a listening mode, continuously monitors a 485 bus feedback signal, identifies a signal level change frequency band and calculates a duration, registers signal band data in a stable period with instruction number time nodes, establishes a corresponding sequence of signals and numbers, and generates a feedback signal time interval; S202: According to the feedback signal time interval, each slave node parses the received broadcast number and extracts identification information, takes the difference value of the number relative to the broadcast number as the reference, triggers the internal timing circuit to form the response delay period of each node, performs time difference calculation on the delay period of all nodes, screens the node pairs with adjacent delay times and records the relative time interval, and obtains the node response delay interval; S203: Based on the node response delay interval, the host captures the response signal returned by the slave, performs matching comparison on the identification code in the response signal and the broadcast request number, calculates the arrival interval of the matching successful signal, arranges the response sequence in ascending order of the arrival interval, and records the start and end time data of each response according to the node identification code, and generates a node response time distribution table.

5. The method for automatic discovery and dynamic address assignment of 485 bus devices as claimed in claim 1, wherein: The acquisition step of S3 is: S301: Obtain the response signal distribution interval and time domain feature data in the node response time distribution table, the host selects the time interval at which the response signals are densely arrived from the node response time distribution table, compares the arrival time of each response signal in the interval with the average time interval, judges the concentration degree of the signal arrival and extracts the start and end time nodes of the dense section, and generates a key time period boundary interval; S302: Based on the key time period boundary interval, the host calls the recorded slave node response signal sequence, performs waveform comparison on the response signal samples in the interval according to the sampling order, judges the overlapping or conflict area according to the waveform amplitude change and sampling interval, rearranges the response signal order after stripping the detected overlapping band, and obtains a node independent response sample group; S303: According to the node independent response sample group, the host detects the amplitude change trend of the response signal in the time domain, compares the waveform continuity between adjacent samples, calculates the interval ratio and time allocation difference between the signals, adjusts the sampling frequency and interval, recalibrates the response start and end sequence corresponding to each slave node, and generates a node response rhythm mapping table.

6. The method for automatic discovery and dynamic address assignment of 485 bus devices as claimed in claim 1, wherein: The acquisition step of S4 is: S401: Obtain the slave node identification code and corresponding response time sequence parameter in the node response rhythm mapping table, the host sorts all identification codes according to the response time, extracts the response start and end time of each node and calculates the time interval, arranges the time interval data in ascending order to form an addressing sequence index, and binds the identification code, and generates an addressing sequence index set; S402: Based on the addressing sequence index set, the host generates an allocation number for each slave node, combines the allocation number with the corresponding identification code to form an address instruction unit, reviews the continuity of all instruction unit numbers and corrects the number interval, writes the instruction unit into the communication task buffer area according to the addressing sequence order, and generates an address instruction sorting set; S403: According to the address instruction sorting set, the host sequentially issues instructions in the communication channel, and the slave receives and compares the instruction identification information with the local identification code and records the matching results. When the comparison value is consistent, the local address is updated and an acknowledgement signal is returned. The host records the node information according to the order of the return signal and summarizes the return sequence to generate a device dynamic address allocation table.

7. The method for automatic discovery and dynamic address assignment of 485 bus devices as claimed in claim 1, wherein: The method further comprises: S5: Based on the slave node dynamic address, allocation sequence and corresponding communication timing parameters in the device dynamic address allocation table, the address confirmation signals returned by each slave node are monitored, and the response drift is corrected compared with the return order. The timing position of the slave node detected to have response drift or time drift is adjusted, the communication rhythm parameters of the slave node are recalibrated, and the synchronization state is updated to generate a node address synchronization state table. The node address synchronization state table comprises node dynamic address, communication timing parameter, synchronization offset, rhythm correction parameter and state record information.

8. The method for automatic discovery and dynamic address assignment of 485 bus devices according to claim 7, characterized in that: The acquisition step of S5 is: S501: Acquire the slave node dynamic address, allocation sequence and communication timing parameter in the device dynamic address allocation table. The host monitors the address confirmation signals returned by each slave node, compares the arrival time of the confirmation signal with the corresponding communication timing reference value, calculates the response offset of each node and marks the data segment exceeding the time threshold, sorts the offset results obtained by comparison according to the node number, and generates a node response offset sequence; S502: Based on the node response offset sequence, the host reads the corresponding communication timing parameter of the slave node with response offset, calculates the time drift and compares it with the set timing reference interval, judges the offset direction and amplitude, adjusts the timing position of the node in the addressing sequence, reorders the adjustment result to form the corrected communication rhythm record, and obtains the node communication rhythm matrix; S503: According to the node communication rhythm matrix, the host calibrates the matching relationship between the dynamic address of each slave node and the corresponding response period, judges the synchronization state of the updated rhythm parameter, extracts the timing synchronization flag of each slave and summarizes it to the control terminal, establishes the synchronization state index and records it to the terminal state buffer area, and generates a node address synchronization state table.

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