A back-contact tandem solar cell, its fabrication method, and a photovoltaic module.

Abstract

This application relates to a back-contact tandem solar cell, its fabrication method, and a photovoltaic module, belonging to the field of photovoltaic technology. The back-contact tandem solar cell includes a back-contact bottom cell and a perovskite top cell, with the perovskite top cell electrically connected to the front side of the back-contact bottom cell via an interconnect layer. The back-contact bottom cell includes a substrate, and the perovskite top cell includes an electron transport layer, a perovskite layer, and a hole transport layer sequentially disposed on the interconnect layer. The surface of the substrate facing the perovskite layer has a textured structure, so that the surfaces of the interconnect layer and the electron transport layer facing the perovskite top cell also have textured structures. The textured structure includes multiple pyramidal structures, and the surface of the pyramidal structures includes multiple recessed structures. The perovskite precursor liquid is guided downward by the recessed structures, promoting the uniform spreading of the perovskite precursor liquid on the surface of the electron transport layer, reducing the risk of pinholes in the perovskite layer, and improving the quality of the perovskite layer.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and in particular to a back-contact tandem cell, its preparation method, and a photovoltaic module. Background Technology

[0002] Traditional back-contact solar cells are completely metal-free solar cells on the front. In back-contact stacked structures, perovskite cells need to be deposited on the back contact cell to achieve higher photoelectric conversion efficiency. Although the standard pyramidal textured surface inside the back contact cell is beneficial for light trapping in the silicon cell itself, it can lead to difficulties in coating the perovskite solution during the fabrication of the perovskite layer. This results in uneven perovskite film coverage, a risk of pinholes, and ultimately, poor perovskite film quality. Summary of the Invention

[0003] This application provides a back-contact tandem solar cell, its fabrication method, and a photovoltaic module, which addresses the problem of poor perovskite layer film quality in back-contact tandem solar cells.

[0004] The first aspect of this application provides a back-contact stacked battery, which includes a back-contact bottom battery and a perovskite top battery, wherein the perovskite top battery and the front side of the back-contact bottom battery are electrically connected via an interconnect layer.

[0005] The back-contact bottom cell includes a substrate, and the perovskite top cell includes an electron transport layer, a perovskite layer and a hole transport layer sequentially disposed on the interconnect layer along the thickness direction of the back-contact stacked cell.

[0006] Along the thickness direction of the back contact stacked cell, the surface of the substrate facing the perovskite layer has a textured structure, the textured structure including multiple pyramidal structures, and the surface of the pyramidal structures including multiple recessed structures.

[0007] The textured structure can improve the film quality of the perovskite layer and enhance the optical performance of the back-contact tandem solar cell. Specifically, firstly, during the fabrication of the perovskite layer on the electron transport layer, the perovskite precursor solution flows downwards under the guidance of the recessed structure, further promoting the uniform spreading of the perovskite precursor solution on the surface of the electron transport layer; secondly, the recessed structure can improve the roughness of the electron transport layer, promoting the uniform spreading of the perovskite precursor solution on the surface of the electron transport layer; thirdly, the recessed structure on the pyramid surface helps to increase the surface area of ​​the textured structure, thereby increasing the contact area between the perovskite precursor solution and the textured structure, and increasing the adhesion of the perovskite precursor solution on the electron transport layer. The textured surface, with its recessed structure, enhances interface anchoring, enabling the perovskite precursor solution to continuously, uniformly, and completely cover the surface of the electron transport layer. This improves the wettability of the substrate, passivation layer, interconnect layer, and electron transport layer, promoting the uniform spreading of the perovskite precursor solution on the surface of the electron transport layer. Consequently, it reduces the risk of dry spots during perovskite layer fabrication and the risk of pinholes in the perovskite layer. This facilitates the formation of a uniform, dense, and pinhole-free perovskite layer, improves the film quality of the perovskite layer, and enhances the photoelectric conversion efficiency of the back-contact tandem solar cell.

[0008] In this scheme, the depth dimension D of the recessed structure satisfies: 50nm≤D≤300nm.

[0009] In this scheme, the opening size L of the recessed structure satisfies: 20nm≤L≤100nm.

[0010] In this scheme, the recessed structure is a conical groove or an arc groove. Along the thickness direction of the back contact stacked battery, the dimension H1 of the pyramid structure satisfies: 1μm≤H1≤5μm, and the side length S of the pyramid base satisfies: 1μm≤S≤5μm.

[0011] In this design, multiple recessed structures are disposed on the outer periphery of the sidewalls of the pyramid structure.

[0012] In this design, the recessed structure is located at the top of the pyramid structure.

[0013] In this scheme, the distance P1 between adjacent center points of the pyramid structure satisfies: 3μm≤P1≤10μm.

[0014] In this scheme, at least one of the following conditions must be met: the thickness H2 of the interconnect layer satisfies: 5nm≤H2≤20nm; the thickness H3 of the electron transport layer satisfies: 2nm≤H3≤5nm; the thickness H4 of the perovskite layer satisfies: 300nm≤H4≤900nm; and the thickness H5 of the hole transport layer satisfies: 2nm≤H5≤5nm.

[0015] In this scheme, the interconnect layer includes a metal composite layer, a first dielectric layer and a second dielectric layer. Along the thickness direction of the back contact stacked battery, the metal composite layer is located between the first dielectric layer and the second dielectric layer.

[0016] In this scheme, along the thickness direction of the back contact stacked battery, the thickness dimension H6 of the metal composite layer satisfies: 8nm≤H6≤12nm, the thickness dimension H7 of the first dielectric layer satisfies: 3nm≤H7≤10nm, the thickness dimension H8 of the second dielectric layer satisfies: 3nm≤H8≤10nm, and the sheet resistance R of the interconnect layer satisfies: R≤50Ω.

[0017] The second aspect of this application provides a method for preparing a back-contact stacked battery, the method comprising at least:

[0018] Provide substrate;

[0019] A first textured structure is formed on the front side of the substrate. The first textured structure includes a plurality of raised pyramidal structures and a plurality of recessed structures disposed on the surface of the pyramidal structures.

[0020] An interconnect layer and an electron transport layer are sequentially deposited above the first textured structure, such that the surfaces of the interconnect layer and the electron transport layer opposite to the substrate along the thickness direction of the back contact stacked cell both form a second textured structure with the same shape as the first textured structure.

[0021] A perovskite precursor solution is spin-coated onto the surface of the electron transport layer to prepare a perovskite layer. The spin-coating speed V of the perovskite precursor solution satisfies: 2000 rpm / s ≤ V ≤ 4000 rpm / s.

[0022] In this scheme, the annealing temperature T1 for preparing the perovskite layer satisfies: 100℃≤T1≤150℃, and the annealing time M for preparing the perovskite layer satisfies: 5min≤M≤10min.

[0023] In this scheme, when preparing the interconnect layer, a low-temperature deposition method is used to prepare the interconnect layer on the first textured structure, and the low-temperature deposition temperature T2 of the interconnect layer satisfies: T2≤150℃;

[0024] The interconnect layer includes a first dielectric layer, a second dielectric layer, and a metal composite layer, wherein the metal composite layer is located between the first dielectric layer and the second dielectric layer. In the step of preparing the metal composite layer, the method for preparing the back contact stacked battery includes:

[0025] An oxide seed layer is pre-prepared on the surface of the second dielectric layer, and the metal composite layer is deposited on the surface of the oxide seed layer;

[0026] Alternatively, during the deposition of the metal composite layer, the deposition temperature is reduced to a temperature T3, where T3 ≤ 50°C.

[0027] In this scheme, the method for fabricating the back contact stacked battery in the steps of preparing the first dielectric layer and the second dielectric layer includes:

[0028] When the first and second dielectric layers are prepared by reactive sputtering, a molybdenum target is provided, and argon and oxygen are introduced. The ratio F of the amount of argon introduced to the amount of oxygen introduced satisfies: 0.05≤F≤0.1, and the DC power W applied to the molybdenum target satisfies: W≤1.5W / cm².

[0029] A third aspect of this application provides a photovoltaic module, the photovoltaic module comprising the back-contact tandem cell described above, or the photovoltaic module comprising a back-contact tandem cell prepared by the back-contact tandem cell preparation method described above.

[0030] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a specific embodiment of the back-contact stacked battery provided in this application;

[0032] Figure 2 This is a schematic diagram of a specific embodiment of the back-contact stacked battery provided in this application;

[0033] Figure 3 This is a partially enlarged view of a specific embodiment of the back-contact stacked battery provided in this application;

[0034] Figure 4 This is a schematic diagram of the structure of the substrate provided in this application in a specific embodiment;

[0035] Figure 5 for Figure 4 A magnified view of part A in the middle;

[0036] Figure 6 This is a schematic diagram of the structure of the substrate provided in this application in another specific embodiment;

[0037] Figure 7 This is a schematic diagram of the preparation sequence of the first velvet structure provided in this application in a specific embodiment;

[0038] Figure 8 This is a schematic diagram of the preparation sequence of the first velvet structure provided in this application in another specific embodiment;

[0039] Figure 9 A schematic diagram of the preparation sequence of the first velvet structure provided in this application in another specific embodiment;

[0040] Figure 10 This is a schematic diagram of the structure of the interconnect layer provided in this application in a specific embodiment;

[0041] Figure 11 A flowchart of a specific embodiment of the method for preparing the back contact tandem battery provided in this application;

[0042] Figure 12 A schematic diagram of a connection method between the back contact bottom cell and the perovskite top cell provided in this application;

[0043] Figure 13 A schematic diagram illustrating another connection method between the back contact bottom cell and the perovskite top cell provided in this application;

[0044] Figure 14 This is a schematic diagram of another connection method between the back contact bottom cell and the perovskite top cell provided in this application;

[0045] Figure 15 This is a schematic diagram of the structure of a photovoltaic module provided in this application in one specific embodiment.

[0046] Explanation of reference numerals in the attached figures:

[0047] 1-Back contact stacked battery;

[0048] 11-Back contact bottom battery;

[0049] 111-substrate;

[0050] 1111 - Suede texture;

[0051] 1111a - Pyramid structure;

[0052] 1111b - Depression structure;

[0053] 112 - Passivation layer;

[0054] 113 - Back contact structure;

[0055] 1131 - First semiconductor layer;

[0056] 1132 - Second semiconductor layer;

[0057] 12-Perovskite Top Cell;

[0058] 121 - Electron transport layer;

[0059] 122-Perovskite layer;

[0060] 123 - Hole transport layer;

[0061] 13-Interconnect layer;

[0062] 131 - First dielectric layer;

[0063] 132 - Metal composite layer;

[0064] 133 - Second dielectric layer;

[0065] 14-Transparent electrode;

[0066] 2- Photovoltaic modules;

[0067] 21-Welding strip;

[0068] 22-Front plate;

[0069] 23 - Front encapsulation layer;

[0070] 24 - Backside encapsulation layer;

[0071] 25 - Backplate.

[0072] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. Detailed Implementation

[0073] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0074] In one specific embodiment, the present application will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0075] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0076] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0077] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0078] It should be noted that the directional terms such as "upper," "lower," "left," and "right" described in the embodiments of this application are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this application. Furthermore, in the context, it should be understood that when it is mentioned that an element is connected "upper" or "lower" to another element, it can be directly connected to the other element "upper" or "lower," or indirectly connected to the other element "upper" or "lower" through an intermediate element.

[0079] This application provides a back-contact stacked battery 1, such as Figure 1 , Figure 3 , Figure 5 and Figure 6 As shown, the back contact tandem solar cell 1 includes a back contact bottom cell 11 and a perovskite top cell 12. The perovskite top cell 12 is electrically connected to the front side of the back contact bottom cell 11 via an interconnect layer 13. The back contact bottom cell 11 includes a substrate 111. The perovskite top cell 12 includes an electron transport layer 121, a perovskite layer 122, and a hole transport layer 123, which are sequentially disposed on the interconnect layer 13 along the thickness direction of the back contact tandem solar cell 1.

[0080] Along the thickness direction of the back-contact stacked cell 1, the surface of the substrate 111 facing the perovskite top cell 12 has a textured structure 1111, so that the surfaces of the interconnect layer 13 and the electron transport layer 121 facing the top perovskite layer also have textured structures 1111. The textured structure 1111 includes a pyramid structure 1111a, and the surface of the pyramid structure 1111a includes multiple recessed structures 1111b. The recess depth dimension D of the recessed structure 1111b satisfies: 50nm ≤ D ≤ 300nm, wherein the maximum distance between the opening position of the same recessed structure 1111b and the inner wall of the recessed structure 1111b is the recess depth dimension D.

[0081] Specifically, the back contact bottom cell 11 includes a passivation layer 112 disposed on the surface of the textured structure 1111 of the substrate 111. The passivation layer 112 is used to improve the passivation effect of the back contact stacked cell 1. Because the passivation layer 112, interconnect layer 13 and electron transport layer 121 are relatively thin and are all sequentially deposited on the substrate 111 with a textured structure 1111 during the fabrication of the back contact tandem solar cell 1, the surfaces of the passivation layer 112, interconnect layer 13 and electron transport layer 121 facing the top perovskite layer can all have the same textured structure 1111 as the substrate 111. That is, the passivation layer 112, interconnect layer 13 and electron transport layer 121 all have a raised pyramid structure 1111a and a recessed structure 1111b disposed on the surface of the pyramid structure 1111a. It should be noted that in this application, the pyramid structure 1111a is a raised tower-shaped structure, and the recessed structure 1111b is disposed on the surface of the pyramid structure 1111a. That is, the pyramid structure 1111a can include the recessed structure 1111b.

[0082] The textured structure 1111 can improve the film quality of the perovskite layer 122 and enhance the optical performance of the back-contact tandem solar cell 1. Specifically, firstly, when the perovskite layer 122 is fabricated on the electron transport layer 121, the perovskite precursor liquid flows downwards in the shallow recessed structure 1111b due to capillary action, further promoting the uniform spreading of the perovskite precursor liquid on the surface of the electron transport layer 121; secondly, the shallow recessed structure 1111b can improve the roughness of the electron transport layer 121, promoting the uniform spreading of the perovskite precursor liquid on the surface of the electron transport layer 121; thirdly, the recessed structure 1111b on the pyramid surface helps to increase the surface area of ​​the textured structure 1111, thereby increasing the contact area between the perovskite precursor liquid and the textured structure 1111, and increasing the perovskite precursor liquid in the electron transport layer. The adhesion on 121 is beneficial to enhancing interface anchoring, so that the perovskite precursor liquid can continuously, uniformly and completely cover the surface of the electron transport layer 121. Therefore, the textured structure 1111 with the recessed structure 1111b is beneficial to improving the wettability of the substrate 111, passivation layer 112, interconnect layer 13 and electron transport layer 121, promoting the uniform spreading of the perovskite precursor liquid on the surface of the electron transport layer 121, thereby reducing the risk of dry spots when preparing the perovskite layer 122, reducing the risk of pinholes in the perovskite layer 122, and promoting the formation of a uniform, dense and pinhole-free perovskite layer 122, improving the film quality of the perovskite layer 122, and improving the photoelectric conversion efficiency of the back contact tandem solar cell 1.

[0083] Furthermore, multiple recessed structures 1111b are provided on the surface of the pyramid structure 1111a. While the raised pyramid structure 1111a itself increases the light-trapping properties of the back-contact tandem solar cell 1, the recessed structures 1111b increase the scattering of incident light, reduce optical losses, and further improve the light-trapping properties of the back-contact tandem solar cell 1, thereby enhancing its photoelectric conversion efficiency. Simultaneously, by providing the recessed contact structures, the surface area of ​​the textured structure 1111 is increased, thereby increasing the effective contact area between the perovskite top solar cell 12 and the interconnect layer 13, the effective contact area between the interconnect layer 13 and the passivation layer 112, and the effective contact area between the passivation layer 112 and the substrate 111, thus improving the photoelectric conversion efficiency of the back-contact tandem solar cell 1.

[0084] Along the thickness direction of the back contact stacked battery 1, the depth dimension D of the recessed structure 1111b satisfies: 50nm ≤ D ≤ 300nm. This ensures that the depth dimension D of the recessed structure 1111b is moderate, preventing it from becoming too large. This improves the roughness of the textured structure 1111 of the electron transport layer 121, enhances the capillary action between the recessed structure 1111b and the perovskite precursor solution, and reduces the impact of other deposits such as the perovskite layer 122 and the interconnect layer 13 on the textured structure 1111b. The risk of film cracking on 111 is reduced, improving the electrical performance of the back contact stacked battery 1; at the same time, the depth dimension D of the recessed structure 1111b is not too small, and the depth dimension D of the recessed structure 1111b is greater than the thickness of the passivation layer 112, the interconnect layer 13 and the electron transport layer 121, improving the reliability of the recessed structure 1111b on the surface of the passivation layer 112, the interconnect layer 13 and the electron transport layer 121 after deposition, while increasing light scattering and improving the anti-reflection performance of the recessed structure 1111b.

[0085] It should be noted that, as Figure 3As shown, during the deposition of passivation layer 112, because the depth dimension D of the recessed structure 1111b is greater than the thickness of passivation layer 112, the raw materials for preparing passivation layer 112 cannot completely fill the recessed structure 1111b of substrate 111, so that passivation layer 112 can form a pyramid structure 1111a with the same recessed structure 1111b as substrate by deposition; during the deposition of interconnect layer 13, because the depth dimension D of the recessed structure 1111b is greater than the thickness of interconnect layer 13, the raw materials for preparing interconnect layer 13 cannot completely fill the recessed structure 1111b of passivation layer 112, so that interconnect layer 13 can form a pyramid structure 1111a with the same recessed structure 1111b as substrate by deposition; during the deposition of electron transport layer 121 .... If the dimension D is greater than the thickness of the electron transport layer 121, the raw materials used to prepare the electron transport layer 121 cannot completely fill the recessed structure 1111b of the interconnect layer 13, so that the electron transport layer 121 can form a pyramid structure 1111a with the same recessed structure 1111b as the substrate by deposition. Optionally, the recessed depth dimension D of the recessed structure 1111b satisfies: 50nm≤D≤300nm. D can be 50nm, 60nm, 80nm, 100nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 200nm, 220nm, 230nm, 240nm, 250nm, 260nm, 270nm, 280nm or 300nm, or other values ​​within the above range. This embodiment does not limit this. It should be noted that the depth dimension D of the recessed structure 1111b can be measured by SEM (Scanning Electron Microscope).

[0086] It is worth noting that, Figure 1 To clearly illustrate the various film layers located above substrate 111, and to facilitate the labeling of the dimensions of each film layer above substrate 111, Figure 1 The thicknesses of the films located at least above the substrate 111 are scaled up during rendering and are not the actual ratio of the size of the recessed structure 1111b to the thickness of each film layer. Figure 3 As shown, the actual depth dimension D of the recessed structure 1111b should be at least greater than the thickness of the passivation layer 112, the interconnect layer 13 and the electron transport layer 121. For actual data, please refer to the text description in this application.

[0087] In addition, the back contact bottom battery 11 includes a back contact structure 113, which includes a first semiconductor layer 1131 and a second semiconductor layer 1132, the first semiconductor layer 1131 and the second semiconductor layer 1132 having opposite conductivity types.

[0088] In some embodiments, the back contact battery 11 can be any one of the following: interdigitated back contact (IBC), heterojunction back contact (HBC), or tunnel oxide back contact (TBC).

[0089] For an IBC cell, along its thickness direction, it sequentially includes a silicon nitride inversion layer, an N+ front surface field, an N-type substrate silicon layer, intersecting adjacent P+ emitters and N+ back fields, an aluminum oxide passivation layer, a silicon nitride antireflection layer, and a silver electrode. IBC cells utilize ion implantation technology to obtain P- and N-regions with good uniformity and precisely controllable junction depth. The absence of grid lines on the front side eliminates light-blocking current loss from the metal electrodes, maximizing the utilization of incident photons and improving short-circuit current by approximately 7% compared to conventional solar cells. Due to its back-contact structure, grid line shading is not a concern, allowing for a wider grid line ratio, thus reducing series resistance and achieving a high fill factor. Optimized design of surface passivation and light-trapping structures can be achieved, resulting in lower front surface recombination rates and surface reflection.

[0090] HBC cells effectively combine the advantages of IBC and heterojunction cells. Their front surface passivation layer 112 is made of hydrogenated amorphous silicon, while N-type and P-type amorphous silicon thin films are deposited on the back side to form a heterojunction. HBC cells fully utilize the superior surface passivation properties of amorphous silicon, and the heterojunction structure formed on the back side has excellent passivation effects, enabling the simultaneous achievement of higher short-circuit current and open-circuit voltage, thereby improving photoelectric conversion efficiency.

[0091] For TBC cells, the advantages of Topcon's tunneling oxide layer technology and IBC back-side electrode arrangement are combined, resulting in significantly improved passivation and open-circuit voltage, achieving higher cell conversion efficiency while maintaining economic viability. The complete production process of TBC cells mainly includes depositing tunneling oxide layers and P-type and N-type polycrystalline silicon layers, depositing passivation films, and printing electrodes on the back of the silicon wafer. Based on the TOPCon production process, TBC cells require additional back-side electrode processes such as masking, laser grooving, PN region fabrication, and etching. Masking is mainly done using APCVD or PECVD, PN region fabrication is mainly done using PECVD, etching mainly uses traditional wet processing equipment, and grooving is performed using laser equipment.

[0092] In this application, the substrate 111 can be an N-type silicon substrate (abbreviated as N-type c-Si), and the doping element of the N-type silicon substrate can be any one or more of phosphorus, arsenic, antimony, and bismuth. Alternatively, the substrate 111 can be a P-type silicon substrate (abbreviated as P-type c-Si), and the doping element of the P-type silicon substrate can be any one or more of boron, aluminum, gallium, or indium.

[0093] In one possible implementation, such as Figure 1 , Figure 3 , Figure 5 and Figure 6 As shown, the opening size L of the recessed structure 1111b satisfies: 20nm≤L≤100nm, making the numerical range of the opening size L of the recessed structure 1111b moderate, so that the opening size L is not too large, improving the roughness of the textured structure 1111 of the electron transport layer 121, enhancing the capillary interaction between the recessed structure 1111b and the perovskite precursor liquid, reducing the difficulty of depositing perovskite layer 122, interconnect layer 13 and other films on the textured structure 1111, reducing the risk of cracking of perovskite layer 122, interconnect layer 13 and other films deposited on the textured structure 1111, and improving the electrical performance of the back contact tandem battery 1; at the same time, it ensures that the opening size L is not too small, improving the anti-reflection performance of the recessed structure 1111b.

[0094] Optionally, the opening size L of the recessed structure 1111b satisfies: 20nm≤L≤100nm. L can be 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm or 100nm, or other values ​​within the above range. This embodiment does not limit this value.

[0095] It should be noted that the opening size L of the recessed structure 1111b can be measured using SEM (Scanning Electron Microscope).

[0096] In summary, the depth dimension D of the recessed structure 1111b satisfies: 50nm ≤ D ≤ 300nm, and the opening dimension L of the recessed structure 1111b satisfies: 20nm ≤ L ≤ 100nm, making the recessed structure 1111b a nanoscale structure. This improves the surface roughness of the textured structure 1111 and allows the recessed structure 1111b to generate capillary action with the perovskite precursor liquid, improving the quality of the perovskite layer 122. At the same time, the size of the recessed structure 1111b is not too large compared to the pyramid structure 1111a, so that more recessed structures 1111b can be prepared on the pyramid structure 1111a, improving the capillary action between the textured structure 1111 and the perovskite precursor liquid, improving the interfacial wettability between the perovskite precursor liquid and the electron transport layer 121, and improving the antireflection performance of the textured structure 1111.

[0097] In one possible implementation, such as Figure 4 and Figure 6 As shown, the recessed structure 1111b is a conical groove or an arc-shaped groove. The conical or arc-shaped groove enhances the anti-reflective properties and improves light-trapping performance. Specifically, the conical groove 1111b has a conical cross-sectional shape, meaning the surface of the conical groove is an inclined plane; as shown... Figure 5 As shown, the cross-sectional shape of the concave structure 1111b of the arc-shaped groove is arc-shaped, that is, the surface of the arc-shaped groove is an arc surface.

[0098] Along the thickness direction of the back-contact stacked cell 1, the dimension H1 of the pyramid structure 1111a satisfies: 1μm≤H1≤5μm. This ensures that the numerical range of the dimension H1 of the pyramid structure 1111a is moderate, preventing the height of the pyramid structure 1111a from being too high. This improves the adhesion of the deposition solution to the textured structure 1111, thereby reducing the difficulty of depositing the passivation layer 112 on the substrate 111, reducing the difficulty of depositing the interconnect layer 13 on the passivation layer 112, and reducing the difficulty of depositing the perovskite layer 122 on the electron transport layer 121. This reduces the risk of stress concentration inside the passivation layer 112, interconnect layer 13, and perovskite layer 122 during fabrication, prevents cracks or pores from appearing inside the passivation layer 112, interconnect layer 13, and perovskite layer 122, and improves the film quality of the passivation layer 112, interconnect layer 13, and perovskite layer 122; at the same time, it ensures that the height of the pyramid structure 1111a is not too small, improves the light scattering ability of the textured structure 1111, effectively extends the optical path, improves the light trapping properties of the back contact stacked cell 1, and increases the short-circuit current density of the back contact stacked cell 1.

[0099] Optionally, the dimension H1 of the pyramid structure 1111a satisfies: 1μm≤H1≤5μm. H1 can be 1μm, 1.2μm, 1.4μm, 1.5μm, 1.6μm, 1.8μm, 2μm, 2.2μm, 2.4μm, 2.5μm, 2.6μm, 2.8μm, 3μm, 3.2μm, 3.4μm, 3.5μm, 3.6μm, 3.8μm, 4μm, 4.2μm, 4.4μm, 4.5μm, 4.6μm, 4.8μm, or 5μm, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0100] like Figure 4 and Figure 6 As shown, the side length S of the base of the pyramid structure 1111a satisfies: 1μm≤S≤5μm. This ensures that the value range of the side length S of the base of the pyramid structure 1111a is moderate, preventing the side length S from becoming too large. This increases the contact area between the perovskite precursor solution and the textured structure 1111, thus promoting the uniform spreading of the perovskite precursor solution on the electron transport layer 121 and the uniform spreading of the interconnect layer 13 on the passivation layer 112. This improves the quality of the interconnect layer 13, the perovskite layer 122, and other films deposited on the textured structure 1111. This reduces the amount of light trapped by the textured structure 1111, while also ensuring that the side length S of the pyramid base is not too small, preventing the pyramid structure 1111a from being too dense and too sharp. This reduces the difficulty of fabricating other films deposited on the textured structure 1111, such as the interconnect layer 13 and the perovskite layer 122, and prevents the pyramid structure 1111a from piercing the film layer. It also allows sufficient space for the grains in each film layer to grow, so that the number of grain boundaries in each film layer is moderate, thereby improving the quality of other films deposited on the textured structure 1111, such as the interconnect layer 13 and the perovskite layer 122.

[0101] Optionally, the side length S of the base of the pyramid structure 1111a satisfies: 1μm≤S≤5μm. S can be 1μm, 1.2μm, 1.4μm, 1.5μm, 1.6μm, 1.8μm, 2μm, 2.2μm, 2.4μm, 2.5μm, 2.6μm, 2.8μm, 3μm, 3.2μm, 3.4μm, 3.5μm, 3.6μm, 3.8μm, 4μm, 4.2μm, 4.4μm, 4.5μm, 4.6μm, 4.8μm, or 5μm, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0102] It should be noted that the dimensions H1 and S of the base of the pyramid structure 1111a can be measured using SEM (Scanning Electron Microscope). In summary, along the thickness direction of the back contact stacked battery 1, the depth D of the recessed structure 1111b satisfies: 50nm ≤ D ≤ 300nm, and the opening size L of the recessed structure 1111b satisfies: 20nm ≤ L ≤ 100nm. Simultaneously, along the thickness direction of the back contact stacked battery 1, the dimension H1 of the pyramid structure 1111a satisfies: 1μm ≤ H1 ≤ 5μm, and the base S of the pyramid structure 1111a satisfies: 1μm ≤ S ≤ 5μm. This ensures that the dimensions of both the pyramid structure and the recessed structure are moderate, thereby balancing the effects of both structures. Together, these improve the light-trapping and wettability of the textured structure 1111. While maintaining the good light-trapping properties of the textured structure 1111, the recessed structure 1111b can further enhance light scattering and increase the anti-reflection performance of the textured structure 1111. At the same time, since the size of the recessed structure 1111b is smaller than that of the pyramid structure 1111a, the recessed structure 1111b can improve the surface roughness of the pyramid structure 1111a and increase the surface area of ​​the pyramid structure, which greatly improves the quality of other films deposited on the textured structure 1111, such as the interconnect layer 13 and the perovskite layer 122.

[0103] In one possible implementation, such as Figure 5 As shown, the outer periphery of the sidewall of the pyramid structure 1111a is provided with multiple recessed structures 1111b distributed at intervals. Since most light is scattered through the sidewall of the pyramid structure, the multiple recessed structures 1111b on the outer periphery of the sidewall of the pyramid structure 1111a are conducive to further promoting the light scattering effect of the pyramid structure, greatly improving the light trapping property of the textured structure 1111, thereby improving the photoelectric conversion efficiency of the back contact tandem solar cell 1.

[0104] In one possible implementation, such as Figure 5 and Figure 6As shown, the recessed structure 1111b is disposed on the top of the pyramid structure 1111a. Firstly, it prevents the pyramid structure 1111a from cracking the films deposited on the textured surface, such as the perovskite layer 122 and the interconnect layer 13, thereby reducing the risk of film cracking and improving the quality of the interconnect layer 13 and the perovskite layer 122, as well as other films deposited on the textured surface 1111. Secondly, it improves the anti-reflective properties of the top of the pyramid structure 1111a, so that both the sidewalls and the top of the pyramid structure 1111a have good light-trapping properties, further improving the light-trapping properties of the textured surface 1111. Thirdly, it makes the top of the pyramid structure 1111a gentler, improving the adhesion of the perovskite precursor liquid to the top of the pyramid structure 1111a, further promoting the uniform coverage of perovskite on the textured surface 1111, which is beneficial for forming a continuous, dense, and pore-free perovskite layer 122.

[0105] In addition, in some embodiments, a recessed structure 1111b may also be provided at the bottom of the pyramid structure, that is, a recessed structure 1111b may also be provided at the junction of two adjacent pyramid structures, further improving the light trapping and wettability of the velvet structure 1111.

[0106] In one possible implementation, such as Figure 5 As shown, the distance P1 between the center points of adjacent pyramid structures 1111a satisfies: 3μm≤P1≤10μm. The intersection of the lines connecting the midpoints of the sides of each base of pyramid structure 1111a is the center point of pyramid structure 1111a. When P1 satisfies: 3μm≤P1≤10μm, the value of the distance P1 between the center points of adjacent pyramid structures 1111a is moderate, ensuring that the distance P1 between the center points of adjacent pyramid structures 1111a is not too small, which facilitates the uniform spreading of the perovskite solution and prevents excessive local deposition of the perovskite solution. At the same time, the distance P1 between the center points of adjacent pyramid structures 1111a is not too large, which increases the angle of incident light scattering, increases light scattering, and improves the light-trapping property of the textured structure 1111. Optionally, the distance P1 between the center points of adjacent pyramid structures 1111a satisfies: 3μm≤P1≤10μm. P1 can be 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, 9.5μm or 10μm, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0107] It should be noted that the distance P1 between the center points of adjacent pyramid structures 1111a can be measured using SEM (Scanning Electron Microscope).

[0108] In one possible implementation, such as Figure 1 As shown, along the thickness direction of the back contact stacked cell 1, the thickness dimension H2 of the interconnect layer 13 satisfies: 5nm ≤ H2 ≤ 20nm. This ensures that the numerical range of the thickness dimension H2 of the interconnect layer 13 is moderate, preventing it from becoming too large. This prevents the thickness dimension H2 of the interconnect layer 13 from exceeding the recess depth dimension D of the recessed structure 1111b, improving the reliability of the interconnect layer 13 in successfully forming the textured structure 1111 with the recessed structure 1111b through deposition, and preventing the interconnect layer 13 from being damaged due to… Excessive thickness leads to excessive internal stress, which in turn prevents excessive stress accumulation in the entire film layer after the deposition of electron transport layer 121 and perovskite layer 122. This prevents the electron transport layer 121 and perovskite layer 122 from cracking or peeling off from interconnect layer 13, and also helps to reduce parasitic absorption and improve short-circuit current. At the same time, it ensures that the thickness dimension H2 of interconnect layer 13 is not too small, preventing interconnect layer 13 from not completely covering the passivation layer 112 below, and preventing pinholes in interconnect layer 13, preventing local short circuits, and improving the conductivity of interconnect layer 13.

[0109] Optionally, the thickness H2 of the interconnect layer 13 satisfies: 5nm≤H2≤20nm. H2 can be 5nm, 6nm, 7nm, 8nm, 7nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm or 20nm, or other values ​​within the above range. This embodiment does not limit this.

[0110] In one possible implementation, such as Figure 2 As shown, along the thickness direction of the back-contact stacked battery 1, the thickness H3 of the electron transport layer 121 satisfies: 2nm ≤ H3 ≤ 5nm. This ensures that the numerical range of the thickness H3 of the electron transport layer 121 is moderate, preventing it from becoming too large. This prevents the thickness H3 of the electron transport layer 121 from exceeding the recess depth D of the recessed structure 1111b, improving the reliability of the electron transport layer 121 in successfully forming the textured structure 1111 with the recessed structure 1111b through deposition. It also prevents surface roughness and cracks caused by internal stress in the electron transport layer 121, thus ensuring the calcium... The titanium dioxide precursor solution can spread and crystallize uniformly, which is beneficial for forming a dense and uniform perovskite layer 122, improving the series resistance, and reducing the probability of interfacial recombination between the perovskite layer 122 and the electron transport layer 121. At the same time, it ensures that the thickness H3 of the electron transport layer 121 is not too small, preventing the electron transport layer 121 from not completely covering the interconnect layer 13, preventing pinholes in the electron transport layer 121, preventing the risk of uneven deposition caused by abnormal deposition of perovskite solution at pinholes, improving the film quality of the perovskite layer 122, reducing the series resistance of the back contact tandem cell 1, and improving the fill factor of the back contact tandem cell 1.

[0111] It is worth noting that, Figure 2 To clearly illustrate the various film layers located above substrate 111, and to facilitate the labeling of the dimensions of each film layer above substrate 111, Figure 2 The thicknesses of the films located at least above the substrate 111 are scaled up during rendering and are not the actual ratio of the size of the recessed structure 1111b to the thickness of each film layer. Figure 3 As shown, the actual depth dimension D of the recessed structure 1111b should be at least greater than the thickness of the passivation layer 112, the interconnect layer 13 and the electron transport layer 121. For actual data, please refer to the text description in this application.

[0112] Optionally, the thickness H3 of the electron transport layer 121 satisfies: 2nm ≤ H3 ≤ 5nm. H3 can be 2nm, 2.1nm, 2.2nm, 2.3nm, 2.4nm, 2.5nm, 2.6nm, 2.7nm, 2.8nm, 2.9nm, 3nm, 3.1nm, 3.2nm, 3.3nm, 3.4nm, 3.5nm, 3.6nm, 3.7nm, 3.8nm, 3.9nm, 4nm, 4.1nm, 4.2nm, 4.3nm, 4.4nm, 4.5nm, 4.6nm, 4.7nm, 4.8nm, 4.9nm, or 5nm, or other values ​​within the above range. This embodiment does not impose any restrictions on this value.

[0113] In summary, along the thickness direction of the back contact stacked cell 1, the thickness dimension H2 of the interconnect layer 13 satisfies: 5nm≤H2≤20nm, and the thickness dimension H3 of the electron transport layer 121 satisfies: 2nm≤H3≤5nm. This ensures that the thickness dimensions of both the interconnect layer 13 and the electron transport layer 121 are moderate, so that the interconnect layer 13 and the electron transport layer 121 together provide a good substrate for the perovskite layer 122, and jointly promote the formation of a dense, uniform, and pinhole-free perovskite layer 122.

[0114] In one possible implementation, such as Figure 1 and Figure 2 As shown, along the thickness direction of the back contact stacked cell 1, the thickness dimension H4 of the perovskite layer 122 satisfies: 300nm≤H4≤900nm.

[0115] Along the thickness direction of the back contact stacked cell 1, the thickness dimension H4 of the perovskite layer 122 satisfies: 300nm≤H4≤900nm. This ensures that the numerical range of the thickness dimension H4 of the perovskite layer 122 is moderate, preventing the thickness dimension H4 of the perovskite layer 122 from being too large, thus preventing cracking of the perovskite layer 122, improving the quality of the perovskite layer 122, and making it easier to prepare a uniform and dense hole transport layer 123 on the perovskite layer 122. At the same time, this ensures that the thickness dimension H4 of the perovskite layer 122 is not too small, preventing the perovskite layer 122 from being too thin, which would lead to discontinuities and multiple pinholes, thereby improving the mechanical strength of the perovskite layer 122 and increasing the short-circuit current density.

[0116] Optionally, the thickness H4 of the perovskite layer 122 satisfies: 300nm≤H4≤900nm. H4 can be 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, 750nm, 800nm, 850nm or 900nm, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0117] In one possible implementation, such as Figure 1 and Figure 2 As shown, along the thickness direction of the back contact stacked battery 1, the thickness dimension H5 of the hole transport layer 123 satisfies: 2nm≤H5≤5nm, which makes the numerical range of the thickness dimension H5 of the hole transport layer 123 moderate, reduces the series resistance, reduces parasitic absorption, and improves the fill factor and open circuit voltage.

[0118] Optionally, the thickness H5 of the hole transport layer 123 satisfies: 2nm ≤ H5 ≤ 5nm. H5 can be 2nm, 2.1nm, 2.2nm, 2.3nm, 2.4nm, 2.5nm, 2.6nm, 2.7nm, 2.8nm, 2.9nm, 3nm, 3.1nm, 3.2nm, 3.3nm, 3.4nm, 3.5nm, 3.6nm, 3.7nm, 3.8nm, 3.9nm, 4nm, 4.1nm, 4.2nm, 4.3nm, 4.4nm, 4.5nm, 4.6nm, 4.7nm, 4.8nm, 4.9nm, or 5nm, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0119] In addition, along the thickness direction of the back contact stacked cell 1, a transparent electrode 14 is provided on the surface of the hole transport layer 123 facing away from the perovskite layer 122. The transparent electrode 14 is used to provide a transport channel for electricity.

[0120] It should be noted that, because the thickness H4 of the perovskite layer 122 is greater than or equal to the depth D of the recessed structure 1111b, the perovskite precursor solution may completely fill the recessed structure 1111b of the electron transport layer 121, so that the surface of the perovskite layer 122 along the thickness direction of the back contact stacked cell 1 fails to form a textured structure 1111 with the recessed structure 1111b. Consequently, the hole transport layer 123 and the transparent electrode layer deposited sequentially on the perovskite layer 122 also fail to form a textured structure 1111 with the recessed structure 1111b on the surface along the thickness direction of the back contact stacked cell 1.

[0121] In one possible implementation, such as Figure 1 and Figure 10 As shown, the interconnect layer 13 can be one or a combination of the following materials: an ultrathin metal oxide composite layer, a high-mobility transparent conductive oxide prepared at low temperature, a composite of conductive polymer and metal nanowires, a composite of conductive polymer and graphene, or a two-dimensional material thin film.

[0122] When the interconnect layer 13 is an ultrathin metal oxide composite layer, the interconnect layer 13 includes a metal composite layer 132, a first dielectric layer 131, and a second dielectric layer 133. Along the thickness direction of the back contact stacked cell 1, the metal composite layer 132 is located between the first dielectric layer 131 and the second dielectric layer 133. The first dielectric layer 131 can be used to enhance the light transmittance and anti-reflection performance of the back contact stacked cell 1. The first dielectric layer 131 and the second dielectric layer 133 are located to protect the metal composite layer 132 and reduce the risk of oxidation or corrosion on the surface of the metal composite layer 132. The metal composite layer 132 serves as a conductive layer for collecting and transferring charge. Compared to conventional interconnect layers using a single indium tin oxide (ITO), in this embodiment, the ultrathin metal oxide composite layer of the interconnect layer 13 has superior conductivity and light transmittance, significantly reduces parasitic absorption and lowers series resistance, and improves the fill factor.

[0123] The first dielectric layer 131 and the second dielectric layer 133 can be any one of molybdenum oxide (MoOx), tungsten oxide (WOx), vanadium pentoxide (V2O5), titanium dioxide (TiO2), and zinc oxide (ZnO), and the metal composite layer 132 can be any one of silver (Ag), gold (Au), and copper (Cu).

[0124] For example, the first dielectric layer 131 and the second dielectric layer 133 can be molybdenum trioxide (MoO3), and the metal composite layer 132 can be silver (Ag), so that the first dielectric layer 131 and the second dielectric layer 133 have good anti-reflection properties and hole extraction properties, and the metal composite layer 132 has good conductivity.

[0125] In one possible implementation, such as Figure 10As shown, along the thickness direction of the back contact stacked battery 1, the thickness dimension H6 of the metal composite layer 132 satisfies: 8nm≤H6≤12nm, the thickness dimension H7 of the first dielectric layer 131 satisfies: 3nm≤H7≤10nm, and the thickness dimension H8 of the second dielectric layer 133 satisfies: 3nm≤H8≤10nm, so that the sheet resistance R of the interconnect layer 13 satisfies: R≤50Ω.

[0126] The thickness H6 of the metal composite layer 132 satisfies: 8nm≤H6≤12nm. This moderate range of thickness H6 facilitates the formation of a continuous but not completely closed island structure, resulting in excellent high light transmittance and low sheet resistance. Furthermore, the thickness of the metal composite layer 132 is not excessively thick, thus increasing short-circuit current; conversely, the thickness is not excessively thin, ensuring good continuity of the island structure and reducing sheet resistance.

[0127] Optionally, the thickness H6 of the metal composite layer 132 satisfies: 8nm≤H6≤12nm. H6 can be 8nm, 8.5nm, 9nm, 9.5nm, 10nm, 10.5nm, 11nm, 11.5nm or 12nm, or other values ​​within the above range. This embodiment does not limit this.

[0128] The thickness H7 of the first dielectric layer 131 satisfies: 3nm≤H7≤10nm, and the thickness H8 of the second dielectric layer 133 satisfies: 3nm≤H8≤10nm. This ensures that the thicknesses of both the first and second dielectric layers 131 and 133 are moderate, which is beneficial for forming continuous, dense, and pinhole-free first and second dielectric layers 131 and 133. Furthermore, ensuring that the thicknesses of the first and second dielectric layers 131 and 133 are not too small improves hole extraction efficiency and prevents leakage or short circuits. Simultaneously, ensuring that the thicknesses of the first and second dielectric layers 131 and 133 are not too large reduces series resistance and improves the fill factor.

[0129] Optionally, the thickness H7 of the first dielectric layer 131 satisfies: 3nm≤H7≤10nm. H7 can be 3nm, 3.5nm, 4nm, 4.5nm, 5nm, 5.5nm, 6nm, 6.5nm, 7nm, 7.5nm, 8nm, 8.5nm, 9nm, 9.5nm or 10nm, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0130] Optionally, the thickness H8 of the second dielectric layer 133 satisfies: 3nm≤H8≤10nm. H8 can be 3nm, 3.5nm, 4nm, 4.5nm, 5nm, 5.5nm, 6nm, 6.5nm, 7nm, 7.5nm, 8nm, 8.5nm, 9nm, 9.5nm or 10nm, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0131] Precise control of the thicknesses of the first dielectric layer 131, the metal composite layer 132, and the second dielectric layer 133 helps reduce the sheet resistance of the interconnect layer 13, ensuring that the sheet resistance R of the interconnect layer 13 satisfies: R ≤ 50Ω, and the average light transmittance of the interconnect layer 13 in the wavelength range of 300nm-1200nm is > 95%, thereby improving the conductivity and transmittance of the interconnect layer 13. Specifically, when the sheet resistance R of the interconnect layer 13 satisfies: R ≤ 50Ω, the sheet resistance of the interconnect layer 13 is not excessive, allowing for uniform current collection, reducing power loss, improving the conductivity of the interconnect layer 13, and significantly increasing the fill factor of the back contact tandem solar cell 1.

[0132] It should be noted that surface resistance refers to the relationship between current and voltage per unit area, and is usually used to describe the ability of a material surface to conduct current. Surface resistance can be measured using the four-probe method.

[0133] Optionally, the surface resistance R of the interconnect layer 13 satisfies: R≤50Ω, and R can be 10Ω, 15Ω, 20Ω, 25Ω, 30Ω, 35Ω, 40Ω, 45Ω or 50Ω, or other values ​​within the above range. This embodiment does not limit this.

[0134] This application also provides a method for preparing a back-contact stacked battery 1. The back-contact stack in any of the above embodiments can be prepared by this method for preparing the back-contact stacked battery 1. Figure 1 and Figure 11 As shown, the method for preparing the back-contact tandem battery 1 includes at least the following:

[0135] S1: Provide a substrate 111, and fabricate a back contact structure 113 on the back side of the substrate 111 to fabricate a back contact bottom battery 11.

[0136] S2: A first textured structure is formed on the front side of the substrate 111. The first textured structure includes a plurality of raised pyramidal structures 1111a and a plurality of recessed structures 1111b disposed on the surface of the pyramidal structures 1111a.

[0137] S3: A passivation layer 112, an interconnect layer 13, and an electron transport layer 121 are sequentially deposited on the surface of the first textured structure, so that the passivation layer 112, the interconnect layer 13, and the electron transport layer 121 all form a second textured structure with the same shape as the first textured structure on the surface away from the substrate 111 along the thickness direction of the back contact stacked battery 1. The first textured structure serves as a substrate so that the passivation layer 112, the interconnect layer 13, and the electron transport layer 121 subsequently deposited on the first textured structure all have the same second textured structure as the first textured structure.

[0138] S4: Spin-coat the surface of the electron transport layer 121 with a perovskite precursor solution to prepare the perovskite layer 122. The spin-coating speed V of the perovskite precursor solution satisfies: 2000rpm / s≤V≤4000rpm / s.

[0139] Specifically, since a first textured structure is formed on the front side of the substrate 111 in step S2, a second textured structure identical to the first textured structure can be formed on the front side of the passivation layer 112, interconnect layer 13, and electron transport layer 121 by deposition in step S3. This eliminates the need for a separate step to prepare the textured structure 1111 of the passivation layer 112, interconnect layer 13, and electron transport layer 121. Then, in step S4, when the perovskite solution is spin-coated onto the electron transport layer 121, capillary action occurs between the recessed structure 1111b of the second textured structure and the perovskite solution, assisting the perovskite solution to flow downwards for uniform spreading. This ensures that the perovskite solution can continuously, uniformly, and completely cover the surface of the electron transport layer 121, improving the film quality of the perovskite layer 122.

[0140] In one possible implementation, such as Figure 7 As shown, in the step of fabricating the first textured structure on the front side of the substrate 111, the method for fabricating the back contact stacked battery 1 includes the following steps: processing a pyramid structure 1111a on the front side of the substrate 111, and then fabricating a recessed structure 1111b on the surface of the pyramid structure 1111a.

[0141] In this embodiment, a V-groove array can be fabricated on the surface of the substrate 111 using photolithography and anisotropic etching, so that the sidewalls of two adjacent V-grooves form a raised pyramid structure 1111a, thereby fabricating multiple pyramid structures 1111a on the substrate 111. Then, a recessed structure 1111b is etched at the bottom of each V-groove, the sidewalls of each pair of adjacent V-grooves, and the top of each V-groove using metal-catalyzed chemical etching, so that the recessed structure 1111b is disposed at the top, sidewalls, and bottom of each pyramid structure.

[0142] In the metal-catalyzed chemical etching process, a 2nm-5nm thick gold or silver film can be deposited on the surface of each V-groove and annealed to form nano-island particles as a catalyst. Etching is then performed for 30-120 seconds in a mixed solution of 4.8mol / L hydrofluoric acid and 0.4mol / L-0.6mol / L hydrogen peroxide, thereby precisely controlling the size and distribution density of the recessed structure 1111b. Furthermore, the sidewall inclination angle of the V-groove is 54.74°, which is also the sidewall inclination angle of the pyramid structure 1111a. This allows for the first fabrication of the standard pyramid structure 1111a before the preparation of the recessed structure 1111b, which improves light-trapping properties.

[0143] In another possible implementation, such as Figure 8 and Figure 9 As shown, multiple recesses are formed on the front side of substrate 111, and then a pyramid structure 1111a is processed on the front side of substrate 111, so that a portion of the unprocessed multiple recesses is retained on the surface of the pyramid structure 1111a. This retained portion is formed as the recess structure 1111b, wherein, as... Figure 8 and Figure 9 The red line segment represents the recessed structure 1111b on the surface of the pyramid structure 1111a.

[0144] In this embodiment, multiple recesses are prepared using deep reactive ion etching (DRIE). A mixed gas of sulfur hexafluoride and octafluorocyclobutane is used for DIE, with the etching depth controlled at 130 nm-170 nm to create multiple recesses. Then, a low-concentration anisotropic alkaline solution is used for etching to prepare a pyramid structure with recesses. The anisotropic alkaline solution can be a 1.5 wt%-3 wt% potassium hydroxide solution with 10 vol%-15 vol% isopropanol as a catalyst. The anisotropic etching temperature is controlled at 70°C-80°C, and the anisotropic etching time is 15 min-25 min. The use of a low-concentration anisotropic alkaline solution and isopropanol catalyst helps to prepare a smoother and more regular textured surface structure.

[0145] When the spin coating speed V of the perovskite precursor solution satisfies the following condition: 2000 rpm / s ≤ V ≤ 4000 rpm / s, the spin coating speed V of the perovskite precursor solution is not too fast, which improves the uniformity of the perovskite precursor solution spreading on the electron transport layer 121, prevents the formation of pinholes, and allows for precise control of the thickness of the perovskite layer 122, as well as improving the number of grain boundaries and reducing carrier recombination. At the same time, the spin coating speed V of the perovskite precursor solution is not too slow, which prevents the formation of grains that are too large and disordered, so that the number of grains inside the perovskite layer 122 is moderate, thus improving the film quality of the perovskite layer 122.

[0146] Optionally, the spin coating speed V of the perovskite precursor solution satisfies: 2000 rpm / s ≤ V ≤ 4000 rpm / s. V can be 2000 rpm / s, 2100 rpm / s, 2200 rpm / s, 2300 rpm / s, 2400 rpm / s, 2500 rpm / s, 2600 rpm / s, 2700 rpm / s, 2800 rpm / s, 2900 rpm / s, 3000 rpm / s, 3100 rpm / s, 3200 rpm / s, 3300 rpm / s, 3400 rpm / s, 3500 rpm / s, 3600 rpm / s, 3700 rpm / s, 3800 rpm / s, 3900 rpm / s, or 4000 rpm / s, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0147] In one possible implementation, such as Figure 11 As shown, the annealing temperature T1 for preparing the perovskite layer 122 satisfies: 100℃≤T1≤150℃, and the annealing time M for preparing the perovskite layer 122 satisfies: 5min≤M≤10min.

[0148] When the annealing temperature T1 of the perovskite layer 122 satisfies: 100℃≤T1≤150℃, and the annealing time M of the perovskite layer 122 satisfies: 5min≤M≤10min, the annealing time and temperature are moderate, which promotes the internal crystallization of the perovskite layer 122, promotes uniform grain growth, forms high-quality grains, and is conducive to the formation of a dense and pinhole-free perovskite layer 122, thereby improving the open-circuit voltage, fill factor and short-circuit current.

[0149] Optionally, the annealing temperature T1 of the perovskite layer 122 satisfies: 100℃≤T1≤150℃. T1 can be 100℃, 105℃, 110℃, 115℃, 120℃, 125℃, 130℃, 135℃, 140℃, 145℃ or 150℃, or other values ​​within the above range. This embodiment does not limit this.

[0150] Optionally, the annealing time M of the perovskite layer 122 satisfies: 5min≤M≤10min. M can be 5min, 6min, 7min, 8min, 9min or 10min, or other values ​​within the above range. This embodiment does not limit this.

[0151] In one possible implementation, such as Figure 1 and Figure 10As shown, when preparing the interconnect layer 13, any one of reactive sputtering, atomic layer deposition, plasma-enhanced chemical vapor deposition, or solution coating can be used to achieve low-temperature deposition of the interconnect layer 13. The interconnect layer 13 includes a first dielectric layer 131, a second dielectric layer 133, and a metal composite layer 132. The metal composite layer 132 is located between the first dielectric layer 131 and the second dielectric layer 133. When the low-temperature deposition temperature T2 satisfies: T2≤150℃, the risk of non-radiative recombination between the metal composite layer 132 and the first dielectric layer 131 and the second dielectric layer 133 is reduced, which is beneficial to forming a clear and stable interface between the metal composite layer 132 and the first dielectric layer 131 and the second dielectric layer 133, thereby improving the open-circuit voltage of the back contact stacked battery 1.

[0152] Furthermore, in the step of preparing the metal composite layer 132, the method for preparing the back contact stacked cell 1 includes: pre-preparing an ultrathin oxide seed layer on the surface of the second dielectric layer 133 away from the substrate 111 along the thickness direction of the back contact stacked cell 1; depositing the metal composite layer 132 on the surface of the oxide seed layer away from the substrate 111 along the thickness direction of the back contact stacked cell 1; or, during the deposition of the metal composite layer 132, lowering the deposition temperature to a temperature T3, where T3 ≤ 50°C; either depositing the metal composite layer 132 on the oxide seed layer or directly depositing the metal composite layer 132 on the second dielectric layer 133 at a lower temperature is beneficial for promoting the formation of a continuous but not completely closed island-shaped film in the metal composite layer 132, improving the film quality of the metal composite layer 132, and making the metal composite layer 132 form a smooth and continuous film layer, thereby reducing the sheet resistance of the metal composite layer 132, and further reducing the sheet resistance of the interconnect layer 13, and improving the conductivity of the interconnect layer 13.

[0153] The oxide seed layer can be titanium dioxide (TiO2) or zinc oxide (ZnO), and the thickness of the oxide seed layer is between 1 nm and 2 nm along the thickness direction of the back contact stacked battery 1.

[0154] Optionally, the deposition temperature T3 satisfies the following condition: T3≤50℃. T3 can be 10℃, 15℃, 20℃, 25℃, 30℃, 35℃, 40℃, 45℃ or 50℃, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0155] In one possible implementation, such as Figure 11 As shown, in the steps of fabricating the first dielectric layer 131 and the second dielectric layer 133, the method for fabricating the back contact stacked cell 1 includes:

[0156] When the first dielectric layer 131 and the second dielectric layer 133 are prepared by reactive sputtering, a molybdenum target is provided, and argon and oxygen are introduced. Argon is used to generate plasma, bombard the molybdenum target, and transport molybdenum particles; that is, argon provides the molybdenum source, and oxygen acts as the oxygen source and reacts chemically with the molybdenum particles to generate molybdenum oxide. The ratio F of the argon to oxygen flow rate satisfies: 0.05 ≤ F ≤ 0.1, and the DC power W applied to the molybdenum target satisfies: W ≤ 1.5 W / cm². This means that the first dielectric layer 131 and the second dielectric layer 133 are prepared by low-power reactive magnetron sputtering. When the DC power W satisfies: W ≤ 1.5 W / cm², the energy of the sputtered particles is reduced, which helps to reduce the risk of plasma damage to the passivation layer 112.

[0157] Optionally, when the DC power W satisfies: W≤1.5W / cm², W can be: 0.1W / cm², 0.4W / cm², 0.5W / cm², 0.6W / cm², 0.8W / cm², 1W / cm², 1.1W / cm², 1.2W / cm², 1.3W / cm², 1.4W / cm², or 1.5W / cm², or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0158] When the ratio F of argon gas to oxygen gas is 0.05 ≤ F ≤ 0.1, the ratio F is moderate, ensuring that the oxygen content is not too low relative to the argon gas, allowing for sufficient reaction between the molybdenum source and the oxygen source, thus improving the work function of interconnect layer 13. Simultaneously, the ratio of oxygen to argon gas is also moderate, increasing the deposition rate. Therefore, when F satisfies 0.05 ≤ F ≤ 0.1, the efficiency of fabricating the first dielectric layer 131 and the second dielectric layer 133 is improved, which is beneficial for depositing a molybdenum oxide film with a near-ideal stoichiometric ratio, improving the work function of interconnect layer 13, enhancing the band structure of electron transport layer 121, and consequently reducing the interfacial recombination loss between perovskite layer 122 and electron transport layer 121, thereby increasing the open-circuit voltage of the back-contact tandem solar cell.

[0159] Optionally, the ratio F of the argon gas flow rate to the oxygen gas flow rate satisfies: 0.05 ≤ F ≤ 0.1, where F can be 0.05, 0.055, 0.06, 0.065, 0.07, 0.075, 0.08, 0.085, 0.09, 0.095 or 0.1, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0160] After the perovskite layer 122 is prepared, the method for preparing the back contact tandem solar cell 1 includes the following steps: S5: along the thickness direction of the back contact tandem solar cell 1, a hole transport layer 123 and a transparent electrode 14 are sequentially deposited on the surface of the perovskite layer 122 away from the substrate 111 to reduce the series resistance, reduce parasitic absorption, and improve the fill factor and open circuit voltage.

[0161] This application also provides a photovoltaic module 2, such as Figure 15 As shown, the photovoltaic module 2 includes the back contact stacked cell 1 in any of the above embodiments, or the photovoltaic module includes the back contact stacked cell 1 prepared by the preparation method of the back contact stacked cell 1 in any of the above embodiments.

[0162] Specifically, the photovoltaic module 2 includes a battery module, which in turn includes several battery strings. Each battery string includes back-contact tandem batteries 1 as described in any of the above embodiments. The back-contact tandem batteries 1 can be sequentially connected together via solder strips 21 to form a battery string. The individual battery strings in the battery module can achieve current collection and output by connecting them in series, parallel, or a combination of series and parallel connections using busbars.

[0163] like Figure 15 As shown, the photovoltaic module 2 also includes a front panel 22, a front encapsulation layer 23, a back encapsulation layer 24, and a back sheet 25. The front panel 22 and the back sheet 25 together sandwich the front encapsulation layer 23, the photovoltaic cells, the solder ribbons 21, and the back encapsulation layer 24, and form the photovoltaic module 2 through lamination. The front encapsulation layer 23 protects the light-facing side of the photovoltaic cells, and the back encapsulation layer 24 protects the back-facing side of the photovoltaic cells. During the lamination process of the photovoltaic module 2, the front encapsulation layer 23 and the back encapsulation layer 24 encapsulate and protect the photovoltaic cells and solder ribbons 21, preventing external environmental factors from affecting their performance. They also bond the front panel 22, the back sheet 25, the photovoltaic cells, and the solder ribbons 21 into a single unit. The photovoltaic cells are the back-contact tandem cells 1 in any of the above embodiments.

[0164] The front panel 22 and back panel 25 can be made of rigid materials such as tempered glass, polyethylene terephthalate (PET), and polycarbonate (PC), or flexible materials such as polyvinyl fluoride (PVF), ethylene-tetrafluoroethylene copolymer (ETFE), and polyvinylidene fluoride (PVDF). The front and back encapsulation layers 24 are adhesive films, which can be made of materials such as ethylene-vinyl acetate copolymer (EVA), polyolefin elastomer (POE), and polyvinyl butyral (PVB). The front encapsulation layer 23 and back encapsulation layer 24 can also be EPE film (EVA-POE-EVA co-extrusion structure) or EP film (EVA-EP co-extrusion structure).

[0165] In some embodiments, the back contact structure 113 of the back contact bottom battery 11 includes a first grid line and a second grid line for collecting currents of different polarities.

[0166] In some embodiments, such as Figure 12 As shown, the back-contact stacked battery 1 can be a three-terminal back-contact stacked battery, that is, the perovskite top battery 12 and the back-contact bottom battery 11 form a three-terminal stacked structure. A terminal is led out from the end of the perovskite top battery 12 away from the back-contact bottom battery 11. The first grid line and the second grid line in the back-contact bottom battery 11 are led out as two independent terminals respectively. The mismatch current can be output through the extra terminal to ensure that the back-contact stacked battery 1 operates at a higher power.

[0167] In other embodiments, such as Figure 13 As shown, the back-contact stacked battery 1 can be a two-end back-contact stacked battery, that is, the perovskite top battery 12 and the back-contact bottom battery 11 form a two-end stacked structure. The positive electrode of the perovskite top battery 12 is electrically connected to one of the first grid line and the second grid line in the back-contact bottom battery 11 to form a terminal. The negative electrode of the perovskite top battery 12 is electrically connected to the other of the first grid line and the second grid line in the back-contact bottom battery 11 to form another terminal.

[0168] In some other embodiments, such as Figure 14 As shown, the back-contact stacked battery 1 can be a four-terminal back-contact stacked battery, that is, the perovskite top battery 12 and the back-contact bottom battery 11 form a four-terminal stacked structure. The positive and negative electrodes in the perovskite top battery 12 are respectively led out as independent terminals, and the first grid line and the second grid line in the back-contact bottom battery 11 are also respectively led out as independent terminals. Therefore, in this embodiment, the circuits of the perovskite top battery 12 and the back-contact bottom battery 11 are independent of each other and each outputs independently. The above description is only a specific implementation of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of this application should be determined by the protection scope of the claims.

Claims

1. A back-contact stacked battery, characterized in that, The back contact stacked cell (1) includes a back contact bottom cell (11) and a perovskite top cell (12), and the perovskite top cell (12) is electrically connected to the front side of the back contact bottom cell (11) via an interconnect layer (13). The back contact bottom cell (11) includes a substrate (111), and the perovskite top cell (12) includes an electron transport layer (121), a perovskite layer (122) and a hole transport layer (123) sequentially disposed on the interconnect layer (13) along the thickness direction of the back contact stacked cell (1). Along the thickness direction of the back contact stacked cell (1), the surface of the substrate (111) facing the perovskite layer (122) has a textured structure (1111), the textured structure (1111) includes a plurality of pyramid structures (1111a), and the surface of the pyramid structure (1111a) includes a plurality of recessed structures (1111b), the recessed depth dimension D of the recessed structure (1111b) is greater than the thickness dimension H2 of the interconnect layer (13).

2. The back-contact stacked battery according to claim 1, characterized in that, The depth dimension D of the recessed structure (1111b) satisfies: 50nm≤D≤300nm.

3. The back-contact stacked battery according to claim 1 or 2, characterized in that, The opening size L of the recessed structure (1111b) satisfies: 20nm≤L≤100nm.

4. The back-contact stacked battery according to claim 1 or 2, characterized in that, The recessed structure (1111b) is a conical groove or an arc-shaped groove. Along the thickness direction of the back contact stacked battery (1), the size H1 of the pyramid structure (1111a) satisfies: 1μm≤H1≤5μm, and the side length S of the base of the pyramid structure (1111a) satisfies: 1μm≤S≤5μm.

5. The back-contact stacked battery according to claim 1, characterized in that, Multiple recessed structures (1111b) are disposed on the outer periphery of the sidewall of the pyramid structure (1111a).

6. The back-contact stacked battery according to claim 1, 2, or 5, characterized in that, The recessed structure (1111b) is located on top of the pyramid structure (1111a).

7. The back-contact stacked battery according to claim 1, 2, or 5, characterized in that, The distance P1 between the center points of adjacent pyramid structures (1111a) satisfies: 3μm≤P1≤10μm.

8. The back-contact stacked battery according to claim 7, characterized in that, The following conditions must be met: the thickness dimension H2 of the interconnect layer (13) satisfies: 5nm≤H2≤20nm; the thickness dimension H3 of the electron transport layer (121) satisfies: 2nm≤H3≤5nm; the thickness dimension H4 of the perovskite layer (122) satisfies: 300nm≤H4≤900nm; and the thickness dimension H5 of the hole transport layer (123) satisfies: 2nm≤H5≤5nm.

9. The back-contact stacked battery according to claim 8, characterized in that, The interconnect layer (13) includes a metal composite layer (132), a first dielectric layer (131), and a second dielectric layer (133). Along the thickness direction of the back contact stacked battery (1), the metal composite layer (132) is located between the first dielectric layer (131) and the second dielectric layer (133).

10. The back-contact stacked battery according to claim 9, characterized in that, Along the thickness direction of the back contact stacked battery (1), the thickness dimension H6 of the metal composite layer (132) satisfies: 8nm≤H6≤12nm, the thickness dimension H7 of the first dielectric layer (131) satisfies: 3nm≤H7≤10nm, the thickness dimension H8 of the second dielectric layer (133) satisfies: 3nm≤H8≤10nm, and the sheet resistance R of the interconnect layer (13) satisfies: R≤50Ω.

11. A method for preparing a back-contact stacked battery, characterized in that, The method for preparing the back-contact stacked battery (1) includes at least the following: Substrate (111) is provided; A first textured structure is formed on the front side of the substrate (111). The first textured structure includes a plurality of raised pyramidal structures (1111a) and a plurality of recessed structures (1111b) disposed on the surface of the pyramidal structures (1111a). An interconnect layer (13) and an electron transport layer (121) are sequentially deposited above the first textured structure. The recess depth dimension D of the recessed structure (1111b) is greater than the thickness dimension H2 of the interconnect layer (13), so that the surfaces of the interconnect layer (13) and the electron transport layer (121) opposite to the substrate (111) along the thickness direction of the back contact stacked battery (1) both form a second textured structure with the same shape as the first textured structure. A perovskite precursor solution is spin-coated onto the surface of the electron transport layer (121) to prepare a perovskite layer (122), wherein the spin-coating speed V of the perovskite precursor solution satisfies: 2000 rpm / s ≤ V ≤ 4000 rpm / s.

12. The method for preparing a back-contact stacked battery according to claim 11, characterized in that, The annealing temperature T1 for preparing the perovskite layer (122) satisfies: 100℃≤T1≤150℃, and the annealing time M for preparing the perovskite layer (122) satisfies: 5min≤M≤10min.

13. The method for preparing a back-contact stacked battery according to claim 11, characterized in that, When preparing the interconnect layer (13), the interconnect layer (13) is prepared on the first textured structure by low-temperature deposition. The low-temperature deposition temperature T2 for preparing the interconnect layer (13) satisfies: T2≤150℃; The interconnect layer (13) includes a first dielectric layer (131), a second dielectric layer (133), and a metal composite layer (132). The metal composite layer (132) is located between the first dielectric layer (131) and the second dielectric layer (133). In the step of preparing the metal composite layer (132), the method for preparing the back contact stacked battery (1) includes: An oxide seed layer is pre-prepared on the surface of the second dielectric layer (133), and the metal composite layer (132) is deposited on the surface of the oxide seed layer. Alternatively, during the deposition of the metal composite layer (132), the deposition temperature is reduced to a temperature T3, where T3 satisfies: T3≤50℃.

14. The method for preparing a back-contact stacked battery according to claim 13, characterized in that, In the steps of preparing the first dielectric layer (131) and the second dielectric layer (133), the method for preparing the back contact stacked battery (1) includes: When the first dielectric layer (131) and the second dielectric layer (133) are prepared by reactive sputtering, a molybdenum target is provided, and argon and oxygen are introduced. The ratio F of the amount of argon introduced to the amount of oxygen introduced satisfies: 0.05 ≤ F ≤ 0.1, and the DC power W applied to the molybdenum target satisfies: W ≤ 1.5 W / cm². 2 .

15. A photovoltaic module, characterized in that, The photovoltaic module includes a back-contact tandem cell (1) according to any one of claims 1-10, or the photovoltaic module includes a back-contact tandem cell (1) prepared by the method of preparing the back-contact tandem cell (1) according to any one of claims 11-14.

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