Counter for lightning arrester

Abstract

The counter comprises a power supply circuit and a detection circuit, the power supply circuit provides a power supply for the detection circuit, and the detection circuit is used for detecting and metering the number of lightning stroke discharge wave crests; the detection circuit comprises a signal acquisition circuit unit, a lightning stroke discharge peak holding circuit unit and an accumulation circuit unit, the signal acquisition circuit unit is used for acquiring a lightning current signal, and the lightning stroke discharge peak holding circuit unit detects a current peak based on the lightning current signal. And the accumulation circuit unit is used for accumulating and metering the number of times of the current peak value. The counter can effectively detect the number of lightning stroke discharge wave crests, and the problem that an existing counter cannot effectively meter return stroke discharge actions is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of lightning protection, in particular to a lightning arrester counter. BACKGROUND

[0002] The lightning arrester is a device for protecting electrical equipment from high transient overvoltage, and the lightning arrester counter is a device for monitoring the discharge action (including the number of times) of the lightning arrester. After natural lightning occurs, the main discharge lightning is usually accompanied by several to dozens of back-stroke discharges. Since the interval time between the main discharge and the back-stroke discharge is usually only tens of milliseconds, the current conventional mechanical lightning arrester counter uses a capacitor energy storage to drive an electromagnetic mechanism to drive a mechanical counter, and the counting action response time needs hundreds of milliseconds, so it cannot monitor and record the multiple back-stroke discharge actions in a short time. The back-stroke discharge action can only be recorded as a lightning stroke action together with the main discharge, thereby resulting in inaccurate counting results. SUMMARY

[0003] The present application aims to solve the problem that the prior art cannot accurately record the back-stroke discharge action, and provides a lightning arrester counter which can simultaneously record the main discharge and back-stroke discharge actions.

[0004] A lightning arrester counter comprises a power supply circuit and a detection circuit, the power supply circuit provides power supply for the detection circuit, and the detection circuit is used for detecting and measuring the number of lightning discharge peaks. The detection circuit comprises a signal acquisition circuit unit, a lightning discharge peak value retention circuit unit and an accumulation circuit unit. The signal acquisition circuit unit is used for acquiring a lightning current signal, the lightning discharge peak value retention circuit unit detects the current peak value based on the lightning current signal, and the accumulation circuit unit is used for accumulating the number of times of the current peak value.

[0005] Each main discharge or back-stroke discharge has a current peak. In the above scheme, the lightning current signal is acquired by the signal acquisition circuit unit, the number of peaks of the lightning current waveform is detected by the lightning discharge peak value retention circuit unit, and the accumulation circuit unit is used for accumulation counting, so that the number of times of the main discharge and back-stroke discharge can be detected and recorded.

[0006] In a further optimized scheme, the detection circuit further comprises a lightning discharge following circuit unit and an automatic discharge circuit unit. The input end of the lightning discharge following circuit unit is connected to the output end of the signal acquisition circuit unit, the output end of the lightning discharge following circuit unit and the output end of the lightning discharge peak value retention circuit unit are both connected to the input end of the automatic discharge circuit unit, and the output end of the automatic discharge circuit unit is connected to the input end of the accumulation circuit unit. The lightning discharge following circuit unit is used for monitoring the amplitude change of the lightning current, and the automatic discharge circuit unit is used for automatically controlling the charging and discharging of the lightning discharge peak value retention circuit unit.

[0007] The lightning discharge peak hold circuit unit can detect the number of current peaks. However, if the peak amplitude is too low and exceeds the detection range, the peak count may be inaccurate, leading to inaccurate recording of the main discharge and return stroke discharge counts. In the above solution, the lightning discharge follower circuit unit, the automatic discharge circuit unit, and the lightning discharge peak hold circuit unit work together to simultaneously detect the amplitude and peak values. This expands the peak detection range; for example, the current amplitude range is extended from 50kA-100kA to 1A-100KA. Therefore, peaks in the 1A-50KA range can also be accurately detected, thereby improving the accuracy of recording the main discharge and return stroke discharge counts.

[0008] In a preferred embodiment, the lightning discharge peak holding circuit unit includes a first resistor, a second resistor, a first operational amplifier, a first diode, and a first capacitor. The output terminal of the signal acquisition circuit unit is connected to the non-inverting input terminal of the first operational amplifier through the second resistor. The two ends of the first resistor are connected to the non-inverting input terminal and the output terminal of the first operational amplifier, respectively. The inverting input terminal of the first operational amplifier is grounded. The output terminal of the first operational amplifier is connected to the positive terminal of the first diode. The negative terminal of the first diode is connected to one end of the first capacitor, and the other end of the first capacitor is grounded.

[0009] In the above scheme, for the signal detection circuit with high output impedance and weak driving capability, and insufficient driving force when charging the first capacitor, an operational amplifier is added to amplify the signal. On the one hand, this increases the current driving capability, and on the other hand, it amplifies the amplitude of the lightning waveform to a level suitable for subsequent circuit detection, thereby improving the accuracy of the detection results.

[0010] The lightning discharge follower circuit unit includes a third resistor, a fourth resistor, a second operational amplifier, a second diode, a third diode, and a second capacitor. The output terminal of the signal acquisition circuit unit is connected to the non-inverting input terminal of the second operational amplifier through the fourth resistor. The two ends of the third resistor are connected to the non-inverting input terminal and the output terminal of the second operational amplifier, respectively. The inverting input terminal of the second operational amplifier is grounded. The output terminal of the second operational amplifier is connected to the positive terminal of the third diode and the negative terminal of the second diode. The positive terminal of the second diode and the negative terminal of the third diode are both connected to one end of the second capacitor, and the other end of the second capacitor is grounded. The parameters of the first resistor and the third resistor are the same, and the parameters of the second resistor and the fourth resistor are the same.

[0011] If the resistors are inconsistent, the output signal amplitudes of the two operational amplifiers will differ when they have the same input. This will result in a voltage difference even when the voltages of the first and second capacitors are equal. If this difference exceeds the comparator's offset voltage, it will cause a discharge misjudgment. In other words, by ensuring that the parameters of the first and third resistors are consistent, and the parameters of the second and fourth resistors are consistent, discharge misjudgment can be avoided.

[0012] The automatic discharge circuit unit includes a comparator and a PMOS transistor. The non-inverting input terminal of the comparator is connected to the negative terminal of the first diode and the source terminal of the PMOS transistor. The inverting input terminal of the comparator is connected to the negative terminal of the third diode and the positive terminal of the second diode. The drain terminal of the PMOS transistor is grounded. The output terminal of the comparator is connected to the gate terminal of the PMOS transistor and the input terminal of the accumulator circuit unit.

[0013] In one scheme that does not perform current amplitude detection, the lightning discharge peak holding circuit unit includes a first resistor, a second resistor, a first operational amplifier, and a first diode. The output terminal of the signal acquisition circuit unit is connected to the non-inverting input terminal of the first operational amplifier through the second resistor. The two ends of the first resistor are connected to the non-inverting input terminal and the output terminal of the first operational amplifier, respectively. The inverting input terminal of the first operational amplifier is grounded. The output terminal of the first operational amplifier is connected to the positive terminal of the first diode. The negative terminal of the first diode is connected to the input terminal of the accumulation circuit unit.

[0014] In the optimized scheme, the signal acquisition circuit unit includes a current sensor, a load resistor, and a bridge rectifier diode. The output terminal of the current sensor is connected in parallel with the load resistor and then connected to the AC input pin of the bridge rectifier diode. The negative output pin of the bridge rectifier diode is grounded. The positive output terminal of the bridge rectifier diode is connected to the non-inverting input pin of the first operational amplifier through a second resistor. The input terminal of the current sensor is used to connect to the grounding wire of the surge arrester.

[0015] The peak current of a lightning strike can typically reach several thousand to tens of thousands of amperes. Directly connecting it to a circuit for data acquisition would damage the circuit. In the above solution, a current sensor is used to reduce the lightning strike current, converting the large current into a small current for acquisition, thus avoiding damage to the circuit from high voltage and high current input.

[0016] The accumulator circuit unit includes multiple JK flip-flops. The CP input pin of the first JK flip-flop serves as the input terminal of the accumulator circuit unit. The Q pin of the previous JK flip-flop is connected to the CP pin of the next JK flip-flop, leading out the Q pins of all JK flip-flops. The J and K pins of all JK flip-flops are connected to a high-level pin in the detection circuit.

[0017] In the above scheme, the accumulator circuit unit is composed of JK flip-flops. The number of JK flip-flops determines the counting range. This circuit structure can not only realize counting, but also realize automatic clearing and reset.

[0018] In a further optimized scheme, the accumulator circuit unit leads out a reset pin, and the R pins of all JK flip-flops are connected to the reset pin; the surge arrester counter also includes a control interface connected to the reset pin.

[0019] In the above scheme, by bringing out the reset pin and connecting it to the control interface, an external switch can be connected to achieve manual clearing and reset, making the whole circuit more flexible.

[0020] In a further optimized scheme, the counter also includes an output interface, which is connected to the Q pin of all JK flip-flops.

[0021] In the above scheme, by setting the output interface, indicator lights or decoding circuits can be connected to display the current number of discharges, or data acquisition devices can be connected for remote data acquisition, thus expanding the function of the counter.

[0022] Compared with the prior art, the present invention has the following technical advantages: The operational amplifiers, comparators, JK flip-flops and other electronic devices used generally have response capabilities ranging from several nanoseconds to tens of nanoseconds. The circuit's response capability is much higher than the duration of lightning discharge (tens of microseconds). Therefore, it can effectively detect the number of lightning discharge peaks and solve the problem that existing counters cannot effectively measure the return stroke discharge action. The detection circuit has an automatic or manual zeroing function; The output is a digital level signal with good scalability; The data acquisition is implemented using pure hardware circuitry, eliminating the need for embedded devices such as MCUs and DSPs, and offering advantages such as low power consumption and high stability. Attached Figure Description

[0023] Figure 1 This is an electrical schematic diagram of the detection circuit in the surge arrester counter of the present invention.

[0024] Figure 2 This is a schematic diagram showing the change of lightning current amplitude over time.

[0025] Figure 3 This is a schematic diagram showing how the voltage level at point P0 changes over time.

[0026] Figure 4 This is a schematic diagram showing how the voltage level at point Q0 changes over time.

[0027] Figure 5 This is a schematic diagram showing how the voltage level at point Q1 changes over time. Detailed Implementation

[0028] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0029] The surge arrester counter provided in this embodiment includes a detection circuit, a power supply circuit, an output interface, and a control interface. The detection circuit is mainly responsible for detecting the number of lightning discharge peaks. The power supply circuit provides power to the entire circuit; the power supply circuit can be a battery, a solar photovoltaic panel, an AC-to-DC power supply, etc. The output interface connects to the detection circuit (specifically...). Figure 1 Q0 to Qn-1 in the circuit can be connected to indicator lights or decoding circuits to display the current number of discharges, or it can be connected to a data acquisition device for remote data acquisition; the control interface connects to the detection circuit (specifically...). Figure 1 The reset pin P2 can be connected to an external switch or control terminal to achieve the function of resetting and clearing the discharge count.

[0030] Please see Figure 1 The detection circuit mainly includes a signal acquisition circuit unit, a lightning discharge peak hold circuit unit, a lightning discharge follower circuit unit, an automatic discharge circuit unit, and an accumulation circuit unit. The input terminals of the lightning discharge peak hold circuit unit and the lightning discharge follower circuit unit are connected to the output terminal of the signal acquisition circuit unit. The output terminals of the lightning discharge follower circuit unit and the lightning discharge peak hold circuit unit are connected to the input terminal of the automatic discharge circuit unit. The output terminal of the automatic discharge circuit unit is connected to the input terminal of the accumulation circuit unit. The signal acquisition circuit unit is used to acquire the lightning current signal. The lightning discharge peak hold circuit unit detects the current peak value based on the lightning current signal. The lightning discharge follower circuit unit is used to monitor the amplitude change of the lightning current. The automatic discharge circuit unit is used to automatically control the charging and discharging of the lightning discharge peak hold circuit unit. The accumulation circuit unit is used to accumulate and measure the number of current peak values. Each main discharge or return stroke discharge has a current peak (refer to...). Figure 2 Therefore, by collecting lightning current signals and detecting the number of peaks in the lightning current waveform, the number of main discharges and backstrokes can be detected.

[0031] like Figure 1In the structure shown, the signal acquisition circuit unit includes a current sensor T1, a load resistor RL, and a bridge rectifier diode D4. The output terminal of the current sensor T1 is connected in parallel with the load resistor RL and then connected to the AC input pin of the bridge rectifier diode D4. The negative output pin of the bridge rectifier diode D4 is grounded (GND). The input terminal of the current sensor T1 is connected to the grounding wire of the surge arrester, acquiring the large current discharge signal in the surge arrester's grounding wire non-contactly and proportionally transforming it into a small current signal. The purpose of this reduction is that the peak current of lightning discharge can typically reach several thousand to tens of thousands of amperes. Directly connecting it to the circuit for acquisition would damage the circuit. Therefore, a non-contact current sensor is used to sample the signal, converting the large current into a small current for acquisition, avoiding damage from high voltage and high current input to the circuit. Non-contact sensors such as current transformers, Rogowski coils, and Hall effect sensors can be used as the current sensor. It is important to note that the terms "large current" and "small current" here are relative concepts, emphasizing the reduction of the current from a large value to a small value.

[0032] The current signal is then converted into a voltage signal by the load resistor RL. The bridge rectifier diode D4 converts the negative discharge waveform into a positive waveform.

[0033] The lightning discharge peak holding circuit unit includes a first resistor R1, a second resistor R2, a first operational amplifier U1, a first diode D1, and a first capacitor C1. The positive output terminal of the bridge rectifier diode D4 is connected to the non-inverting input terminal of the first operational amplifier U1 through the second resistor R2. The two ends of the first resistor R1 are connected to the non-inverting input terminal and the output terminal of the first operational amplifier U1, respectively. The inverting input terminal of the first operational amplifier U1 is grounded. The output terminal of the first operational amplifier U1 is connected to the positive terminal of the first diode D1. The negative terminal of the first diode D1 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded.

[0034] The function of the first operational amplifier U1 is to amplify the amplitude of the input voltage signal, reduce the output impedance, increase the driving capability, and charge and discharge the first capacitor C1. The first resistor R1 and the second resistor R2 serve as matching resistors for the operational amplifier parameters, and their resistance values ​​determine the amplification factor of the first operational amplifier. The function of the first capacitor C1 is to maintain the peak voltage when the lightning current begins to decrease after reaching its peak value.

[0035] The lightning discharge follower circuit unit includes a third resistor R3, a fourth resistor R4, a second operational amplifier U2, a second diode D2, a third diode D3, and a second capacitor C2. The positive output terminal of the bridge rectifier diode D4 is connected to the non-inverting input terminal of the second operational amplifier U2 through the fourth resistor R4. The two ends of the third resistor R3 are connected to the non-inverting input terminal and the output terminal of the second operational amplifier U2, respectively. The inverting input terminal of the second operational amplifier U2 is grounded. The output terminal of the second operational amplifier U2 is connected to the positive terminal of the third diode D3 and the negative terminal of the second diode D2. The positive terminal of the second diode D2 and the negative terminal of the third diode D3 are connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded.

[0036] The function of the second operational amplifier U2 is to amplify the amplitude of the input voltage signal, reduce the output impedance, increase the driving capability, and charge and discharge the second capacitor C2. The third resistor R3 and the fourth resistor R4 are used for parameter matching of the operational amplifier; their resistance values ​​determine the amplification factor of the second operational amplifier U2. The first capacitor C1 and the second capacitor C2 are capacitors with the same model parameters. The function of the second capacitor C2 is to offset the voltage drop generated during the charging process of the first capacitor C1, ensuring that the voltages across the first capacitor C1 and the second capacitor C2 are the same during charging.

[0037] In this circuit, the parameters of the first resistor R1 and the third resistor R3 are the same, and the parameters of the second resistor R2 and the fourth resistor R4 are the same. Therefore, the amplification factors of the first operational amplifier U1 and the second operational amplifier U2 are the same. The first diode D1, the second diode D2, and the third diode D3 can be low-voltage-drop diodes or MOS ideal diodes with the same model parameters. The function of the first diode D1 is unidirectional isolation; the first operational amplifier U1 can charge the first capacitor C1 through the first diode D1, and conversely, the first capacitor C1 cannot discharge to the first operational amplifier U1 through the first diode D1, thus maintaining the voltage of the first capacitor C1 at the peak voltage output of the first operational amplifier U1. The function of the third diode D3 is to cancel the voltage drop caused by the first diode D1, making the voltage drops through the first diode D1 and the third diode D3 the same. The function of the second diode D2 is to provide a path for the reverse discharge of the second operational amplifier U2. The first operational amplifier U1 and the second operational amplifier U2 can be high-speed operational amplifiers.

[0038] The automatic discharge circuit unit includes a comparator U3 and a PMOS transistor PM1. The non-inverting input of comparator U3 is connected to the negative terminal of the first diode D1 and the source of PMOS transistor PM1. The inverting input of comparator U3 is connected to the negative terminal of the third diode D3 and the positive terminal of the second diode D2. The drain of PMOS transistor PM1 is grounded, and the gate of PMOS transistor PM1 is connected to the output of comparator U3. Comparator U3 can be a low offset voltage model.

[0039] The function of comparator U3 is to compare the two input voltages. When the voltage at the non-inverting input terminal (IN+) is higher than that at the inverting input terminal (IN-) and the difference is greater than the device offset voltage, its output terminal (OUT) is high; otherwise, it outputs a low level. When the input voltages are equal or the difference is less than the comparator's offset voltage, the output voltage remains unchanged.

[0040] When comparator U3 outputs a high level, PMOS transistor PM1 is turned on; when it outputs a low level, PMOS transistor PM1 is turned off. The function of PMOS transistor PM1 is to act as a control switch to discharge the first capacitor C1. When PMOS transistor PM1 is turned on, the first capacitor C1 is short-circuited and discharged; when PMOS transistor PM1 is turned off, the discharge stops.

[0041] The accumulator circuit unit includes multiple JK flip-flops. The output of comparator U3 is connected to the CP input pin of the first JK flip-flop X1. When there are multiple JK flip-flops, the Q pin of the previous JK flip-flop is connected to the CP pin of the next JK flip-flop, bringing out the Q pins (Q0 to Qn-1) of all JK flip-flops, and bringing out the reset pin P2. The J and K pins of all JK flip-flops are connected to the high-level pin P1 in the circuit, and the R pins of all JK flip-flops are connected to the reset pin P2.

[0042] Figure 1 In this circuit, JK flip-flops X1-Xn are JK flip-flops of the same model, forming an accumulator to accumulate and count the number of discharge peaks. The binary value is output through the high and low level states of the output pin Q of each JK flip-flop.

[0043] Figure 1 The principle of the detection circuit shown is as follows: like Figure 2 , Figure 3 , Figure 4 , Figure 5As shown, at time t0, the detection circuit is powered on and starts working. At this time, the current sensor T1 does not detect the lightning current, so the current sensor T1 has no secondary output current. The voltage across the load resistor RL is 0, the positive and negative outputs of the fourth diode D4 are 0, the input and output of the first operational amplifier U1 and the second operational amplifier U2 are 0, the voltage across the first capacitor C1 and the second capacitor C2 is 0, the non-inverting and inverting inputs of comparator U3 are equal, the output (P0) of comparator U3 remains in the initial state of power-on, i.e., low level, the PMOS transistor PM1 is cut off, no falling edge is detected at the input pin CP of all JK flip-flops, and all outputs Q are low level, indicating that the current discharge count is 0.

[0044] When the current sensor T1 detects the main amplifier current signal, before the current rise phase (time t1), the voltage across the load resistor RL keeps rising, the output voltage of the fourth diode D4 rises, the input voltages of the first operational amplifier U1 and the second operational amplifier U2 rise with equal amplitude, the output voltages of the first operational amplifier U1 and the second operational amplifier U2 rise with equal amplitude, the voltages across the first capacitor C1 and the second capacitor C2 are equal, the input voltage of comparator U3 is equal, the output of comparator U3 remains at a low level, PMOS transistor PM1 is cut off, the CP pins of all JK flip-flops are not triggered, and all output Q pins are at a low level. After the current reaches its peak value t1, it begins to decrease rapidly. That is, after time t1, the voltage across the load resistor RL begins to decrease, the output voltage of the fourth diode D4 decreases, and the input and output voltages of the first operational amplifier U1 and the second operational amplifier U2 decrease. At this time, the voltage across the first capacitor C1 is higher than the output voltage of the first operational amplifier U1. Due to the reverse isolation of the first diode D1, the first capacitor C1 cannot discharge to the first operational amplifier U1, and the voltage across the first capacitor C1 remains at the peak voltage at time t1. Similarly, the voltage across the second capacitor C2 is higher than the output voltage of the second operational amplifier U2. Since the second diode D2 begins to conduct, the second capacitor C2 begins to discharge to the second operational amplifier U2, and the voltage across the second capacitor C2... As the current begins to decrease, the voltage at the non-inverting input of comparator U3 becomes higher than that at the inverting input, causing comparator U3 to output a high level. At this time, PMOS transistor PM1 turns on, short-circuiting and discharging the first capacitor C1. The voltage drop rate of the first capacitor C1 is much faster than that of the second capacitor C2. When the voltage of the first capacitor C1 falls below the voltage of the second capacitor C2, comparator U3 immediately outputs a low level, PMOS transistor PM1 turns off, and the voltage of the first capacitor C1 quickly returns to the same level as the second capacitor C2. Comparator U3 remains in a low-level state. That is, comparator U3 outputs a pulse signal at the instant the current passes the peak. The falling edge of this pulse signal triggers the first JK flip-flop X1, causing the Q0 pin of X1 to output a high level, indicating that the current discharge count is 1. Similarly, during the second discharge, after the t2 peak, JK flip-flop X1 is triggered again, Q0 outputs a low level, triggering X2, causing Q1 to output a high level, indicating that the current discharge count is 2. The maximum number of discharge records is related to the number of JK flip-flops. With n JK flip-flops, the maximum number of records is... The number of discharges currently recorded can be calculated based on the voltage levels of pins Q0 to Qn-1, using the following formula: When pin Qx is high, Qx=1; when pin Qx is low, Qx=0.

[0045] When the number of records reaches its maximum value, i.e., Q0 to Qn-1 are all high, according to the circuit's working principle, upon detecting the first... During the next discharge, this circuit can automatically reset to zero, meaning that Q0 to Qn-1 all toggle to low level. All JK-triggered reset pins are connected to the reset pin P2, or a low-level reset signal can be input to point P1 to achieve external active reset to zero lightning strike count.

[0046] The aforementioned detection circuit uses operational amplifiers, comparators, JK flip-flops, and other electronic devices with response capabilities generally ranging from several nanoseconds to tens of nanoseconds. The circuit's response capability is far higher than the duration of lightning discharge (tens of microseconds), thus enabling effective detection of the number of lightning discharge peaks and solving the problem that existing counters cannot effectively measure return discharge actions.

[0047] In addition, the detection circuit has automatic or manual zeroing function; the output is a digital level signal with good scalability; the acquisition is implemented by pure hardware circuit, without the need for embedded devices such as MCU and DSP, and has the advantages of low power consumption and high stability.

[0048] Figure 1 The detection circuit shown is a relatively perfect structure, which can detect both the number of peak lightning currents and the amplitude of current changes. It can then detect current peaks one by one starting from a lower current, thereby accurately measuring the main discharge and return discharge actions.

[0049] However, in applications with lower requirements, the lightning discharge follower circuit and automatic discharge circuit in the detection circuit can be omitted. In this case, the first capacitor C1 is also unnecessary in the lightning discharge peak holding circuit, and the negative terminal of the first diode D1 is connected to the CP input pin of the first JK flip-flop. This scheme can also record the number of lightning discharges, but it will be affected by the current amplitude and will only be effective when it is close to the upper limit of the circuit's detection range. Assuming... Figure 1 The circuit shown can detect a discharge range of 1A-100kA. However, if the first diode D1 is directly connected to the first JK flip-flop X1, the detectable discharge range will only be 50kA-100kA, which is a reduction in range.

[0050] The above specific embodiments are merely several optional embodiments of the present invention. Based on the technical solutions of the present invention and the relevant teachings of the above embodiments, those skilled in the art can make various alternative improvements and combinations to the above specific embodiments.

Claims

1. A counter for a surge arrester, characterized in that, The device includes a power supply circuit and a detection circuit. The power supply circuit provides power to the detection circuit, which is used to detect and measure the number of lightning discharge peaks. The detection circuit includes a signal acquisition circuit unit, a lightning discharge peak value holding circuit unit, and an accumulation circuit unit. The signal acquisition circuit unit is used to acquire lightning current signals, the lightning discharge peak value holding circuit unit detects current peak values ​​based on the lightning current signals, and the accumulation circuit unit is used to accumulate and measure the number of current peak values.

2. A surge arrester counter according to claim 1, characterized in that, The detection circuit further includes a lightning discharge following circuit unit and an automatic discharge circuit unit. The input terminal of the lightning discharge following circuit unit is connected to the output terminal of the signal acquisition circuit unit. The output terminals of the lightning discharge following circuit unit and the lightning discharge peak holding circuit unit are both connected to the input terminal of the automatic discharge circuit unit. The output terminal of the automatic discharge circuit unit is connected to the input terminal of the accumulation circuit unit. The lightning discharge following circuit unit is used to monitor the amplitude change of the lightning current, and the automatic discharge circuit unit is used to automatically control the charging and discharging of the lightning discharge peak holding circuit unit.

3. A counter for a surge arrester according to claim 2, characterized in that, The lightning discharge peak holding circuit unit includes a first resistor, a second resistor, a first operational amplifier, a first diode, and a first capacitor. The output terminal of the signal acquisition circuit unit is connected to the non-inverting input terminal of the first operational amplifier through the second resistor. The two ends of the first resistor are connected to the non-inverting input terminal and the output terminal of the first operational amplifier, respectively. The inverting input terminal of the first operational amplifier is grounded. The output terminal of the first operational amplifier is connected to the positive terminal of the first diode. The negative terminal of the first diode is connected to one end of the first capacitor, and the other end of the first capacitor is grounded.

4. A surge arrester counter according to claim 3, characterized in that, The lightning discharge follower circuit unit includes a third resistor, a fourth resistor, a second operational amplifier, a second diode, a third diode, and a second capacitor. The output terminal of the signal acquisition circuit unit is connected to the non-inverting input terminal of the second operational amplifier through the fourth resistor. The two ends of the third resistor are connected to the non-inverting input terminal and the output terminal of the second operational amplifier, respectively. The inverting input terminal of the second operational amplifier is grounded. The output terminal of the second operational amplifier is connected to the positive terminal of the third diode and the negative terminal of the second diode. The positive terminal of the second diode and the negative terminal of the third diode are both connected to one end of the second capacitor, and the other end of the second capacitor is grounded. The parameters of the first resistor and the third resistor are the same, and the parameters of the second resistor and the fourth resistor are the same.

5. A surge arrester counter according to claim 4, characterized in that, The automatic discharge circuit unit includes a comparator and a PMOS transistor. The non-inverting input terminal of the comparator is connected to the negative terminal of the first diode and the source terminal of the PMOS transistor. The inverting input terminal of the comparator is connected to the negative terminal of the third diode and the positive terminal of the second diode. The drain terminal of the PMOS transistor is grounded. The output terminal of the comparator is connected to the gate terminal of the PMOS transistor and the input terminal of the accumulator circuit unit.

6. A surge arrester counter according to claim 1, characterized in that, The lightning discharge peak holding circuit unit includes a first resistor, a second resistor, a first operational amplifier, and a first diode. The output terminal of the signal acquisition circuit unit is connected to the non-inverting input terminal of the first operational amplifier through the second resistor. The two ends of the first resistor are connected to the non-inverting input terminal and the output terminal of the first operational amplifier, respectively. The inverting input terminal of the first operational amplifier is grounded. The output terminal of the first operational amplifier is connected to the positive terminal of the first diode. The negative terminal of the first diode is connected to the input terminal of the accumulation circuit unit.

7. A surge arrester counter according to claim 3 or 6, characterized in that, The signal acquisition circuit unit includes a current sensor, a load resistor, and a bridge rectifier diode. The output terminal of the current sensor is connected in parallel with the load resistor and then connected to the AC input pin of the bridge rectifier diode. The negative output pin of the bridge rectifier diode is grounded. The positive output terminal of the bridge rectifier diode is connected to the non-inverting input pin of the first operational amplifier through a second resistor. The input terminal of the current sensor is used to connect to the grounding wire of the surge arrester.

8. A surge arrester counter according to claim 5 or 6, characterized in that, The accumulator circuit unit includes multiple JK flip-flops. The CP input pin of the first JK flip-flop serves as the input terminal of the accumulator circuit unit. The Q pin of the previous JK flip-flop is connected to the CP pin of the next JK flip-flop, leading out the Q pins of all JK flip-flops. The J and K pins of all JK flip-flops are connected to a high-level pin in the detection circuit.

9. A counter for a surge arrester according to claim 8, characterized in that, A reset pin is provided, and the R pins of all JK flip-flops are connected to the reset pin; the surge arrester counter also includes a control interface connected to the reset pin.

10. A counter for a surge arrester according to claim 8, characterized in that, It also includes an output interface that connects to the Q pin of all JK flip-flops.

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