System management unit of intelligent hardware equipment and management method thereof

Abstract

The invention discloses a system management unit of intelligent hardware equipment and a management method thereof, the system management unit is connected with a main SoC through a communication interface, and the system management unit comprises a power management module, an encryption authorization module, a software watchdog module, an IO expansion module, an industrial purpose module and a power management module, a real-time clock RTC is arranged in the power management module and used for peripheral power management, soft shutdown, timed awakening and ACPI standard S3 dormancy awakening, the encryption authorization module is used for device information management and storing a serial number, a unique identifier and a special key of a device, and the software watchdog module is used for achieving an external timed dog feeding function. The IO expansion module comprises a plurality of GPIO (General Purpose Input / Output) pins and is used for providing additional IO interfaces when IO interfaces of equipment are insufficient, and the industrial purpose module is used as a second control chip and takes over a power supply and a key IO unit when the main SoC crashes. The system can achieve unified equipment management, is high in safety and reliability, is low in cost, and is multifunctional.

Description

Technical Field

[0001] This invention relates to a management system for smart hardware, specifically a system management unit for a smart hardware device and its management method. Background Technology

[0002] With the widespread application of smart hardware devices, their security, manageability, and reliability have become critical issues. Currently, the market lacks a unified device ID interface and device information storage method, leading to numerous inconveniences in device identification, management, and security protection. Existing technologies for smart hardware devices exhibit the following shortcomings in power management, encryption authorization, software watchdog timers, and peripheral device management: 1. Limited power management functions: Existing devices lack functions such as timed soft shutdown, timed power-on, and ACPI standard S3 sleep / wake-up, which affects user experience; 2. Insecure storage of equipment information: The storage methods for equipment serial numbers, unique identifiers, and other information are not standardized, making them easy to tamper with or leak, posing security risks. 3. Inadequate software watchdog functionality: The existing software watchdog functionality of the equipment cannot effectively prevent system crashes or malfunctions, affecting the reliability of the equipment; 4. Insufficient peripheral I / O expansion: The number of I / O interfaces in existing devices is limited and cannot meet the needs of complex application scenarios; 5. Insufficient support for industrial applications: Existing devices cannot effectively take over important I / O units such as power supply when the main SoC crashes, affecting the normal operation of the device. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a system management unit and management method for intelligent hardware devices that can achieve unified device management, high security and reliability, low cost and multiple functions.

[0004] The present invention is achieved through the following technical solution: a system management unit for a smart hardware device, wherein the system management unit is connected to the main SoC through a communication interface, and the system management unit includes a power management module, an encryption authorization module, a software watchdog module, an IO expansion module, and an industrial application module; The power management module has a built-in real-time clock (RTC) for power management of peripherals, enabling soft shutdown, timed power-on, and ACPI standard S3 sleep wake-up. The encryption authorization module is used for device information management and stores the device's serial number (SN), unique identifier (ID), and special key; The software watchdog module is used to implement an external timed watchdog feeding function; The IO expansion module includes several general purpose input / output (GPIO) pins to provide additional IO interfaces when the device's IO interfaces are insufficient. The industrial application module is used as a second control chip to take over the power supply and critical I / O units when the main SoC crashes.

[0005] Furthermore, the communication interface is an I2C interface or a OneWire communication interface, and the software watchdog module includes a WDI-IN interface and an RST-OUT interface.

[0006] Furthermore, the encryption authorization module uses a one-time programmable memory to store the serial number, unique identifier, and special key of the device.

[0007] A method for managing smart hardware devices includes the following steps: Device initialization steps: When the device starts up, the system management unit communicates with the main SoC through the communication interface to complete the device initialization; Power management steps: Based on the device's operating status and user settings, the system management unit uses the power management module to implement soft shutdown, timed power-on, and ACPI standard S3 sleep wake-up; Encryption authorization steps: The system management unit stores the device's SN, ID, special key, and other information through the encryption authorization module, and performs security verification during device operation; Software watchdog process: The system management unit implements an external timed watchdog feeding function through the software watchdog module. When a system abnormality is detected, a reset operation is performed. IO expansion steps: Provide additional IO interfaces to the main SoC through the IO expansion module of the system management unit; Industrial application procedure: When the main SoC crashes, the system management unit takes over the power supply and critical I / O units.

[0008] Furthermore, when the main SOC acts as the master device and the system management unit acts as the slave device, the communication process between the system management unit and the main SOC is as follows: The main SOC, acting as the master device, sends a START signal to initiate communication. The main SOC sends "function address + read bit"; After the system management unit identifies its own function address, it sends an ACK signal to confirm. The main SOC begins sending command data from the functional modules byte by byte, one byte at a time, and waits for ACK from the system management unit. After receiving the required command data, the system management unit begins to execute the corresponding function command and returns the execution result data. After receiving the command execution result data, the main SOC sends a non-acknowledgment signal (NACK) to inform the system management unit to "stop sending"; After receiving the result, the main SOC sends a STOP signal to terminate the current communication.

[0009] Furthermore, the power management steps include: The user presses the power GPIO button to send a power-on message to the system management unit. The system management unit responds to the power-on signal and controls the power management module to supply power to the main SoC. The system management unit receives the soft shutdown command sent by the main SoC through the communication interface, and in response to the soft shutdown command, cuts off the power supply to the main SoC; The system management unit uses a built-in real-time clock (RTC) to trigger power supply to the main SoC to complete timed wake-up or sleep wake-up based on preset timing conditions or wake-up conditions received from the autonomous SoC. The condition for triggering sleep wake-up is that the main SoC sends a wake-up activation condition to the system management unit before entering ultra-low power mode. When the condition is met, the main SoC is quickly woken up. If both timed wake-up and external signal wake-up conditions exist for the main SoC, external signal wake-up takes priority. The execution of cutting off the main SoC's power supply is initiated by the main SoC issuing a power-off command.

[0010] Furthermore, the software watchdog step includes: The system management unit receives the watchdog timeout threshold configured by the main SoC; Monitor whether a dog feed signal is received from the main SoC within the timeout threshold; If the dog feed signal is not received within the timeout period, the main SoC is determined to be abnormal, and a reset operation is triggered. When a timeout triggers a reset operation, the software watchdog module continues to monitor the main SoC during the reset process. If a second timeout occurs, the software watchdog module will trigger again and reset the main SoC again until the main SoC is normal and takes over feeding the watchdog.

[0011] Furthermore, the IO expansion step includes: The system management unit receives I / O control commands sent by the main SoC through the communication interface; Parse I / O control commands and execute the corresponding input or output operations through the GPIO pins of the system management unit.

[0012] Furthermore, the industrial application step includes: When the main SoC is determined to be abnormal, control of critical peripherals is taken over through the GPIO pins of the system management unit; After the main SoC is reset and returns to normal, control of critical peripherals is returned to the main SoC.

[0013] Furthermore, the trigger reset operation includes: performing a power cycle reset operation on the main SoC.

[0014] Compared with the prior art, the present invention has the following beneficial effects: The system management unit of this invention includes a power management module, an encryption authorization module, a software watchdog module, an I / O expansion module, and an industrial application module. It realizes functions such as power management, encryption authorization, software watchdog, and external management, improving the security, manageability, and reliability of the device. Moreover, the system management unit adopts a modular design and communicates with the main SoC through an I2C interface or OneWire communication protocol to achieve unified management and control of the device. It is low-cost, requires no additional external components, reduces the overall cost of the device, and is compact in size, making it suitable for various smart hardware devices. Attached Figure Description

[0015] Figure 1 This is an architecture diagram of a system management unit for a smart hardware device according to the present invention; Figure 2 This is a flowchart of a management method for a smart hardware device according to the present invention; Figure 3 This is a timing diagram showing the interaction between the system management unit and the main SOC of the present invention. Detailed Implementation

[0016] Reference Figure 1 A system management unit for a smart hardware device, wherein the system management unit is connected to the main SoC via a communication interface, and the system management unit includes a power management module, an encryption authorization module, a software watchdog module, an I / O expansion module, and an industrial application module.

[0017] The power management module, which has a built-in real-time clock (RTC), is used for power management of peripherals, enabling soft shutdown, timed power-on, and ACPI standard S3 sleep wake-up.

[0018] The encryption authorization module is used for device information management and stores the device's serial number (SN), unique identifier (ID), and special key.

[0019] The key generation rules are based on the hardware characteristics of the chip device and are generated using a hardware random number generator.

[0020] The software watchdog module is used to implement an external timed watchdog feeding function.

[0021] The IO expansion module includes several general purpose input / output (GPIO) pins to provide additional IO interfaces when the device's IO interfaces are insufficient.

[0022] The number of GPIO pins in the IO expansion module is greater than the number of pins occupied by the core of the system management unit itself. The main SoC implements the IO expansion function by reading and writing the state of the GPIO pins.

[0023] The industrial application module is used as a second control chip to take over the power supply and critical I / O units when the main SoC crashes.

[0024] The communication interface is an I2C interface or a OneWire communication interface, and the software watchdog module includes a WDI-IN interface and an RST-OUT interface.

[0025] The system management unit can be a CH32V003F4P6 in a TSSOP-20 package. The TSSOP-20 package has the following pin functions: one OneWire (ONE_SDA) (which can be reused as an interrupt pin), two I2C signals (I2C_SDA, I2C_SCL), two power signals (PW_KEY, PW_EN), and three watchdog signals (WDT_SDI, WDT_RST, WDT_EN). Excluding the necessary MCU pins, there are eight additional usable GPIOs.

[0026] The encryption authorization module uses a one-time programmable memory to store the serial number, unique identifier, and special key of the device.

[0027] The one-time programmable memory is a 4k OTP memory built into the chip. The certificate is generated using the ED25519 algorithm and automatically fuses after the first initialization, making it unmodifiable.

[0028] Reference Figure 2 A method for managing smart hardware devices includes the following steps: Device initialization steps: When the device starts up, the system management unit communicates with the main SoC through the communication interface to complete the device initialization.

[0029] Power management steps: Based on the device's operating status and user settings, the system management unit uses the power management module to implement soft shutdown, timed power-on, and ACPI standard S3 sleep wake-up.

[0030] Encryption authorization steps: The system management unit stores information such as the device's SN, ID, and special key through the encryption authorization module, and performs security verification during device operation.

[0031] Software watchdog process: The system management unit implements an external timed watchdog feeding function through the software watchdog module. When a system abnormality is detected, a reset operation is performed.

[0032] IO expansion steps: Provide additional IO interfaces to the main SoC through the IO expansion module of the system management unit.

[0033] Industrial application procedure: When the main SoC crashes, the system management unit takes over the power supply and critical I / O units.

[0034] The power management steps include: The user presses the power GPIO button to send a power-on message to the system management unit. In response to the power-on signal, the system management unit controls the power management module to supply power to the main SoC.

[0035] The system management unit receives the soft shutdown command sent by the main SoC through the communication interface, and in response to the soft shutdown command, cuts off the power supply to the main SoC.

[0036] The system management unit uses a built-in real-time clock (RTC) to trigger power supply to the main SoC to complete timed wake-up or sleep wake-up based on preset timing conditions or wake-up conditions received from the autonomous SoC. The condition for triggering sleep wake-up is that the main SoC sends a wake-up activation condition to the system management unit before entering ultra-low power mode. When the condition is met, the main SoC is quickly woken up.

[0037] If both timed wake-up and external signal wake-up conditions exist for the main SoC, external signal wake-up takes priority. The execution of cutting off the main SoC's power supply is handled by the main SoC issuing the power-off command itself.

[0038] The software watchdog process includes: The system management unit receives the watchdog timeout threshold configured by the main SoC.

[0039] Monitor whether a dog feed signal is received from the main SoC within the timeout threshold.

[0040] If the dog feed signal is not received within the timeout period, the main SoC is determined to be abnormal, and a reset operation is triggered.

[0041] The trigger reset operation includes: performing a power cycle reset operation on the main SoC.

[0042] When a timeout triggers a reset, the software watchdog module continues to monitor the main SoC during the reset process. If a second timeout occurs, the software watchdog module will trigger again and reset the main SoC again until the main SoC returns to normal and takes over feeding the watchdog. The timeout period is 5 minutes.

[0043] The IO expansion steps include: The system management unit receives I / O control commands sent by the main SoC through the communication interface.

[0044] Parse I / O control commands and execute the corresponding input or output operations through the GPIO pins of the system management unit.

[0045] The industrial application steps include: When the main SoC is determined to be abnormal, control of critical peripherals is taken over through the GPIO pins of the system management unit.

[0046] After the main SoC is reset and returns to normal, control of critical peripherals is returned to the main SoC.

[0047] Reference Figure 3 , Figure 3 This is a timing diagram of the interaction between the master SOC and the system management unit. The data content in the Data section indicates whether it was sent by the master SOC or returned by the system management unit. The master SOC, as the master device, sends a request, and the system management unit, as the slave device, responds with data. The system management unit notifies the master SOC to process the data via a GPIO interrupt signal.

[0048] Referring to the I2C-like protocol, when the master SOC acts as the master device and the system management unit acts as the slave device, the SCL signal is provided by the master SOC.

[0049] Figure 3 The ADDRESS section contains the request addresses for various functions. For example, the address for the reference power control section is 0x20, and the address for the software watchdog control section is 0x40. When the main SOC acts as the master device and the system management unit acts as the slave device, the communication process between the system management unit and the main SOC is as follows: The main SOC, acting as the master device, sends a START signal to initiate communication. The main SOC sends "function address + read bit"; After the system management unit identifies its own function address, it sends an ACK signal to confirm. The main SOC begins sending command data from the functional modules byte by byte, one byte at a time, and waits for ACK from the system management unit. After receiving the required command data, the system management unit begins to execute the corresponding function command and returns the execution result data. After receiving the command execution result data, the main SOC sends a non-acknowledgment signal (NACK) to inform the system management unit to "stop sending"; After receiving the result, the main SOC sends a STOP signal to terminate the current communication.

[0050] During each communication, the master SOC initiates a communication request by pulling the SDA and SCL signal levels high from low, sending a START signal to start the communication handshake, enabling the SCL clock signal, sending the function module address via SDA, and providing a read / write operation flag. After completion, the master SOC pulls the SDA data line low and waits for a response from the system management unit (SMU). When the SMU receives the function address and flag, if the function exists at the address, it sends an ACK response (otherwise, the communication ends). Upon receiving the ACK response from the SMU, the master SOC sends the requested function data to the SMU. The SMU receives the data and returns an ACK, along with the execution result of the requested command data. The master SOC, upon receiving the data, returns an ACK to inform the SMU that data reception is complete and ends the communication.

[0051] The above detailed description is a specific description of feasible embodiments of the present invention. These embodiments are not intended to limit the patent scope of the present invention. All equivalent implementations or modifications that do not depart from the present invention should be included in the patent scope of this case.

Claims

1. A system management unit for an intelligent hardware device, characterized in that: The system management unit is connected to the main SoC via a communication interface. The system management unit includes a power management module, an encryption and authorization module, a software watchdog module, an I / O expansion module, and an industrial application module. The power management module has a built-in real-time clock (RTC) for power management of peripherals, enabling soft shutdown, timed power-on, and ACPI standard S3 sleep wake-up. The encryption authorization module is used for device information management and stores the device's serial number (SN), unique identifier (ID), and special key; The software watchdog module is used to implement an external timed watchdog feeding function; The IO expansion module includes several general purpose input / output (GPIO) pins to provide additional IO interfaces when the device's IO interfaces are insufficient. The industrial application module is used as a second control chip to take over the power supply and critical I / O units when the main SoC crashes.

2. The system management unit of a smart hardware device according to claim 1, characterized in that: The communication interface is an I2C interface or a OneWire communication interface, and the software watchdog module includes a WDI-IN interface and an RST-OUT interface.

3. The system management unit of a smart hardware device according to claim 1, characterized in that: The encryption authorization module uses a one-time programmable memory to store the serial number, unique identifier, and special key of the device.

4. A method for managing intelligent hardware devices, characterized in that, Includes the following steps: Device initialization steps: When the device starts up, the system management unit communicates with the main SoC through the communication interface to complete the device initialization; Power management steps: Based on the device's operating status and user settings, the system management unit uses the power management module to implement soft shutdown, timed power-on, and ACPI S3 sleep wake-up; Encryption authorization steps: The system management unit stores the device's SN, ID, special key, and other information through the encryption authorization module, and performs security verification during device operation; Software watchdog process: The system management unit implements an external timed watchdog feeding function through the software watchdog module. When a system abnormality is detected, a reset operation is performed. IO expansion steps: Provide additional IO interfaces to the main SoC through the IO expansion module of the system management unit; Industrial application procedure: When the main SoC crashes, the system management unit takes over the power supply and critical I / O units.

5. The management method for a smart hardware device according to claim 4, characterized in that, When the main SOC acts as the master device and the system management unit acts as the slave device, the communication process between the system management unit and the main SOC is as follows: The main SOC, acting as the master device, sends a START signal to initiate communication. The main SOC sends "functional address + read bit"; After the system management unit identifies its own function address, it sends an ACK signal to confirm. The main SOC begins sending command data from the functional modules byte by byte, one byte at a time, and waits for ACK from the system management unit. After receiving the required command data, the system management unit begins to execute the corresponding function command and returns the execution result data. After receiving the command execution result data, the main SOC sends a non-acknowledgment signal (NACK) to inform the system management unit to "stop sending"; After receiving the result, the main SOC sends a STOP signal to terminate the current communication.

6. The management method for a smart hardware device according to claim 4, characterized in that, The power management steps include: The user presses the power GPIO button to send a power-on message to the system management unit. The system management unit responds to the power-on signal and controls the power management module to supply power to the main SoC. The system management unit receives the soft shutdown command sent by the main SoC through the communication interface, and in response to the soft shutdown command, cuts off the power supply to the main SoC; The system management unit uses a built-in real-time clock (RTC) to trigger power supply to the main SoC to complete timed wake-up or sleep wake-up based on preset timing conditions or wake-up conditions received from the autonomous SoC. The condition for triggering sleep wake-up is that the main SoC sends a wake-up activation condition to the system management unit before entering ultra-low power mode. When the condition is met, the main SoC is quickly woken up. If both timed wake-up and external signal wake-up conditions exist for the main SoC, external signal wake-up takes priority. The execution of cutting off the main SoC's power supply is initiated by the main SoC issuing a power-off command.

7. The management method for a smart hardware device according to claim 4, characterized in that, The software watchdog process includes: The system management unit receives the watchdog timeout threshold configured by the main SoC; Monitor whether a dog feed signal is received from the main SoC within the timeout threshold; If the dog feed signal is not received within the timeout period, the main SoC is determined to be abnormal, and a reset operation is triggered. When a timeout triggers a reset operation, the software watchdog module continues to monitor the main SoC during the reset process. If a second timeout occurs, the software watchdog module will trigger again and reset the main SoC again until the main SoC is normal and takes over feeding the watchdog.

8. The management method for a smart hardware device according to claim 4, characterized in that, The IO expansion steps include: The system management unit receives I / O control commands sent by the main SoC through the communication interface; Parse I / O control commands and execute the corresponding input or output operations through the GPIO pins of the system management unit.

9. The management method for a smart hardware device according to claim 4, characterized in that, The industrial application steps include: When the main SoC is determined to be abnormal, control of critical peripherals is taken over through the GPIO pins of the system management unit; After the main SoC is reset and returns to normal, control of critical peripherals is returned to the main SoC.

10. The management method for a smart hardware device according to claim 7, characterized in that, The trigger reset operation includes: performing a power cycle reset operation on the main SoC.

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