Arbitration circuit and arbitration method for battery management system

Abstract

The invention provides an arbitration circuit and an arbitration method for a battery management system, and relates to the technical field of battery management. The arbitration circuit includes: a plurality of input interfaces configured to receive a plurality of wake-up signals; and the priority coding circuit is connected with the plurality of input interfaces. The priority coding circuit comprises a first output pin and a second output pin, wherein the first output pin is configured to be connected with an enabling pin of a power management chip in a battery management unit of the battery management system; and the second output pin is configured to be connected with a micro-control unit in the battery management unit. The priority coding circuit is configured to respond to the existence of an effective wake-up signal in the plurality of wake-up signals: outputting an enable signal to an enable pin of the power management chip through the first output pin, so that the power management chip supplies power to the battery management unit, and outputting a code corresponding to the effective wake-up signal with the highest priority in the plurality of wake-up signals to the micro-control unit through the second output pin.

Description

Technical Field

[0001] This disclosure relates to the field of battery management technology, and in particular to an arbitration circuit and arbitration method for a BMS (Battery Management System). Background Technology

[0002] With the rapid development of new energy vehicles and the electrification of construction machinery, the Battery Management System (BMS), as the "brain" of the power battery pack, plays a crucial role in performance. The BMS is responsible for monitoring battery status (such as voltage, current, and temperature), estimating state of charge, balancing the battery, managing thermally, and diagnosing faults, which directly affects the safety, lifespan, and reliability of the battery pack and the entire vehicle.

[0003] To meet low-power design requirements, especially when the vehicle is off, the Battery Management System (BMS) typically enters a low-power mode (also known as a sleep mode). In this mode, most of the BMS circuitry is de-energized, with only a very few critical units maintaining a microampere-level quiescent current to maximize battery rest time. When the BMS needs to resume normal operation, it must be "wake up" from low-power mode using a specific signal. Summary of the Invention

[0004] The inventors noted that the wake-up of the BMS in related technologies was not timely enough.

[0005] Analysis revealed that in the relevant technology, each of the multiple wake-up signals is connected to the enable pin of the BMS power management chip via a diode in an OR configuration. Each wake-up signal is also connected to the MCU (Microcontroller Unit) via another diode.

[0006] When a valid wake-up signal is present, the MCU in the BMS needs to use software to poll and scan all wake-up signals to determine the highest priority wake-up signal. This results in the MCU not immediately knowing the reason for wake-up after being woken up, delaying the process of the MCU controlling the BMS to quickly enter the corresponding operating mode, leading to reduced battery management reliability. Furthermore, the software processing has a certain delay, which further delays the process of the MCU controlling the BMS to quickly enter the corresponding operating mode, especially failing to meet the immediacy requirements of high-priority wake-ups, and also increasing the power consumption from wake-up to controlling the BMS to enter the corresponding operating mode.

[0007] To address at least one of the above problems, this disclosure provides an arbitration circuit and arbitration method for a BMS, which can wake up the MCU in the BMS in a timely manner to improve the reliability of battery management.

[0008] According to a first aspect of this disclosure, an arbitration circuit for a battery management system is provided, comprising: a plurality of input interfaces configured to receive a plurality of wake-up signals; and a priority encoding circuit connected to the plurality of input interfaces. The priority encoding circuit includes: a first output pin configured to be connected to an enable pin of a power management chip in a battery management unit of the battery management system; and a second output pin configured to be connected to a microcontroller unit in the battery management unit. The priority encoding circuit is configured to, in response to the presence of a valid wake-up signal among the plurality of wake-up signals: output an enable signal to the enable pin of the power management chip via the first output pin, so that the power management chip supplies power to the battery management unit; and output the code corresponding to the highest priority valid wake-up signal among the plurality of wake-up signals to the microcontroller unit via the second output pin.

[0009] In some embodiments, the second output pin includes multiple output pins, and the encoding is binary encoding.

[0010] In some embodiments, the arbitration circuit further includes a signal processing circuit, which includes one or more signal processing sub-circuits. Each signal processing sub-circuit is connected between a corresponding input interface and the priority encoding circuit. Each signal processing sub-circuit includes: a first resistor, a first end of which is connected to the corresponding input interface, and a second end of which is connected to the priority encoding circuit; and a first capacitor connected between the second end of the first resistor and a ground terminal.

[0011] In some embodiments, the one or more signal processing sub-circuits include a first signal processing sub-circuit, which, in addition to the first resistor and the first capacitor, further includes a second capacitor connected between a first terminal of the first resistor and a ground terminal.

[0012] In some embodiments, the wake-up signal received by the corresponding input interface to which the first signal processing sub-circuit is connected comes from outside the battery management unit (BMU) where the arbitration circuit is located.

[0013] In some embodiments, the one or more signal processing sub-circuits include a second signal processing sub-circuit, the second signal processing sub-circuit does not include the second capacitor, and the wake-up signal received by the corresponding input interface to which the second signal processing sub-circuit is connected comes from the BMU where the arbitration circuit is located.

[0014] In some embodiments, each signal processing sub-circuit further includes: a first Schmitt trigger, the input of which is connected to the second terminal of the first resistor, and the output of which is connected to the priority encoding circuit.

[0015] In some embodiments, at least one signal processing sub-circuit further includes a second resistor connected between the input terminal of the first Schmitt trigger and the ground terminal.

[0016] In some embodiments, the priority encoding circuit includes: a priority encoder, including a plurality of input pins connected to the plurality of input interfaces; and a second Schmitt trigger, connected between the first output pin and the enable pin of the power management chip, configured to receive an initial enable signal output from the first output pin and output the enable signal to the enable pin of the power management chip.

[0017] According to a second aspect of the present disclosure, a battery management unit is provided, comprising: an arbitration circuit as described in any of the above embodiments; a power management chip configured to supply power to the battery management unit in response to an enable signal; and a microcontroller unit configured to read the code after the battery management unit is supplied with power, and control the power management system to enter an operating mode corresponding to the code.

[0018] According to a third aspect of the present disclosure, a battery management system is provided, comprising: the battery management unit described in any of the above embodiments.

[0019] According to a fourth aspect of the present disclosure, an arbitration method for a battery management system is provided, based on the arbitration circuit described in any of the above embodiments. The method includes: receiving a plurality of wake-up signals; and in response to the presence of a valid wake-up signal among the plurality of wake-up signals: outputting an enable signal to an enable pin of a power management chip via a first output pin, so that the power management chip supplies power to the battery management unit; and outputting the code corresponding to the valid wake-up signal with the highest priority among the plurality of wake-up signals to the microcontroller unit via a second output pin.

[0020] In this embodiment, the arbitration circuit enables the power management chip to supply power to the BMU when a valid wake-up signal is present, and outputs the code corresponding to the highest priority valid wake-up signal among multiple wake-up signals to the MCU in the BMU. After the BMU is powered on, the MCU performs power-on initialization. By directly reading the code corresponding to the highest priority valid wake-up signal, it can immediately determine which wake-up source has activated the BMU. The MCU can then control the BMS to quickly enter the corresponding operating mode, such as fault handling, charging, or network communication. Thus, the priority arbitration of wake-up signals does not rely on software, has a high response speed (e.g., nanosecond level), ensures immediate response to high-priority wake-ups, and has high reliability, thereby improving the reliability of battery management.

[0021] Other features, aspects, and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0022] The accompanying drawings form part of this specification, illustrating exemplary embodiments of the present disclosure, and together with the specification serve to explain the principles of the present disclosure.

[0023] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, in which:

[0024] Figure 1 This is a schematic diagram of the structure of an arbitration circuit for a BMS according to some embodiments of the present disclosure.

[0025] Figure 2 This is a schematic diagram of the structure of an arbitration circuit for a BMS according to other embodiments of the present disclosure.

[0026] Figure 3A This is a schematic diagram of the structure of a signal processing sub-circuit according to some embodiments of the present disclosure.

[0027] Figure 3B This is a schematic diagram of the structure of a signal processing sub-circuit according to other embodiments of the present disclosure.

[0028] Figure 4 This is a schematic diagram of the structure of an arbitration circuit for a BMS according to some embodiments of the present disclosure.

[0029] Figure 5 This is a schematic flowchart illustrating an arbitration method for a BMS according to some embodiments of the present disclosure.

[0030] It should be understood that the same or similar reference numerals indicate the same or similar components. Detailed Implementation

[0031] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless specifically stated otherwise, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values ​​set forth in these embodiments should be interpreted as exemplary only and not as limiting.

[0032] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "containing" mean that the element preceding the word encompasses the element listed after the word, and do not exclude the possibility of encompassing other elements as well. Terms such as "above" and "below" are used only to indicate relative positional relationships, and these relative positional relationships may also change accordingly when the absolute position of the described object changes.

[0033] In this disclosure, when a specific component is described as being located between a first component and a second component, an intermediary component may or may not be present between the specific component and the first or second component. When a specific component is described as connecting to other components, the specific component may be directly connected to the other components without having an intermediary component, or it may not be directly connected to the other components but may have an intermediary component.

[0034] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0035] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0036] Figure 1 This is a schematic diagram of the structure of an arbitration circuit for a BMS according to some embodiments of the present disclosure.

[0037] like Figure 1 As shown, the arbitration circuit 10 for the BMS includes multiple input interfaces 11 and a priority encoding circuit 12.

[0038] Multiple input interfaces 11 are configured to receive multiple wake-up signals. These wake-up signals may originate from, for example, six wake-up sources: wake-up source 1, wake-up source 2, wake-up source 3, wake-up source 4, wake-up source 5, and wake-up source 6. In some embodiments, the wake-up signals corresponding to wake-up sources 1, 2, 3, 4, 5, and 6 are, in order, BPS (Battery Pack Pressure Sensor) thermal runaway wake-up, KL15 wake-up, CSC (Cell Sensor Controller) wake-up, A+ wake-up, CAN (Controller Area Network) network wake-up, and RTC (Real-Time Clock) timing wake-up, with the priority of the wake-up signals corresponding to wake-up sources 1-6 decreasing sequentially.

[0039] Priority encoding circuit 12 is connected to multiple input interfaces 11. Priority encoding circuit 12 includes a first output pin O1 and a second output pin O2. The first output pin O1 is configured to connect to the enable pin EN of the power management chip 21 in the BMU (Battery Management Unit, also known as the main control board) of the BMS. The second output pin O2 is configured to connect to the MCU 22 in the BMU, for example, to the GPIO (General Purpose Input / Output) of the MCU 22.

[0040] Priority encoding circuit 12 is configured to perform operations 1 and 2 in response to the presence of a valid wake-up signal among multiple wake-up signals. For example, a wake-up signal entering priority encoding circuit 12 is a valid wake-up signal when it is low, and not a valid wake-up signal when it is high. It is understood that priority encoding circuit 12 can perform operations 1 and 2 as long as at least one wake-up signal is a valid wake-up signal.

[0041] Operation 1: Output an enable signal through the first output pin O1 to the enable pin EN of the power management chip 21 so that the power management chip 21 supplies power to the BMU.

[0042] In some embodiments, the power management chip 21 is an SBC (System Basic Chip).

[0043] In some embodiments, the power management chip 21 has four outputs, where S5V is a constant power output (e.g., 5V / 10 mA) used to power one or more of the RTC, BPS, priority encoding circuit 12, and Schmitt triggers mentioned later; the other three (UC, CO, TR) are non-constant power outputs, which are turned off in low-power mode. When the enable pin EN of the power management chip 21 receives an enable signal, the power management chip 21 can power the BMU through the non-constant power outputs.

[0044] As an example, the power consumption of the Schmitt trigger and priority encoder 121 is extremely low, for example, about tens of uA.

[0045] Operation 2: Output the code corresponding to the highest priority valid wake-up signal among multiple wake-up signals to MCU 22 through the second output pin O2.

[0046] In some embodiments, the second output pin O2 includes multiple output pins, such as three output pins A0, A1, and A2. In some embodiments, the code corresponding to the highest priority valid wake-up signal is a binary code, such as a 3-bit binary code. For example, the code corresponding to BPS thermal runaway wake-up is 111, the code corresponding to KL15 wake-up is 110, the code corresponding to CSC wake-up is 101, the code corresponding to A+ wake-up is 100, the code corresponding to CAN network wake-up is 011, and the code corresponding to RTC timed wake-up is 010.

[0047] In the above embodiment, the arbitration circuit 10 enables the power management chip 21 to supply power to the BMU when a valid wake-up signal is present, and outputs the code corresponding to the highest priority valid wake-up signal among multiple wake-up signals to the MCU 22 in the BMU. After the BMU is powered on, the MCU 22 performs power-on initialization. By directly reading the code corresponding to the highest priority valid wake-up signal, it can immediately know which wake-up source woke up the BMS. Then, the MCU 22 can control the BMS to quickly enter the corresponding working mode, such as fault handling, charging, network communication, etc. In this way, the priority arbitration of the wake-up signal does not depend on software, has a high response speed (e.g., nanosecond level), can ensure the immediate response of high-priority wake-ups, and has high reliability, thereby improving the reliability of battery management. In addition, due to the fast response speed, the power consumption of the MCU 22 from wake-up to controlling the BMS to enter the corresponding working mode can also be reduced.

[0048] In some embodiments, the working mode corresponding to wake-up source 1 is the exception handling mode, the working mode corresponding to wake-up source 2 is the driving mode, the working mode corresponding to wake-up source 3 is the exception handling mode, the working mode corresponding to wake-up source 4 is the charging mode, the working mode corresponding to wake-up source 5 is the communication mode (i.e., performing operations according to the instructions of the vehicle controller), and the working mode corresponding to wake-up source 6 is the periodic exception detection mode.

[0049] MCU 22 can determine whether the task executed after wake-up is completed and whether a valid power-down command has been received. If so, it will re-enter low-power mode (also known as sleep mode), that is, power management chip 21 will no longer supply power to BMU.

[0050] The inventors also noted that in some cases, there may be a "false wake-up" phenomenon, that is, due to the interference of the wake-up signal, the arbitration result of whether the wake-up signal is a valid wake-up signal is incorrect, which in turn leads to the BMS being woken up incorrectly when it should not be woken up.

[0051] In view of the above, the present disclosure also proposes the following solutions.

[0052] Figure 2 This is a schematic diagram of the structure of an arbitration circuit for a BMS according to other embodiments of the present disclosure.

[0053] In some embodiments, the arbitration circuit 10 may further include a signal processing circuit 13. The signal processing circuit 13 includes one or more signal processing sub-circuits 131, each signal processing sub-circuit 131 being connected between a corresponding input interface 11 and the priority encoding circuit 12. Here, each signal processing sub-circuit 131 is connected between a corresponding input interface 11 and an input pin (e.g., one of input pins I2-I7) of the priority encoding circuit 12.

[0054] Next, combine Figure 3A and Figure 3B This section introduces different implementations of the signal processing sub-circuit 131.

[0055] Figure 3A This is a schematic diagram of the structure of a signal processing sub-circuit according to some embodiments of the present disclosure.

[0056] In some implementations, such as Figure 3A As shown, the signal processing sub-circuit 131 includes a first resistor R1 and a first capacitor C1. For example, each signal processing sub-circuit 131 includes a first resistor R1 and a first capacitor C1. The resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 in different signal processing sub-circuits 131 may be the same or different.

[0057] The first end of the first resistor R1 is connected to the corresponding input interface 11, and the second end of the first resistor R1 is connected to the priority encoding circuit 12. The resistance value of the first resistor R1 is, for example, 10kΩ.

[0058] The first capacitor C1 is connected between the second terminal of the first resistor R1 and the ground terminal G. For example, the first terminal of the first capacitor C1 is connected to the second terminal of the first resistor R1, and the second terminal of the first capacitor C1 is connected to the ground terminal G. The capacitance value of the first capacitor C1 is, for example, 100nF.

[0059] For example, the time constant of the filter circuit composed of the first resistor R1 and the first capacitor C1 is about 1ms.

[0060] In the above implementation, the signal processing sub-circuit 131 includes a first resistor R1 and a first capacitor C1. Thus, the filter circuit composed of the first resistor R1 and the first capacitor C1 can reduce glitches in the wake-up signal, providing anti-interference capability for the wake-up signal, thereby improving the accuracy of determining whether the arbitration wake-up signal is a valid wake-up signal, and thus improving the reliability of the wake-up BMS.

[0061] In other implementations, such as Figure 3A As shown, the signal processing sub-circuit 131 further includes a first Schmitt trigger U1. For example, each signal processing sub-circuit 131a includes a first Schmitt trigger U1.

[0062] The first Schmitt trigger U1 is connected between the second terminal of the first resistor R1 and the priority encoding circuit 12. It should be understood that the input terminal of the first Schmitt trigger U1 is connected to the second terminal of the first resistor R1, and the output terminal of the first Schmitt trigger U1 is connected to one input pin of the priority encoding circuit 12.

[0063] In the above implementation, the signal processing sub-circuit 131 further includes a first Schmitt trigger U1. Thus, the wake-up signal can be shaped and noise filtered out by the first Schmitt trigger U1, ensuring that the level entering the priority encoding circuit 12 is a defined digital level. This effectively avoids the arbitration circuit from generating erroneous arbitration outputs near the critical voltage due to signal jitter, thereby further improving the accuracy of determining whether the arbitration wake-up signal is a valid wake-up signal and further enhancing the reliability of waking up the BMS.

[0064] In some other implementations, such as Figure 3A As shown, the signal processing sub-circuit also includes a second resistor R2. For example, each signal processing sub-circuit includes a second resistor R2. The resistance value of the second resistor R2 in different signal processing sub-circuits can be the same or different.

[0065] The second resistor R2 is connected between the input terminal of the first Schmitt trigger U1 and the ground terminal G. For example, the first terminal of the second resistor R2 is connected to the input terminal of the first Schmitt trigger U1 and the second terminal of the first resistor R1, and the second terminal of the second resistor R2 is connected to the ground terminal G. For example, the KL15 wake-up source is a 12V input, the high-level input range of the first Schmitt trigger U1 is 1.55~3.13V, the resistance of the first resistor R1 and the second resistor R2 is 3.3kΩ, and the voltage at the input terminal of the first Schmitt trigger U1 is 2.97V.

[0066] In the above implementation, considering that the voltage of the wake-up signal may be large, the second resistor R2 is used as a voltage divider resistor to divide the voltage, so that the voltage at the input terminal of the first Schmitt trigger U1 is within the high level range of the first Schmitt trigger U1, thus ensuring that the first Schmitt trigger U1 works normally.

[0067] Figure 3B This is a schematic diagram of the structure of a signal processing sub-circuit according to other embodiments of the present disclosure.

[0068] In some implementations, one or more signal processing sub-circuits 131 include, for example: Figure 3B The first signal processing sub-circuit 131a is shown. In addition to a first resistor R1 and a first capacitor C1, the first signal processing sub-circuit 131a also includes a second capacitor C2. The second capacitor C2 is connected between the first terminal of the first resistor R1 and the ground terminal G. For example, the first terminal of the second capacitor C2 is connected to the first terminal of the first resistor R1 and the corresponding input interface 11 of the first signal processing sub-circuit 131a, and the second terminal of the second capacitor C2 is connected to the ground terminal G.

[0069] In the above implementation, the second capacitor C2 can play an ESD (electrostatic discharge) protection role. That is, as an ESD capacitor, it can reduce the interference caused by static electricity to the wake-up signal, which can further improve the accuracy of arbitrating whether the wake-up signal is a valid wake-up signal, thereby further improving the reliability of waking up the BMS.

[0070] In some implementations, such as Figure 3B As shown, the first signal processing sub-circuit 131a includes a first resistor R1 and a first capacitor C1, as well as a first Schmitt trigger U1. In some other implementations, such as... Figure 3B As shown, the first signal processing sub-circuit 131a also includes a second resistor R2.

[0071] In some embodiments, the wake-up signal received by the corresponding input interface 11 connected to the first signal processing sub-circuit 131a originates from outside the BMU where the arbitration circuit 12 is located. For example, the type of wake-up signal from outside the BMU where the arbitration circuit 12 is located is KL15 wake-up or CSC reverse wake-up. Thus, considering that the wake-up signal outside the BMU is more susceptible to electrostatic interference, the second capacitor C2 can more effectively reduce the interference caused by electrostatic discharge to the wake-up signal outside the BMU, thereby improving the reliability of the arbitration circuit 10.

[0072] In other implementations, one or more signal processing sub-circuits 131 include a second signal processing sub-circuit 131b. For example... Figure 3A As shown, the second signal processing sub-circuit 131b does not include Figure 3B The second capacitor C2 is shown, and the wake-up signal received by the corresponding input interface 11 connected to the second signal processing sub-circuit 131b comes from the BMU where the arbitration circuit 12 is located. For example, the type of wake-up signal from the BMU where the arbitration circuit 12 is located is BPS thermal runaway wake-up, A+ wake-up, CAN network wake-up, or RTC timed wake-up.

[0073] Thus, considering that the wake-up signal inside the BMU is less susceptible to electrostatic interference, the second signal processing sub-circuit 131b does not need to be additionally equipped with a second capacitor C2, reducing the structural complexity of the arbitration circuit 12, thereby improving the reliability of waking up the BMS with a simple circuit structure.

[0074] In some embodiments, the signal processing circuit 13 includes multiple Figure 3B The first signal processing sub-circuit 131a is shown. In some embodiments, the signal processing circuit 13 includes multiple... Figure 3A The second signal processing sub-circuit 131b is shown.

[0075] In some embodiments, such as Figure 2 As shown, the priority encoding circuit 12 includes a priority encoder 121 and a second Schmitt trigger U2. The priority encoder 121 includes multiple input pins I2-I7 connected to multiple input interfaces 11. The second Schmitt trigger U2 is connected between the first output pin O1 and the enable pin EN of the power management chip 21. The second Schmitt trigger U2 is configured to receive an initial enable signal output from the first output pin O1 and output an enable signal to the enable pin EN of the power management chip 21. For example, the received initial enable signal is a low-level signal, and the output enable signal is a high-level signal.

[0076] For example, priority encoding circuit 12 is a low-level active encoder. According to the truth table, when at least one wake-up source is high, after being inverted by signal processing circuit 13 (e.g., by the first Schmitt trigger U1), at least one wake-up signal is a low-level signal. The first output pin O1 outputs a low-level initial enable signal, which is then inverted by the second Schmitt trigger U2 and outputs a high-level enable signal to the enable pin EN of power management chip 121, thereby enabling power management chip 121 to supply power to BMU.

[0077] In the above embodiments, priority encoding is implemented using priority encoder 121, which is low-cost. Furthermore, by embedding the priority of the wake-up signal internally in the hardware, the determinism and reliability of the arbitration circuit are ensured.

[0078] In some embodiments, a CPLD (Complex Programmable Logic Device) can be used instead of the priority encoder 121 (e.g., a 74-series gate circuit, such as the 74HC148). In this case, the priority of the wake-up signal can be flexibly configured.

[0079] Figure 4 This is a schematic diagram of the structure of an arbitration circuit for a BMS according to some embodiments of the present disclosure.

[0080] In some embodiments, such as Figure 4 As shown, in the signal processing circuit 13, part of the signal processing sub-circuit is the first signal processing sub-circuit 131a, and part of the signal processing sub-circuit is the second signal processing sub-circuit 131b.

[0081] In some embodiments, such as Figure 4 As shown, in the priority encoder 121, the idle input pins I1-I0 can be pulled up to the voltage terminal (e.g., the 5V voltage terminal) through the third resistor R3 to avoid floating interference.

[0082] In some embodiments, such as Figure 4 As shown, the enable input pin EI of the priority encoder 121 is connected to the ground terminal G, so that the output pin can always be active.

[0083] Figure 4 The group selection output pin GS shown can be used as the first output pin O1. Figure 4 The EO output pin and the corresponding GPIO pin numbers 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 13 are also shown.

[0084] This disclosure also provides a BMU, including: an arbitration circuit, a power management chip 21, and an MCU 22, as described in any of the above embodiments. The power management chip 21 is configured to supply power to the BMU in response to an enable signal from the arbitration circuit. The MCU 22 is configured to read the code after the BMU is powered on and control the BMU to enter an operating mode corresponding to the read code.

[0085] This disclosure also provides a BMS, including: the BMU of any of the above embodiments. The BMS can be used in electric vehicles, electric construction machinery, or energy storage systems.

[0086] This disclosure also provides an arbitration method for a BMS based on the arbitration circuit of any of the above embodiments.

[0087] Figure 5 This is a schematic flowchart illustrating an arbitration method for a BMS according to some embodiments of the present disclosure.

[0088] In step 502, multiple wake-up signals are received.

[0089] It should be understood that the BMS maintains a low-power mode in the absence of a wake-up signal.

[0090] If a valid wake-up signal is found among the multiple wake-up signals, steps 504 and 506 are executed. If no valid wake-up signal is found among the multiple wake-up signals, the BMS maintains low-power mode.

[0091] In step 504, an enable signal is output to the enable pin of the power management chip through the first output pin, so that the power management chip supplies power to the BMU.

[0092] In step 506, the code corresponding to the highest priority valid wake-up signal among multiple wake-up signals is output to the MCU through the second output pin.

[0093] After the power management chip supplies power to the BMU, the MCU powers on and initializes, then reads the code output by the arbitration circuit to identify the wake-up source corresponding to the wake-up signal. Afterward, it controls the BMS to enter the operating mode corresponding to the code. Once the task is completed in the corresponding operating mode, the MCU checks for a sleep request. If a sleep request is received, the MCU sends a sleep command to the power management chip, which then stops supplying power to the BMU. Otherwise, the BMS continues to operate in the corresponding mode.

[0094] In the above embodiments, when a valid wake-up signal is present, the power management chip is enabled to supply power to the BMU, and the code corresponding to the highest-priority valid wake-up signal among multiple wake-up signals is output to the MCU in the BMU. After the BMU is powered on, the MCU performs power-on initialization. By directly reading the code corresponding to the highest-priority valid wake-up signal, it can immediately determine which wake-up source has activated the BMU, and thus the MCU can control the BMS to quickly enter the corresponding operating mode. In this way, the priority arbitration of the wake-up signal does not rely on software, has a high response speed, ensures immediate response to high-priority wake-ups, and has high reliability, thereby improving the reliability of battery management.

[0095] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0096] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. An arbitration circuit for a battery management system, comprising: a plurality of input interfaces configured to receive a plurality of wake-up signals; and a priority encoding circuit connected with the plurality of input interfaces, comprising: a first output pin configured to be connected with an enable pin of a power management chip in a battery management unit of the battery management system, and a second output pin configured to be connected with a micro control unit in the battery management unit, the priority encoding circuit is configured to, in response to there being a valid wake-up signal in the plurality of wake-up signals: output an enable signal to the enable pin of the power management chip through the first output pin, so that the power management chip powers the battery management unit, and output an encoding corresponding to the valid wake-up signal with the highest priority in the plurality of wake-up signals to the micro control unit through the second output pin. The second output pin comprises a plurality of output pins, and the encoding is a binary encoding.

2. The arbitration circuit of claim 1, wherein, 3. The arbitration circuit of claim 1, further comprising a signal processing circuit, the signal processing circuit comprising one or more signal processing sub-circuits, each signal processing sub-circuit being connected between a corresponding input interface and the priority encoding circuit, each signal processing sub-circuit comprising: a first resistor, a first end of the first resistor being connected with the corresponding input interface, and a second end of the first resistor being connected with the priority encoding circuit; and a first capacitor connected between the second end of the first resistor and a ground terminal. The one or more signal processing sub-circuits comprise a first signal processing sub-circuit, the first signal processing sub-circuit further comprising, in addition to the first resistor and the first capacitor: a second capacitor connected between the first end of the first resistor and the ground terminal.

4. The arbitration circuit of claim 3, wherein, The wake-up signal received by the corresponding input interface connected with the first signal processing sub-circuit is from outside a battery management unit (BMU) in which the arbitration circuit is located. The one or more signal processing sub-circuits comprise a second signal processing sub-circuit, the second signal processing sub-circuit not comprising the second capacitor, and the wake-up signal received by the corresponding input interface connected with the second signal processing sub-circuit is from the BMU in which the arbitration circuit is located.

5. The arbitration circuit of claim 4, wherein, Each signal processing sub-circuit further comprises:

6. The arbitration circuit of claim 4, wherein, a first Schmitt trigger, an input terminal of the first Schmitt trigger being connected with the second end of the first resistor, and an output terminal of the first Schmitt trigger being connected with the priority encoding circuit.

7. The arbitration circuit of claim 3, wherein, At least one signal processing sub-circuit further comprises: a second resistor connected between the input terminal of the first Schmitt trigger and a ground terminal.

8. The arbitration circuit of claim 7, wherein, The priority encoding circuit comprises: a priority encoder comprising a plurality of input pins connected with the plurality of input interfaces; and 9. The arbitration circuit of any of claims 1-8, wherein, a second Schmitt trigger connected between the first output pin and the enable pin of the power management chip, configured to receive an initial enable signal output by the first output pin and output the enable signal to the enable pin of the power management chip.

10. A battery management unit, comprising: the arbitration circuit of any one of claims 1-9. ​ ​ the power management chip is configured to supply power to the battery management unit in response to the enable signal; and the micro control unit is configured to read the code after the battery management unit is powered and control the power management system to enter a working mode corresponding to the code.

11. A battery management system comprising: The battery management unit of claim 10.

12. An arbitration method for a battery management system, based on the arbitration circuit of any one of claims 1-9, the method comprising: receiving a plurality of wake-up signals; and in response to there being a valid wake-up signal in the plurality of wake-up signals: outputting an enable signal through the first output pin to an enable pin of the power management chip, so that the power management chip supplies power to the battery management unit, and outputting a code corresponding to the highest-priority valid wake-up signal in the plurality of wake-up signals through the second output pin to the micro control unit.

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