An intelligent storage system with edge computing and intrinsic security mechanisms

Abstract

This invention relates to the field of information technology, specifically to an intelligent storage system with edge computing and intrinsic security mechanisms. It addresses the problems of delayed security action, high response latency, and static resource occupancy in existing secure storage technologies under edge computing scenarios. The system includes an edge secure computing module, an authentication state machine, a hard-wired instruction filtering unit, and a controlled instruction execution path. Through a hardware-level authentication mechanism initialized upon power-on, physical connection-gated instruction execution clocks, and dynamic reuse of secure computing buffers and I / O memory, it achieves "default rejection" intrinsic security protection within microsecond-level latency. This application effectively eliminates security vacuum periods, balancing high security, low latency, and efficient resource utilization.

Description

Technical Field

[0001] This invention relates to the fields of solid-state storage control and information security technology, and in particular to an intelligent storage system with edge computing and intrinsic security mechanisms. Background Technology

[0002] With the widespread adoption of 5G mobile communication and the large-scale deployment of industrial IoT and edge AI architectures, the global data production center is undergoing a profound shift. Massive amounts of heterogeneous data no longer rely solely on expensive bandwidth backhauls to the central cloud for processing; instead, they tend to undergo initial cleaning, aggregation, and inference at edge nodes closer to the source. Under this major technological evolution, the role of intelligent storage devices has fundamentally transformed: they are no longer passive "data containers" simply executing block read / write instructions, but are gradually evolving into edge computing microkernels with autonomous computing capabilities and security protection attributes. Especially in scenarios with stringent requirements for instruction response clock levels and physical security, such as industrial control real-time buses, autonomous driving visual perception, and remote precision medicine, storage systems must, while handling high-bandwidth linear throughput, complete sub-millisecond-level legitimacy penetration tests on the instruction stream within a limited controller power consumption budget (TDP).

[0003] This demand for "computing off-grid" storage directly drove the explosion of compute-centric storage technology. Its underlying logic lies in attempting to reduce unnecessary PCIe bus usage caused by data shuttling between host DRAM and storage media by integrating processing units within the storage controller, and to alleviate I / O latency jitter in compute-storage separation architectures. However, while pursuing high-performance computing offloading, the physical security threats faced in edge scenarios have shifted from traditional logical attacks to more complex underlying physical attacks.

[0004] In the current technological ecosystem, the Opal specification, developed by the Encrypting Hard Drive and Trusted Computing Organization, constitutes the mainstream secure storage defense. This architecture achieves static full-disk encryption protection for storage media by integrating a hardware encryption / decryption engine into the controller ASIC. From an early engineering applicability perspective, this solution performs well in controlled environments such as data centers because it links the lifecycle of the decryption key to the operating system's boot process through driver-device interaction. However, a deeper analysis of its underlying implementation logic reveals that this "hardware-software co-operation" design pattern exposes three levels of structural contradictions in the open and highly uncertain edge computing environment:

[0005] First, there is the issue of the "vacuum period" in security defense boundaries. Existing Opal-based defense systems rely heavily on the operating system's kernel loading and the initialization of corresponding drivers for root trust activation. From hardware power-on to firmware loading, and then to the OS driver initiating authentication requests, there exists a security blind spot lasting several seconds or even minutes. Within this window, the storage device is "logically exposed," allowing attackers to bypass the not-yet-effective logical authentication layer and directly tamper with controller registers using physical probe injection, differential power analysis, or direct memory access (DMA) attacks. This "post-authentication" prevents the storage system from establishing a pre-existing physical-level intrinsic security barrier during the device enumeration phase.

[0006] Secondly, there is the issue of the "non-endogenous" nature of the secure execution environment. Existing security decisions are often highly coupled with the scheduling logic of the host CPU. Once the host OS is compromised or the host firmware is tampered with due to a poor edge node environment, the storage device will completely lose its autonomous defense capabilities. The static key mechanism or simple challenge-response protocol it employs is extremely vulnerable to man-in-the-middle interception and replay attacks. The root cause is that existing solutions treat "security" as a logical plug-in superimposed on storage functionality, rather than a physical attribute embedded in the hardware timing path. Even if some solutions attempt to introduce on-chip hardware hash modules, the instruction stream still needs to enter the storage protocol stack for software parsing before being intercepted based on the software's judgment. This passive "receive first, filter later" mode means that malicious instructions have already entered the controller's processing pipeline before being filtered, posing a potential risk of malicious triggering.

[0007] Finally, there is the "technical triangle" between real-time response and resource utilization. In edge computing scenarios, host-side NVMe drivers typically set extremely stringent command timeout thresholds, usually at the microsecond level. If the storage device relies on a general-purpose embedded CPU to execute complex cryptographic algorithms through firmware during the authentication process, the high computational latency not only fails to meet the real-time IOPS requirements but also leads to frequent PCIe bus resets and link instability due to frequent command timeouts. Even more problematic is that the additional memory buffers allocated to support secure computing often use static allocation in current technologies. In resource-constrained and silicon area-cost-sensitive edge controllers, this "zombie memory" cannot be reused by high-speed I / O queues outside of authentication cycles, directly limiting the device's queue depth and burst throughput performance.

[0008] In summary, the shortcomings of the existing solutions are not simply due to weak algorithms, but rather stem from a systemic disconnect in the underlying architecture: in terms of time, they lack the instantaneous response capability of "protection upon power-on," resulting in a serious security vacuum period.

[0009] In terms of spatial dimension, the security action point is located at the software level, and it is impossible to achieve "default denial" hardware cutoff on the physical execution path; in terms of resource dimension, the cost of computation offloading is static memory consumption and insurmountable millisecond-level computation latency.

[0010] Therefore, how to build an intelligent controller architecture that deeply integrates edge offloading computing power and physical-level intrinsic security mechanisms while maintaining the high-performance read / write characteristics of the storage system, enabling it to achieve microsecond-level dynamic identity verification through dedicated hardware cores, and ensuring that unauthorized instructions are physically blocked at the underlying clock level through hard-wired logic, and on this basis, achieve dynamic reclamation and symbiosis of secure computing resources and I / O service memory, has become a key technical challenge restricting the evolution of edge intelligent computing towards a highly reliable, zero-trust architecture. This field urgently needs a new architectural paradigm to completely break the deadlock between security, real-time performance, and resource efficiency. Summary of the Invention

[0011] To achieve the above-mentioned objectives, this invention proposes an intelligent storage system with edge computing and intrinsic security mechanisms, comprising:

[0012] An edge security computing module, integrated within the storage controller, is used to perform identity verification during the power-on initialization phase. The edge security computing module includes a true random number generator and a hardware hash engine. The true random number generator is built based on a dedicated on-chip physical entropy source integrated within the storage controller and is connected to the on-chip physical entropy source to generate dynamic challenge values. The input interface of the hardware hash engine is connected to the registers of the non-volatile key storage area through a dedicated data path.

[0013] The authentication state machine is implemented using synchronous sequential logic circuits. Its reset terminal is connected to the system reset signal so that it is set to the "unauthorized" state by default when powered on. The authentication state machine receives the authorization signal from the edge security computing module to trigger a state transition to the "authorized" state. After the authentication state machine is reset, it locks the system in the "unauthorized" state. In conjunction with the hard-wired instruction filtering unit to physically block I / O operations, an intrinsic security defense mechanism of "default denial" is built at the hardware level.

[0014] The hard-wired command filtering unit is composed of pure combinational logic circuits. Its state input terminal is directly coupled to the output terminal of the authentication state machine through a physical path of hard-wired metal layer, ensuring that there is no software or firmware intervention delay in signal transmission. It is used to decode NVMe commands in real time and output a prohibition signal according to the level signal of the authentication state machine.

[0015] The instruction execution path has its clock enable pin connected to the output of the hardwired instruction filtering unit; when the disable signal is received, the operating clock of the instruction execution path is physically cut off to block I / O operations targeting the user data namespace.

[0016] Preferably, the non-volatile key storage area adopts an antifuse or fuse physical structure, which is electrically isolated from the external bus, debug interface and JTAG port in physical layout, and only supports read-only access at the circuit level.

[0017] Preferably, the hardware hash engine is a four-stage pipeline structure, with each stage configured to process 16 bytes of data; a dedicated private bus with a width of 256 bits is provided between the hardware hash engine and the non-volatile key storage area, which is independent of the general-purpose AXI bus matrix of the storage controller.

[0018] Preferably, the hard-wired instruction filtering unit includes:

[0019] An opcode decoder is used to identify read, write, compare, and refresh opcodes in the NVMe protocol in parallel.

[0020] The namespace ID comparator is used to check whether the NSID field in a command message is non-zero;

[0021] The state gating selector has its inputs connected to the opcode decoder, the namespace ID comparator, and the authentication state machine, respectively, and its output is connected to the clock enable terminal of the instruction execution path. The propagation delay of the entire combinational logic path does not exceed 2 nanoseconds.

[0022] Preferably, the dynamically reused memory unit includes an on-chip SRAM buffer with a 4KB buffer; during the authentication phase, this buffer is exclusively allocated to the edge security computing module by the hardware arbitrator for temporarily storing dynamic challenge values ​​and intermediate states of hash operations.

[0023] Preferably, the system further includes a dedicated zeroing controller; after the authentication state machine jumps to the "authorized" state, the dedicated zeroing controller is triggered to initiate a DMA all-zero write request with a burst length of 64 ticks to the 4KB buffer, and releases the buffer to the NVMe protocol stack's commit queue memory pool after the write is completed.

[0024] Preferably, the 4KB buffer is located in a volatile storage area and is configured to automatically disappear its contents when the system power is interrupted, so as to achieve self-aware protection against physical removal or power outage attacks.

[0025] Preferably, the logic for the edge security computing module to perform identity verification includes: sending a dynamic challenge value generated by the true random number generator to the host via a vendor-defined management command; receiving a first hash result returned by the host; calculating a second hash result by a hardware hash engine; and outputting the authorization signal when the first and second hash results are matched byte by byte.

[0026] Preferably, the processing logic of the vendor-defined management commands is hard-coded in the NVMe command parser, and its execution path is physically independent of the regular I / O command queue.

[0027] Preferably, the 4KB buffer is located in a volatile SRAM buffer, and its contents are naturally lost when the device experiences an abnormal power outage or power interruption, without the need to execute additional erase instructions.

[0028] The beneficial effects of this invention are as follows: The intelligent storage system proposed in this invention achieves decoupling and collaborative control of computation offloading, physical gating and dynamic resource reuse at the architecture level, which solves the irreconcilable triangular contradiction between security, real-time performance and resource efficiency in existing technologies, and provides an engineering-ready technical solution for high-security, low-latency edge application scenarios such as industrial control, intelligent transportation and telemedicine. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only for this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the overall structure of an intelligent storage system with edge computing and intrinsic security mechanisms according to the present invention.

[0031] Figure 2 This is a schematic diagram illustrating the connection relationship and working principle of the authentication state machine and the hard-wired instruction filtering unit in this invention;

[0032] Figure 3 This is a schematic diagram illustrating the method steps of the edge security computing module of the present invention to perform the identity verification process;

[0033] Figure 4 This is a schematic diagram illustrating the timing of the dynamic memory reuse mechanism in this invention as it switches between secure computing and I / O queues. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0035] This invention provides an intelligent storage system with edge computing and intrinsic security mechanisms. Its core lies in building a secure execution environment within the storage controller through a hardware-level integrated architecture. This environment is power-on, unbypassable, and has microsecond-level response capabilities. At the physical level, the system deeply couples identity verification, command filtering, and resource management, ensuring that even in extreme scenarios where the host operating system or firmware is completely compromised, the user data namespace remains physically isolated, thus achieving true intrinsic security.

[0036] The intelligent storage system uses the NVMe protocol as its basic communication framework, and its physical carrier is a solid-state storage device based on a PCIe interface. The internal main control chip adopts a multi-core heterogeneous architecture, including a general-purpose RISC-V processor core, a dedicated DMA engine, an NVMe protocol processing unit, and the edge secure computing module defined in this invention. This edge secure computing module is not a software-configurable coprocessor, but is directly embedded in the front-end logic of the storage controller in the form of hard-wired logic. Its functional boundaries and execution paths are fixed during the chip manufacturing stage, and it is not subject to any firmware or operating system intervention during operation.

[0037] The core components of the edge security computing module include a true random number generator, a hardware hash engine, a 4KB buffer, and a key register set. The true random number generator is built on an on-chip physical entropy source. Specifically, it utilizes the nondeterministic characteristics of cross-clock domain sampling, combined with the physical thermal noise of a subthreshold inverter chain, to perform multi-source entropy fusion. This suppresses the deterministic drift of a single entropy source under specific voltage fluctuations. After sampling by a ring oscillator, the data is fed into a corrector to eliminate bias, ultimately outputting a true random bitstream conforming to the NIST SP 800-90B standard. This generator is automatically activated each time the system powers on and resets or receives an external re-authentication trigger signal. It outputs a 32-byte dynamic challenge value at a time. This value is only valid within the current authentication cycle and is not transmitted externally through any bus; it is used only internally within the module for subsequent hash operations.

[0038] The hardware hash engine is a dedicated SHA-256 algorithm logic unit, employing a four-stage pipeline design, processing 16 bytes of input data per stage and supporting single-cycle throughput. Its internal constant table is implemented via hard-wired logic instead of a lookup table, reducing on-chip SRAM usage and improving electromagnetic interference immunity, message scheduling logic, compression functions, and intermediate state register sets. The engine's input interface is directly connected to the security key register in the non-volatile key storage area, linked by a dedicated 256-bit data path independent of the controller's internal general-purpose AXI bus matrix. This ensures that key data does not pass through any shared cache, DMA channel, or CPU-visible address space during read operations. The completion time for a single complete SHA-256 operation (including 512-bit message block processing) is measured to be no more than 10 microseconds, meeting the stringent command timeout threshold requirements of the NVMe protocol stack.

[0039] The non-volatile key storage area is located within the physically secure area of ​​the storage controller chip and is implemented using antifuse technology. It can only be written to once via laser programming during wafer fabrication and supports read-only access during runtime. This area is physically completely encased in a metal shielding layer and is electrically isolated from the debug interface, JTAG port, and all external pins to prevent key information extraction via side channels or physical probes. The key content is a 256-bit symmetric key, pre-shared with the host for generating and verifying challenge-response pairs.

[0040] The authentication state machine is a synchronous sequential logic circuit implemented based on a finite state automaton model, containing two stable states: "Unauthorized" and "Authorized". The reset signal for this state machine comes directly from the POR (Power-On Reset) signal of the power management unit, ensuring that its initial state is forcibly locked to "Unauthorized" under any power-on scenario, and this state cannot be modified by software register writes or firmware instructions. The sole trigger condition for state transition is a valid authorization signal output by the edge security computing module after completing the full identity verification process. This signal is a single-cycle pulse, transmitted across the clock domain via a synchronizer to the state machine's control logic, driving its state transition. Once in the "Authorized" state, the state remains unchanged unless the system is powered on again or receives an explicit security reset instruction.

[0041] The hardwired instruction filtering unit is composed of pure combinational logic circuits. Its inputs receive the raw command header parsed by the NVMe protocol processing unit, including the Opcode field and the NSID field (namespace ID). This unit contains three parallel sub-modules: an opcode decoder, a namespace ID comparator, and a state gating selector. The opcode decoder employs a wide decoding structure, performing fully parallel decoding on the 8-bit value of the opcode to identify four sensitive operation types: 0x02 (read), 0x01 (write), 0x05 (compare), and 0x00 (refresh). The namespace ID comparator checks if the NSID is equal to zero; if it is, it's determined to be a management command (such as Identify, Get Features, Set Features, etc.), allowing unconditional access. The state gating selector receives the current state signal from the authentication state machine. If the state is "unauthorized" and the current command simultaneously satisfies both conditions (NSID ≠ 0 and Opcode ∈ {0x00, 0x01, 0x02, 0x05}), it immediately outputs a high-level inhibit signal. The state gating selector also integrates an anti-glitch synchronization circuit to ensure that during the transient transition of the authentication state, the inhibit signal will not cause unexpected opening of the instruction path due to combinational logic contention.

[0042] This disable signal is physically connected directly to the clock enable pin of the core execution engine in the instruction execution path. In modern digital circuit design, the clock enable pin controls whether the flip-flops sample data on the rising edge of the clock. When the disable signal is active, the clock enable is pulled low, causing the entire instruction execution engine to freeze in the subsequent clock cycles, unable to parse or execute any commands. This mechanism achieves physical blocking of illegal I / O operations from the circuit level, with a response delay that is only the combinational logic propagation delay, confirmed by static timing analysis to be no more than 2 nanoseconds, far below the minimum time granularity of NVMe command processing.

[0043] The instruction execution path is the core logic path within the storage controller responsible for translating NVMe commands into flash physical addresses, scheduling ECC checks, managing wear leveling, and executing actual read / write operations. Its front end receives the command stream filtered by the hard-wired instruction filtering unit, and its back end connects to the flash channel controller. In the "unauthorized" state, all operations involving the user data namespace, except for management commands with NSID=0, are physically blocked. Even if the host maliciously injects forged commands or the firmware is implanted with a backdoor, this hardware gating mechanism cannot be bypassed.

[0044] Furthermore, to optimize resource utilization efficiency, this invention introduces a dynamic memory reuse mechanism. When performing identity verification tasks, the edge security computing module needs to temporarily store the dynamic challenge value, the first hash result returned by the host, and the intermediate calculation state of the hash engine. To this end, the system reserves a physically contiguous 4KB memory page frame in the controller's on-chip SRAM. The address range is fixed and the memory management unit marks it as "security-dedicated" during the initialization phase. This buffer is allocated exclusively to the edge security computing module when the authentication process begins, and its access permissions are forcibly isolated by a hardware arbitrator. During this period, the general-purpose processor core and DMA engine cannot access this area.

[0045] After the authentication state machine successfully transitions to the "authorized" state, the system immediately triggers an overwrite zeroing operation. This operation is executed by a dedicated zeroing controller. Upon receiving the state machine transition completion signal, the controller immediately generates a DMA write request with a burst length of 64 ticks, targeting the starting address of the 4KB buffer, and containing all zeros. Since the on-chip SRAM supports atomic write operations with a maximum burst length of 64 ticks, the entire zeroing process is completed in a single bus transaction, taking no more than 800 nanoseconds. After zeroing is complete, the zeroing controller sends a release signal to the memory management unit, which updates the page frame's state from "security-dedicated" to "idle" and adds it to the NVMe protocol stack's commit queue memory pool for use by subsequent I / O command command descriptors or PRP lists. This mechanism achieves seamless switching between secure computing resources and high-speed I / O queue memory, avoiding the permanent retention of static memory for security functions in resource-constrained edge controllers, and significantly improving memory utilization.

[0046] As a preferred embodiment of the present invention, the specific execution flow of the intrinsic security access control method is as follows: During the initialization phase before NVMe device enumeration is completed, after the storage controller completes the basic register configuration, it immediately activates the edge security computing module and sets the authentication state machine to the "unauthorized" state. Simultaneously, the hard-wired command filtering unit begins real-time filtering of all incoming commands. Subsequently, the edge security computing module calls a true random number generator to generate a 32-byte dynamic challenge value, and encapsulates this challenge value through a Vendor Specific Command in the NVMe management command channel before sending it to the host. Upon receiving this command, the host operating system or security agent performs a SHA-256 operation on the challenge value based on the pre-shared key stored locally, generating a 32-byte first hash result, which is then returned to the storage device through the response path of the same vendor-defined command.

[0047] After receiving the first hash result, the storage controller temporarily stores it at a specified offset in the 4KB buffer. Subsequently, the edge security computing module starts the hardware hash engine, reads the key from the security key register, and performs an independent SHA-256 operation on the original challenge value to generate a second hash result. The two hash results are compared byte-by-byte in a dedicated comparator. If all 32 bytes are identical, a valid authorization signal is output; otherwise, the system remains in the "unauthorized" state and can choose to log a failure or trigger a security alarm. The valid authorization signal drives the authentication state machine to transition to the "authorized" state, and the hard-wired instruction filtering unit then removes the blockade on the instruction execution path, allowing all legitimate I / O commands to pass.

[0048] To verify the technical effects of the present invention, the following embodiments and comparative examples were designed for comparative testing.

[0049] In one specific embodiment, a prototype intelligent storage system based on the present invention is constructed. This embodiment is verified on a Xilinx UltraScale+ FPGA prototype platform, with the main control chip simulated using a 28nm process. The test host is a server with an Intel Xeon processor, equipped with a standard PCIe Gen4 slot supporting the NVMe 1.4 protocol, and integrates an edge security computing module, an authentication state machine, and a hardwired instruction filtering unit. After power-on, the system completes initialization within 1.18 milliseconds and enters a state waiting for challenge responses. After receiving the challenge value, the host returns the hash result within 50 microseconds. The storage system completes local hash calculation and comparison within 10 microseconds, the state machine successfully transitions, and the total authentication latency is 64.7 microseconds. During this period, all read and write commands to the user data namespace are physically blocked. After authentication, the 4KB buffer is cleared and released back to the I / O memory pool within 800 nanoseconds. Under continuous high-load I / O stress testing, the system shows a 12% improvement in memory utilization without any security bypass events.

[0050] In the comparative example, a traditional firmware-based secure storage solution was used. Identity verification was performed by the main control CPU, the key was stored in a read-write OTP area, and command filtering was implemented through firmware hook functions. Under the same test conditions, after power-on, the system needed to wait for firmware loading (approximately 8 milliseconds) before the authentication process could begin. The authentication calculation took approximately 150 microseconds, resulting in a total latency of 158 milliseconds. During this security vacuum, attackers could inject malicious commands to directly read user data. Furthermore, the static allocation of 4KB of memory for security functions limited the I / O queue depth, leading to an approximately 9% decrease in IOPS under high concurrency scenarios.

[0051] The table below summarizes the key performance and safety metrics of the embodiments and comparative examples:

[0052]

[0053] The above data demonstrates that, through deep hardware integration, this invention achieves pre-emptive security action points, physical security mechanisms, and dynamic resource utilization without sacrificing performance. Its technical solution is fully disclosed, and those skilled in the art can reproduce all the technical features of this invention based on the above description and in conjunction with the standard NVMe controller design process.

[0054] Furthermore, the design of the overwrite and zeroing operation not only serves resource reuse but also endows the system with the ability to self-aware of changes in the physical environment. Since the 4KB buffer is located in volatile SRAM, its contents will be naturally lost if the device experiences an abnormal power outage, physical movement causing a power interruption, or a cold start attack, without relying on additional erase commands or secure erase protocols. This feature enables the system to automatically clear sensitive intermediate data in the face of physical theft or disassembly attacks, reducing the risk of information leakage.

[0055] Furthermore, the combinational logic circuit of the hard-wired instruction filtering unit is physically implemented using a fully custom design, with its critical path rigorously time-optimized to ensure a 2-nanosecond delay constraint is met even at the highest operating frequency. The opcode decoder employs a priority encoding structure to avoid the risk of multiple opcodes hitting simultaneously; the namespace ID comparator uses a high-speed subtractor for zero-value detection; and the state gating selector uses transmission gate logic to achieve fast signal switching with minimal area overhead. Simulation calculations show that the power consumption of the entire unit only increases the overall controller power consumption by 0.3% under typical workloads, with a negligible impact on energy efficiency.

[0056] The interaction between the edge secure computing module and the NVMe protocol stack is implemented through predefined vendor-defined commands, specifically Opcodes 0xC0 (Get Challenge) and 0xC1 (Verify Response). The Get Challenge command has no data payload, only triggering the generation and distribution of the challenge value; the Verify Response command carries a 32-byte hash result as its data payload. The processing logic of these two commands is hard-coded in the NVMe command parser, and its execution path is independent of the regular command queue, ensuring that secure communication is given priority even under I / O congestion.

[0057] In summary, the intelligent storage system with edge computing and intrinsic security mechanisms proposed in this invention constructs a secure storage architecture that is effective from power-on, has a microsecond-level response time, is resource-efficient, and cannot be bypassed by offloading security verification tasks to the storage edge, implementing physical-level instruction gating using hard-wired logic, and introducing a dynamic memory reuse protocol. This system is highly feasible in engineering implementation, as all its modules can be integrated based on existing semiconductor processes and IP libraries, providing a reliable data storage infrastructure for edge computing scenarios with stringent requirements for both security and real-time performance, such as industrial automation, connected vehicles, and remote surgical robots.

[0058] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An intelligent storage system with edge computing and intrinsic security mechanisms, characterized in that, include: The edge secure computing module, integrated within the storage controller, is used to perform identity verification during the power-on initialization phase. The edge security computing module includes a true random number generator and a hardware hash engine; wherein, the true random number generator is connected to an on-chip physical entropy source to generate dynamic challenge values, and the input interface of the hardware hash engine is connected to the registers of the non-volatile key storage area through a dedicated data path. The authentication state machine is implemented using synchronous sequential logic circuits. Its reset terminal is connected to the system reset signal so that the authentication state machine is set to the "unauthorized" state by default when powered on. The authentication state machine receives the authorization signal from the edge security computing module to trigger a state transition to the "authorized" state. The hard-wired instruction filtering unit, composed of pure combinational logic circuits, has its state input terminal directly coupled to the output terminal of the authentication state machine via physical wiring; it is used to decode NVMe commands in real time and output a prohibition signal according to the level signal of the authentication state machine. The instruction execution path has its clock enable pin connected to the output of the hardwired instruction filtering unit; when the disable signal is received, the operating clock of the instruction execution path is physically cut off to block I / O operations targeting the user data namespace.

2. The intelligent storage system according to claim 1, characterized in that, The non-volatile key storage area adopts an antifuse or fuse physical structure, which is electrically isolated from the external bus, debug interface and JTAG port in terms of physical layout, and only supports read-only access at the circuit level.

3. The intelligent storage system according to claim 1, characterized in that, The hardware hash engine is a four-stage pipeline structure, with each stage configured to process 16 bytes of data. A dedicated private bus with a width of 256 bits is provided between the hardware hash engine and the non-volatile key storage area. This bus is independent of the general-purpose AXI bus matrix of the storage controller.

4. The intelligent storage system according to claim 1, characterized in that, The hard-wire instruction filtering unit includes: An opcode decoder is used to identify read, write, compare, and refresh opcodes in the NVMe protocol in parallel. The namespace ID comparator is used to check whether the NSID field in the command message is non-zero; The state gating selector has its inputs connected to the opcode decoder, the namespace ID comparator, and the authentication state machine, respectively, and its output is connected to the clock enable terminal of the instruction execution path. The propagation delay of the entire combinational logic path does not exceed 2 nanoseconds.

5. The intelligent storage system according to claim 1, characterized in that, The system also includes a dynamically reused memory unit, which contains an on-chip SRAM buffer with a 4KB buffer. During the authentication phase, the 4KB buffer is exclusively allocated to the edge security computing module by the hardware arbitrator and is used to temporarily store dynamic challenge values ​​and intermediate states of hash operations.

6. The intelligent storage system according to claim 5, characterized in that, The system also includes a dedicated zeroing controller; after the authentication state machine jumps to the "authorized" state, the dedicated zeroing controller is triggered to initiate a DMA all-zero write request with a burst length of 64 ticks to the 4KB buffer, and releases the 4KB buffer to the NVMe protocol stack's commit queue memory pool after the write is completed.

7. The intelligent storage system according to claim 6, characterized in that, The 4KB buffer is located in a volatile storage area and is configured to automatically disappear its contents when the system power is interrupted, so as to achieve self-aware protection against physical removal or power outage attacks.

8. The intelligent storage system according to claim 1, characterized in that, The logic for the edge security computing module to perform identity verification includes: sending a dynamic challenge value generated by the true random number generator to the host via a vendor-defined management command; receiving a first hash result returned by the host; calculating a second hash result by a hardware hash engine; and outputting the authorization signal when the first and second hash results are matched byte by byte.

9. The intelligent storage system according to claim 8, characterized in that, The processing logic of the vendor-defined management commands is hard-coded in the NVMe command parser, and its execution path is physically independent of the regular I / O command queue.

10. The intelligent storage system according to claim 5, characterized in that, The 4KB buffer is located in a volatile SRAM buffer, and its contents are naturally lost when the device experiences an abnormal power outage or power interruption, without the need to execute additional erase instructions.

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