Low-noise amplifier circuit design method, low-noise amplifier circuit and chip

Abstract

The invention discloses a low-noise amplifier circuit design method, a low-noise amplifier circuit and a low-noise amplifier chip. The low-noise amplifier circuit design method comprises the following steps: constructing a small-signal equivalent circuit diagram of a transistor added into a feedback network; obtaining the input impedance and the output impedance of the transistor according to the small signal equivalent circuit diagram; according to the input impedance and the output impedance, obtaining a feedback gain of a transistor added to the feedback network and an intrinsic gain of a transistor without the feedback network, and according to the feedback gain and the intrinsic gain, obtaining a proportionality coefficient; constructing a noise analysis equivalent circuit diagram of the transistor added into the feedback network; obtaining a total noise coefficient according to the noise analysis equivalent circuit diagram, and obtaining an influence coefficient according to the total noise coefficient; and constructing a contour map about feedback parameters of the feedback network according to the proportionality coefficient and the influence coefficient, and analyzing the gain flatness and noise performance of the transistor according to the contour map. According to the invention, a low noise coefficient, a high power gain and an excellent gain flatness index are synchronously realized in an ultra-wide frequency band.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a low-noise amplifier circuit design method, a low-noise amplifier circuit, and a chip. Background Technology

[0002] In modern high-speed communication, radar, and satellite receiving systems, the low-noise amplifier (LNA) at the beginning of the link plays a crucial role, directly determining the receiving sensitivity, dynamic range, and anti-interference capability of the entire system. With the rapid development of Ka / K band multiple-input multiple-output (MIMO) technology and satellite communication, unprecedentedly stringent requirements have been placed on LNA performance: high gain, low noise figure (NF), excellent gain flatness, and unconditional stability must be achieved simultaneously over an ultra-wide bandwidth. Traditional discrete-device LNAs can provide good gain and noise figure, but traditional methods are inherently limited by their large size, high weight, and complex assembly and debugging, making it difficult to meet the space and integration requirements of large-scale array systems. Against this backdrop, monolithic microwave integrated circuit (MMIC) technology, with its higher integration density and significant miniaturization advantages, has attracted increasing attention. This technology provides a key technical path for achieving high-performance, high-density integrated broadband LNA chips by directly integrating passive components (such as capacitors, inductors, and transmission lines) with active transistors on the same chip.

[0003] In low-noise amplifier design, source degradation and lossy matching are mainstream bandwidth extension techniques. However, there is an inherent trade-off between gain and bandwidth, requiring the sacrifice of maximum gain for gain flatness and bandwidth improvement. Specifically, standalone source degradation feedback structures often fail to achieve ideal gain flatness, and their bandwidth extension capability is typically limited to within three octaves. To overcome the bandwidth bottleneck of traditional methods, distributed amplifier technology effectively counteracts the parasitic capacitance effect of transistors by constructing artificial transmission line networks, achieving a significant extension of the operating bandwidth. However, distributed amplifier technology relies on the cascaded structure of multi-stage transistor units, inevitably leading to increased power consumption and chip area, which is detrimental to applications in power-sensitive systems and high-density integration scenarios.

[0004] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a low-noise amplifier circuit design method, a low-noise amplifier circuit and chip, so as to solve the problems of high power consumption and large chip area in the existing low-noise amplifier bandwidth extension technology.

[0006] The technical solution of the present invention is as follows: In a first aspect, the present invention provides a low-noise amplifier design method, comprising: Construct the small-signal equivalent circuit diagram of the transistor with added feedback network; The input and output impedances of the transistors are obtained based on the small-signal equivalent circuit diagram. The feedback gain of the transistor with the feedback network and the intrinsic gain of the transistor without the feedback network are obtained based on the input impedance and output impedance of the transistor, and the scaling factor is obtained based on the feedback gain and the intrinsic gain. Construct the equivalent circuit diagram for noise analysis of the transistor with added feedback network; The total noise figure is obtained based on the equivalent circuit diagram of the noise analysis, and the influence coefficient of the feedback network on the total noise figure is obtained based on the total noise figure. Based on the proportionality coefficient and the influence coefficient, a contour plot of the feedback parameters of the feedback network is constructed, and the gain flatness and noise performance of the transistor are analyzed based on the contour plot.

[0007] In a further embodiment of the present invention, the feedback network includes a first capacitor, a first resistor, and a first inductor connected in sequence; the step of obtaining the input impedance and output impedance of the transistor based on the small-signal equivalent circuit diagram includes: The input impedance is calculated using Kirchhoff's current law, and its expression is as follows: ;in, Indicates the drain-source impedance of a transistor. Indicates the impedance of the feedback loop. Indicates the transconductance of a transistor. Indicates gate-source capacitance. Indicates gate parasitic resistance; The output impedance is calculated using Kirchhoff's voltage law, and its expression is as follows: .

[0008] A further provision of the present invention states that, in the step of obtaining the feedback gain of the transistor with the feedback network and the intrinsic gain of the transistor without the feedback network based on the input and output impedances of the transistor, the feedback gain... The expression is: ; The intrinsic gain The expression is: ,in, Indicates load power. Indicates the available power provided by the source. This represents the small-signal output resistance of the transistor. Indicates the transistor cutoff frequency. Indicates the operating frequency; The proportionality coefficient The expression is: ,in, This indicates the value of the first resistor. This represents the value of the first inductance; when the proportional coefficient... When the value is less than 1, the low-noise amplifier circuit exhibits negative feedback, and the feedback network reduces the gain at the center frequency. When the proportional coefficient... When the value is greater than 1, the low-noise amplifier circuit exhibits positive feedback, and the feedback network increases the gain at the center frequency.

[0009] In a further provision of the present invention, in the steps of obtaining the total noise figure based on the noise analysis equivalent circuit diagram and obtaining the influence coefficient of the feedback network on the total noise figure based on the total noise figure, the expression for the total noise figure F is: Where k represents the Boltzmann constant and T represents the thermodynamic temperature. , The thermal noise of the source resistor and the gate resistor are respectively. and This refers to the thermal noise current of the gate and drain. For the thermal noise of the feedback resistor, This is the sum of the thermal noise currents observed at the output terminal. Indicates the source resistance; The influence coefficient The expression is: .

[0010] A further provision of the present invention is that the drain-source impedance of the transistor... The expression is: ; The impedance of the feedback loop The expression is: ;in, This indicates the value of the first resistor. This represents the value of the first inductance.

[0011] Secondly, the present invention also provides a low-noise amplifier circuit according to the low-noise amplifier design method described above, comprising: an input matching network, a plurality of transistors, an inter-stage matching network, a plurality of feedback networks, and an output matching network; wherein, The input terminal of the input matching network is connected to the radio frequency input terminal, and the output terminal of the input matching network is connected to the gate of the first-stage transistor. The input terminal of the interstage matching network is connected to the drain of the transistor in the previous stage, and the output terminal of the interstage matching network is connected to the gate of the transistor in the next stage. The feedback network is connected between the gate and drain of the transistor in the same stage, and the feedback network is used to adjust the full-band gain characteristics. The input terminal of the output matching network is connected to the drain of the last stage transistor, and the output terminal of the output matching network is connected to the radio frequency output terminal.

[0012] In a further embodiment of the present invention, the feedback network is connected to the transistors from the second stage to the last stage; the feedback network includes: a first capacitor, a first resistor, and a first inductor; One end of the first capacitor is connected to the gate of the transistor, and the other end of the first capacitor is connected to one end of the first resistor; The other end of the first resistor is connected to one end of the first inductor, and the other end of the first inductor is connected to the drain of the transistor.

[0013] In a further embodiment of the present invention, the input matching network includes: a second capacitor, a third capacitor, a fourth capacitor, a second inductor, a third inductor, a fourth inductor, and a second resistor; One end of the second capacitor is connected to the radio frequency input terminal, the other end of the second capacitor is connected to one end of the third capacitor and one end of the second inductor, and the other end of the second capacitor is grounded. The other end of the second inductor is connected to one end of the third inductor and one end of the fourth inductor, respectively; The other end of the second inductor is connected to one end of the fourth capacitor and one end of the second resistor, respectively. The other end of the fourth capacitor is grounded, and the other end of the second resistor is connected to the first power supply voltage. The other end of the fourth inductor is connected to the gate of the transistor.

[0014] In a further embodiment of the present invention, the interstage matching network includes: a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a fifth inductor, a sixth inductor, a seventh inductor, an eighth inductor, and a third resistor; One end of the fifth inductor is connected to the drain of the transistor, and the other end of the fifth inductor is connected to one end of the sixth inductor and one end of the fifth capacitor, respectively. The other end of the sixth inductor is connected to the second power supply voltage, one end of the sixth capacitor is connected to the sixth inductor, and the other end of the sixth capacitor is grounded; The other end of the fifth capacitor is connected to one end of the seventh capacitor and one end of the seventh inductor, respectively, and the other end of the seventh capacitor is grounded; The other end of the seventh inductor is connected to one end of the eighth inductor and the gate of the transistor, respectively. One end of the eighth inductor is connected to one end of the eighth capacitor and one end of the third resistor, respectively. The other end of the eighth capacitor is grounded, and the other end of the third resistor is connected to the first power supply voltage. The output matching network includes: a ninth inductor, a tenth inductor, a ninth capacitor, and a tenth capacitor; wherein... One end of the ninth inductor is connected to the drain of the transistor, and the other end of the ninth inductor is connected to one end of the tenth inductor and one end of the ninth capacitor. The other end of the tenth inductor is connected to the second power supply voltage, and the other end of the ninth capacitor is connected to the radio frequency output terminal. One end of the tenth capacitor is connected to one end of the tenth inductor, and the other end of the tenth capacitor is grounded.

[0015] Thirdly, the present invention also provides a chip comprising the low-noise amplifier circuit described above.

[0016] This invention provides a low-noise amplifier circuit design method, a low-noise amplifier circuit, and a chip. The low-noise amplifier design method includes: constructing a small-signal equivalent circuit diagram of a transistor with a feedback network; obtaining the input impedance and output impedance of the transistor based on the small-signal equivalent circuit diagram; obtaining the feedback gain of the transistor with the feedback network and the intrinsic gain of the transistor without the feedback network based on the input impedance and output impedance, and obtaining a scaling factor based on the feedback gain and the intrinsic gain; constructing a noise analysis equivalent circuit diagram of the transistor with the feedback network; obtaining the total noise figure based on the noise analysis equivalent circuit diagram, and obtaining the influence coefficient of the feedback network on the total noise figure based on the total noise figure; constructing a contour plot of the feedback parameters of the feedback network based on the scaling factor and the influence coefficient, and analyzing the gain flatness and noise performance of the transistor based on the contour plot. This invention uses a feedback network to actively suppress gain in the low-frequency range and compensate for gain attenuation in the high-frequency range, achieving effective control of the gain frequency response characteristics, and ultimately achieving excellent gain flatness over a wide bandwidth. Compared with existing technologies, it does not require a cascaded structure of multiple transistors, reducing chip area and power consumption. Furthermore, by constructing a dual-parameter contour plot of gain flatness and noise figure, a trade-off between the gain flatness and noise performance of transistors can be intuitively achieved, thereby enabling the circuit to obtain the lowest noise figure and optimal gain flatness. Ultimately, low noise figure, high power gain, and excellent gain flatness can be achieved simultaneously in an ultra-wide bandwidth, making it suitable for power-sensitive systems and high-density integration scenarios. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 This is a schematic block diagram of a low-noise amplifier circuit in one embodiment of the present invention.

[0019] Figure 2 This is a circuit diagram of a low-noise amplifier circuit in one embodiment of the present invention.

[0020] Figure 3 This is a flowchart illustrating a low-noise amplifier circuit design method in one embodiment of the present invention.

[0021] Figure 4 This is a small-signal equivalent circuit diagram of a transistor with a feedback network added in one embodiment of the present invention.

[0022] Figure 5 This is an equivalent circuit diagram of the transistor circuit with added feedback network in one embodiment of the present invention when performing noise analysis.

[0023] Figure 6 This is a contour plot showing the influence of the total noise figure in one embodiment of the present invention.

[0024] Figure 7 This is a contour map with a scaling factor in one embodiment of the present invention.

[0025] Figure 8 This is a diagram showing the minimum low-noise coefficient under different feedback conditions in one embodiment of the present invention.

[0026] Figure 9 This is a maximum available gain diagram under different feedback parameters in one embodiment of the present invention.

[0027] Figure 10 This is a diagram showing the chip test results in one embodiment of the present invention.

[0028] The labels in the attached diagram are as follows: 1. Input matching network; 2. Interstage matching network; 3. Feedback network; 4. Output matching network; M. Transistor. Detailed Implementation

[0029] This invention provides a low-noise amplifier circuit design method, a low-noise amplifier circuit, and a chip. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0030] In the implementation methods and claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of the present invention involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0031] It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements present. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any of the units and all combinations thereof of one or more associatedly listed items.

[0032] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0033] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0034] Please also refer to Figures 1 to 2 The present invention provides a preferred embodiment of a low-noise amplifier circuit.

[0035] In some embodiments, such as Figure 1 As shown, the present invention also provides a low-noise amplifier circuit, comprising: an input matching network 1, a plurality of transistors M, an interstage matching network 2, a plurality of feedback networks 3, and an output matching network 4. The input terminal of the input matching network 1 is connected to the RF input terminal RFin, and the output terminal of the input matching network 1 is connected to the gate of the first-stage transistor M; the input terminal of the interstage matching network 2 is connected to the drain of the preceding-stage transistor M, and the output terminal of the interstage matching network 2 is connected to the gate of the following-stage transistor M; the feedback network 3 is connected between the gate and drain of the transistor M in the same stage, and the feedback network 3 is used to adjust the full-band gain characteristics; the input terminal of the output matching network 4 is connected to the drain of the last-stage transistor M, and the output terminal of the output matching network 4 is connected to the RF output terminal RFout.

[0036] In this embodiment, the low-noise amplifier circuit consists of an input matching network 1, transistors M, an interstage matching network 2, a feedback network 3, and an output matching network 4. The input matching network 1 is connected to the RF input terminal RFin and the external source impedance, and the output matching network 4 is connected to the RF output terminal RFout and the external source impedance. The input matching network 1 and the output matching network 4 are used to achieve impedance matching. The interstage matching network 2 is connected between the preceding and following transistors M, enabling optimal power transfer and gain flattening. The feedback network 3 is connected between the gate and drain of transistors M from the second to the last stage. The feedback network 3 can provide deep negative feedback to suppress gain in frequency bands below the center frequency and can reduce capacitive losses to compensate for gain attenuation in frequency bands above the center frequency, achieving full-band gain adjustment and thus optimizing broadband flatness.

[0037] In the above technical solution, the present invention uses feedback network 3 to actively suppress the gain in the low-frequency band and compensate for the gain attenuation in the high-frequency band, thereby reducing the low-frequency gain of transistor M and improving the high-frequency gain of transistor M. This achieves effective control over the gain frequency response characteristics and ultimately achieves excellent gain flatness over a wide bandwidth. Compared with the prior art, it does not require the cascaded structure of multiple transistors M, reducing chip area and power consumption. It simultaneously achieves low noise figure, high power gain and excellent gain flatness in an ultra-wide bandwidth, ultimately achieving synergistic optimization of comprehensive performance. This meets the stringent requirements of high-performance communication systems for core components of the receiving link and is suitable for power-sensitive systems and high-density integration scenarios.

[0038] In some embodiments, such as Figure 1 and Figure 2 As shown, the feedback network 3 includes: a first capacitor C1, a first resistor R1, and a first inductor L1. One end of the first capacitor C1 is connected to the gate of the transistor M, and the other end of the first capacitor C1 is connected to one end of the first resistor R1; the other end of the first resistor R1 is connected to one end of the first inductor L1, and the other end of the first inductor L1 is connected to the drain of the transistor M.

[0039] In this embodiment, the first resistor R1 is a feedback resistor, the first inductor L1 is a feedback inductor, and the first resistor R1 and the first inductor L1 constitute the main feedback network 3, which can adjust the full-band gain characteristics. The first capacitor C1 is connected between the gate and drain of the transistor M, which can isolate the DC bias between the drain and the gate of the transistor M.

[0040] In some embodiments, such as Figure 1 and Figure 2As shown, the input matching network 1 includes: a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a second inductor L2, a third inductor L3, a fourth inductor L4, and a second resistor R2. One end of the second capacitor C2 is connected to the RF input terminal RFin, and the other end of the second capacitor C2 is connected to one end of the third capacitor C3 and one end of the second inductor L2, respectively, with the other end of the second capacitor C2 grounded; the other end of the second inductor L2 is connected to one end of the third inductor L3 and one end of the fourth inductor L4, respectively; the other end of the second inductor L2 is connected to one end of the fourth capacitor C4 and one end of the second resistor R2, with the other end of the fourth capacitor C4 grounded; the other end of the second resistor R2 is connected to the first power supply voltage V1; the other end of the fourth inductor L4 is connected to the gate of the transistor M.

[0041] In this embodiment, the capacitor structure formed by the parallel connection of the second capacitor C2 and the third capacitor C3, together with the second inductor L2, the third inductor L3, and the fourth inductor L4, constitutes a T-type inductor network, forming a bandpass structure. The first power supply voltage V1 is 1.5V.

[0042] In low-noise amplifiers, the source impedance for achieving the minimum noise figure is typically not equal to the conjugate matched source impedance for achieving maximum power transfer. The combination of a T-type inductor network (usually containing a series inductor and a parallel ground inductor) and a parallel capacitor provides multiple tunable degrees of freedom. By independently adjusting the values ​​of each inductor and capacitor in the T-type network, the trajectory of the input impedance can be independently and precisely controlled on the Smith chart, thus finding an optimal trade-off point. This allows for good power matching close to 50Ω at the target frequency while remaining very close to the optimal noise matching point, ultimately achieving an extremely low noise figure and thus simultaneously achieving good power and noise matching. Furthermore, the input matching network 1 itself constitutes a second-order or higher-order bandpass filter, giving it bandpass filtering capabilities. It can selectively pass signals in the desired frequency band while effectively suppressing out-of-band interference signals. This reduces the load on subsequent circuitry and improves the system's signal-to-noise ratio and anti-interference capability. Furthermore, the parallel ground inductor in the T-type network can naturally serve as the DC bias feed path for the amplifying transistor M, eliminating the need for an additional RF choke, simplifying the circuit structure, and improving integration.

[0043] In some embodiments, such as Figure 1 and Figure 2As shown, the interstage matching network 2 includes: a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a fifth inductor L5, a sixth inductor L6, a seventh inductor L7, an eighth inductor L8, and a third resistor R3. One end of the fifth inductor L5 is connected to the drain of the transistor M, and the other end of the fifth inductor L5 is connected to one end of the sixth inductor L6 and one end of the fifth capacitor C5. The other end of the sixth inductor L6 is connected to the second power supply voltage V2, one end of the sixth capacitor C6 is connected to the sixth inductor L6, and the other end of the sixth capacitor C6 is grounded. The other end of the fifth capacitor C5 is connected to one end of the seventh capacitor C7 and one end of the seventh inductor L7, and the other end of the seventh capacitor C7 is grounded. The other end of the seventh inductor L7 is connected to one end of the eighth inductor L8 and the gate of the transistor M. One end of the eighth inductor L8 is connected to one end of the eighth capacitor C8 and one end of the third resistor R3, and the other end of the eighth capacitor C8 is grounded. The other end of the third resistor R3 is connected to the first power supply voltage V1. The second power supply voltage V2 is 10V.

[0044] In this embodiment, the interstage matching network 2 is connected between two consecutive transistors M, achieving optimal power transfer and gain flattening. Specifically, matching the output impedance of the first-stage amplifier (transistor M) with the input impedance of the second-stage amplifier maximizes power transfer and improves the overall amplifier's usable gain and gain flatness. Furthermore, in multi-stage low-noise amplifier design, the overall noise figure is primarily determined by the first stage, but the second stage also contributes. Therefore, the interstage matching network 2 can further reduce the overall system noise figure while maintaining gain, achieving optimized noise figure. Moreover, the interstage matching network 2, connected between two adjacent transistors M, isolates the influence between the preceding and following stages, thereby improving the amplifier's linearity (e.g., IP3) and stability, preventing circuit self-oscillation, and thus enhancing linearity and stability.

[0045] In some embodiments, such as Figure 1 and Figure 2 As shown, the output matching network 4 includes: a ninth inductor L9, a tenth inductor L10, a ninth capacitor C9, and a tenth capacitor C10; wherein, one end of the ninth inductor L9 is connected to the drain of the transistor M, and the other end of the ninth inductor L9 is connected to one end of the tenth inductor L10 and one end of the ninth capacitor C9; the other end of the tenth inductor L10 is connected to the second power supply voltage V2, and the other end of the ninth capacitor C9 is connected to the RF output terminal RFout; one end of the tenth capacitor C10 is connected to one end of the tenth inductor L10, and the other end of the tenth capacitor C10 is grounded.

[0046] In this embodiment, the drain of the last stage transistor M at one end of the ninth inductor L9 is connected, the ninth capacitor C9 is connected to the RF output terminal, and the output matching network 4 can match the external source impedance to the highest gain impedance point of transistor M, so that transistor M obtains the best gain while completing the broadband matching of the low noise amplifier circuit.

[0047] In some embodiments, such as Figure 3 As shown, the present invention also provides a low-noise amplifier design method, which includes the following steps: S100. Construct the small-signal equivalent circuit diagram of the transistor with added feedback network; Specifically, such as Figure 1 and Figure 4 As shown, the first resistor and the first inductor form the main feedback network. Indicates the transconductance of a transistor. Indicates gate-source capacitance. Indicates gate parasitic resistance. Indicates the drain-source capacitance. This indicates the value of the first resistor. This represents the value of the first inductance. For simplicity, the gate-drain capacitance of the transistor is ignored. .

[0048] S200. Obtain the input impedance and output impedance of the transistor according to the small-signal equivalent circuit diagram. Specifically, after constructing the small-signal equivalent circuit diagram of the transistor with the feedback network, the input impedance of the transistor after the feedback network is added can be calculated according to Kirchhoff's current law and Kirchhoff's voltage law. With output impedance .

[0049] The input impedance is calculated according to Kirchhoff's current law, and its expression is as follows: ;in, Indicates the drain-source impedance of a transistor. Indicates the impedance of the feedback loop. Indicates the transconductance of a transistor. Indicates gate-source capacitance. This represents the gate parasitic resistance.

[0050] The output impedance is calculated using Kirchhoff's voltage law, and its expression is as follows: .

[0051] Furthermore, the drain-source impedance of the transistor The expression is: ; The impedance of the feedback loop The expression is: ;in, This indicates the value of the first resistor. This represents the value of the first inductance.

[0052] S300. Based on the input impedance and output impedance of the transistor, obtain the feedback gain of the transistor with the added feedback network and the intrinsic gain of the transistor without the feedback network, and obtain the scaling factor based on the feedback gain and the intrinsic gain. Specifically, after calculating the input and output impedances of the transistor after the heating feedback network is obtained, the feedback gain of the transistor with the feedback network and the intrinsic gain of the transistor without the feedback network are obtained based on the input and output impedances of the transistor.

[0053] Wherein, the feedback gain The expression is: ; The intrinsic gain The expression is: ,in, Indicates load power. Indicates the available power provided by the source. This represents the small-signal output resistance of the transistor. Indicates the transistor cutoff frequency. Indicates the operating frequency.

[0054] Having obtained the feedback gain of the transistor with the feedback network and the intrinsic gain of the transistor without the feedback network, the scaling factor is defined as the ratio of the feedback gain to the intrinsic gain.

[0055] The proportionality coefficient The expression is: ,in, This indicates the value of the first resistor. This represents the value of the first inductance.

[0056] Based on the expression for the proportionality coefficient, it can be seen that when the frequency is low, At this point, the circuit exhibits negative feedback, meaning the feedback loop reduces the maximum gain at low frequencies; due to the quadratic function characteristics, when When the value is greater than the corresponding value of the axis of symmetry of this quadratic function, β begins to follow... If β increases with ω, then there must exist a frequency point ω0 such that when ω>ω0, β>1. At this point, the circuit exhibits positive feedback, meaning that as the feedback loop increases, the maximum gain expression will differ from the previous one. and The external constant is almost independent of frequency. Therefore, by properly setting the feedback loop... and The value is reduced to decrease the low-frequency gain of the transistor and increase the high-frequency gain of the transistor, thereby achieving excellent gain flatness over a wide range, and achieving good matching over a wide range by realizing different frequency responses.

[0057] When the device parameters and frequency (i.e. , , , Given, according to the expression for the proportionality coefficient, It can be represented as Therefore, different functions can be obtained through numerical calculation. Value and The trajectory curve. Different and Combinations will yield different results This value will result in different gain effects at the center frequency. When When the feedback network reduces the gain at the center frequency, and when At this time, the feedback network will increase the gain at the center frequency. By establishing different Value and The trajectory curves allow for a direct observation of the impact of the feedback network parameters on the circuit gain response, thus effectively assisting in broadband circuit design.

[0058] S400, Construct the equivalent circuit diagram for noise analysis of the transistor with added feedback network; Specifically, such as Figure 5 As shown, after adding the feedback network, the equivalent circuit diagram for noise analysis of the transistor with the added feedback network is constructed. Figure 5 middle, , The thermal noise of the source resistor and the gate resistor are respectively. and This refers to the thermal noise current of the gate and drain. For the thermal noise of the feedback resistor, This is the sum of the thermal noise currents observed at the output terminal. Indicates the source resistance.

[0059] S500. Obtain the total noise figure based on the equivalent circuit diagram of the noise analysis, and obtain the influence coefficient of the feedback network on the total noise figure based on the total noise figure. Specifically, an equivalent circuit diagram for noise analysis of the transistor with added feedback network is constructed, and the overall noise figure of the circuit is calculated based on the equivalent circuit diagram. The expression for the total noise figure F is as follows: Where k represents the Boltzmann constant and T represents the thermodynamic temperature. , The thermal noise of the source resistor and the gate resistor are respectively. and This refers to the thermal noise current of the gate and drain. For the thermal noise of the feedback resistor, This is the sum of the thermal noise currents observed at the output terminal. Indicates the source resistance.

[0060] By combining the total noise figure expression with The relevant terms are listed separately, which describes the impact of the feedback network on the total noise figure, the impact coefficients. The expression is: .

[0061] Similarly, It can be represented as Therefore, different functions can be obtained through numerical calculation. Value and The trajectory curve. Therefore, by establishing about and The trajectory curves allow for a direct observation of the impact of feedback network parameters on circuit noise, thus guiding designers to obtain the corresponding feedback parameters while introducing minimal additional noise. and The possible values ​​of .

[0062] S600. Construct a contour plot of the feedback parameters of the feedback network based on the proportional coefficient and the influence coefficient, and analyze the gain flatness and noise performance of the transistor based on the contour plot.

[0063] Specifically, after obtaining the proportionality coefficient Influence coefficient of prime numbers Then, draw them separately. and about and The trajectory curve, also known as the contour plot, can intuitively show the trade-off between the gain flatness and noise performance of a transistor, thereby enabling the circuit to achieve the lowest noise figure and the optimal gain flatness.

[0064] In some embodiments, the present invention also provides a chip comprising the low-noise amplifier circuit as described above. Specific examples of a low-noise amplifier circuit are described herein and will not be repeated here.

[0065] To verify the superiority of the feedback network design method in this embodiment, this embodiment uses 2×75um GaN transistors to draw a diagram. and about and Contour map, such as Figure 6 As shown, right It has a dominant influence. However, when Time, change This will further affect NF, indicating that proper tuning is necessary. and It can enhance noise performance. For example... Figure 7 As shown, the performance of 2×75µm GaN transistors at 20 GHz is displayed. Outline (0.7 / 1 / 1.3). Due to This reflects the gain enhancement capability of the feedback network; therefore, a higher value will increase the center frequency gain but will typically decrease gain flatness. To balance noise, gain, and gain flatness, from... and Three solutions (cases I-III) were selected from the tangents of the contour lines, such as Figure 6 and Figure 7 As shown. The corresponding minimum NF (NFmin) and maximum available gain (MAG) in the 10–30 GHz range are as follows. Figure 8 and Figure 9 As shown. It can be observed that, although Case I It provides the highest peak gain, but it is affected by gain roll-off and a higher NFmin. Considering gain flatness and NFmin, Case III... It provides the most favorable compromise and demonstrates an effective solution for broadband, high-performance, low-noise amplifiers.

[0066] In addition, this implementation used a 0.15 μm GaN-on-SiC commercial process for wafer fabrication and testing. Figure 10 Test results of the chip manufactured for an ultra-wideband high-gain low-noise amplifier circuit, including: Figure 10 In this context, (a) represents the S-parameter. Figure 10In this context, (b) indicates a low noise figure. Based on... Figure 10 The ultra-wideband high-gain low-noise amplifier chip was tested at a frequency of 10-30 GHz, with a test bandwidth of 20 GHz. The small-signal gain across the entire band was 26.5-29.5 dB, the measured noise figure was 2.1-3.1 dB, the input return loss S11 <-8 dB, and the output return loss S22 <-10 dB. The test results demonstrate that the low-noise amplifier can achieve a low noise figure and good gain and gain flatness within an ultra-wide bandwidth of 10-30 GHz, providing an effective hardware solution for next-generation broadband receiving systems.

[0067] In summary, the low-noise amplifier circuit design method, low-noise amplifier circuit, and chip provided by this invention have the following beneficial effects: By applying a feedback network to the drain-gate branch of the transistor, effective control of the gain frequency response characteristics is achieved by actively suppressing the gain in the low-frequency range and compensating for the gain attenuation in the high-frequency range, ultimately achieving excellent gain flatness over a wide bandwidth. Compared with existing technologies, this eliminates the need for a cascaded structure of multiple transistors, reducing chip area and power consumption. It simultaneously achieves low noise figure, high power gain, and excellent gain flatness in an ultra-wide bandwidth, ultimately achieving synergistic optimization of overall performance. This meets the stringent requirements of high-performance communication systems for core components of the receiver link and is suitable for power-sensitive systems and high-density integration scenarios. A quantitative analytical model of the noise-gain characteristics of feedback networks and transistor circuits is presented, which systematically reveals the nonlinear control mechanism of the noise figure (NF) and gain flatness by resistive and inductive feedback elements. Furthermore, a design method based on gain flatness-noise figure co-optimization is proposed: by constructing a two-parameter contour plot of gain flatness and noise figure, the performance trade-off relationship caused by the values ​​of resistance and inductance in the feedback loop is visualized, thereby accurately locating the optimal design point. This breaks through the limitations of traditional empirical trial and error, and simultaneously achieves the co-optimization of bandwidth expansion (>3 octaves), gain fluctuation suppression (≤±1.5dB), and ultra-low noise (NF≤3dB) in a single Ku / Ka band LNA. This provides a high-performance solution for millimeter-wave large-scale array receivers and effectively breaks through the core technical bottleneck of broadband high gain and low noise co-optimization in Ku / K / Ka band satellite communication and MIMO systems. The input matching network is a bandpass structure, which can achieve good power matching and noise matching at the same time. It has bandpass filtering function and can also provide a DC bias feed path for transistors. Interstage matching networks are connected between transistors in the preceding and following stages. They can achieve optimal power transfer and gain flattening, and can further reduce the overall noise figure of the system while maintaining the gain, thereby optimizing the noise figure. They can also isolate the influence between the preceding and following stages, thereby improving the linearity and stability of the amplifier, preventing circuit self-oscillation, and thus improving linearity and stability.

[0068] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method of designing a low noise amplifier, characterized by, The method comprises the following steps: constructing a small signal equivalent circuit diagram of the transistor with the feedback network; acquiring input impedance and output impedance of the transistor according to the small signal equivalent circuit diagram; acquiring feedback gain of the transistor with the feedback network and intrinsic gain of the transistor without the feedback network according to the input impedance and the output impedance of the transistor, and acquiring a proportional coefficient according to the feedback gain and the intrinsic gain; constructing a noise analysis equivalent circuit diagram of the transistor with the feedback network; acquiring total noise coefficient according to the noise analysis equivalent circuit diagram, and acquiring an influence coefficient of the feedback network on the total noise coefficient according to the total noise coefficient; constructing an isopleth map of feedback parameters of the feedback network according to the proportional coefficient and the influence coefficient, and analyzing gain flatness and noise performance of the transistor according to the isopleth map.

2. The low noise amplifier design method of claim 1, wherein, The feedback network comprises a first capacitor, a first resistor and a first inductor connected in sequence; the step of acquiring input impedance and output impedance of the transistor according to the small signal equivalent circuit diagram comprises the following steps: calculating the input impedance according to Kirchhoff's current law, and the expression of the input impedance is: ; wherein, represents the transistor drain-source impedance, represents the impedance of the feedback loop, represents the transistor transconductance, represents the gate-source capacitance, represents the gate parasitic resistance; calculating the output impedance according to Kirchhoff's voltage law, and the expression of the output impedance is: 。 3. The low noise amplifier design method of claim 1, wherein, In the step of deriving the feedback gain of the transistor with the feedback network added and the intrinsic gain of the transistor without the feedback network from the input impedance and the output impedance of the transistor, the feedback gain is expressed by: ； The intrinsic gain The expression for the intrinsic gain is: wherein, represents the load power, represents the source provided supply power, represents the transistor small signal output resistance, represents the transistor cutoff frequency, represents the operating frequency; The proportionality coefficient The expression for the proportionality coefficient is wherein represents the value of the first resistance, represents the value of the first inductance; when the proportionality coefficient is less than 1, the low noise amplifier circuit behaves as a negative feedback, the feedback network reducing the gain at the central frequency, when the proportionality coefficient is greater than 1, the low noise amplifier circuit behaves as a positive feedback, the feedback network increasing the gain at the central frequency.

4. The low noise amplifier design method of claim 1, wherein, In the step of acquiring total noise coefficient according to the noise analysis equivalent circuit diagram, and acquiring an influence coefficient of the feedback network on the total noise coefficient according to the total noise coefficient, the expression of the total noise coefficient F is: where k is the Boltzmann constant and T is the thermodynamic temperature, , the thermal noise of the source resistance and gate resistance, respectively, and the thermal noise current of the gate and drain, the thermal noise of the feedback resistance, the sum of the thermal noise currents observed at the output, denotes the source resistance; The influence coefficient The expression of the influence coefficient is: 。 5. The low noise amplifier design method of claim 2, wherein, The transistor drain-source impedance The expression for the transistor drain-source impedance is ； Impedance of the feedback loop The expression for the impedance of the feedback loop is ; wherein represents a value of the first resistance, represents a value of the first inductance.

6. A low noise amplifier circuit based on the low noise amplifier design method of any of claims 1-5, characterized by The method comprises the following steps: input matching network, a plurality of transistors, inter-stage matching network, a plurality of feedback networks and output matching network; wherein, the input end of the input matching network is connected with the radio frequency input end, and the output end of the input matching network is connected with the gate of the transistor of the first stage; the input end of the inter-stage matching network is connected with the drain of the transistor of the previous stage, and the output end of the inter-stage matching network is connected with the gate of the transistor of the next stage; the feedback network is connected between the gate and the drain of the transistor of the same stage, and the feedback network is used for adjusting the gain characteristic of the full frequency band; the input end of the output matching network is connected with the drain of the transistor of the last stage, and the output end of the output matching network is connected with the radio frequency output end.

7. The low noise amplifier circuit of claim 6, wherein, The feedback network is connected between the transistors of the second stage to the last stage. The feedback network comprises a first capacitor, a first resistor and a first inductor; one end of the first capacitor is connected with the gate of the transistor, and the other end of the first capacitor is connected with one end of the first resistor; the other end of the first resistor is connected with one end of the first inductor, and the other end of the first inductor is connected with the drain of the transistor.

8. The low noise amplifier circuit of claim 7, wherein, The input matching network comprises a second capacitor, a third capacitor, a fourth capacitor, a second inductor, a third inductor, a fourth inductor and a second resistor; one end of the second capacitor is connected with the radio frequency input end, and the other end of the second capacitor is respectively connected with one end of the third capacitor and one end of the second inductor, and the other end of the second capacitor is grounded; the other end of the second inductor is respectively connected with one end of the third inductor and one end of the fourth inductor; Another end of the second inductor is connected with one end of the fourth capacitor and one end of the second resistor respectively, another end of the fourth capacitor is grounded, and another end of the second resistor is connected with the first power voltage; Another end of the fourth inductor is connected with the gate of the transistor.

9. The low noise amplifier circuit of claim 6, wherein, The inter-stage matching network comprises a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a fifth inductor, a sixth inductor, a seventh inductor, an eighth inductor and a third resistor; One end of the fifth inductor is connected with the drain of the transistor, and another end of the fifth inductor is connected with one end of the sixth inductor and one end of the fifth capacitor respectively; Another end of the sixth inductor is connected with the second power voltage, one end of the sixth capacitor is connected with the sixth inductor, and another end of the sixth capacitor is grounded; Another end of the fifth capacitor is connected with one end of the seventh capacitor and one end of the seventh inductor respectively, and another end of the seventh capacitor is grounded; Another end of the seventh inductor is connected with one end of the eighth inductor and the gate of the transistor respectively; One end of the eighth inductor is connected with one end of the eighth capacitor and one end of the third resistor respectively; Another end of the eighth capacitor is grounded, and another end of the third resistor is connected with the first power voltage; The output matching network comprises a ninth inductor, a tenth inductor, a ninth capacitor and a tenth capacitor; wherein, One end of the ninth inductor is connected with the drain of the transistor, and another end of the ninth inductor is connected with one end of the tenth inductor and one end of the ninth capacitor respectively; Another end of the tenth inductor is connected with the second power voltage, and another end of the ninth capacitor is connected with the radio frequency output end; One end of the tenth capacitor is connected with one end of the tenth inductor, and another end of the tenth capacitor is grounded.

10. A chip, characterized by The low noise amplifier circuit comprises the low noise amplifier circuit according to any one of claims 6-9.

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