Clock circuit with self-diagnosis function, clock circuit diagnosis method, and chip
By introducing pulse generation, selection, self-test, and comparison modules into the clock circuit, combined with JTAG network and pulse source switching, the problem of not being able to detect the normal operation of the on-chip clock control module during full-speed testing was solved, improving fault diagnosis capability and chip yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN JIANGYUAN TECHNOLOGY CO LTD
- Filing Date
- 2026-01-19
- Publication Date
- 2026-05-15
AI Technical Summary
In the existing technology, the full-speed test circuit cannot detect whether the on-chip clock control module in the circuit is working properly, which makes it impossible to accurately determine the cause of the fault when the full-speed test fails.
Design a clock circuit with self-diagnostic function. By adding a pulse generation module, a pulse selection module, a pulse self-test module, and a result comparison module, the circuit can detect clock pulses and diagnose faults, including frequency testing and pulse count. The detection results are output using a JTAG network, and the pulse source switching control module switches to an external backup test clock when the functional clock fails.
This technology enables accurate detection of faults in the on-chip clock control module when full-speed testing fails, improving the diagnostic capabilities of full-speed testing and chip yield.
Smart Images
Figure CN121547025B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a clock circuit with self-diagnostic function, a clock circuit diagnostic method, and a chip. Background Technology
[0002] The full-speed test circuit consists of a functional clock, an on-chip clock (OCC) control module, and a scan chain (a link consisting of at least one data flip-flop connected in series). The functional clock generates test clock pulses, the on-chip clock control module controls the frequency and number of the generated test clock pulses, and the scan chain latches the input data and outputs the internal state bit by bit to an external test device for analysis to ensure that the chip can work normally at the highest operating frequency.
[0003] In related technologies, during the chip measurement process using a full-speed test circuit based on a scan chain, it is only possible to determine whether the on-chip clock control module in the full-speed test circuit is normal based on the detection results of the scan chain. However, when the full-speed test fails, it is impossible to determine whether the on-chip clock control module in the circuit can work properly. Summary of the Invention
[0004] This disclosure provides a clock circuit with self-diagnostic function, a clock circuit diagnostic method, and a chip to solve the problem in related technologies where it is impossible to detect whether the on-chip clock control module in the circuit can work properly when the full-speed test fails.
[0005] The first aspect of this disclosure provides a clock circuit with self-diagnostic function, the clock circuit including a pulse generation module, a pulse selection module, a pulse self-test module and a result comparison module;
[0006] The first input terminal of the pulse generation module is connected to the first pulse source, and the second input terminal of the pulse generation module is connected to the second pulse source.
[0007] The input terminal of the pulse selection module is connected to the output terminal of the pulse generation module, and the pulse selection module is used to select the target pulse;
[0008] The input terminal of the pulse self-test module is connected to the output terminal of the pulse selection module, and the pulse self-test module is used to test the target pulse.
[0009] The input terminal of the result comparison module is connected to the output terminal of the pulse self-test module, and the result comparison module is used to determine whether the pulse source corresponding to the target pulse is faulty.
[0010] In one embodiment, the pulse self-test module includes:
[0011] Frequency test module and pulse count module;
[0012] The input terminal of the frequency testing module is connected to the output terminal of the pulse selection module, and the frequency testing module is used to test the frequency of the target pulse.
[0013] The input terminal of the pulse count module is connected to the output terminal of the pulse selection module, and the pulse count module is used to calculate the number of target pulses.
[0014] In one embodiment, the clock circuit further includes a pulse source switching control module;
[0015] The input terminal of the pulse source switching control module is connected to the output terminal of the result comparison module, and the first output terminal of the pulse source switching control module is connected to the pulse selection input terminal of the pulse selection module. The pulse source switching control module is used to switch the pulse source to the first pulse source or to the second pulse source.
[0016] In one embodiment, the pulse source switching control module includes:
[0017] Pulse switching control module, pulse number configuration module, and pulse frequency configuration module;
[0018] The pulse switching control module is used to control the pulse selection module to select the corresponding pulse source;
[0019] The pulse count configuration module is used to configure the target number of pulses;
[0020] The pulse frequency configuration module is used to configure the frequency value of the target pulse.
[0021] In one embodiment, the result comparison module includes:
[0022] The first input terminal of the result comparison module is connected to the output terminal of the frequency test module, the second input terminal of the result comparison module is connected to the output terminal of the pulse count module, and the third input terminal of the result comparison module is connected to the second output terminal of the pulse source switching control module. The result comparison module is used to control the pulse selection module to select the corresponding pulse source through the pulse switching control module in the pulse source switching control module.
[0023] In one embodiment, the pulse source switching control module adopts a first preset communication protocol.
[0024] A second aspect of this disclosure provides a clock circuit diagnostic method, applicable to any clock circuit provided in the first aspect of this disclosure, comprising:
[0025] The target pulse is determined from the first pulse and the second pulse, wherein the first pulse is used to indicate the pulse generated by the first pulse source and the second pulse is used to indicate the pulse generated by the second pulse source.
[0026] The target pulse is first detected to obtain the detection result corresponding to the target pulse;
[0027] Based on the detection results corresponding to the target pulse, it is determined whether the pulse source corresponding to the target pulse is invalid.
[0028] In one embodiment, after determining whether the pulse source corresponding to the target pulse is faulty based on the detection result corresponding to the target pulse, the method further includes:
[0029] In response to the failure of the pulse source corresponding to the target pulse, the pulse source is switched by the pulse source switching control module.
[0030] In one embodiment, switching the pulse source via the pulse source switching control module includes:
[0031] Based on the comparison result of the result comparison module and the pulse configuration information in the pulse source switching control module, the pulse selection module is controlled by the pulse switching control module to select the corresponding pulse source.
[0032] A third aspect of this disclosure provides a chip including any of the clock circuits provided in the first aspect of this disclosure.
[0033] In summary, this disclosure proposes a clock circuit with self-diagnostic function, a clock circuit diagnostic method, and a chip. The clock circuit includes a pulse generation module, a pulse selection module, a pulse self-test module, and a result comparison module. The first input terminal of the pulse generation module is connected to a first pulse source, and the second input terminal of the pulse generation module is connected to a second pulse source. The input terminal of the pulse selection module is connected to the output terminal of the pulse generation module, and the pulse selection module is used to select a target pulse. The input terminal of the pulse self-test module is connected to the output terminal of the pulse selection module, and the pulse self-test module is used to test the target pulse. The input terminal of the result comparison module is connected to the output terminal of the pulse self-test module, and the result comparison module is used to determine whether the pulse source corresponding to the target pulse is faulty.
[0034] The clock circuit provided in this disclosure detects clock pulses by adding a pulse self-test module and obtains the detection results. In the event of a failure in the full-speed test, it can detect whether the pulse source corresponding to the target pulse is faulty, and thus determine whether the on-chip clock control module in the circuit can work normally.
[0035] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.
[0037] Figure 1 This is a schematic diagram of the full-speed test circuit provided in an embodiment of the present disclosure;
[0038] Figure 2 A schematic diagram of the clock circuit provided in an embodiment of this disclosure;
[0039] Figure 3 This is a schematic diagram of the structure of the pulse self-test module 103 provided in an embodiment of this disclosure;
[0040] Figure 4 This is a schematic diagram of the structure of the pulse source switching control module provided in an embodiment of this disclosure;
[0041] Figure 5 This is a schematic flowchart of a clock circuit diagnostic method provided in an embodiment of the present disclosure. Detailed Implementation
[0042] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.
[0043] In related technologies, the fully automated structured testing process for chips involves full-speed testing based on a scan chain. For example... Figure 1As shown, the system includes a functional clock, on-chip clock control, DFFs (D flip-flops), and combinational logic. The functional clock is the original clock signal during normal chip operation. Multiple pulses in the diagram represent continuous clock signals. The on-chip clock control receives the functional clock and generates a specific period and number of test clock pulses according to test requirements, as shown by the three output pulses in the diagram. The DFF is a timing unit that receives the test clock pulses and drives subsequent logic circuits. Combinational logic refers to the logic operation circuits within the chip. The flip-flops on the right are used to capture the output results of the combinational logic, completing the sampling of test data. Specifically, the functional clock provides the basic clock source; the on-chip clock control module trims or adjusts the functional clock, outputting clock pulses that meet test requirements. The test clock drives the D flip-flops, controlling the timing of the combinational logic operations. Finally, the results are collected through subsequent flip-flops to complete the test of the chip's logic function.
[0044] Therefore, it is necessary to design an on-chip clock generation circuit to generate several test clock pulses for full-speed testing based on the functional clock. The clock period of the test clock pulses needs to be consistent with the functional clock, so that the high-frequency timing path for testing the logic function in fully automatic testing can meet the functional requirements.
[0045] The above-mentioned full-speed test circuit structure has certain drawbacks. The full-speed test circuit can only infer whether its function is normal based on the final test results and the diagnostic results of the vector generation tool. When the full-speed test fails, there is no debugging method to completely eliminate the failure of the on-chip clock module. Specifically, the failure of the full-speed test may be caused by the failure of the on-chip clock module or by the failure of any data trigger in the scan chain.
[0046] To address the issue in related technologies where the on-chip clock control module cannot be detected as working properly when the full-speed test fails, the clock circuit provided in this disclosure adds a pulse self-test module to detect the clock pulse and obtain the detection result. This allows the circuit to detect whether the pulse source corresponding to the target pulse is faulty when the full-speed test fails, thereby determining whether the on-chip clock control module in the circuit can work properly.
[0047] like Figure 2 As shown, Figure 2 A schematic diagram of the clock circuit provided in an embodiment of this disclosure.
[0048] The clock circuit provided in this embodiment includes a pulse generation module 101, a pulse selection module 102, a pulse self-test module 103, and a result comparison module 104. The first input terminal of the pulse generation module 101 is connected to a first pulse source, and the second input terminal of the pulse generation module 101 is connected to a second pulse source. The input terminal of the pulse selection module 102 is connected to the output terminal of the pulse generation module 101, and the pulse selection module 102 is used to select a target pulse. The input terminal of the pulse self-test module 103 is connected to the output terminal of the pulse selection module 102, and the pulse self-test module 103 is used to test the target pulse. The input terminal of the result comparison module 104 is connected to the output terminal of the pulse self-test module 103, and the result comparison module 104 is used to determine whether the pulse source corresponding to the target pulse is faulty.
[0049] In one embodiment, the pulse generation module 101 is used to generate pulses.
[0050] In one embodiment, to avoid the inability to provide test clock pulses for full-speed testing after a single pulse source fails, the pulse generation module 101 described in this application may have at least two pulse sources. Preferably, this application has two pulse sources: a functional clock and an external backup test clock. The functional clock refers to the clock signal used to synchronize various logic modules and data processing units in the normal operating mode of the chip, which can ensure that each part inside the chip can correctly execute tasks according to a predetermined timing sequence. This functional clock usually refers to the on-chip clock module. The external backup test clock refers to a backup clock signal used to replace the functional clock signal when the functional clock fails. This backup clock usually comes from inside the chip outside the on-chip clock module, specifically from other on-chip clock generation circuits that have not failed.
[0051] In one embodiment, the first pulse source can be either the aforementioned functional clock or an external backup test clock, such as the first pulse source being the functional clock.
[0052] In one embodiment, the second pulse source can be either the functional clock or the external backup test clock. For example, when the first pulse source is the functional clock, the second pulse source is the external backup test clock; when the first pulse source is the external backup test clock, the second pulse source is the functional clock.
[0053] In one embodiment, the pulse selection module 102 is used to select a target pulse from the pulses generated by the pulse generation module 101.
[0054] In one embodiment, a pulse selection control command can be used to control the pulse selection module 102 to select the pulse corresponding to the pulse selection control command as the target pulse.
[0055] In one embodiment, the pulse self-test module 103 is used to detect the target pulse and obtain the detection result corresponding to the target pulse.
[0056] In one embodiment, the detection result corresponding to the target pulse can be directly output to the outside of the chip for observation through the Joint Test Action Group (JTAG) network to obtain the test result. The JTAG network is used to debug and test the hardware interface standard of the chip. The pins of the JTAG network allow the test device to communicate with the test logic inside the chip through a standardized interface. The outside of the chip refers to the test device, test fixture, computer or other control system.
[0057] In one embodiment, the detection result corresponding to the target pulse can also be input into the result comparison module 104. The result comparison module 104 directly obtains the test result by comparing the detection result corresponding to the target pulse and the pulse configuration information. The pulse configuration information refers to the preset pulse information, which includes at least pulse frequency information and pulse number information.
[0058] Based on this, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of the pulse self-test module 103 provided in an embodiment of this disclosure. The pulse self-test module 103 includes: a frequency test module 1031 and a pulse count module 1032; the input terminal of the frequency test module 1031 is connected to the output terminal of the pulse selection module 102, and the frequency test module 1031 is used to test the frequency of the target pulse; the input terminal of the pulse count module 1032 is connected to the output terminal of the pulse selection module 102, and the pulse count module 1032 is used to calculate the number of the target pulses.
[0059] In one embodiment, the target pulse is detected by the frequency test module 1031 to obtain the actual frequency of the target pulse. Then, the actual frequency of the target pulse is output to the outside of the chip through the JTAG network for observation to determine whether the pulse source corresponding to the target pulse is faulty.
[0060] In one embodiment, the target pulse is detected by the pulse count module 1032 to obtain the pulse count of the target pulse. Then, the actual pulse count of the target pulse is output to the outside of the chip for observation through the JTAG network to help determine whether the pulse source corresponding to the target pulse is faulty.
[0061] In one embodiment, the actual frequency and pulse count of the acquired target pulse can also be input into the result comparison module 104 and compared with the pulse frequency and pulse count in the pulse configuration information to determine whether the clock circuit is normal.
[0062] In one embodiment, if the actual frequency of the target pulse is the same as the pulse frequency in the pulse configuration information, and the number of pulses of the target pulse is also the same as the number of pulses in the pulse configuration information, then the clock circuit is considered to be functioning normally.
[0063] In one embodiment, if the actual frequency of the target pulse is different from the pulse frequency in the pulse configuration information, and the number of pulses of the target pulse is also different from the number of pulses in the pulse configuration information, then the clock circuit is considered to be malfunctioning.
[0064] In one embodiment, if the actual frequency of the target pulse is different from the pulse frequency in the pulse configuration information, or if the number of pulses of the target pulse is different from the number of pulses in the pulse configuration information, then it can be determined whether the clock circuit function is faulty according to specific requirements.
[0065] In one embodiment, the pulse self-test module 103 may further include a pulse phase test module for detecting the phase of the target pulse.
[0066] In one embodiment, in order to enable switching to an external backup test clock to complete the full-speed test when the on-chip functional clock fails, the clock circuit further includes a pulse source switching control module;
[0067] The input terminal of the pulse source switching control module is connected to the output terminal of the result comparison module, and the first output terminal of the pulse source switching control module is connected to the pulse selection input terminal of the pulse selection module. The pulse source switching control module is used to switch the pulse source to the first pulse source or to the second pulse source.
[0068] In one embodiment, during the full-speed test, after the clock self-test vector is tested by the Automatic Test Equipment (ATE), if the test passes, it indicates that the on-chip functional clock is normal, and the aforementioned clock self-test vector is directly used to complete the subsequent Automatic Test Pattern Generation (ATPG) test; if the test fails, it indicates that the on-chip functional clock is faulty, and an external backup test clock is used as the test clock to regenerate the ATPG test vector to complete the subsequent ATPG test. The clock self-test vector is generated by the test vector generation tool.
[0069] In one embodiment, by adding a pulse source switching control module, when the on-chip functional clock fails, the pulse source can be switched to an external backup test clock to complete the full-speed test, thereby improving the diagnostic capability of the full-speed test and further improving the yield of the chip.
[0070] In one embodiment, such as Figure 4 As shown, Figure 4 A schematic diagram of the pulse source switching control module provided in an embodiment of this disclosure. The pulse source switching control module includes:
[0071] Pulse switching control module 1051, pulse number configuration module 1052, and pulse frequency configuration module 1053;
[0072] The pulse switching control module 1051 is used to control the pulse selection module 102 to select the corresponding pulse source;
[0073] The pulse number configuration module 1052 is used to configure the number of target pulses;
[0074] The pulse frequency configuration module 1053 is used to configure the frequency value of the target pulse.
[0075] In one embodiment, the output terminal of the pulse switching control module 1051 is connected to the control signal input terminal of the pulse selection module 102.
[0076] In one embodiment, the pulse switching control module 1051 controls the pulse selection module 102 to select and switch the corresponding pulse source through a control signal.
[0077] In one embodiment, the number of target pulses configured by the pulse number configuration module 1052 and the frequency value of the target pulses configured by the pulse frequency configuration module 1053 can be used to compare with the detection results of the pulse self-test module 103, and can also be used to select and switch pulses in the pulse selection module 102.
[0078] In one embodiment, the result comparison module 104 includes:
[0079] The first input terminal of the result comparison module 104 is connected to the output terminal of the frequency test module 1031, the second input terminal of the result comparison module 104 is connected to the output terminal of the pulse count module 1032, and the third input terminal of the result comparison module 104 is connected to the second output terminal of the pulse source switching control module. The result comparison module 104 is used to control the pulse selection module 102 to select the corresponding pulse source through the pulse switching control module 1051 in the pulse source switching control module.
[0080] In one embodiment, the third input terminal of the result comparison module 104 is also the output terminal of the result comparison module 104.
[0081] In one embodiment, the second output terminal of the pulse source switching control module is also the input terminal of the pulse source switching control module.
[0082] In one embodiment, the result comparison module 104 is used to compare the pulse configuration information with the detection results of the pulse frequency and the pulse number.
[0083] In one embodiment, the comparison result in the result comparison module 104 can also be used to select a pulse source. Specifically, the selection and switching of the pulse source can be achieved based on the comparison result and pulse configuration information. If the comparison result indicates that the functional clock has failed, the functional clock is switched to an external backup test clock based on the pulse configuration information.
[0084] In one embodiment, the pulse source switching control module adopts a first preset communication protocol.
[0085] In one embodiment, the first preset communication protocol may be the JTAG1687 protocol, the JTAG1149 protocol, or other communication protocols. This disclosure does not limit the specific communication protocol used. Preferably, the first preset communication protocol is the JTAG1687 protocol. The JTAG1687 protocol is a standard used for integrated circuit testing and debugging, extending the functionality of the traditional JTAG interface and providing a higher level of abstraction and management functions. Specifically, control commands can be sent via the JTAG1687 protocol to instruct the pulse source switching control module to switch the pulse source. The JTAG1687 protocol can also monitor the status of the functional clock; if the functional clock fails, a control command is sent to switch the clock source.
[0086] In one embodiment, by employing a first preset communication protocol, the pulse source switching control module can manage the switching of the clock source more efficiently and reliably, ensuring the smooth progress of the full-speed test.
[0087] In one embodiment, such as Figure 5 As shown, Figure 5 This is a flowchart illustrating a clock circuit diagnostic method provided in an embodiment of the present disclosure. This method can be applied to fault location during full-speed testing.
[0088] In one embodiment, the clock circuit diagnostic method includes:
[0089] Step 501: Determine the target pulse from the first pulse and the second pulse, wherein the first pulse is used to indicate the pulse generated by the first pulse source and the second pulse is used to indicate the pulse generated by the second pulse source;
[0090] In one embodiment, taking the first pulse source as a functional clock and the second pulse source as an external backup test clock in the aforementioned embodiment as an example, determining the target pulse from the first pulse and the second pulse means determining the target pulse from the first pulse generated by the functional clock and the second pulse generated by the external backup test clock. Preferably, the first pulse generated by the functional clock is usually determined as the target pulse.
[0091] Step 502: Perform a first detection on the target pulse to obtain the detection result corresponding to the target pulse;
[0092] In one embodiment, the first detection includes at least pulse frequency detection and pulse number detection.
[0093] In one embodiment, the actual pulse frequency and pulse number of the target pulse can be obtained by performing a first detection on the target pulse.
[0094] Step 503: Determine whether the pulse source corresponding to the target pulse is invalid based on the detection result corresponding to the target pulse.
[0095] In one embodiment, by comparing the actual pulse frequency and pulse number of the target pulse with the pulse frequency and pulse number in the pulse configuration information, it can be determined whether the pulse source corresponding to the target pulse is faulty. Specifically, if the actual pulse frequency and pulse number of the target pulse are the same as those in the pulse configuration information, it can be determined that the pulse source corresponding to the target pulse is normal; if the actual pulse frequency and pulse number of the target pulse are different from those in the pulse configuration information, it can be determined that the pulse source corresponding to the target pulse is faulty.
[0096] In one embodiment, after determining whether the pulse source corresponding to the target pulse is faulty based on the detection result corresponding to the target pulse, the method further includes:
[0097] In response to the failure of the pulse source corresponding to the target pulse, the pulse source is switched by the pulse source switching control module.
[0098] In one embodiment, the pulse source is switched by the pulse source switching control module. The pulse source can be switched using the control command so. Specifically, when so is 1, the functional clock is selected, and when so is 0, an external backup test clock is selected.
[0099] In one embodiment, taking the pulse source corresponding to the target pulse as the functional clock as an example, in response to the failure of the pulse source corresponding to the target pulse, the functional clock is switched to an external backup test clock through the pulse source switching control module; taking the pulse source corresponding to the target pulse as the external backup test clock as an example, in response to the failure of the pulse source corresponding to the target pulse, the external backup test clock is switched to the functional clock through the pulse source switching control module.
[0100] In one embodiment, taking the pulse source corresponding to the target pulse as the functional clock as an example, in response to the failure of the pulse source corresponding to the target pulse, the pulse source is switched by the pulse source switching control module. When the functional clock fails, an external backup test clock can be used to continue to provide test clock pulses for full-speed testing, thereby improving the diagnostic capability of full-speed testing and further improving the yield of the chip.
[0101] In one embodiment, switching the pulse source via the pulse source switching control module includes:
[0102] Based on the comparison result of the result comparison module and the pulse configuration information in the pulse source switching control module, the pulse selection module is controlled by the pulse switching control module to select the corresponding pulse source.
[0103] In one embodiment, based on the comparison result of the result comparison module and the pulse configuration information in the pulse source switching control module, the pulse source is switched by controlling the pulse switching control module in the pulse source switching control module, thereby improving the diagnostic capability of full-speed testing and further improving the yield of the chip.
[0104] This invention also provides a chip that includes any of the aforementioned clock circuits.
[0105] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0106] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0107] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0108] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0109] In this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0110] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
Claims
1. A clock circuit with self-diagnostic function, characterized in that, It includes a pulse generation module, a pulse selection module, a pulse self-test module, a result comparison module, and a pulse source switching control module; The first input terminal of the pulse generation module is connected to the first pulse source, and the second input terminal of the pulse generation module is connected to the second pulse source. The input terminal of the pulse selection module is connected to the output terminal of the pulse generation module, and the pulse selection module is used to select the target pulse; The input terminal of the pulse self-test module is connected to the output terminal of the pulse selection module, and the pulse self-test module is used to test the target pulse. The input terminal of the result comparison module is connected to the output terminal of the pulse self-test module. The result comparison module is used to determine whether the pulse source corresponding to the target pulse is invalid when the full-speed test fails. The input terminal of the pulse source switching control module is connected to the output terminal of the result comparison module, and the first output terminal of the pulse source switching control module is connected to the pulse selection input terminal of the pulse selection module. The pulse source switching control module is used to switch the pulse source to the first pulse source or the second pulse source according to the comparison result of the result comparison module and the pulse configuration information in the pulse source switching control module.
2. The clock circuit according to claim 1, characterized in that, The pulse self-test module includes: Frequency test module and pulse count module; The input terminal of the frequency testing module is connected to the output terminal of the pulse selection module, and the frequency testing module is used to test the frequency of the target pulse. The input terminal of the pulse count module is connected to the output terminal of the pulse selection module, and the pulse count module is used to calculate the number of target pulses.
3. The clock circuit according to claim 1, characterized in that, The pulse source switching control module includes: Pulse switching control module, pulse number configuration module, and pulse frequency configuration module; The pulse switching control module is used to control the pulse selection module to select the corresponding pulse source; The pulse count configuration module is used to configure the target number of pulses; The pulse frequency configuration module is used to configure the frequency value of the target pulse.
4. The clock circuit according to claim 2, characterized in that, The result comparison module includes: The first input terminal of the result comparison module is connected to the output terminal of the frequency test module, the second input terminal of the result comparison module is connected to the output terminal of the pulse count module, and the third input terminal of the result comparison module is connected to the second output terminal of the pulse source switching control module. The result comparison module is used to control the pulse selection module to select the corresponding pulse source through the pulse switching control module in the pulse source switching control module.
5. The clock circuit according to claim 1, characterized in that, The pulse source switching control module adopts a first preset communication protocol.
6. A clock circuit diagnostic method, applied to the clock circuit according to any one of claims 1 to 5, characterized in that, include: The target pulse is determined from the first pulse and the second pulse, wherein the first pulse is used to indicate the pulse generated by the first pulse source and the second pulse is used to indicate the pulse generated by the second pulse source. The target pulse is first detected to obtain the detection result corresponding to the target pulse; Based on the detection results corresponding to the target pulse, it is determined whether the pulse source corresponding to the target pulse is invalid.
7. The clock circuit diagnostic method according to claim 6, characterized in that, After determining whether the pulse source corresponding to the target pulse is faulty based on the detection result corresponding to the target pulse, the method further includes: In response to the failure of the pulse source corresponding to the target pulse, the pulse source is switched by the pulse source switching control module.
8. The clock circuit diagnostic method according to claim 7, characterized in that, The step of switching the pulse source via the pulse source switching control module includes: Based on the comparison result of the result comparison module and the pulse configuration information in the pulse source switching control module, the pulse selection module is controlled by the pulse switching control module to select the corresponding pulse source.
9. A chip, characterized in that, The clock circuit includes any one of claims 1 to 5.