Method for satellite positioning terminal uplink signal synchronization header expansion and device thereof

Abstract

The embodiment of the application provides a synchronization header expansion method and device for satellite positioning terminal uplink signals, and relates to the technical field of satellite positioning. The method comprises the following steps: obtaining a power amplifier pre-starting time, a code rate of a to-be-sent data segment, an initial phase code chip sequence, and a preset polynomial of a linear feedback shift register; determining a target total code chip quantity according to the power amplifier pre-starting time and the code rate; recursively obtaining a plurality of target code chips according to the preset polynomial of the linear feedback shift register and the initial phase code chip sequence, and recording each target code chip one by one until the number of recorded code chips reaches the target total code chip quantity, thereby obtaining a target code chip sequence; and modulating the target code chip sequence and a preset pseudo-synchronization header to obtain a synchronization header of the to-be-sent data segment. The synchronization header obtained by the method can avoid single-tone interference caused by a single carrier while starting the antenna power amplifier of an open power detection type antenna.

Description

Technical Field

[0001] This application relates to the field of satellite positioning technology, specifically to a method and apparatus for expanding the synchronization header of uplink signals for satellite positioning terminals. Background Technology

[0002] The uplink frequency band of BeiDou RDSS (Radio Determination Satellite Service) is 1610~1625.5MHz. The RF chip modulates the spread spectrum signal onto a high-frequency carrier, which is then amplified and transmitted by the antenna power amplifier. Antennas can be divided into two types based on the power amplifier activation method: power-detection antennas, which actively activate the power amplifier upon detecting a high-power carrier signal; and level-controlled antennas, where the baseband activates the power amplifier by pulling up a dedicated GPIO pin of the antenna power amplifier. The mainstream method used by domestic baseband manufacturers to pre-activate the power amplifier in power-detection antennas involves controlling the RF chip to transmit a single carrier (single tone) at the same frequency as the uplink frequency. When the antenna detects a high-power single carrier, it activates the power amplifier, transmitting the single carrier and the modulated spread spectrum signal to the BeiDou satellite system. Globalstar is a low Earth orbit (LEO) US satellite communication system that primarily provides voice, short message, and low-speed data communication services, covering the globe. The uplink frequency band of GlobalSatellite (1610-1625.5MHz) partially overlaps with the uplink frequency band of BeiDou RDSS (1610-1625.5MHz), resulting in co-channel interference.

[0003] According to Section 5.364 of the ITU Radio Regulations (RR), the 1610-1625.5MHz band is shared by multiple services (BeiDou RDSS, Globalstar, and aviation navigation), requiring that the transmit power in the band not exceed the peak equivalent isotropic radiated power density (EPFD) of -15dB (W / kHz). Therefore, how to eliminate single-tone interference is an important technical problem that urgently needs to be solved and has certain international significance. Summary of the Invention

[0004] The purpose of this application is to provide a method and apparatus for expanding the synchronization header of uplink signals for satellite positioning terminals.

[0005] To achieve the above objectives, the first aspect of this application provides a synchronization header expansion method for uplink signals of a satellite positioning terminal, comprising:

[0006] Obtain the power amplifier pre-start time, the code rate of the data segment to be transmitted, the initial phase chip sequence, and the preset polynomial of the linear feedback shift register;

[0007] The total number of target chips is determined based on the power amplifier pre-start time and code rate.

[0008] Multiple target chips are obtained by recursively deriving the preset polynomial and initial phase chip sequence of the linear feedback shift register, and each target chip is recorded one by one until the number of recorded chips reaches the total number of target chips, thus obtaining the target chip sequence.

[0009] The synchronization header of the data segment to be transmitted is obtained by modulating the target chip sequence and the preset pseudo synchronization header.

[0010] In this embodiment, the process of recursively obtaining multiple target chips based on a preset polynomial of a linear feedback shift register and an initial phase chip sequence includes: determining a first target chip based on the initial phase chip sequence and the preset polynomial; obtaining the least significant bit of the initial phase chip sequence; right-shifting each chip in the initial phase chip sequence to obtain the values ​​of each chip in the updated initial phase chip sequence except for the first chip; determining the value of the first chip based on the least significant bit and the first target chip to obtain the updated initial phase chip, wherein the updated initial phase chip is used to recursively obtain a second target chip.

[0011] In this embodiment of the application, determining the first target chip based on the initial phase chip sequence and the preset polynomial includes: performing an AND operation on the initial phase chip sequence and the preset polynomial to obtain the first chip sequence; and performing an XOR operation on each chip in the first chip sequence to obtain the first target chip.

[0012] In this embodiment of the application, determining the value of the first bit chip based on the least significant bit chip and the first target chip includes: performing an XOR operation on the least significant bit chip and the first target chip to obtain the value of the first bit chip.

[0013] In this embodiment of the application, the synchronization head expansion method further includes: obtaining a preset chip sequence; recursively obtaining multiple preceding chips based on a preset polynomial of a linear feedback shift register and the preset chip sequence, wherein the preceding chip obtained in any recursion is used to update the preset chip sequence required for the next recursion; when the preset chip sequence is an initial phase chip sequence, recursively obtaining multiple target chips based on the preset polynomial of the linear feedback shift register and the initial phase chip sequence, and recording each target chip one by one until the number of recorded chips reaches the total number of target chips to obtain the target chip sequence.

[0014] In this embodiment of the application, the synchronization header expansion method further includes: obtaining the bit width of the linear feedback shift register; determining the total number of chips to be recursively calculated in a single cycle based on the bit width; recursively obtaining multiple target chips based on the preset polynomial and the initial phase chip sequence of the linear feedback shift register, and recording each target chip one by one until the number of recorded chips reaches the total number of target chips. Obtaining the target chip sequence includes: when the number of multiple preceding chips and the total number of target chips are greater than the total number of chips to be recursively calculated in a single cycle, recursively obtaining a first number of target chips based on the preset polynomial and the initial phase chip sequence of the linear feedback shift register, and recording each target chip one by one; recording a second number of preceding chips from front to back in the multiple preceding chips according to the recursion order, wherein the second number of preceding chips is recorded after the first number of target chips, and the second number is the difference between the total number of target chips and the first number.

[0015] In this embodiment of the application, determining the total number of recursive chips per cycle based on the bit width includes: determining the total number of recursive chips per cycle based on the power of the bit width of two.

[0016] In this embodiment of the application, determining the total target chip quantity based on the power amplifier pre-start time and code rate includes: determining the product of the power amplifier pre-start time and code rate as the total target chip quantity.

[0017] A second aspect of this application provides a synchronization header expansion device for uplink signals of a satellite positioning terminal, comprising: a processor configured to execute a synchronization header expansion method for uplink signals of a satellite positioning terminal according to a first aspect of the embodiments of this application.

[0018] A third aspect of this application provides a machine-readable storage medium storing instructions that, when executed by a processor, configure the processor to perform a synchronization header augmentation method for uplink signals of a satellite positioning terminal according to a first aspect of the embodiments of this application.

[0019] Through the above technical solution, the synchronization header expansion method for uplink signals of satellite positioning terminals provided in this application determines the total number of target chips based on the power amplifier pre-start time and the code rate of the data segment to be transmitted, and obtains multiple target chips based on the initial phase chip sequence and the preset polynomial of the linear feedback register. Each target chip is recorded to obtain a target chip sequence in which the number of chips equals the total number of target chips. Thus, the target chip sequence and the preset pseudo synchronization header can be modulated to obtain the synchronization header of the data segment to be transmitted. The synchronization header can turn on the power detection antenna of the satellite positioning terminal, so that the power detection antenna amplifies the uplink signal including the data segment to be transmitted and transmits the uplink signal, thereby eliminating single-tone interference while turning on the antenna power amplifier of the power detection antenna.

[0020] Other features and advantages of the embodiments of this application will be described in detail in the following detailed description section. Attached Figure Description

[0021] The accompanying drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the following detailed description to explain the embodiments of this application, but do not constitute a limitation on the embodiments of this application. In the drawings:

[0022] Figure 1 The illustration shows a flowchart of a synchronization header expansion method for uplink signals of a satellite positioning terminal according to an embodiment of this application;

[0023] Figure 2 The illustration shows a flowchart of another synchronization header expansion method for uplink signals of a satellite positioning terminal according to an embodiment of this application;

[0024] Figure 3 The illustration shows a flowchart of another synchronization header expansion method for uplink signals of a satellite positioning terminal according to an embodiment of this application;

[0025] Figure 4 The diagram illustrates a time-domain signal of an uplink signal using a single carrier as a synchronization header.

[0026] Figure 5 This illustration schematically shows a time-domain signal diagram of the uplink signal of the synchronization header obtained using the synchronization header expansion method for uplink signals of satellite positioning terminals provided in the embodiments of this application.

[0027] Figure 6 The diagram illustrates the internal structure of a computer device according to an embodiment of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for illustration and explanation of the embodiments of this application and are not intended to limit the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0029] It should be noted that if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0030] The acquisition, transmission, storage, use, and processing of data in this application comply with relevant laws and regulations. Furthermore, it should be noted that certain software, components, models, and other existing industry solutions may be mentioned in the embodiments of this application. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this application, and do not imply that the applicant has already used or necessarily used such solutions.

[0031] The theoretical bandwidth of a single carrier is 0 Hz, but in reality, due to factors such as hardware noise, the bandwidth of a single carrier is approximately 1~100 Hz, and the calculated EPFD is approximately -10 (W / kHz), exceeding the ITU standard of -15 (W / kHz). Given that major domestic baseband manufacturers use power-detection antennas, there is an urgent need to propose a technical solution that can enable power-detection antennas and eliminate single-carrier interference.

[0032] Therefore, this application provides a synchronization header expansion method for uplink signals of satellite positioning terminals. During the process of the satellite positioning terminal transmitting uplink signals including data segments to be transmitted, a power detection antenna can be turned on based on the synchronization header generated by this method, so that the satellite positioning terminal can successfully transmit the uplink signal. Moreover, the EPFD of the synchronization header is lower than -15 (W / kHz) as specified by ITU, which can avoid single-carrier interference.

[0033] Figure 1 A schematic flowchart illustrating a synchronization header augmentation method for uplink signals of a satellite positioning terminal according to an embodiment of this application is shown. Figure 1 As shown in one embodiment of this application, a synchronization header expansion method for uplink signals of a satellite positioning terminal is provided. This embodiment mainly illustrates the application of this method to a satellite positioning terminal. The satellite positioning terminal may include user devices with satellite positioning functions such as smartphones, personal computers, vehicle navigation systems, and drones. The synchronization header expansion method for uplink signals of a satellite positioning terminal includes the following steps:

[0034] S102, obtain the power amplifier pre-start time, the code rate of the data segment to be transmitted, the initial phase chip sequence, and the preset polynomial of the linear feedback shift register.

[0035] Specifically, the power amplifier pre-start time refers to the preparation time required for a power-sensing antenna to turn on the power amplifier in advance. The power amplifier pre-start time of a power-sensing antenna is generally fixed, typically within 100ms. The initial phase chip sequence is a pre-acquired chip sequence, and a preset polynomial determines the chips generated by the linear feedback shift register in each iteration.

[0036] S104. Determine the total number of target chips based on the power amplifier pre-start time and code rate;

[0037] S106. Based on the preset polynomial and initial phase chip sequence of the linear feedback shift register, multiple target chips are recursively obtained, and each target chip is recorded one by one until the number of recorded chips reaches the total number of target chips, thus obtaining the target chip sequence.

[0038] S108. Modulate the target chip sequence and the preset pseudo-synchronization header to obtain the synchronization header of the data segment to be transmitted.

[0039] Specifically, the target chip sequence can be modulated with a pre-expanded pseudo-synchronization header consisting of all zeros or all Fs, thereby expanding a baseband signal with the same frequency and bandwidth as the transmitted signal to replace the single-carrier signal and turn on the power amplifier, thus achieving the function of eliminating single-tone interference.

[0040] The synchronization header expansion method for uplink signals of satellite positioning terminals provided in this application determines the total number of target chips based on the power amplifier pre-start time and the code rate of the data segment to be transmitted. Multiple target chips are obtained by recursion based on the initial phase chip sequence and a preset polynomial of the linear feedback register. Each target chip is recorded sequentially to obtain a target chip sequence whose number equals the total number of target chips. This target chip sequence and a preset pseudo-synchronization header are then modulated to obtain the synchronization header for the data segment to be transmitted. This synchronization header can activate the power-sensing antenna of the satellite positioning terminal, enabling the power-sensing antenna to amplify the uplink signal, including the data segment to be transmitted, and transmit the uplink signal. The synchronization header expansion method for uplink signals of satellite positioning terminals provided in this application does not require modification of the baseband chip of the satellite positioning terminal, nor does it require changing the hardware state. It can eliminate single carriers by designing it in software, while enabling the antenna power amplifier (power amplification function) of the power detection antenna. The generated synchronization header, as a spread spectrum signal with the same frequency and bandwidth as the data segment to be transmitted, can meet the ITU-customized EPFD threshold value. Moreover, the synchronization header expansion method for uplink signals of satellite positioning terminals provided in this application does not limit the power amplifier pre-start time. The power amplifier pre-start time can be set in software to meet the preparation time required for the power amplifier of all power detection antennas to be turned on.

[0041] In some embodiments of this application, step S104 includes: determining the product of the power amplifier startup time and the code rate as the target total number of chips.

[0042] Existing uplink signals consist of a single carrier and a spread spectrum baseband signal. The spread spectrum baseband signal is formed by modulating the data segment to be transmitted onto a spreading code. The frame format of the baseband signal begins with a synchronization header. The synchronization header extension method for uplink signals of satellite positioning terminals provided in this application eliminates the single carrier by extending a synchronization header signal to replace the single carrier signal. The number of chips in the extended synchronization header is the same as the target number of chips, thereby obtaining a spread spectrum signal with the same frequency and bandwidth as the data segment to be transmitted.

[0043] See Figure 2 In some embodiments of this application, step S106, which recursively obtains multiple target chips based on the preset polynomial of the linear feedback shift register and the initial phase chip sequence, may include:

[0044] S202. Determine the first target chip based on the initial phase chip sequence and the preset polynomial;

[0045] S204. Obtain the least significant bit of the initial phase chip sequence;

[0046] S206. Shift each chip in the initial phase chip sequence to the right to obtain the values ​​of each chip in the updated initial phase chip sequence except for the first chip.

[0047] S208. Determine the value of the first bit based on the least significant bit and the first target bit to obtain the updated initial phase bit. The updated initial phase bit is then used to recursively obtain the second target bit.

[0048] Figure 2 Any one of the recursion steps S202 to S208 shown can obtain a target chip, namely the first target chip determined according to the initial phase chip sequence and the preset polynomial. While obtaining the first target chip, it is also necessary to prepare for the next recursion. After shifting each chip in the initial phase chip sequence to the right in the above steps, the values ​​of each chip except the first chip can be obtained. The value of the first chip in the updated initial phase chip sequence is determined based on the least significant bit chip of the initial phase chip sequence and the first target chip, thereby obtaining the values ​​of each chip in the updated initial phase chip. The updated initial phase chip is then used for another recursion to obtain the second target chip.

[0049] In some embodiments of this application, determining the first target chip based on the initial phase chip sequence and the preset polynomial may include: performing an AND operation on the initial phase chip sequence and the preset polynomial to obtain a first chip sequence; and performing an XOR operation on each chip in the first chip sequence to obtain the first target chip.

[0050] The preset polynomial reflects which chips in the initial phase chip sequence participate in subsequent processing to obtain the first target chip. Performing a bitwise AND operation between the initial phase chip sequence and the preset polynomial is equivalent to filtering out the chips in the initial phase chip sequence that participate in subsequent processing. These chips that participate in subsequent processing constitute the first chip sequence. The first target chip is obtained by successively performing an XOR operation on each chip in the first chip sequence.

[0051] In some embodiments of this application, the process of determining the value of the first chip in the updated initial phase chip sequence, based on the least significant bit chip and the first target chip, may include: performing an XOR operation on the least significant bit chip and the first target chip to obtain the value of the first chip. Based on the above steps and the right shift of the initial phase chip, the values ​​of each chip in the updated initial phase chip sequence can be determined, thereby determining the updated initial phase chip sequence for recursion of subsequent target chips.

[0052] In some embodiments of this application, the synchronization header expansion method for uplink signals of satellite positioning terminals may further include: obtaining a preset chip sequence; recursively obtaining multiple preceding chips based on a preset polynomial of a linear feedback shift register and the preset chip sequence, wherein the preceding chip obtained in any recursion is used to update the preset chip sequence required for the next recursion; when the preset chip sequence is an initial phase chip sequence, recursively obtaining multiple target chips based on the preset polynomial of the linear feedback shift register and the initial phase chip sequence, and recording each target chip one by one until the number of recorded chips reaches the total number of target chips to obtain the target chip sequence.

[0053] In the above embodiments, the recursion based on a preset polynomial starts with obtaining a preset chip sequence. Each recursion yields a preceding chip, and the preset chip sequence for the next recursion is updated based on the preceding chip. The update method of the preset chip sequence and the recursion method of the preceding chip are similar to the update method of the updated initial phase chip and the recursion method of the target chip described above. Based on the above steps, the recursion is first performed using the preset chip sequence until the updated preset chip sequence is the initial phase chip sequence. Only then is the required target chip recorded. The target chip sequence obtained in this way has a certain degree of confidentiality due to the setting of the initial phase chip sequence, which helps to improve the security of the uplink signal of the satellite positioning terminal.

[0054] In some embodiments of this application, the synchronization header expansion method for uplink signals of satellite positioning terminals may further include: obtaining the bit width of a linear feedback shift register; and determining the total number of recursive chips per cycle based on the bit width.

[0055] Multiple target chips are recursively obtained based on the preset polynomial and initial phase chip sequence of the linear feedback shift register. Each target chip is recorded one by one until the number of recorded chips reaches the total number of target chips, resulting in a target chip sequence including:

[0056] When the number of multiple preceding chips and the total number of target chips are greater than the total number of chips recursively generated in a single cycle, the first number of target chips is obtained by recursion based on the preset polynomial of the linear feedback shift register and the initial phase chip sequence, and the target chips are recorded one by one.

[0057] In a series of pre-chips, a second number of pre-chips are recorded from front to back according to a recursive order. The second number of pre-chips is recorded after the first number of target chips, and the second number is the difference between the total number of target chips and the first number.

[0058] The number of chips in the target chip sequence obtained by the synchronization header expansion method for uplink signals of satellite positioning terminals provided in this application embodiment is limited by the total number of target chips. Since the chip sequence output by the linear feedback shift register is periodic, if the number of multiple preceding chips and the total number of target chips are greater than the total number of chips recursively calculated in a single period, it indicates that some chips in the target chip sequence have already been generated and are preceding chips. Therefore, after recording the first number of target chips, a second number of preceding chips can be recorded from front to back according to their recursive order among the multiple preceding chips. The sum of the first and second numbers is the total number of target chips, thus obtaining the target chip sequence. In the above process, it is not necessary to regenerate the target chips corresponding to the aforementioned second number of preceding chips; instead, the previously generated second number of preceding chips are directly recorded. This controls the computational load required for the target chip sequence within the computational load required to determine the total number of chips recursively calculated in a single period, avoiding an unlimited increase in the computational load of the target chip sequence due to a large total number of target chips. This controls and reduces the computational load and time required to obtain the target chip sequence.

[0059] Generally, the total number of recursive chips in a single cycle of a linear feedback shift register is much larger than the total number of target chips. However, in some embodiments, the total number of recursive chips in a single cycle may be less than the total number of target chips. In this case, the second quantity is still the difference between the total number of target chips and the first quantity, and the second quantity of preceding chips includes at least the preceding chips and target chips within the single-cycle recursive chips. As an example, if the total number of recursive chips in a single cycle is less than the total number of target chips, and the total number of target chips is 1.5 times the total number of recursive chips in a single cycle, and half of the total number of recursive chips in a single cycle consists of preceding chips and the other half consists of target chips, the target chip sequence may, in order, include: the first quantity of target chips, all the preceding chips in the total number of recursive chips in a single cycle, and the first quantity of target chips.

[0060] In some embodiments of this application, determining the total number of recursive chips per cycle based on the bit width includes: determining the total number of recursive chips per cycle based on two powers of the bit width.

[0061] The bit width of a linear feedback shift register corresponds to the order of magnitude of a binary number. Increasing the bit width by one increases the order of magnitude of the binary number by one. Therefore, the bit width can be taken as a power of two, and the total number of chips per cycle can be determined based on the power of the bit width.

[0062] In some embodiments of this application, determining the target total number of chips based on the power amplifier pre-start time and code rate includes: determining the product of the power amplifier pre-start time and code rate as the target total number of chips.

[0063] See below. Figure 3 The following example illustrates the synchronization header expansion method for uplink signals of satellite positioning terminals provided in this application:

[0064] S302, Obtain the power amplifier pre-start time, the code rate of the data segment to be transmitted, the initial phase chip sequence, the preset polynomial and bit width of the linear feedback shift register, and the preset chip sequence;

[0065] S304. Determine the total number of target chips based on the power amplifier pre-start time and code rate, and determine the total number of chips per cycle based on the bit width.

[0066] S306. Multiple pre-chips are obtained by recursion based on the preset polynomial and preset chip sequence of the linear feedback shift register. The pre-chip obtained in any one recursion is used to update the preset chip sequence required for the next recursion.

[0067] S308. When the preset chip sequence is the initial phase chip sequence, and the number of multiple preceding chips and the total number of target chips are greater than the total number of chips recursively calculated in a single cycle, the first number of target chips is obtained by recursion based on the preset polynomial of the linear feedback shift register and the initial phase chip sequence, and the target chips are recorded one by one.

[0068] For the recursion and recording of the target chip, please refer to Figure 2 Steps S202 to S208 are shown;

[0069] S310. Record a second number of pre-chips from front to back in a recursive order among multiple pre-chips, wherein the second number of pre-chips is recorded after the first number of target chips, and the second number is the difference between the total number of target chips and the first number.

[0070] The following is a peak equivalent isotropic radiated power density (EPFD) test of the synchronization header obtained by the synchronization header expansion method for uplink signals of satellite positioning terminals provided in the embodiments of this application. Assume transmit power Ptx = 10 dBW, transmit bandwidth deltaF = 8.16 MHz, antenna gain Gtx = 0 dBi, and feeder loss Lfeed = 0 dBi.

[0071] Step 1: Calculate EIRP (Equivalent Isotropic Radiated Power):

[0072] EIRP=Ptx+Gtx-Lfeed=10dbW+0dbi-0dbi=10dbW;

[0073] Step 2: Calculate EPFD (Equivalent Isotropic Radiated Power Density):

[0074] EPFD is the EIRP per unit bandwidth, EPFD = EIRP - 10log(deltaF); where deltaF = 8.16 * 1e6 Hz.

[0075] Calculate the logarithmic term within the bandwidth: 10log(deltaF) = 10log(8.16*1e6) = 69.1dB; Therefore: EPFD = 10dBW - 69.1dB = -59.1dB (W / Hz);

[0076] Step 3: Convert to commonly used ITU units (e.g., dB(W / 4kHz)):

[0077] EPFD(4kHZ)=EPHD(HZ)+10log(4000)=-59.1+36=-23.1dB(W / 4kHZ).

[0078] The results above show that the EPFD is -23.1dB, which is less than the ITU requirement of -15dB (W / 4kHz), and meets the standard.

[0079] like Figure 4 A schematic diagram of the time domain signal of an uplink signal using a single carrier as the synchronization header is shown. Figure 5 A schematic diagram of the time domain signal of the uplink signal of the synchronization header is shown, obtained using the synchronization header expansion method for uplink signals of satellite positioning terminals provided in the embodiments of this application.

[0080] from Figure 4 As can be seen, between the power amplifier not being turned on and the data segment, there is a high-frequency sinusoidal narrowband single-tone signal. This single-tone signal is the single carrier used to turn on the antenna power amplifier. The data segment is a segment of irregular broadband spread spectrum signal that matches the modulation pseudocode and message.

[0081] from Figure 5 As can be seen, there is no single-tone signal between the power amplifier not being turned on and the data segment. Instead, there is a pseudo-spread spectrum signal with the same frequency and bandwidth as the effective data segment. This small pseudo-spread spectrum signal is the synchronization head obtained by using the synchronization head expansion method for uplink signals of satellite positioning terminals provided in the embodiments of this application, which is used to turn on the antenna power amplifier.

[0082] It should be understood that although the steps in the flowcharts of the embodiments of this application are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0083] This application provides a synchronization header expansion device for uplink signals of a satellite positioning terminal. The synchronization header expansion device includes a processor configured to execute the synchronization header expansion method for uplink signals of a satellite positioning terminal provided in this application.

[0084] This application provides a machine-readable storage medium storing instructions that, when executed by a processor, configure the processor to perform the synchronization header expansion method for uplink signals of a satellite positioning terminal provided in this application.

[0085] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 6 As shown in the figure, the computer device includes a processor A01, a network interface A02, a display screen A04, an input device A05, and a memory (not shown) connected via a system bus. The processor A01 provides computing and control capabilities. The memory includes internal memory A03 and a non-volatile storage medium A06. The non-volatile storage medium A06 stores an operating system B01 and a computer program B02. The internal memory A03 provides an environment for the operation of the operating system B01 and the computer program B02 stored in the non-volatile storage medium A06. The network interface A02 is used for communication with external terminals via a network connection. When the computer program is executed by the processor A01, it implements a synchronization header expansion method for uplink signals of satellite positioning terminals. The display screen A04 can be a liquid crystal display (LCD) or an e-ink display. The input device A05 can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.

[0086] Those skilled in the art will understand that Figure 6The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0087] In one embodiment, the synchronization header expansion device for uplink signals of a satellite positioning terminal provided in this application can be implemented as a computer program, which can be implemented in the form of, for example... Figure 6 The computer device shown operates on this device. The computer device's memory can store various program modules that constitute the synchronization header expansion device for uplink signals of a satellite positioning terminal. The computer program, composed of these program modules, causes the processor to execute the steps in the synchronization header expansion method for uplink signals of a satellite positioning terminal described in the various embodiments of this application.

[0088] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0089] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0090] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0091] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0092] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0093] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0094] Computer-readable media include both permanent and non-permanent, removable and non-removable media, which can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0095] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0096] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for expanding the synchronization header of uplink signals in a satellite positioning terminal, characterized in that, include: Obtain the power amplifier pre-start time, the code rate of the data segment to be transmitted, the initial phase chip sequence, and the preset polynomial of the linear feedback shift register; The total number of target chips is determined based on the power amplifier pre-start time and the code rate; Multiple target chips are recursively obtained based on the preset polynomial of the linear feedback shift register and the initial phase chip sequence, and each target chip is recorded one by one until the number of recorded chips reaches the total number of target chips, thus obtaining the target chip sequence. The synchronization header of the data segment to be transmitted is obtained by modulating the target chip sequence and the preset pseudo synchronization header; The step of recursively obtaining multiple target chips based on the preset polynomial of the linear feedback shift register and the initial phase chip sequence includes: The first target chip is determined based on the initial phase chip sequence and the preset polynomial; Obtain the least significant bit of the initial phase chip sequence; Shift each chip in the initial phase chip sequence to the right to obtain the values ​​of each chip in the updated initial phase chip sequence except for the first chip. The value of the first bit is determined based on the least significant bit and the first target bit to obtain the updated initial phase bit, wherein the updated initial phase bit is used to recursively obtain the second target bit. The step of determining the first target chip based on the initial phase chip sequence and the preset polynomial includes: Perform a bitwise AND operation between the initial phase chip sequence and the preset polynomial to obtain the first chip sequence; The first target chip is obtained by sequentially XORing each chip in the first chip sequence. The target chip sequence is modulated with a pseudo-synchronization header consisting of all zeros or all Fs to obtain a baseband signal with the same frequency and bandwidth as the transmitted signal, which serves as the synchronization header. The preset polynomial is used to reflect the chips in the initial phase chip sequence that participate in subsequent processing, so as to obtain the first target chip.

2. The synchronization head expansion method according to claim 1, characterized in that, Determining the value of the first bit chip based on the least significant bit chip and the first target chip includes: The least significant bit and the first target bit are XORed to obtain the value of the first bit.

3. The synchronization head expansion method according to claim 1, characterized in that, The synchronization head expansion method further includes: Obtain the preset chip sequence; Multiple preceding chips are recursively obtained based on the preset polynomial of the linear feedback shift register and the preset chip sequence, wherein the preceding chip obtained in any one recursion is used to update the preset chip sequence required for the next recursion. When the preset chip sequence is the initial phase chip sequence, multiple target chips are recursively obtained according to the preset polynomial of the linear feedback shift register and the initial phase chip sequence, and each target chip is recorded one by one until the number of recorded chips reaches the total number of target chips to obtain the target chip sequence.

4. The synchronization head expansion method according to claim 3, characterized in that, The synchronization head expansion method further includes: Obtain the bit width of the linear feedback shift register; The total number of recursive chips per cycle is determined based on the bit width; The step of recursively obtaining multiple target chips based on the preset polynomial of the linear feedback shift register and the initial phase chip sequence, and recording each target chip one by one until the number of recorded chips reaches the total number of target chips to obtain the target chip sequence includes: When the number of the multiple preceding chips and the total number of target chips are greater than the total number of chips in a single cycle, a first number of target chips are obtained by recursion based on the preset polynomial of the linear feedback shift register and the initial phase chip sequence, and the target chips are recorded one by one. In the plurality of preceding chips, a second number of preceding chips are recorded from front to back according to a recursive order, wherein the second number of preceding chips is recorded after the first number of target chips, and the second number is the difference between the total number of target chips and the first number.

5. The synchronization head expansion method according to claim 4, characterized in that, The step of determining the total number of recursive chips per single cycle based on the bit width includes: The total number of single-cycle recursive chips is determined by the power of the bit width described in point 2.

6. The synchronization head expansion method according to claim 1, characterized in that, Determining the total target chip count based on the power amplifier pre-start time and the code rate includes: The product of the power amplifier pre-start time and the code rate is determined as the total target number of chips.

7. A synchronization header expansion device for uplink signals of a satellite positioning terminal, characterized in that, The synchronization head expansion device includes a processor configured to execute the synchronization head expansion method for uplink signals of a satellite positioning terminal according to any one of claims 1 to 6.

8. A machine-readable storage medium storing instructions thereon, characterized in that, When executed by a processor, this instruction causes the processor to be configured to perform the synchronization header augmentation method for uplink signals of a satellite positioning terminal according to any one of claims 1 to 6.

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