Power supply IC with good waterproof effect

Abstract

The invention discloses a power supply IC with a good waterproof effect, and belongs to the technical field of power supply management integrated circuits, the power supply IC comprises a packaging shell, a chip, a pin and a waterproof assembly, the chip is arranged in the packaging shell, one end of the pin is electrically connected with the chip, the other end of the pin extends out of the packaging shell, the waterproof assembly comprises a composite passivation layer covering the surface of the chip, and the composite passivation layer covers the surface of the chip. The composite passivation layer is formed by sequentially overlapping a silicon oxide layer and a silicon nitride layer, waterproof sealant is filled among the chip, the pin and the packaging shell, a sealing ring is arranged outside the pin, the sealing ring is in interference fit with the packaging shell, and the outer surface of the packaging shell is coated with a hydrophobic coating. The power source IC with the good waterproof effect can solve the problems that an existing power source IC is prone to failure in waterproof performance, large in size and high in cost, and can be widely applied to waterproof requirement scenes such as outdoors and wearing.

Description

Technical Field

[0001] This invention belongs to the field of power management integrated circuit technology, and specifically relates to a power IC with good waterproof performance. Background Technology

[0002] Power ICs are the "energy center" of electronic devices, responsible for core functions such as voltage conversion, current control, and power protection. Their operational stability directly determines the reliability of electronic devices. With the expansion of electronic device applications, scenarios such as outdoor monitoring equipment (e.g., weather sensors, outdoor cameras), wearable devices (e.g., waterproof watches, fitness trackers), and smart home outdoor components (e.g., waterproof lamps, outdoor charging stations) place stringent requirements on the waterproof performance of power ICs. They must withstand long-term exposure to humid environments, rain immersion, and condensation to prevent moisture infiltration that could lead to short circuits, performance degradation, or complete failure.

[0003] Some existing power ICs rely solely on a single structure consisting of a package housing and a waterproof adhesive coating. However, when the waterproof adhesive (such as ordinary epoxy resin) is subjected to high and low temperature cycling (-40℃ to 85℃) for a long time, it is prone to cracking and delamination due to thermal aging. Furthermore, micro-gaps can easily form at the interface between the adhesive layer and the IC chip and pins, allowing moisture to seep into the IC and thus affecting the waterproof performance of the power IC. Summary of the Invention

[0004] The purpose of this invention is to provide a power IC with good waterproof performance, so as to solve the problem that some existing power ICs with a single waterproof structure are prone to failure as mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a power IC with good waterproof performance, comprising a package housing, a chip, pins, and a waterproof component. The chip is disposed within the package housing. One end of the pin is electrically connected to the chip, and the other end extends out of the package housing. The waterproof component includes a composite passivation layer covering the surface of the chip. The composite passivation layer is formed by sequentially stacking a silicon oxide layer and a silicon nitride layer. Waterproof sealant is filled between the chip, the pins, and the package housing. A sealing ring is provided at the contact position between the pins and the package housing. The sealing ring is interference-fitted with the package housing. The outer surface of the package housing is coated with a hydrophobic coating.

[0006] In a further embodiment, a ceramic substrate is fixed to the bottom wall of the inner cavity of the packaging shell, the chip is fixed on the ceramic substrate, and waterproof sealant is also filled between the ceramic substrate and the packaging shell.

[0007] In a further embodiment, the pin surface is sequentially plated with a nickel layer and a gold layer. The nickel layer is directly plated on the metal substrate surface of the pin, and the gold layer covers the nickel layer surface and extends into the package housing and contacts the waterproof sealant.

[0008] In a further embodiment, the encapsulation housing is made of PPS plastic, and the edges of the encapsulation housing are provided with a chamfered structure of 45° to 60°.

[0009] In a further embodiment, the hydrophobic coating is a polytetrafluoroethylene coating with a thickness of 8μm to 12μm and a water contact angle ≥110°.

[0010] In a further embodiment, the thickness of the silicon oxide layer in the composite passivation layer is 200 nm to 400 nm, and the thickness of the silicon nitride layer is 400 nm to 600 nm.

[0011] In a further embodiment, the waterproof sealant is a modified epoxy resin sealant, which comprises: 60wt% to 70wt% epoxy resin matrix, 8wt% to 12wt% nano-silica filler, 2wt% to 3wt% silane coupling agent, and 15wt% to 25wt% curing agent, wherein the particle size of the nano-silica filler is 40nm to 60nm.

[0012] The technical effects and advantages of this invention are as follows:

[0013] This highly waterproof power IC employs a full-link waterproof design consisting of a hydrophobic coating, a sealing ring, waterproof sealant, and a composite passivation layer. This forms a closed loop from external blocking to internal protection. The hydrophobic coating reduces moisture adhesion, the sealing ring eliminates pin gaps, the modified epoxy resin sealant resists heat aging, and the composite passivation layer provides dense protection for the chip, completely solving the problem of easy cracking and water vapor leakage in single waterproof structures.

[0014] The encapsulation shell is made of PPS plastic and paired with a thin ceramic substrate. There is no need for complex and large waterproof components. The process adopts mature technologies such as PECVD and vacuum infusion, which not only controls the overall volume, but also avoids high-cost special structures, balancing economy and miniaturization, and is suitable for wearable devices and other scenarios that are sensitive to size.

[0015] The nickel-gold plating on the pins enhances corrosion resistance, and the modified sealant containing nano-silica filler strengthens the structure. The entire component can withstand long-term exposure to humid, rain-soaked, and condensation environments, making it widely applicable in outdoor monitoring equipment, waterproof watches, outdoor charging stations, and other scenarios. It ensures the stability of the power IC's core functions such as voltage conversion and current control. This highly waterproof power IC solves the problems of existing power ICs being prone to waterproofing failures, having large size, and high cost, and can be widely used in outdoor, wearable, and other waterproof applications. Attached Figure Description

[0016] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of the present invention;

[0018] Figure 2 This is a schematic diagram of the structure of the present invention in a cut-out state;

[0019] Figure 3 For the present invention Figure 2 Enlarged view of point A in the middle;

[0020] Figure 4 For the present invention Figure 2 Enlarged view of point B in the middle.

[0021] In the diagram: 1. Package housing; 2. Ceramic substrate; 3. Chip; 4. Silicon oxide layer; 5. Silicon nitride layer; 6. Waterproof sealant; 7. Lead; 8. Sealing ring; 9. Nickel layer; 10. Gold layer; 11. Hydrophobic coating. Detailed Implementation

[0022] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0023] Unless otherwise defined, the directions mentioned herein, such as up, down, left, right, front, back, inside, and outside, are based on the directions shown in the figures of this invention, and are explained here together.

[0024] This invention provides, for example Figure 1-4The power IC shown includes a package housing 1, a chip 3, pins 7, and a waterproof component. The package housing 1 is made of PPS plastic and has a chamfered edge of 45° to 60°. The chip 3 is disposed inside the package housing 1. A ceramic substrate 2 is fixed to the bottom wall of the inner cavity of the package housing 1. The chip 3 is fixed on the ceramic substrate 2. Waterproof sealant 6 is filled between the ceramic substrate 2 and the package housing 1. One end of the pin 7 is electrically connected to the chip 3, and the other end extends out of the package housing 1. The waterproof component includes a composite passivation layer covering the surface of the chip 3. The composite passivation layer is formed by sequentially stacking a silicon oxide layer 4 and a silicon nitride layer 5. The silicon oxide layer 4 has a thickness of 200nm to 400nm and is prepared by plasma-enhanced chemical vapor deposition (PECVD) to fill micro-defects on the surface of the chip 3. The silicon nitride layer 5 has a thickness of 400nm to 600nm and is also prepared by PECVD. Its density is better than that of the silicon oxide layer 4 and can prevent water vapor from contacting the active area of ​​the chip 3.

[0025] A waterproof sealant 6 is filled between chip 3, pin 7 and package housing 1. The waterproof sealant 6 is a modified epoxy resin sealant, whose components include: epoxy resin matrix (60wt%~70wt%), nano silica filler (8wt%~12wt%, particle size 40nm~60nm), silane coupling agent (2wt%~3wt%), and curing agent (15wt%~25wt%). Vacuum potting process (vacuum degree -0.095MPa~-0.1MPa) is used during filling to eliminate air bubbles in the gap and prevent air bubbles from becoming water vapor channels. After potting, it is cured at 120℃±5℃ for 2h±0.5h to ensure that the waterproof sealant 6 is tightly bonded to chip 3, package housing 1 and the root of pin 7 without interface gaps.

[0026] The surface of pin 7 is sequentially plated with a nickel layer 9 and a gold layer 10. The nickel layer 9 is directly plated on the metal substrate surface of pin 7, and the gold layer 10 covers the surface of the nickel layer 9 and extends into the encapsulation housing 1 and contacts the waterproof sealant 6. The nickel layer 9 improves the corrosion resistance of pin 7, and the gold layer 10 enhances the bonding force with the waterproof sealant 6. A sealing ring 8 is provided at the contact position between pin 7 and encapsulation housing 1. The sealing ring 8 is interference-fitted with encapsulation housing 1 (interference amount 0.04mm~0.06mm) to eliminate the fit gap between pin 7 and encapsulation housing 1. The outer surface of encapsulation housing 1 is coated with a hydrophobic coating 11. The hydrophobic coating 11 is a polytetrafluoroethylene coating with a thickness of 8μm~12μm, prepared by electrostatic spraying process. After spraying, it is dried at 80℃±5℃ for 30min±5min. The water contact angle of this coating is ≥110°, which can reduce the adhesion and retention of external moisture on the housing surface and reduce water vapor permeation pressure.

[0027] All standard parts used in this invention can be purchased from the market, and irregular parts can be customized according to the description and drawings. The specific connection methods of each part adopt conventional methods such as bolts, rivets, and welding that are mature in the prior art. The machinery, parts and equipment adopt conventional models in the prior art. In addition, the circuit connection adopts conventional connection methods in the prior art, which will not be described in detail here. The contents not described in detail in this specification belong to the prior art known to those skilled in the art.

[0028] In the description of this invention, it should be understood that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this invention and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0029] Working principle:

[0030] In this waterproof power IC, external moisture first comes into contact with the polytetrafluoroethylene hydrophobic coating 11 on the outer surface of the package housing 1. This coating reduces the adhesion and retention of moisture on the surface of the housing through its high hydrophobicity, thereby reducing the water vapor penetration pressure. The package housing 1 is made of PPS plastic and has chamfered edges to further reduce moisture accumulation and improve the structural stability of the housing. If a small amount of moisture penetrates to the junction of the housing and the pin 7, the sealing ring 8 outside the pin 7 eliminates the gap between the two by interference fit with the package housing 1, thus preventing moisture from continuing to enter.

[0031] After entering the packaging housing 1, the modified epoxy resin waterproof sealant 6 fills the space between the chip 3, pins 7 and the housing, which can tightly bond the components to fill the internal gaps. At the same time, the chip 3 is fixed on the ceramic substrate 2, and the sealant is also filled between the ceramic substrate 2 and the housing to further strengthen the sealing effect. The composite passivation layer (composed of silicon oxide layer 4 and silicon nitride layer 5) covering the surface of the chip 3 directly protects the active area of ​​the chip 3 from the influence of residual moisture. The nickel layer 9 on the surface of the pins 7 improves corrosion resistance, and the gold layer 10 extends into the housing to contact the waterproof sealant 6 to enhance the bonding force. Finally, waterproofing is achieved in all scenarios, ensuring that the power IC operates stably in harsh environments.

[0032] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A power IC with good waterproof effect, comprising a package shell (1), a chip (3), a pin (7) and a waterproof assembly, characterized in that: The chip (3) is arranged in the package shell (1), one end of the pin (7) is electrically connected with the chip (3), and the other end extends out of the package shell (1), the waterproof assembly comprises a composite passivation layer covering the surface of the chip (3), the composite passivation layer is formed by sequentially stacking a silicon oxide layer (4) and a silicon nitride layer (5), the chip (3), the pin (7) and the package shell (1) are filled with waterproof sealant (6), the pin (7) is provided with a sealing ring (8) at a contact position of the pin (7) and the package shell (1), the sealing ring (8) is in interference fit with the package shell (1), and the outer surface of the package shell (1) is coated with a hydrophobic coating (11).

2. The power IC with good waterproof effect according to claim 1, characterized in that: The bottom wall of the inner cavity of the package shell (1) is fixed with a ceramic substrate (2), the chip (3) is fixed on the ceramic substrate (2), and the ceramic substrate (2) and the package shell (1) are also filled with waterproof sealant (6).

3. The power IC with good waterproof effect according to claim 1, characterized in that: The surface of the pin (7) is sequentially plated with a nickel layer (9) and a gold layer (10), the nickel layer (9) is directly plated on the surface of the metal base material of the pin (7), the gold layer (10) covers the surface of the nickel layer (9), and the gold layer (10) extends into the package shell (1) and contacts the waterproof sealant (6).

4. The power IC with good waterproof effect according to claim 1, characterized in that: The material of the package shell (1) is PPS plastic, and the edge of the package shell (1) is provided with a chamfer structure of 45°-60°.

5. The power IC with good waterproof effect according to claim 1, characterized in that: The hydrophobic coating (11) is a polytetrafluoroethylene coating, the thickness is 8-12 microns, and the water contact angle is greater than or equal to 110°.

6. The power IC with good waterproof effect according to claim 1, characterized in that: The thickness of the silicon oxide layer (4) in the composite passivation layer is 200-400 nm, and the thickness of the silicon nitride layer (5) is 400-600 nm.

7. The power IC with good waterproof effect according to claim 1, characterized in that: The waterproof sealant (6) is a modified epoxy resin sealant, and the modified epoxy resin sealant comprises: 60-70 wt% of an epoxy resin matrix, 8-12 wt% of nano-silica filler, 2-3 wt% of a silane coupling agent, and 15-25 wt% of a curing agent, and the particle size of the nano-silica filler is 40-60 nm.

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