Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. An array substrate in the display panel comprises a gate drive circuit, a common bus and a plurality of switch transistors. The switch transistor and the common bus extending in the first direction are located in the first area, and the gate drive circuit is located in the second area; the second region surrounds the first region; the common bus is located on the side, close to the gate drive circuit, of the multiple switching transistors. Supporting columns are respectively arranged in the first area and the second area; the supporting columns located in the second area comprise first supporting columns, the first supporting columns are adjacent to the common bus in the second direction, in the thickness direction of the display panel, the thickness of a film layer which is located between the substrate and the supporting columns in the first area and belongs to the array substrate is d1, the thickness of a film layer which is located between the substrate and the first supporting columns and belongs to the array substrate is d2, and d2lt is obtained; d1. Display yellowing caused by box thickness difference can be avoided, and the display quality is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In liquid crystal display (LCD) panels, support pillars are required between the array substrate and the color filter substrate to support the thickness of the liquid crystal cell. However, localized differences in cell thickness on the LCD panel can affect the path and polarization state of light as it passes through the liquid crystal layer, leading to color distortion, manifested as localized or overall yellowing, and impacting display quality. Summary of the Invention

[0003] This invention provides a display panel and a display device to solve the technical problem in the prior art where uneven thickness of the display panel leads to yellowing and affects display quality.

[0004] In a first aspect, embodiments of the present invention provide a display panel, the display panel including an array substrate and an opposing substrate disposed opposite each other; the array substrate includes a gate driving circuit, a common bus and a plurality of switching transistors; The display panel includes a first area and a second area, with the second area surrounding the first area; switching transistors and a common bus extending along a first direction are located in the first area, and a gate driving circuit is located in the second area; the common bus is located on the side of the plurality of switching transistors closer to the gate driving circuit. The display panel also includes support columns, with support columns respectively provided in the first and second zones; the support column located in the second zone includes a first support column, which is adjacent to the common bus in the second direction and intersects the first direction in the second direction. The array substrate includes a substrate; along the thickness direction of the display panel, the thickness of the film layer belonging to the array substrate between the substrate and the support pillar in the first region is d1, and the thickness of the film layer belonging to the array substrate between the substrate and the first support pillar is d2, wherein d2 <d1。

[0005] Secondly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel provided in any embodiment of the present invention.

[0006] The display panel and display device provided in this invention have the following beneficial effects: Support pillars are respectively disposed in a first region and a second region. A common bus and a switching transistor are disposed in the first region, and a gate driving circuit is disposed in the second region, which is a non-display area. The first support pillar disposed in the second region is adjacent to the common bus extending along a first direction. The first support pillar is the support pillar closest to the display area in the non-display area, thus the cell thickness supported by the first support pillar has a significant impact on the cell thickness at the boundary between the display area and the non-display area. Compared to the support pillar disposed in the first region, the film layer thickness belonging to the array substrate between the substrate and the first support pillar is smaller, which can reduce the cell thickness at the support position of the first support pillar. The difference in array substrate film layer thickness between the support pillar positions in the second region and the first region is used to compensate for the difference in support pillar support height between the two regions caused by process fluctuations. This invention can improve the problem of excessive cell thickness in the non-display area supported by the first support pillar due to process fluctuations, avoid yellowing of the display caused by cell thickness differences, and improve display quality. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of a related technology; Figure 2 A schematic diagram of a display panel provided in an embodiment of the present invention; Figure 3 for Figure 2 A schematic diagram of a cross-section at the position of the tangent AA′; Figure 4 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 5 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 6 for Figure 2 Another cross-sectional view at the location of the tangent AA′; Figure 7 for Figure 2 Another cross-sectional view at the location of the tangent AA′; Figure 8A This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 8B A schematic cross-sectional view of the transition structure location; Figure 9A This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 9B A schematic cross-sectional view of the transition structure location; Figure 10 for Figure 2 Another cross-sectional view at the location of the tangent AA′; Figure 11 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 12 This is another partial top view of a display panel provided in an embodiment of the present invention; Figure 13 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 14 This is another schematic cross-sectional view of a display panel provided in an embodiment of the present invention; Figure 15 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention; Figure 16 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention; Figure 17 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention; Figure 18 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 19 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0010] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0011] In related technologies, support pillars are provided in both the display area and non-display area of ​​the display panel. The support pillars in the display area play a primary role in supporting the liquid crystal cell thickness, while the support pillars in the non-display area play a secondary role. However, due to fluctuations in the manufacturing process of the support pillars, the height of the support pillars at different locations may vary, resulting in differences in the liquid crystal cell thickness. In addition, film thickness issues at the stacking locations of the support pillars in the non-display area can cause the cell thickness at the support pillar locations in the non-display area to be greater than the liquid crystal cell thickness in the display area. Figure 1 This is a schematic diagram of a related technology, such as Figure 1 As shown, support pillar 01 is disposed on the side of color filter substrate 02, on which a black matrix BM and a color filter 021 are disposed. The black matrix BM within display area AA has an opening, and the color filter 021 is located within the opening. At the non-display area NA, the black matrix BM does not have an opening, and the color filter 021 directly stacks with the black matrix BM, increasing the film thickness at that location. Therefore, the height of the support pillar 01 at this location is higher than the height of the support pillar 01 within display area AA. This height is compared with the height of the support pillar 01 within display area AA using the same reference plane. After the color filter substrate 02 and the array substrate are bonded together to form a cell, a cell thickness difference will occur between the non-display area NA and display area AA, which are close to display area AA. Whether the height difference of the support pillar itself is due to fluctuations in the support pillar manufacturing process, or the height difference of the support pillar due to differences in film thickness at the stacking position, both will cause a yellowing of the display, affecting display quality.

[0012] To address the problems existing in related technologies, embodiments of the present invention provide a display panel in which a first support pillar arranged in the non-display area near the display area is positioned such that the film thickness at the intersection of the array substrate side and the first support pillar is smaller. This reduces the difference between the cell thickness at the support position of the first support pillar and the cell thickness of the display area, improves the yellowing problem, and enhances the display quality.

[0013] Figure 2 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 3 for Figure 2 A schematic diagram of a cross-section at the location of the tangent AA′. (See diagram below.) Figure 2As shown, the display panel includes a first region A1 and a second region A2, with the second region A2 surrounding the first region A1. Switching transistors T and a common bus 12 extending along a first direction y are located in the first region A1, and a gate driving circuit 11 is located in the second region A2. The common bus 12 is located on the side of the plurality of switching transistors T closest to the gate driving circuit 11. The first region A1 includes a plurality of sub-pixels sp, data lines Data extending along the first direction y, and gate lines Gate extending along a second direction x, which intersects the first direction y. The intersection of the data lines Data and the gate lines Gate defines the area where the sub-pixels sp are located. The sub-pixels sp include switching transistors T and pixel electrodes 23. The switching transistor T can be a top-gate transistor or a bottom-gate transistor. The gate of the switching transistor T is connected to the gate line Gate, the source is connected to the data line Data, and the drain is connected to the pixel electrode 23. The display panel also includes a common electrode, which cooperates with the pixel electrode 23 to drive the liquid crystal molecules for polarization. The common electrode is electrically connected to the common bus 12. It can be understood that... Figure 2 The common bus 12 is located in the peripheral area of ​​multiple transistors T, that is, the common bus 12 is located in the periphery of the display area composed of multiple sub-pixels sp. Figure 2 The first zone A1 in the middle may be slightly larger than the actual display area of ​​the display panel. The area on the side of the common bus 12 opposite to the gate drive circuit 11 is the display area.

[0014] Combination Figure 3 The display panel includes an array substrate 10 and an opposing substrate 20 disposed opposite to each other, and liquid crystal molecules are disposed between the array substrate 10 and the opposing substrate 20. Figure 3 (Not shown). The array substrate 10 includes a substrate 00, a gate driving circuit 11, a common bus 12, and multiple switching transistors T. The array substrate 10 also includes a common electrode, which is electrically connected to the common bus 12. The opposing substrate 20 is a color filter substrate, which includes a black matrix and color resist units. The color resist units include color resists for red, green, and blue colors, and each sub-pixel sp includes one color resist.

[0015] The display panel also includes support pillars 21, which are respectively provided in the first area A1 and the second area A2. The support pillars 21 can be made on the array substrate 10 side, on the opposing substrate 20 side, or on both the array substrate 10 side and the opposing substrate 20 side. Figure 3 The diagram illustrates a support pillar 21 fabricated on the side of the opposing substrate 20, meaning the support pillar 21 is located on the opposing substrate 20, and its top surface faces the array substrate 10. The support pillar 21 located in the second region A2 includes a first support pillar 211. Tangent AA′ extends along the second direction x, combined with... Figure 2It can be understood that the first support column 211 is adjacent to the common bus 12 in the second direction x. That is, the first support column 211 is the support column 21 closest to the common bus 12 in the second direction x within the second region A2.

[0016] Along the thickness direction e of the display panel, the thickness of the film layer belonging to the array substrate 10 between the substrate 00 and the support column 21 in the first region A1 is d1, and the thickness of the film layer belonging to the array substrate 10 between the substrate 00 and the first support column 211 is d2, where d2 < d1. The thickness direction e of the display panel is the direction perpendicular to the plane where the substrate 00 is located. For the relationship of d2 < d1, that is, viewed with the plane where the substrate 00 is located as the reference plane, the film layer height of the array substrate 10 overlapping with the first support column 211 is relatively lower. When the support column 21 is fabricated on the side of the counter substrate 20, the film layer thickness of the array substrate 10 overlapping with the first support column 211 is relatively smaller. When the support column 21 is fabricated on the side of the array substrate 10, the film layer thickness of the array substrate 10 between the first support column 211 and the substrate 00 below is relatively smaller.

[0017] An embodiment of the present invention provides a display panel. Support columns 21 are respectively provided in the first region A1 and the second region A2. A common bus 12 and a switching transistor T are provided in the first region A1. The sub-pixel sp includes the switching transistor T. At least a plurality of regions where the switching transistors T are located are display regions. A gate driving circuit 11 is provided in the second region A2, and the second region A2 is a non-display region. The first support column 211 provided in the second region A2 is adjacent to the common bus 12 extending in the first direction y. The first support column 211 is the support column 21 closest to the display region provided in the non-display region. Then, the cell thickness supported by the first support column 211 has a greater impact on the cell thickness at the boundary between the display region and the non-display region. Compared with the support columns 21 provided in the first region A1, the thickness of the film layer belonging to the array substrate 10 between the substrate 00 and the first support column 211 is smaller, which can reduce the cell thickness at the position supported by the first support column 211. By using the difference in the film layer thickness of the array substrate 10 at the position of the first support column 211 in the second region A2 and the position of the support column 21 in the first region A1, the difference in the support height of the support columns in the two regions caused by the process fluctuation is compensated. The embodiment of the present invention can improve the problem that the cell thickness of the non-display region supported by the first support column 211 is too large due to the process fluctuation, and can avoid the display yellowing caused by the cell thickness difference, and improve the display quality.

[0018] In some embodiments, Figure 4 It is a partial schematic diagram of another display panel provided by an embodiment of the present invention. Figure 4 It is a partial top view of the display panel. As Figure 4As shown, the first region A1 includes a gate line Gate, and the gates of a plurality of switching transistors T arranged in the second direction x are electrically connected to the gate line Gate; the gate drive circuit 11 includes a plurality of cascaded shift register units VSR. Figure 4 The diagram illustrates shift registers VSR(n) to VSR(n+3) of level n, where n is a positive integer. The second region A2 includes a transition structure 22, with the output terminal of the shift register VSR electrically connected to the transition structure 22, and one end of the gate line also electrically connected to the transition structure 22. The transition structure 22 is essentially a signal output terminal for transmitting the output signal of the shift register VSR. The side of the transition structure 22 closest to the first region A1 has a first boundary Y1, at least a portion of which lies on a first virtual line X1 extending along a first direction y. The first boundary Y1 can be a curve, a broken line, or a straight line.

[0019] Among them, the surface of the first support pillar 211 closest to the substrate 00 is the first surface 211m (e.g., Figure 3 (The location indicated in the middle); the orthographic projection of the first surface 211m onto the substrate 00 lies between the orthographic projection of the shift register unit VSR onto the substrate 00 and the orthographic projection of the first virtual line X1 onto the substrate 00. That is, along the direction perpendicular to the plane where the substrate 00 is located, the first surface 211m of the first support pillar 211 overlaps with the area between the shift register unit VSR and the first virtual line X1. Figure 4 This is a partial top view of the display panel, combined with... Figure 3 As shown in the schematic cross-sectional view of the display panel, when the support pillar 21 is positioned on the side of the opposing substrate 20, the first surface 211m is the top surface of the first support pillar 211, and the surface of the first support pillar 211 away from the array substrate 10 is its bottom surface. The first support pillar 211 is trapezoidal in cross-section, meaning the area of ​​its bottom surface is slightly larger than the area of ​​its first surface 211m. Similarly, when the support pillar 21 is positioned on the side of the array substrate 10, the first surface 211m is the bottom surface of the first support pillar 211, and the surface of the first support pillar 211 closer to the opposing substrate 20 is its top surface. The area of ​​the first surface 211m is slightly larger than the area of ​​the top surface of the first support pillar 211.

[0020] In this embodiment, the first surface 211m of the first support pillar 211 overlaps with the area between the shift register unit VSR and the first virtual line X1. Only some traces and transition structures 22 are provided between the shift register unit VSR and the first virtual line X1, and no transistor structure is provided. Therefore, the film structure of the array substrate 10 in the area between the shift register unit VSR and the first virtual line X1 is simple and the total film thickness is small. It is possible to set the first support pillar 211 to overlap with the area of ​​the array substrate 10 where the film thickness is reduced, thereby reducing the cell thickness at the support position of the first support pillar 211. This improves the problem of excessive cell thickness in the non-display area supported by the first support pillar 211 due to process fluctuations, avoids yellowing of the display caused by cell thickness differences, and improves display quality.

[0021] For example, in combination Figure 3 and Figure 4 In the first region A1, along the thickness direction e of the display panel, the support pillar 21 overlaps with the switching transistor T. Each sub-pixel in the first region A1 includes one switching transistor T, which occupies a certain space within the first region A1. The black matrix arranged in the opposing substrate 20 will obscure the first switching transistor T, and by setting the support pillar 21 to overlap with the switching transistor T, the influence of the support pillar 21 on the sub-pixel opening can be avoided. The location of the switching transistor T is provided with the transistor's active layer, gate, source, and drain, resulting in a larger film thickness in the area of ​​the array substrate 10 overlapping with the support pillar 21. In this embodiment of the invention, compared to the support pillar 21 in the first region A1, the film thickness belonging to the array substrate 10 between the substrate 00 and the first support pillar 211 in the second region A2 is smaller. This reduces the cell thickness at the support position of the first support pillar 211, improving the problem of excessive cell thickness in the non-display area supported by the first support pillar 211 due to process fluctuations, avoiding yellowing caused by cell thickness differences, and improving display quality.

[0022] Depend on Figure 4 As can be seen, a gate line connects multiple switching transistors T arranged along the second direction x, that is, multiple sub-pixels are arranged into sub-pixel rows in the second direction x, and a gate line drives one sub-pixel row. Figure 4 This is illustrated by showing a shift register (VSR) connected to a gate line (Gate). In other embodiments, Figure 5 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 5 As shown, the gate drive circuit 11 includes multiple cascaded shift register units (VSRs). Figure 5The diagram illustrates the nth-level shift register unit VSR(n) and the (n+1)th-level shift register unit VSR(n+1). The output of one shift register unit VSR is connected to two gate lines via the adapter structure 22, meaning that one shift register unit VSR drives two sub-pixel rows.

[0023] For example, Figure 6 for Figure 2 A schematic diagram of another cross-section at the location of the tangent AA′. The tangent AA′ extends along the second direction x. (From...) Figure 6 It can be seen that the transition structure 22 and the shift register unit VSR are arranged along the second direction x. The projection direction of the first surface 211m onto the plane containing the substrate 00 is parallel to the thickness direction e of the display panel. Therefore, from... Figure 5 It can be seen that the orthographic projection of the first surface 211m of the first support pillar 211 onto the substrate 00 lies between the orthographic projection of the shift register unit VSR onto the substrate 00 and the orthographic projection of the transition structure 22 onto the substrate 00. Combined with... Figure 4 The output of the shift register unit VSR is electrically connected to the adapter structure 22 via the output connection line 31. Only the output connection line 31 is arranged between the shift register unit VSR and the adapter structure 22. The output connection line 31 is typically made using a single metal layer, such as the output connection line 31 being on the same layer as the common bus 12. Therefore, the film thickness in the region between the shift register unit VSR and the adapter structure 22 in the array substrate 10 is relatively thin. The first surface 211m of the first support pillar 211 is positioned between the orthogonal projections of the shift register unit VSR and the adapter structure 22 on the substrate 00. This ensures that the first support pillar 211 supports the cell thickness in the region between the shift register unit VSR and the adapter structure 22, reducing the cell thickness at the support position of the first support pillar 211. This improves the problem of excessive cell thickness in the non-display area supported by the first support pillar 211 due to process fluctuations, avoids yellowing caused by cell thickness differences, and improves display quality.

[0024] Indicative, such as Figure 6As shown, along the second direction x, the distance from the transition structure 22 to the shift register unit VSR is L1, and the distance from the transition structure 22 to the common bus 12 is L2, where L1 > L2. That is, in the second direction x, the distance from the transition structure 22 to the shift register unit VSR is greater than its distance to the common bus 12. Within the limited space of the display panel, the distance from the transition structure 22 to the common bus 12 can be appropriately reduced to increase the distance from the transition structure 22 to the shift register unit VSR, so that a larger distance is reserved between the transition structure 22 and the shift register unit VSR. Thus, when setting the first support column 211, the first surface 211m of the first support column 211 can overlap with part of the transition structure 22, or the first surface 211m can overlap with the area between the shift register unit VSR and the transition structure 22. This allows for a smaller film thickness on the array substrate 10 at the support position of the first support pillar 211, thereby reducing the cell thickness supported by the first support pillar 211 and improving the problem of excessive cell thickness in the non-display area supported by the first support pillar 211 due to process fluctuations.

[0025] Considering that when the distance between the adapter structure 22 and the shift register unit VSR is too small, electrostatic discharge will occur, affecting the signal output of the adapter structure 22, illustratively, setting L1 > 20μm can avoid the generation of electrostatic discharge, allowing the shift register unit VSR to output signals normally to the gate line Gate through the adapter structure 22.

[0026] When the distance between the adapter structure 22 and the common bus 12 is too small, i.e., the adapter structure 22 is too close to the display area, the signal output of the adapter structure 22 will be affected by static electricity or coupling capacitance. Illustratively, setting L2 > 20μm can avoid the generation of static electricity, allowing the shift register unit VSR to output signals normally to the gate line Gate through the adapter structure 22.

[0027] Indicative, such as Figure 6 As shown, along the second direction x, the distance between the transition structure 22 and the shift register unit VSR is L1, and the length of the first surface 211m is L3, where L1 > L3. This allows the first surface 211m of the first support pillar 211 to overlap with the areas between the transition structure 22 and the shift register unit VSR, ensuring that the first surface 211m of the first support pillar 211 does not overlap with either the transition structure 22 or the shift register unit VSR. This results in a smaller film thickness between the first support pillar 211 and the substrate 00 belonging to the array substrate 10, thereby reducing the cell thickness at the support position of the first support pillar 211.

[0028] like Figure 6As shown, along the second direction x, the distance from the transition structure 22 to the shift register unit VSR is L1, the length of the first surface 211m is L3, and the distance from the transition structure 22 to the common bus 12 is L2, where L1>L3>L2. This embodiment sets L1>L2 so that by appropriately reducing the distance from the transition structure 22 to the common bus 12, the distance from the transition structure 22 to the shift register unit VSR can be increased, thus allowing for a larger distance between the transition structure 22 and the shift register unit VSR. Furthermore, setting L1>L3 allows the first surface 211m of the first support pillar 211 to overlap with the area between the transition structure 22 and the shift register unit VSR when the first support pillar 211 is set, thereby reducing the film thickness of the first support pillar 211 and the substrate 00 belonging to the array substrate 10, and reducing the cell thickness at the support position of the first support pillar 211. By coordinating the sizes of L1, L2, and L3, the cell thickness at the support position of the first support pillar 211 can be reduced, thus improving the problem of excessive cell thickness in the non-display area supported by the first support pillar 211 due to process fluctuations. This can avoid yellowing of the display caused by cell thickness differences and improve display quality.

[0029] For example, Figure 7 for Figure 2 A schematic diagram of another cross-section at the location of the tangent AA′. The tangent AA′ extends along the second direction x. (From...) Figure 7 It can be seen that the orthographic projection of the first surface 211m of the first support pillar 211 onto the substrate 00 at least partially overlaps with the orthographic projection of the transition structure 22 onto the substrate 00. In some display panels, the bezel size of the display panel is limited. When the distance L1 from the transition structure 22 to the shift register unit VSR along the second direction x is set to be greater than the distance L2 from the transition structure 22 to the common bus 32, the size L1 cannot be set too large. This results in the first surface 211m of the first support pillar 211 at least partially overlapping with the transition structure 22. Since the transition structure 22 is a two-layer metal stacked structure or a bridging structure, the film thickness of the array substrate 10 at the location of the transition structure 22 is also relatively small. Setting the first support pillar 211 to at least partially overlap with the transition structure 22 can also reduce the cell thickness at the support position of the first support pillar 211.

[0030] For example, Figure 8A This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 8B This is a schematic cross-sectional view of the transition structure location. (Combined with...) Figure 8A and Figure 8BThe adapter structure 22 includes a first metal pattern 221, a second metal pattern 222, and a bridging pattern 223, which are located on different layers. The output terminal of the shift register unit VSR is electrically connected to the first metal pattern 221 via the output connection line 31, and the gate line is electrically connected to the second metal pattern 222. One end of the bridging pattern 223 is connected to the first metal pattern 221 via a first via V1, and the other end is connected to the second metal pattern 222 via a second via V2. The adapter structure 22 is essentially a signal output terminal for transmitting the output signal of the shift register unit VSR. In this embodiment, the adapter structure 22 is configured as a bridging structure composed of the first metal pattern 221, the second metal pattern 222, and the bridging pattern 223, which enables the electrical connection between the output terminal of the shift register unit VSR and the gate line. Furthermore, the film layer stacking thickness of the bridging structure is relatively thin. Even if the first surface 211m of the first support pillar 211 overlaps with the transition structure 22 at least partially, the cell thickness at the support position of the first support pillar 211 can be reduced, thus improving the problem of excessive cell thickness in the non-display area supported by the first support pillar 211 due to process fluctuations.

[0031] Optionally, the first metal pattern 221 is located on the same layer as the data line (Data), and the second metal pattern 222 is located on the same layer as the gate line (Gate). Pixel electrodes and common electrodes are also fabricated in the array substrate 10, with the bridging pattern 223 located on the same layer as the pixel electrode, or the bridging pattern 223 located on the same layer as the common electrode.

[0032] For example, Figure 9A This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 9B This is a schematic cross-sectional view of the transition structure location. (Combined with...) Figure 9A and Figure 9BAs shown, the转接结构22 includes a first metal pattern 221 and a second metal pattern 222, and the first metal pattern 221 and the second metal pattern 222 are located on different layers. The output terminal of the shift register unit VSR is electrically connected to the first metal pattern 221, the gate line Gate is electrically connected to the second metal pattern 222, and the first metal pattern 221 and the second metal pattern 222 are connected through a third via V3. Optionally, the first metal pattern 221 and the data line Data are on the same layer, and the second metal pattern 222 and the gate line Gate are on the same layer. The output connection line 31 is on the same layer as the first metal pattern 221. One end of the output connection line 31 is connected to the output terminal of the shift register unit VSR, and the other end is connected to the first metal pattern 221. In this embodiment, the first metal pattern 221 and the second metal pattern 222 are connected through vias to form the转接结构22, and the electrical connection between the output terminal of the shift register unit VSR and the gate line Gate is realized by using the转接结构22. Moreover, the film stack thickness of the转接结构22 is relatively thin. Even if the first surface 211m of the first support column 211 overlaps at least partially with the转接结构22, the cell thickness at the support position of the first support column 211 can be reduced, and the problem of the偏大 cell thickness in the non-display area supported by the first support column 211 caused by the process fluctuation can be improved.

[0033] Schematically, Figure 10 For Figure 2 Another cross-sectional schematic view at the position of the mid-tangent line A-A'. As Figure 10 shown, along the second direction x, the maximum length of the first support column 211 is Lm1, and the maximum length of the support column 21 in the first region A1 is Lm2. The height of the first support column 211 is h1, and the height of the support column 21 in the first region A1 is h2. The height of the first support column 211 is calculated by the distance between its top surface and bottom surface, and the height of the support column 21 in the first region A1 is also calculated by the distance between its top surface and bottom surface. Among them, Lm1 < Lm2, and / or, h1 < h2. The size of the first support column 211 can be reduced by reducing the maximum length Lm1 of the first support column 211 in the second direction x, and / or reducing the height h1 of the first support column 211. By reducing the size of the first support column 211 and cooperating with the design of the smaller film thickness of the array substrate 10 at the overlapping position of the first support column 211, the cell thickness at the support position of the first support column 211 can be further reduced. In some embodiments, the spacing L1 between the转接结构22 and the shift register unit VSR in the second direction x is limited, and the first support column 211 will overlap at least partially with the转接结构22. At this time, the cell thickness at the support position of the first support column 211 can be reduced by reducing the size of the first support column 211, thereby improving the problem of the偏大 cell thickness in the non-display area supported by the first support column 211 caused by the process fluctuation.

[0034] For example, in the second region A2, n1 first support columns 211 are arranged along the first direction y; in the first region A1, n2 support columns 21 are arranged along the first direction y and are adjacent to the common bus 12 respectively; wherein, n1>n2. Figure 11 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 11 This is a top view of the display panel, by Figure 11 As illustrated in the diagram of a local area, it can be seen that the number of first support columns 211 arranged along the first direction y in the second area A2 is greater than the number of support columns 21 adjacent to the common bus 12 in the first area A1. Combined with... Figure 10 In the embodiment, in the scheme of reducing the size of the first support column 211 to reduce the box thickness at the support position of the first support column 211, the box thickness support capacity at the edge position of the second area A2 can be enhanced by increasing the number of first support columns 211, so as to ensure the stability of the box thickness support.

[0035] Indicative, Figure 12 Another partial top view of the display panel provided in an embodiment of the present invention, such as... Figure 12 As shown, the shift register cell VSR and the connecting structure 22 connected to it at least partially overlap in the first direction y. The projection direction of the orthographic projection onto the plane containing the substrate 00 is parallel to the top view direction. Figure 12 As can be seen from the top view, the orthographic projection of the first surface 211m of the first support pillar 211 onto the substrate 00 lies between the orthographic projection of the shift register unit VSR onto the substrate 00 and the orthographic projection of the transition structure 22 onto the substrate 00. This embodiment sets the shift register unit VSR and the transition structure 22 to at least partially overlap in the first direction y, which can shorten the distance between the edge of the shift register unit VSR and the common bus 12, thus facilitating a narrower bezel. Furthermore, the design of the orthographic projection position of the first surface 211m of the first support pillar 211 allows for a smaller film thickness belonging to the array substrate 10 between the substrate 00 and the first support pillar 211, reducing the cell thickness at the support position of the first support pillar 211 and mitigating the problem of excessive cell thickness in the non-display area supported by the first support pillar 211 due to process fluctuations.

[0036] like Figure 12As shown, the boundary of the shift register unit VSR near the first region A1 is the second boundary Y2, and the shape of the second boundary Y2 is a broken line. The second boundary Y2 includes a first line segment 41 extending along the first direction y and a second line segment 42 extending along the second direction x. It can be seen that the first line segment 41 and the second line segment 42 are connected to each other to form a notch. Along the first direction y, the transition structure 22 is adjacent to the notch, and the transition structure 22 and the notch at least partially overlap. In this embodiment, the arrangement of transistors in the shift register unit VSR can be set so that the second boundary Y2 formed by the shift register unit VSR is a non-linear boundary. By using the second boundary Y2 to form a notch and setting the transition structure 22 adjacent to the notch, and the transition structure 22 and the notch at least partially overlapping in the first direction y, the distance between the edge of the shift register unit VSR and the common bus 12 can be shortened, and the border can be narrowed. Furthermore, the thickness of the support cell in the area between the first support pillar 211 and the transition structure 22 and the second boundary Y2 can be set so that the thickness of the film layer belonging to the array substrate 10 between the substrate 00 and the first support pillar 211 is smaller, which can reduce the cell thickness at the support position of the first support pillar 211 and improve the problem of excessive cell thickness in the non-display area supported by the first support pillar 211 due to process fluctuations.

[0037] For example, Figure 13 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 13 Only the area surrounding a single shift register unit (VSR) is shown. For example... Figure 13 As shown, the shape of the second boundary Y2 of the shift register unit VSR near the first region A1 is a broken line. This arrangement allows the shift register unit VSR and the connecting structure 22 connected to it to at least partially overlap in the first direction y, and a first support column 211 is provided in the area between the second boundary Y2 and the connecting structure 22. Figure 13 As shown, multiple support columns 21 are arranged in the second zone A2, and some of the support columns 21 overlap with the shift register unit VSR.

[0038] refer to Figure 4As illustrated in the diagram, the distance between the first support pillar 211 and the adjacent support pillar 21 located in the second direction x and in the first region A1 is D1; ​​the spacing between two adjacent support pillars 21 in the second direction x in the first region A1 is D2; where D1>D2. The first support pillar 211 is the support pillar 21 located in the non-display area that is closest to the display area. In the second region A2, along the direction away from the first region A1, the first support pillar 211 is the first support pillar 21 located in the second region A2. By adjusting the distance between the first support pillar 211 and the support pillars 21 in the first region A1, and setting D1>D2, so that the first support pillar 211 located in the second region A2 is farther away from the common bus 12, the first support pillar 211 can be supported at a position where the film layer thickness of the array substrate 10 is smaller, thereby reducing the cell thickness at the support position of the first support pillar 211.

[0039] Optionally, multiple support columns 21 within the first zone A1 are arranged at equal intervals in the second direction x.

[0040] Optionally, the distance between two adjacent support columns 21 in the second direction x within the first zone A1 is D2, where D2 = 1 / 3. Pixel width - support pillar diameter. Pixel width refers to the width of the pixel composed of red, green and blue sub-pixels in the second direction x. Support pillar diameter refers to the maximum length of support pillar 21 in the second direction x.

[0041] For example, Figure 3114 is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention. Figure 14 As shown, the support column 21 located in the second zone A2 includes a main support column 21A and an auxiliary support column 21B. The height of the main support column 21A in the second zone A2 is H1, and the height of the auxiliary support column 21B is H2, where H1>H2. The height of the support column is calculated based on the distance between its top and bottom surfaces. Among them, the first support column 211 is the main support column 21A. Figure 14 The diagram illustrates that within the first zone A1, the support column 21 includes a main support column 21A and an auxiliary support column 21B. The height of the main support column 21A is greater than the height of the auxiliary support column 21B. The main support column 21A plays a primary role in supporting the cell thickness. When the display panel is subjected to a certain pressure, the main support column 21A is compressed first, and its height decreases. When the height of the main support column 21A decreases to the same height as the auxiliary support column 21B, the auxiliary support column 21B and the main support column 21A together provide support for the liquid crystal cell thickness to ensure cell thickness stability.

[0042] For example, Figure 15 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention. Figure 15 The shift register unit VSR is shown in a simplified diagram. Figure 15As shown, the support pillar 21 located in the second region A2 includes a second support pillar 212; along the second direction x, the distance of the second support pillar 212 from the common bus 12 is greater than the distance of the first support pillar 211 from the common bus 12. The gate drive circuit 11 includes a shift register unit VSR, and a reserved area Q1 is included at the location of the shift register unit VSR. The wiring in the shift register unit VSR is arranged around the reserved area Q1; that is, by setting the transistor positions and connection lines in the shift register unit VSR, there is an area where no wiring is set at the location occupied by the shift register unit VSR. Among them, the surface of the second support pillar 212 near the substrate 00 is the second surface 212m; the orthographic projection of the second surface 212m on the substrate 00 is located within the orthographic projection of the reserved area Q1 on the substrate 00. Since the wiring of the shift register unit VSR surrounds the reserved area Q1, the film thickness of the array substrate 10 at the location of the reserved area Q1 is relatively thin. Setting the orthographic projection of the second surface 212m within the orthographic projection of the reserved area Q1 can reduce the cell thickness supported by the second support pillar 212. Both the first support pillar 211 and the second support pillar 212 are located in the second region A2. Although the second support pillar 212 is farther from the display area than the first support pillar 211, since the second region A2 is a border area with a relatively small width, the number of support pillars 21 arranged along the second direction x in the second region A2 is limited. Therefore, the support pillars 21 in the second region A2 are significantly affected by process fluctuations, which greatly influence the cell thickness difference between the first region A1 and the second region A2. That is, not only does the height fluctuation of the first support pillar 211, which is closer to the common bus 12, affect the cell thickness difference between the first region A1 and the second region A2, but the height fluctuation of the second support pillar 212, which is relatively farther from the common bus 12, also affects the cell thickness difference between the first region A1 and the second region A2. In this embodiment of the invention, the first support pillar 211 and the second support pillar 212 are both arranged to overlap with the thinner areas of the array substrate 10. This can reduce the cell thickness at the support position of the first support pillar 211 and also reduce the cell thickness at the support position of the second support pillar 212. This can improve the problem of excessive cell thickness of the support pillar 21 in the second region A2 caused by process fluctuations.

[0043] In this embodiment of the invention, the arrangement of the support columns 21 in the second zone A2 is not limited. In some embodiments, the arrangement of the support columns 21 in the first zone A1 can be used to set the arrangement of the support columns 21 in the second zone A2, so that the arrangement pattern of the support columns 21 in the second zone A2 is roughly the same as the arrangement pattern of the support columns 21 in the first zone A1.

[0044] In other embodiments, the support columns 21 can be arranged according to the existing wiring in the second zone A2. For example, Figure 16 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention. (See diagram below.) Figure 16As shown, the area where the shift register unit VSR is located has a region Q2 with a relatively small film thickness of the array substrate 10. If there is only a single layer of metal wiring in region Q2, the support pillar 21 can be set at the corresponding position in region Q2 in accordance with the original wiring of the shift register unit VSR. That is, the orthogonal projection of part of the support pillar 21 in the second region A2 onto the substrate is located within the orthogonal projection of region Q2 onto the substrate.

[0045] Figure 15 The diagram illustrates that the top view of the second support post 212 is circular, meaning that the orthographic projection of the second support post 212 onto the plane of the substrate is circular. In other embodiments, the orthographic projection of the second support post 212 onto the substrate 00 is elliptical, rectangular, triangular, or irregular in shape. Figure 17 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention. (See diagram below.) Figure 17 As shown, a reserved area Q1 is included at the location of the shift register unit VSR. The wiring in the shift register unit VSR is arranged around the reserved area Q1. As can be seen from the top view, the second support post 212 overlaps with the reserved area Q1, that is, the orthographic projection of the second support post 212 on the substrate is located within the orthographic projection of the reserved area Q1 on the substrate. In the top view, the shape of the second support post 212 is rectangular, that is, the orthographic projection shape of the second support post 212 on the substrate is rectangular.

[0046] Indicative, Figure 18 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 18As shown in the figure, the support column 21 located in the second area A2 includes a main support column 21A and an auxiliary support column 21B, and the height of the main support column 21A is greater than that of the auxiliary support column 21B; the height of the support column is calculated by the spacing between its top surface and bottom surface. In the second area A2: along the thickness direction e of the display panel, the thickness of the film layer belonging to the array substrate 10 between the substrate 00 and the main support column 21A is d3, and the thickness of the film layer belonging to the array substrate 10 between the substrate 00 and the auxiliary support column 21B is d4, and d3 < d4. Among them, the first support column adjacent to the common bus 12 arranged in the second area A2 is the first support column 211, and the first support column 211 is a main support column 21A. The thickness of the film layer belonging to the array substrate 10 between the first support column 211 and the substrate 00 is d2, then d2 < d4. In this embodiment, the main support column 21A and the auxiliary support column 21B with different heights are arranged in the second area A2 to support the liquid crystal cell thickness stably when the display panel bears different pressures. In the second area A2, according to the height difference between the main support column 21A and the auxiliary support column 21B, the film thickness between the two and the substrate 00 belonging to the array substrate 10 is set differently. The main support column 21A is preferentially arranged at the position with a smaller film thickness of the array substrate 10 to reduce the cell thickness supported by the main support column 21A in the second area A2, improve the problem that the cell thickness supported by the main support column 2IA in the second area A2 is too large caused by the process fluctuation, and thus avoid the display yellowing caused by the cell thickness difference and improve the display quality.

[0047] Based on the same inventive concept, the embodiment of the present invention further provides a display device Figure 19 which is a schematic diagram of a display device provided by an embodiment of the present invention, as Figure 19 shown. The display device includes the display panel 100 provided by any embodiment of the present invention. The structure of the display panel 100 has been described in the above embodiments and will not be repeated here. The display device provided by the embodiment of the present invention can be, for example, an electronic device with a display function such as a mobile phone, a tablet computer, a computer, a television, a smart wearable product, etc.

[0048] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the scope of protection of the present invention.

[0049] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes an array substrate and an opposing substrate disposed opposite each other; the array substrate includes a gate driving circuit, a common bus, and a plurality of switching transistors; The display panel includes a first area and a second area, the second area surrounding the first area; the switching transistors and the common bus extending along a first direction are located in the first area, and the gate driving circuit is located in the second area; the common bus is located on the side of the plurality of switching transistors closer to the gate driving circuit. The display panel further includes support columns, which are respectively provided in the first area and the second area; the support column located in the second area includes a first support column, which is adjacent to the common bus in a second direction and intersects the first direction in the second direction. The array substrate includes a substrate; Along the thickness direction of the display panel, the thickness of the film layer belonging to the array substrate between the substrate and the support pillar in the first region is d1, and the thickness of the film layer belonging to the array substrate between the substrate and the first support pillar is d2, wherein d2 <d1。 2. The display panel according to claim 1, characterized in that, The first region includes a gate line, and the gates of a plurality of the switching transistors arranged in the second direction are electrically connected to the gate line; The gate drive circuit includes multiple cascaded shift register units; The second region includes a switching structure, the output terminal of the shift register unit is electrically connected to the switching structure, and one end of the gate line is electrically connected to the switching structure; the side of the switching structure near the first region has a first boundary, at least a portion of which is located on a first virtual line extending along the first direction; The surface of the first support post closest to the substrate is the first surface; The orthographic projection of the first surface onto the substrate lies between the orthographic projection of the shift register unit onto the substrate and the orthographic projection of the first virtual line onto the substrate.

3. The display panel according to claim 2, characterized in that, The switching structure and the shift register unit are arranged along the second direction; The orthographic projection of the first surface onto the substrate lies between the orthographic projection of the shift register unit onto the substrate and the orthographic projection of the transition structure onto the substrate.

4. The display panel according to claim 2, characterized in that, Along the second direction, the distance between the adapter structure and the shift register unit is L1, and the distance between the adapter structure and the common bus is L2, where L1 > L2.

5. The display panel according to claim 3, characterized in that, Along the second direction, the distance between the transition structure and the shift register unit is L1, and the length of the first surface is L3, where L1>L3.

6. The display panel according to claim 5, characterized in that, Along the second direction, the distance between the adapter structure and the common bus is L2; Among them, L3 > L2.

7. The display panel according to claim 2, characterized in that, The orthographic projection of the first surface onto the substrate at least partially overlaps with the orthographic projection of the transition structure onto the substrate.

8. The display panel according to claim 2, characterized in that, The transition structure includes a first metal pattern, a second metal pattern, and a bridging pattern, wherein the first metal pattern, the second metal pattern, and the bridging pattern are located on different layers; The output terminal of the shift register unit is electrically connected to the first metal pattern, the gate line is electrically connected to the second metal pattern, and one end of the bridging pattern is connected to the first metal pattern through a first via and the other end is connected to the second metal pattern through a second via.

9. The display panel according to claim 2, characterized in that, The transition structure includes a first metal pattern and a second metal pattern, wherein the first metal pattern and the second metal pattern are located on different layers; The output terminal of the shift register unit is electrically connected to the first metal pattern, the gate line is electrically connected to the second metal pattern, and the first metal pattern and the second metal pattern are connected through a third via.

10. The display panel according to claim 2, characterized in that, Along the second direction, the maximum length of the first support column is less than the maximum length of the support column in the first area; And / or, the height of the first support column is less than the height of the support column in the first area.

11. The display panel according to claim 10, characterized in that, In the second zone, n1 of the first support columns are arranged along the first direction; In the first region, n2 support columns are arranged along the first direction and are adjacent to the common bus; wherein, n1>n2.

12. The display panel according to claim 2, characterized in that, The shift register unit and the adapter structure connected thereto overlap at least partially in the first direction; The orthographic projection of the first surface onto the substrate lies between the orthographic projection of the shift register unit onto the substrate and the orthographic projection of the transition structure onto the substrate.

13. The display panel according to claim 12, characterized in that, The boundary of the shift register unit near the first area is the second boundary, and the shape of the second boundary is a broken line; the second boundary includes a first line segment extending along the first direction and a second line segment extending along the second direction, and the first line segment and the second line segment are connected to each other to form a notch; Along the first direction, the transition structure is adjacent to the notch, and the transition structure and the notch at least partially overlap.

14. The display panel according to claim 1, characterized in that, The distance between the first support column and the support column adjacent to it in the second direction and located in the first region is D1; In the first region, the spacing between two adjacent support columns in the second direction is D2; Where D1 > D2.

15. The display panel according to claim 1, characterized in that, The support column located in the second zone includes a main support column and an auxiliary support column, wherein the height of the main support column is greater than the height of the auxiliary support column; The first support column is the main support column.

16. The display panel according to claim 1, characterized in that, The support column located in the second zone includes a second support column; along the second direction, the distance of the second support column from the common bus is greater than the distance of the first support column from the common bus; The gate drive circuit includes a shift register unit, and a reserved area is included at the location of the shift register unit. The wiring in the shift register unit is arranged around the reserved area. The side of the second support post closest to the substrate is the second side; The orthographic projection of the second surface onto the substrate lies within the orthographic projection of the reserved area onto the substrate.

17. The display panel according to claim 16, characterized in that, The second support post has a circular, elliptical, rectangular, triangular, or irregular shape when projected onto the substrate.

18. The display panel according to claim 1, characterized in that, The support column located in the second zone includes a main support column and an auxiliary support column, wherein the height of the main support column is greater than the height of the auxiliary support column; Within the second region: along the thickness direction of the display panel, the film thickness belonging to the array substrate between the substrate and the main support pillar is d3, and the film thickness belonging to the array substrate between the substrate and the auxiliary support pillar is d4. <d4。 19. The display panel according to claim 1, characterized in that, In the first region: along the thickness direction of the display panel, the support pillar overlaps with the switching transistor.

20. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 19.

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