An integrated power supply driving control chip circuit with high adaptability to power supply voltage

Abstract

This invention proposes an integrated power drive control chip circuit with high adaptability to power supply voltage, including a control unit, a battery charging circuit, a voltage regulator circuit, and a drive output circuit. The control unit is connected to both the battery charging circuit and the drive output circuit. The voltage regulator circuit includes a power supply boost circuit, a bias current source circuit, and a voltage regulator circuit. The power supply boost circuit provides the bias current source circuit and the voltage regulator circuit with a working voltage twice the power supply voltage, significantly improving adaptability to low power supply voltages. The bias current source circuit, based on its balanced feedback circuit, reduces the system's power supply voltage requirements. The voltage regulator circuit is used to generate a reference voltage unaffected by temperature changes. When using the integrated power drive control chip with the voltage regulator circuit of this invention, the adaptability to battery voltage is significantly enhanced, the load output is more stable, and the drive system using this integrated power drive control chip circuit has better battery life.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to an integrated power drive control chip circuit with high adaptability to power supply voltage. Background Technology

[0002] In common rechargeable electric appliances (such as rechargeable shavers and portable water pumps), integrated power charging and driving control chips are used. The integrated power driving control chip manages the battery and controls the output of battery power to the driving load. It generally includes a control unit, a charging circuit, a voltage regulator circuit, and a drive output circuit. The control unit acts as a central controller to control the charging circuit and the drive output circuit. When an external power source is connected, the external power source charges the battery through the charging circuit. When in use, the battery power is output to the drive output circuit through the voltage regulator circuit, thereby driving the load motor.

[0003] However, stable operation of a load depends on a stable voltage output, and long-lasting battery life has always been a pressing need for circuit systems. Battery power supply voltage fluctuates with usage and aging, requiring voltage regulator circuits to provide stable output while adapting to low-voltage operating environments to achieve long-lasting battery life for the entire circuit system. Existing integrated circuit voltage regulators cannot adapt to low-voltage operating environments. Summary of the Invention

[0004] The problem solved by this invention is how to provide an integrated power drive control chip circuit with high adaptability to power supply voltage.

[0005] To address the aforementioned problems, this invention provides an integrated power drive control chip circuit with high adaptability to power supply voltage, comprising a control unit, a battery charging circuit, a voltage regulator circuit, and a drive output circuit. The control unit is connected to both the battery charging circuit and the drive output circuit. The output terminal of the battery charging circuit is connected to the battery port, the input terminal of the voltage regulator circuit is connected to the battery port, and the output terminal supplies power to the drive output circuit. The output terminal of the drive output circuit is connected to the motor power port to supply power to the load motor.

[0006] The voltage regulator circuit includes a power supply boost circuit, a bias current source circuit, and a voltage regulator circuit.

[0007] The power supply boost circuit is connected to the bias current source circuit and the voltage regulator circuit respectively. The power supply boost circuit generates twice the battery power supply voltage and transmits it as the working voltage to the bias current source circuit and the voltage regulator circuit.

[0008] The bias current source circuit is connected to the voltage regulator circuit. The bias current source circuit generates a bias current that is unaffected by changes in the power supply voltage and transmits it to the voltage regulator circuit to maintain the normal operation of the voltage regulator circuit.

[0009] The voltage regulator circuit generates a reference voltage that is unaffected by temperature changes and outputs it to the drive output circuit through the port.

[0010] The power boost circuit includes the BYDC port.

[0011] The bias current source circuit includes ports SVDC, JXBA, and VREB.

[0012] The voltage regulator circuit includes ports JZDC, PZBA, and VREF.

[0013] The BYDC port is connected to the SVDC port to transmit the boosted operating voltage Vtdd.

[0014] Port BYDC is connected to port JZDC to transmit the boosted operating voltage Vtdd.

[0015] Port JXBA is connected to port PZBA to transmit bias current Ibsn.

[0016] The VREF port is used to output the reference voltage Vre generated by the system.

[0017] Port VREF is connected to port VREB and is used to transmit the reference voltage Vre, which serves as the bias.

[0018] The power supply boost circuit includes a positive phase boost circuit and an inverting phase boost circuit.

[0019] The positive boost circuit and the negative boost circuit are connected and operate in a complementary manner, jointly maintaining a power supply boost circuit outputting twice the power supply voltage to the bias current source circuit and the voltage regulator circuit. When the positive boost circuit is boosting the output voltage, the negative boost circuit is in a charging state. When the positive boost circuit is in a charging state, the negative boost circuit is boosting the output voltage.

[0020] The bias current source circuit includes a balanced feedback circuit and a bias output circuit.

[0021] The balanced feedback circuit is connected to the bias output circuit. Based on its negative feedback, the balanced feedback circuit ensures that the bias current Ibsn generated by the bias output circuit is unaffected by changes in the power supply voltage. The bias output circuit generates the bias current Ibsn under low power consumption conditions and outputs it through a port.

[0022] A voltage regulator circuit includes a mirror circuit and a load circuit.

[0023] The mirror circuit is connected to the load circuit. The mirror circuit replicates the received bias current to each branch of the load circuit, maintaining the normal operation of the load circuit. The load circuit generates a reference voltage Vre that is unaffected by temperature changes and outputs it to the drive output circuit through the port.

[0024] The integrated power drive control chip circuit also includes an indicator circuit and a button circuit connected to the control unit. The indicator circuit is connected to the LED output port, and the button circuit is connected to the switch input port.

[0025] Compared with the prior art, the beneficial effects of the present invention are:

[0026] The integrated power drive control chip circuit of this invention employs a highly adaptable voltage regulator circuit to provide voltage to the drive output circuit, thereby driving the load. The voltage regulator circuit includes a power supply boost circuit, a bias current source circuit, and a voltage regulator circuit. The power supply boost circuit provides the bias current source circuit and the voltage regulator circuit with an operating voltage twice the power supply voltage, significantly improving the adaptability of this invention to low power supply voltages. Based on its balanced feedback circuit, the bias current source circuit generates a bias current unaffected by power supply voltage changes, while simultaneously reducing the system's power supply voltage requirements. The voltage regulator circuit generates a reference voltage unaffected by temperature changes; its main MOSFETs operate in the subthreshold region, making the voltage regulator circuit's power supply voltage requirements extremely low. Therefore, the integrated power drive control chip using the above-mentioned voltage regulator circuit exhibits significantly enhanced adaptability to battery voltage, more stable load output, and better battery life for the circuit system using this integrated power drive control chip circuit. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the overall principle and structure of the present invention;

[0028] Figure 2 This is a schematic diagram of the principle structure of the voltage regulator circuit of the present invention;

[0029] Figure 3 This is a schematic diagram of the principle structure of the power supply boosting circuit of the present invention;

[0030] Figure 4 This is a schematic diagram of the bias current source circuit of the present invention.

[0031] Figure 5 This is a schematic diagram of the principle structure of the voltage regulator circuit of the present invention;

[0032] Figure 6 This is a schematic diagram of the package structure of the integrated power drive control chip of the present invention;

[0033] Figure 7 This is a typical application circuit diagram of the integrated power drive control chip of the present invention.

[0034] Explanation of reference numerals in the attached figures:

[0035] 1-Voltage regulator circuit; 2-Drive output circuit; 3-Battery charging circuit; 4-Control unit; 5-Button circuit; 6-Indicator circuit; 11-Power supply boost circuit; 12-Bias current source circuit; 13-Voltage regulator circuit; 111-Non-phase boost circuit; 112-Inverting boost circuit; 121-Balance feedback circuit; 122-Bias output circuit; 131-Mirror circuit; 132-Load circuit. Detailed Implementation

[0036] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] like Figure 1 As shown, this invention provides an integrated power drive control chip circuit with high adaptability to power supply voltage, including a control unit 4, a battery charging circuit 3, a voltage regulator circuit 1, a drive output circuit 2, an indicator circuit 6, and a button circuit 5. The control unit 4 is connected to the battery charging circuit 3 and the drive output circuit 2. The output terminal of the battery charging circuit 3 is connected to the battery port. The input terminal of the voltage regulator circuit 1 is connected to the battery port, and its output terminal supplies power to the drive output circuit 2. The output terminal of the drive output circuit 2 is connected to the motor power port to supply power to the load motor. The indicator circuit 6 and the button circuit 5 are connected to the control unit 4. The indicator circuit 6 is connected to the LED output port, and the button circuit 5 is connected to the switch input port.

[0038] like Figure 2 As shown, the voltage regulator circuit 1 includes a power supply boost circuit 11, a bias current source circuit 12, and a voltage regulator circuit 13.

[0039] The power supply boost circuit 11 is connected to the bias current source circuit 12 and the voltage regulator circuit 13, respectively. The power supply boost circuit 11 generates twice the power supply voltage BAT and transmits it as the operating voltage to the bias current source circuit 12 and the voltage regulator circuit 13. The bias current source circuit 12 is connected to the voltage regulator circuit 13. The bias current source circuit 12 generates a bias current that is unaffected by changes in the power supply voltage and transmits it to the voltage regulator circuit 13 to maintain the normal operation of the voltage regulator circuit 13. The voltage regulator circuit 13 generates a reference voltage that is unaffected by temperature changes and outputs it to the drive output circuit 2 through the port.

[0040] The power supply boost circuit 11 includes port BYDC. The bias current source circuit 12 includes ports SVDC, JXBA, and VREB. The voltage regulator circuit 13 includes ports JZDC, PZBA, and VREF.

[0041] Ports BYDC and SVDC are connected to transmit the boosted operating voltage Vtdd. Ports BYDC and JZDC are connected to transmit the boosted operating voltage Vtdd. Ports JXBA and PZBA are connected to transmit the bias current Ibsn. Port VREF is used to output the reference voltage Vre generated by the system. Ports VREF and VREB are connected to transmit the bias reference voltage Vre.

[0042] like Figure 2 As shown, the power supply boost circuit 11 includes a positive boost circuit 111 and an inverting boost circuit 112.

[0043] The positive boost circuit 111 and the negative boost circuit 112 are connected and operate in a complementary manner, jointly maintaining the output voltage of the power supply boost circuit 11 at twice the power supply voltage to the bias current source circuit 12 and the voltage regulator circuit 13. When the positive boost circuit 111 is boosting the output voltage, the negative boost circuit 112 is in a charging state. When the positive boost circuit 111 is in a charging state, the negative boost circuit 112 is boosting the output voltage.

[0044] like Figure 2 As shown, the bias current source circuit 12 includes a balanced feedback circuit 121 and a bias output circuit 122.

[0045] The balanced feedback circuit 121 is connected to the bias output circuit 122. Based on its negative feedback, the balanced feedback circuit 121 ensures that the bias current Ibsn generated by the bias output circuit 122 is unaffected by changes in the power supply voltage. The bias output circuit 122 generates the bias current Ibsn under low power consumption conditions and outputs it through a port.

[0046] like Figure 2 As shown, the voltage regulator circuit 13 includes a mirror circuit 131 and a load circuit 132.

[0047] The mirror circuit 131 is connected to the load circuit 132. The mirror circuit 131 replicates the received bias current to each branch of the load circuit 132, maintaining the normal operation of the load circuit 132. The load circuit 132 generates a reference voltage Vre that is unaffected by temperature changes and outputs it to the subsequent power-consuming modules through the port.

[0048] like Figure 3 As shown, the positive phase boost circuit 111 includes a positive phase charging circuit and a positive phase discharging circuit.

[0049] The positive charging circuit is connected to the positive discharging circuit. The positive charging circuit charges capacitor C1 during the first half-cycle of the clock control signal. During the second half-cycle of the clock control signal, the positive discharging circuit makes the voltage of capacitor C1 twice the power supply voltage and outputs this capacitor voltage through the port.

[0050] The positive charging circuit includes MOSFET M3, MOSFET M7, port CKCN2, port CKCP2, and capacitor C1.

[0051] The drain of MOSFET M3 is connected to the drain of MOSFET M1, the gate of MOSFET M3 is connected to port CKCN2, and the source of MOSFET M3 is grounded. The source of MOSFET M7 is connected to power supply BAT, the gate of MOSFET M7 is connected to port CKCP2, and the drain of MOSFET M7 is connected to the drain of MOSFET M8. The left end of capacitor C1 is connected to the drain of MOSFET M3, and the right end of capacitor C1 is connected to the drain of MOSFET M7.

[0052] MOSFET M7 is a P-type MOSFET with its gate connected to port CKCP2, and MOSFET M3 is an N-type MOSFET with its gate connected to port CKCN2. Port CKCP2 receives clock control signal S1, and port CKCN2 receives clock control signal S2. Clock control signal S2 is the inverted version of clock control signal S1. During the first half-cycle of clock control signals S1 and S2, MOSFETs M7 and M3 are in the ON state, and power supply BAT charges capacitor C1 until its voltage equals the power supply voltage. During the second half-cycle of clock control signals S1 and S2, MOSFETs M7 and M3 are in the OFF state, and the charging path from power supply BAT to capacitor C1 is broken.

[0053] The positive discharge circuit includes MOSFETs M1, M2, M8, and M9, capacitor C1, port CKCN1, port CKCN3, port CKCP1, port CKCP3, and port BYDC.

[0054] The source of MOSFET M1 is connected to power supply BAT, the gate of MOSFET M1 is connected to port CKCN1, and the drain of MOSFET M1 is connected to the drain of MOSFET M3. The drain of MOSFET M2 is connected to the source of MOSFET M1, the gate of MOSFET M2 is connected to port CKCP1, and the source of MOSFET M2 is connected to the drain of MOSFET M1. The drain of MOSFET M8 is connected to the source of MOSFET M9, the gate of MOSFET M8 is connected to port CKCP3, and the source of MOSFET M8 is connected to the drain of MOSFET M9. The source of MOSFET M9 is connected to the drain of MOSFET M7, the gate of MOSFET M9 is connected to port CKCN3, and the drain of MOSFET M9 is connected to port BYDC. The left end of capacitor C1 is connected to the drain of MOSFET M1, and the right end of capacitor C1 is connected to the drain of MOSFET M8.

[0055] MOSFET M1 is a P-type MOSFET with its gate connected to port CKCN1. MOSFET M2 is an N-type MOSFET with its gate connected to port CKCP1. MOSFET M8 is an N-type MOSFET with its gate connected to port CKCP3. MOSFET M9 is a P-type MOSFET with its gate connected to port CKCN3. The connection of MOSFETs M1 and M2 forms a control switch structure that can suppress power supply voltage fluctuations, and the connection of MOSFETs M8 and M9 forms a control switch structure that can suppress power supply voltage fluctuations. This control switch structure effectively improves the power supply rejection ratio of the power supply boost circuit 11.

[0056] Ports CKCP1 and CKCP3 receive clock control signal S1, and ports CKCN1 and CKCN3 receive clock control signal S2. During the first half-cycle of clock control signals S1 and S2, the control switch formed by MOSFETs M1 and M2, as well as the control switch formed by MOSFETs M8 and M9, is off, cutting off the discharge path of capacitor C1. During the second half-cycle of clock control signals S1 and S2, the control switch formed by MOSFETs M1 and M2, as well as the control switch formed by MOSFETs M8 and M9, is on, opening the discharge path of capacitor C1. At this time, the voltage of power supply BAT is applied to the negative terminal of capacitor C1, making the voltage at the positive terminal of capacitor C1 twice the voltage of power supply BAT. This higher voltage is output through port BYDC.

[0057] like Figure 3 As shown, the inverting boost circuit 112 includes an inverting charging circuit and an inverting discharging circuit.

[0058] The inverting charging circuit is connected to the inverting discharging circuit. During the first half-cycle of the clock control signal, the inverting discharging circuit makes the voltage across capacitor C2 twice the power supply voltage and outputs this voltage through the port. During the second half-cycle of the clock control signal, the inverting charging circuit charges capacitor C2.

[0059] The inverting charging circuit includes MOSFET M4, MOSFET M12, port CKCP4, port CKCN6, and capacitor C2.

[0060] The drain of MOSFET M4 is connected to the drain of MOSFET M5, the gate of MOSFET M4 is connected to port CKCP4, and the source of MOSFET M4 is grounded. The source of MOSFET M12 is connected to power supply BAT, the gate of MOSFET M12 is connected to port CKCN6, and the drain of MOSFET M12 is connected to the drain of MOSFET M10. The left end of capacitor C2 is connected to the drain of MOSFET M4, and the right end of capacitor C2 is connected to the drain of MOSFET M12.

[0061] MOSFET M4 is an N-type MOSFET, with its gate connected to port CKCP4. MOSFET M12 is a P-type MOSFET, with its gate connected to port CKCN6. Port CKCP4 receives clock control signal S1, and port CKCN6 receives clock control signal S2. Clock control signal S2 is the inverted version of clock control signal S1. During the first half-cycle of clock control signals S1 and S2, MOSFETs M4 and M12 are off, and the charging path from power supply BAT to capacitor C2 is interrupted. During the second half-cycle of clock control signals S1 and S2, MOSFETs M4 and M12 are on, and power supply BAT charges capacitor C2 until its voltage equals the power supply voltage.

[0062] The reverse discharge circuit includes MOSFETs M5, M6, M10, and M11, capacitor C2, port CKCN4, port CKCN5, port CKCP5, and port CKCP6.

[0063] The source of MOSFET M5 is connected to power supply BAT, the gate of MOSFET M5 is connected to port CKCP6, and the drain of MOSFET M5 is connected to the drain of MOSFET M4. The drain of MOSFET M6 is connected to the source of MOSFET M5, the gate of MOSFET M6 is connected to port CKCN5, and the source of MOSFET M6 is connected to the drain of MOSFET M5. The drain of MOSFET M10 is connected to the source of MOSFET M11, the gate of MOSFET M10 is connected to port CKCN4, and the source of MOSFET M10 is connected to the drain of MOSFET M11. The source of MOSFET M11 is connected to the drain of MOSFET M12, the gate of MOSFET M11 is connected to port CKCP5, and the drain of MOSFET M11 is connected to port BYDC. The left end of capacitor C2 is connected to the drain of MOSFET M5, and the right end of capacitor C2 is connected to the drain of MOSFET M10.

[0064] MOSFET M5 is a P-type MOSFET with its gate connected to port CKCP6. MOSFET M6 is an N-type MOSFET with its gate connected to port CKCN5. MOSFET M10 is an N-type MOSFET with its gate connected to port CKCN4. MOSFET M11 is a P-type MOSFET with its gate connected to port CKCP5. The connection of MOSFETs M5 and M6 forms a control switch structure that can suppress power supply voltage fluctuations, and the connection of MOSFETs M10 and M11 forms a control switch structure that can suppress power supply voltage fluctuations. This control switch structure effectively improves the power supply rejection ratio of the power supply boost circuit 11.

[0065] Ports CKCP6 and CKCP5 receive clock control signal S1, and ports CKCN5 and CKCN4 receive clock control signal S2. During the first half-cycle of clock control signals S1 and S2, the control switch formed by MOSFETs M5 and M6 is on, and the control switch formed by MOSFETs M10 and M11 is also on, thus opening the discharge path of capacitor C2. At this time, the voltage of power supply BAT is applied to the negative terminal of capacitor C2, making the voltage at the positive terminal of capacitor C2 twice the voltage of power supply BAT. This higher voltage is output through port BYDC. During the second half-cycle of clock control signals S1 and S2, the control switch formed by MOSFETs M5 and M6 is off, and the control switch formed by MOSFETs M10 and M11 is also off, thus closing the discharge path of capacitor C2.

[0066] The voltage twice that of the power supply BAT output by the inverting boost circuit 112 in the first half of the clock control signal cycle, together with the voltage twice that of the power supply BAT output by the non-inverting boost circuit 111 in the first and second cycles of the clock control signal cycle, constitute the working voltage Vtdd output by the power supply boost circuit 11 throughout the entire clock control signal cycle, and the working voltage Vtdd is twice the voltage of the power supply BAT.

[0067] like Figure 4 As shown, the balanced feedback circuit 121 includes MOSFETs M13, M14, M15, and M16, and port SVDC.

[0068] The source of MOSFET M13 is connected to port SVDC, and the gate of MOSFET M13 is connected to its drain. The drain of MOSFET M13 is connected to the drain of MOSFET M14. The drain of MOSFET M14 is connected to the gate of MOSFET M13, and the gate of MOSFET M14 is connected to the drain of MOSFET M18. The source of MOSFET M14 is connected to the drain of MOSFET M15. The drain of MOSFET M15 is connected to the source of MOSFET M14, and the gate of MOSFET M15 is connected to its drain. The source of MOSFET M15 is grounded. The drain of MOSFET M16 is connected to its source, and the gate of MOSFET M16 is connected to the gate of MOSFET M14. The source of MOSFET M16 is grounded.

[0069] Port SVDC is connected to the source of MOSFET M13, providing the boosted operating voltage Vtdd to the balanced feedback circuit 121. MOSFET M15 has a diode connection and functions as a resistor in the balanced feedback circuit 121. The source and drain of MOSFET M16 are connected, and it functions as a capacitor in the balanced feedback circuit 121. The connection structure of MOSFETs M15 and M16 maintains the stability of the output current of the bias current source circuit 12.

[0070] MOSFETs M13 and M14, together with MOSFETs M19, M20, M21, and M18 in the bias output circuit 122, form a negative feedback loop, providing negative feedback gain for the bias current source circuit 12. MOSFETs M13 and M14, together with MOSFETs M17 and M18 in the bias output circuit 122, form a positive feedback loop, providing positive feedback gain for the bias current source circuit 12. The negative feedback gain in the bias current source circuit 12 is greater than the positive feedback gain to maintain the continuous and stable operation of the bias current source circuit 12. The expression for the negative feedback gain provided by the negative feedback loop formed by MOSFETs M13, M14, M19, M20, M21, and M18 is shown below.

[0071] ;

[0072] In the formula, Gm19 is the transconductance of MOSFET M19, Rm19 is the impedance of MOSFET M19, Gm18 is the transconductance of MOSFET M18, Rm18 is the impedance of MOSFET M18, Gm14 is the transconductance of MOSFET M14, and Rm14 is the impedance of MOSFET M14.

[0073] Based on the connection relationship between the balanced feedback circuit 121 and the bias output circuit 122, and their circuit structures, the expressions for the small-signal bias current ibsn, the small-signal gate voltage vm18 of MOSFET M18, the small-signal gate voltage vm14 of MOSFET M14, and the small-signal gate voltage vm19 of MOSFET M19 can be derived as follows.

[0074] ;

[0075] ;

[0076] ;

[0077] ;

[0078] In the above formula, Gm19 is the transconductance of MOSFET M19, Vtdd is the operating voltage of the balanced feedback circuit 121, rm19 is the small-signal equivalent resistance of MOSFET M19, Gm18 is the transconductance of MOSFET M18, rm18 is the small-signal equivalent resistance of MOSFET M18, Gm14 is the transconductance of MOSFET M14, and rm14 is the small-signal equivalent resistance of MOSFET M14.

[0079] The following results can be further derived from the expressions for the small-signal bias current ibsn, the small-signal gate voltage vm18 of MOSFET M18, the small-signal gate voltage vm14 of MOSFET M14, and the small-signal gate voltage vm19 of MOSFET M19.

[0080] ;

[0081] As can be seen from the above formula, under the action of the balanced feedback circuit 121, the bias current ibsn generated by the bias output circuit 122 is not affected by the change of the operating voltage Vtdd, and has strong stability. The circuit structure included in the bias current source circuit 12 avoids the use of operational amplifier circuits with high power supply voltage requirements. Under the premise of meeting the circuit performance requirements, it simplifies the circuit and significantly reduces the circuit's power supply voltage requirements.

[0082] like Figure 4 As shown, the bias output circuit 122 includes MOSFETs M17, M18, M19, M20, and M21, port JXBA, and port VREB.

[0083] The source of MOSFET M17 is connected to port SVDC, the gate of MOSFET M17 is connected to the gate of MOSFET M19, and the drain of MOSFET M17 is connected to the drain of MOSFET M18. The drain of MOSFET M18 is connected to the drain of MOSFET M17, the gate of MOSFET M18 is connected to the gate of MOSFET M20, and the source of MOSFET M18 is grounded. The source of MOSFET M19 is connected to the source of MOSFET M17, the gate of MOSFET M19 is connected to the gate of MOSFET M13, the gate of MOSFET M19 is connected to port JXBA, and the drain of MOSFET M19 is connected to the drain of MOSFET M20. The drain of MOSFET M20 is connected to the drain of MOSFET M19, the gate of MOSFET M20 is connected to the drain of MOSFET M20, and the source of MOSFET M20 is connected to the drain of MOSFET M21. The drain of MOSFET M21 is connected to the source of MOSFET M20, the gate of MOSFET M21 is connected to port VREB, and the source of MOSFET M21 is grounded.

[0084] Both MOSFETs M18 and M20 operate in the subthreshold region. The expressions for the gate-source voltage Vgsm18 of MOSFET M18 and the gate-source voltage Vgsm20 of MOSFET M20 are shown below.

[0085] ;

[0086] ;

[0087] In the above formula, Vthm18 is the threshold voltage of MOSFET M18, Ka is the subthreshold slope factor of MOSFET, UT is the thermal voltage, Idm18 is the drain current of MOSFET M18, u is the electron mobility, Cox is the capacitance per unit area of ​​the gate oxide layer of MOSFET, Sm18 is the aspect ratio of MOSFET M18, Vthm20 is the threshold voltage of MOSFET M20, Idm20 is the drain current of MOSFET M20, and Sm20 is the aspect ratio of MOSFET M20.

[0088] The gate of MOSFET M21 is connected to port VREB, and receives the reference voltage Vre output by the system as a bias voltage through port VREB. Under the action of the bias voltage, MOSFET M21 operates in the deep transistor region, and its on-resistance Rdsm21 is expressed as follows.

[0089] ;

[0090] In the above formula, u is the electron mobility, Cox is the capacitance per unit area of ​​the gate oxide layer of the MOS transistor, Sm21 is the aspect ratio of the MOS transistor M21, Vgsm21 is the gate-source voltage of the MOS transistor M21, and Vthm21 is the threshold voltage of the MOS transistor M21.

[0091] If MOSFETs M18 and M20 have the same threshold voltage, then the expression for the drain-source voltage Vdsm21 of MOSFET M21 is as follows.

[0092] ;

[0093] In the above formula, Vgsm18 is the gate-source voltage of MOSFET M18, Vgsm20 is the gate-source voltage of MOSFET M20, Ka is the subthreshold slope factor of MOSFET, UT is the thermal voltage, Idm18 is the drain current of MOSFET M18, Sm20 is the width-to-length ratio of MOSFET M20, Idm20 is the drain current of MOSFET M20, and Sm18 is the width-to-length ratio of MOSFET M18.

[0094] The bias output circuit 122 outputs the current flowing through the drain and source of the MOSFET M21 as the bias current Ibsn. The expression for the bias current Ibsn is as follows.

[0095] ;

[0096] In the formula, Vdsm21 is the drain-source voltage of MOSFET M21, Rdsm21 is the on-resistance of MOSFET M21 when it is operating in the deep transistor region, Ka is the subthreshold slope factor of MOSFET, UT is the thermal voltage, Idm18 is the drain current of MOSFET M18, Sm20 is the width-to-length ratio of MOSFET M20, Idm20 is the drain current of MOSFET M20, and Sm18 is the width-to-length ratio of MOSFET M18.

[0097] The bias current Ibsn flows through the branch containing the drain and source of MOSFET M19. The gate of MOSFET M19 is connected to port JXBA, and MOSFET M19 transmits the bias current Ibsn to the voltage regulator circuit 13 in a mirror manner through port JXBA.

[0098] like Figure 5 As shown, the mirror circuit 131 includes MOSFET M22, MOSFET M25, MOSFET M28, port PZBA, and port JZDC.

[0099] The source of MOSFET M22 is connected to the source of MOSFET M25, the gate of MOSFET M22 is connected to port PZBA, and the drain of MOSFET M22 is connected to the drain of MOSFET M23. The source of MOSFET M25 is connected to the source of MOSFET M28, the gate of MOSFET M25 is connected to the gate of MOSFET M22, and the drain of MOSFET M25 is connected to the drain of MOSFET M26. The source of MOSFET M28 is connected to port JZDC, the gate of MOSFET M28 is connected to the gate of MOSFET M25, and the drain of MOSFET M28 is connected to the drain of MOSFET M29.

[0100] The gates of MOSFETs M22, M25, and M28 are connected to port PZBA. MOSFETs M22, M25, and M28 receive bias current Ibsn through port PZBA in a mirror manner, and transmit the bias current source to the branch where their drain and source are located, thus biasing the MOSFETs in that branch.

[0101] The sources of MOSFETs M22, M25, and M28 are connected to port JZDC. MOSFETs M22, M25, and M28 receive the operating voltage Vtdd through port JZDC to maintain the normal operation of the load circuit 132.

[0102] like Figure 5As shown, the load circuit 132 includes MOSFETs M23, M24, M26, M27, M29, M30, M31, and port VREF.

[0103] The drain of MOSFET M23 is connected to the drain of MOSFET M22, the gate of MOSFET M23 is connected to the drain of MOSFET M23, and the source of MOSFET M23 is connected to the drain of MOSFET M24. The drain of MOSFET M24 is connected to the source of MOSFET M23, the gate of MOSFET M24 is connected to the gate of MOSFET M23, and the source of MOSFET M24 is grounded. The drain of MOSFET M26 is connected to the drain of MOSFET M25, the gate of MOSFET M26 is connected to the drain of MOSFET M26, and the source of MOSFET M26 is connected to the drain of MOSFET M27. The drain of MOSFET M27 is connected to the source of MOSFET M26, the gate of MOSFET M27 is connected to the gate of MOSFET M26, and the source of MOSFET M27 is connected to the source of MOSFET M23.

[0104] The drain of MOSFET M29 is connected to the drain of MOSFET M28, the gate of MOSFET M29 is connected to the drain of MOSFET M29, and the source of MOSFET M29 is connected to the source of MOSFET M26. The source of MOSFET M30 is connected to the drain of MOSFET M28, the gate of MOSFET M30 is connected to the drain of MOSFET M30, and the drain of MOSFET M30 is connected to the gate of MOSFET M31. The drain of MOSFET M31 is connected to the source of MOSFET M31, the gate of MOSFET M31 is connected to port VREF, and the source of MOSFET M31 is grounded.

[0105] MOSFETs M23, M24, M26, M27, and M29 all operate in the subthreshold region. The expression for the gate-source voltage Vgsm29 of MOSFET M29 is shown below.

[0106] ;

[0107] In the above formula, Vthm29 is the threshold voltage of MOSFET M29, Ka is the subthreshold slope factor of MOSFET, UT is the thermal voltage, Idm29 is the drain current of MOSFET M29, u is the electron mobility, Cox is the capacitance per unit area of ​​the gate oxide layer of MOSFET, and Sm29 is the aspect ratio of MOSFET M29.

[0108] Since the temperature characteristic of the threshold voltage Vthm29 is Vthm29(T0) - fa × (T - T0), where T is the temperature, T0 is the room temperature, Vthm29(T0) is the threshold voltage of MOSFET M29 at room temperature, and fa is the first derivative of the threshold voltage Vthm29 with respect to temperature, it is known that the threshold voltage Vthm29 exhibits CTAT (Complementary to Absolute Temperature) characteristics. Furthermore, since the threshold voltage Vthm29 dominates the gate-source voltage Vgsm29 of MOSFET M29, the gate-source voltage Vgsm29 of MOSFET M29 also exhibits CTAT characteristics.

[0109] The connection structure between MOSFETs M30 and M31 provides a low-pass filter, with the source of MOSFET M30 connected to the drain of MOSFET M29. The drain voltage of MOSFET M29 serves as the system's reference voltage Vre. After being filtered by the connection structure of MOSFETs M30 and M31, it is output through port VREF. The expression for the reference voltage Vre is shown below.

[0110] ;

[0111] In the above formula, Vgsm29 is the gate-source voltage of MOSFET M29, Vgsm26 is the gate-source voltage of MOSFET M26, Vgsm27 is the gate-source voltage of MOSFET M27, Vgsm23 is the gate-source voltage of MOSFET M23, Vgsm24 is the gate-source voltage of MOSFET M24, Ka is the subthreshold slope factor of MOSFET, UT is the thermal voltage, Sm26 is the width-to-length ratio of MOSFET M26, Sm23 is the width-to-length ratio of MOSFET M23, Sm27 is the width-to-length ratio of MOSFET M27, and Sm24 is the width-to-length ratio of MOSFET M24.

[0112] Since the thermal voltage UT is expressed as k×T / q, where k is the Boltzmann constant, T is the temperature, and q is the unit charge, the thermal voltage UT exhibits PTAT (Proportional to Absolute Temperature) characteristics. Therefore, the second term in the expression for the reference voltage Vre also exhibits PTAT characteristics.

[0113] Because the first term in the expression for the reference voltage Vre has CTAT characteristics, while the second term has PTAT characteristics, the reference voltage Vre, based on temperature coefficient complementarity, is essentially unaffected by temperature changes and exhibits good stability.

[0114] The voltage regulator circuit 13 generates the reference voltage Vre with a relatively simple circuit structure, and its main MOSFETs all operate in the subthreshold region. Therefore, the voltage regulator circuit 13 has low power consumption and extremely low power supply voltage requirements.

[0115] like Figure 6 As shown, in actual use, the control unit 4, battery charging circuit 3, voltage regulator circuit 1, drive output circuit 2, indicator circuit 6, and button circuit 5 are packaged inside the integrated power drive control chip. They are connected to external power supplies, batteries, and drive motors via chip pins. The integrated power drive control chip uses an SOT23-6 package structure and has 6 pins. BAT is the battery pin, used to connect to the battery. The output of battery charging circuit 3 and the input of voltage regulator circuit 1 are connected to the BAT pin. GND is the ground pin. VIN is the power input pin, connected to the input of battery charging circuit 3. KEY is the button pin, connected to the output of button circuit 5 for connecting an external button. VM is the motor power pin, used to connect an external load motor. The output of drive output circuit 2 is connected to the VM pin. LED is the indicator pin, used to connect an external LED indicator. The output of indicator circuit 6 is connected to the LED pin.

[0116] Integrated power drive control chips can be used in circuits that have rechargeable batteries and require motor drive control, such as rechargeable shavers, facial cleansing devices, and portable water pumps. One typical application is... Figure 7 As shown, in this embodiment, VIN is the input power supply, BAT is connected to the positive terminal of the battery, C101 and C102 are used as filter capacitors for the input power supply and the battery power supply, and capacitors C101 and C102 can be selected from 1uF to 10uF. L1 and L2 are LED indicator lights connected to the LED pin, K1 is the switch button, and the VM pin is connected to the load motor.

[0117] While the disclosure is as stated above, its scope of protection is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of this disclosure, and all such changes and modifications will fall within the protection scope of this invention.

Claims

1. An integrated power drive control chip circuit with high adaptability to power supply voltage, comprising a control unit (4), a battery charging circuit (3), a voltage regulator circuit (1), and a drive output circuit (2), wherein the control unit (4) is connected to the battery charging circuit (3) and the drive output circuit (2) respectively, the output terminal of the battery charging circuit (3) is connected to the battery port, the input terminal of the voltage regulator circuit (1) is connected to the battery port, and the output terminal supplies power to the drive output circuit (2), and the output terminal of the drive output circuit (2) is connected to the motor power port to supply power to the load motor, characterized in that, The voltage regulator circuit (1) includes a power supply boost circuit (11), a bias current source circuit (12), and a voltage regulator circuit (13). The power supply boost circuit (11) is connected to the bias current source circuit (12) and the voltage regulator circuit (13) respectively. The power supply boost circuit (11) generates twice the voltage of the battery power supply and transmits it as the working voltage to the bias current source circuit (12) and the voltage regulator circuit (13). The bias current source circuit (12) is connected to the voltage regulator circuit (13). The bias current source circuit (12) generates a bias current and transmits it to the voltage regulator circuit (13) to maintain the normal operation of the voltage regulator circuit (13). The voltage regulator circuit (13) generates a reference voltage and outputs it to the input terminal of the drive output circuit (2) through the port; The power supply boost circuit (11) includes a positive boost circuit (111) and an inverting boost circuit (112). The positive boost circuit (111) is connected to the negative boost circuit (112). The positive boost circuit (111) and the negative boost circuit (112) are complementary and work together to maintain the output of the power supply boost circuit (11) to the bias current source circuit (12) and the voltage regulator circuit (13) at twice the power supply voltage. The bias current source circuit (12) includes a balanced feedback circuit (121) and a bias output circuit (122); The balance feedback circuit (121) is connected to the bias output circuit (122). Based on its negative feedback effect, the balance feedback circuit (121) makes the bias current Ibsn generated by the bias output circuit (122) unaffected by the power supply voltage change. The bias output circuit (122) generates a bias current Ibsn under low power conditions and outputs it through the port; The voltage regulator circuit (13) includes a mirror circuit (131) and a load circuit (132). The mirror circuit (131) is connected to the load circuit (132). The mirror circuit (131) replicates the received bias current to each branch of the load circuit (132) to maintain the normal operation of the load circuit (132). The load circuit (132) generates a reference voltage Vre that is unaffected by temperature changes and outputs it to the drive output circuit (2) through the port.

2. The integrated power drive control chip circuit with high adaptability to power supply voltage according to claim 1, characterized in that, When the positive boost circuit (111) is boosting output, the negative boost circuit (112) is in the charging state; when the positive boost circuit (111) is in the charging state, the negative boost circuit (112) is boosting output.

3. The integrated power drive control chip circuit with high adaptability to power supply voltage according to claim 2, characterized in that, The positive phase boost circuit (111) includes a positive phase charging circuit and a positive phase discharging circuit; The positive phase charging circuit is connected to the positive phase discharging circuit; the positive phase charging circuit charges capacitor C1 in the first half cycle of the clock control signal. In the second half of the clock control signal cycle, the positive discharge circuit makes the voltage of capacitor C1 twice the power supply voltage and outputs the capacitor voltage through the port.

4. The integrated power drive control chip circuit with high adaptability to power supply voltage according to claim 2, characterized in that, The inverting boost circuit (112) includes an inverting charging circuit and an inverting discharging circuit; The reverse charging circuit is connected to the reverse discharging circuit; during the first half of the clock control signal cycle, the reverse discharging circuit makes the voltage of capacitor C2 twice the power supply voltage and outputs the capacitor voltage through the port. The inverting charging circuit charges capacitor C2 during the second half of the clock control signal cycle.

5. The integrated power drive control chip circuit with high adaptability to power supply voltage according to claim 1, characterized in that, It also includes an indicator circuit (6) and a button circuit (5) connected to the control unit (4). The indicator circuit (6) is connected to the LED output port, and the button circuit (5) is connected to the switch input port.

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