A data alignment method, system, electronic device and storage medium

Abstract

The application discloses a data alignment method and system, an electronic device and a storage medium, and relates to the field of data processing. The method is applied to a transmission link with multiple data channels, and comprises the following steps: for each data channel, at different delay times, detecting whether the sampling edge of a clock signal is in a stable region of a transmission signal based on a preset training code; if yes, and the latched value obtained based on the sampling edge at the current delay time belongs to a first set, recording the detection result as a first flag; otherwise, recording the detection result as a second flag; sorting the first flags of the data channels according to the order of the delay times to obtain a first continuous interval formed by continuous first flags; obtaining a common delay time interval as a first common interval; and delaying the clock signal based on the delay time at the center of the first common interval to correct the phase deviation of any data channel in the transmission link.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of data processing, and particularly relates to a data alignment method and system, an electronic device and a storage medium. BACKGROUND

[0002] A multi-channel transmission link based on differential signals or single-ended signals for data transmission, for a transmission signal waveform in a single data channel, as shown in FIGS. 1 and 2, there are stable regions and transition regions in a signal period. For a transmission link triggered by an external clock signal for sampling (for example, LVDS, Low Voltage Differential Signaling), when the rising edge or falling edge of the clock signal is in the transition region, it is easy to cause errors in the collected data. Therefore, during data transmission, the sampling points of the clock signal are required to fall in the stable region of the transmission signal of each data channel. Figure 1 2 Due to a certain delay of the data transmission line and the data receiving end, it is easy to cause different phase deviations between the clock signal and the transmission signal of each data channel. In order to correct the phase deviation between the clock signal and the transmission signal, so as to ensure that the sampling point of the clock signal is in the stable region. Therefore, at the initial power-on of the transmission link, the link training is performed by delay scanning. However, when the delay step for adjusting the delay time exceeds the transition region, it is easy to fail to detect the transition region in the delay scanning process, so that there is a transition region in the stable time window scanned, resulting in errors in the data alignment result.

[0003] Therefore, there is an urgent need for a data alignment scheme applied to multiple data channels, which avoids the error of aligning the sampling edge of the clock signal to the transition region on the basis of correcting the phase deviation between the clock signal and the transmission signal.

[0004] Therefore, there is an urgent need for a data alignment scheme applied to multiple data channels, which avoids the error of aligning the sampling edge of the clock signal to the transition region on the basis of correcting the phase deviation between the clock signal and the transmission signal. SUMMARY

[0005] The data alignment method, system, electronic device and storage medium provided by the application avoid the error of aligning the sampling edge of the clock signal to the transition region on the basis of correcting the phase deviation between the clock signal and the differential signal.

[0006] To achieve the above object, the application provides the following technical scheme:

[0007] In the first aspect of the application, a data alignment method is provided, applied to a transmission link having multiple data channels, comprising

[0008] ​For each data channel, whether the sampling edge of the clock signal detected based on the preset training code is in a stable region of the transmission signal at different delay times is detected; if yes, and the latched value obtained based on the sampling edge at the current delay time belongs to a first set, a detection result is recorded as a first flag; otherwise, the detection result is recorded as a second flag; wherein, the preset training code has an even binary bit length; the first set is composed of values after the training code is cyclically shifted by an even number of bit positions, or is composed of values after the training code is cyclically shifted by an odd number of bit positions, and the values after the training code is cyclically shifted by the even number of bit positions and the odd number of bit positions are not overlapped; the stable region represents a delay time range in which the latched value obtained based on the sampling edge is constant;

[0009] The first flags of the respective data channels are sorted according to the order of the delay times, to obtain a first continuous interval formed by continuous first flags;

[0010] It is judged whether there is a delay time interval common to the first continuous intervals in all the data channels; if yes, the delay time interval common to the first continuous intervals is obtained as a first common interval;

[0011] The clock signal is delayed based on the delay time at the center of the first common interval, to correct the phase deviation of any data channel in the transmission link.

[0012] Optionally, after it is judged whether there is a delay time interval common to the first continuous intervals in all the data channels, the data alignment method further comprises:

[0013] If no, the delay time interval between adjacent first continuous intervals is obtained as a second continuous interval;

[0014] For each data channel, the delay time range of any first continuous interval in the data channel is obtained, and an interval equal in length to the delay time range is divided in the central region of each second continuous interval as a third continuous interval;

[0015] A delay time interval common to the first continuous intervals and / or the third continuous intervals in all the data channels is obtained as a second common interval;

[0016] The clock signal is delayed based on the delay time at the center of the second common interval, to correct the phase deviation of any data channel in the transmission link.

[0017] Optionally, after the first flags of the respective data channels are sorted according to the order of the delay times to obtain the first continuous intervals formed by continuous first flags, the data alignment method further comprises:

[0018] Delay the transmission signal according to the delay time corresponding to the first flag at the center of any first continuous interval in the data channel, to correct the phase deviation of any data channel in the transmission link.

[0019] Optionally, the step of detecting whether the sampling edge of the preset training code detection clock signal is in the stable region of the differential signal comprises:

[0020] Optionally, the step of inputting the fixed training code into each data channel at different delay times comprises:

[0021] Optionally, the step of inputting the fixed training code into each data channel at different delay times comprises:

[0022] Optionally, the step of inputting the fixed training code into each data channel at different delay times comprises:

[0023] Optionally, the data alignment method further comprises, before the step of inputting the fixed training code into each data channel at different delay times:

[0024] Optionally, the step of delaying the clock signal in the transmission link comprises:

[0025] Optionally, the delay interval between adjacent delay times is fixed, and the highest delay time is not less than 3 signal periods of the transmission signal.

[0026] In a second aspect of the present application, a data alignment system is provided, which is applied to a transmission link having a plurality of data channels, and comprises

[0027] The flag recording module is configured to, for each data channel, detect whether the sampling edge of the clock signal is in the stable region of the transmission signal at different delay times based on a preset training code, and record the detection result as a first flag if the sampling edge is in the stable region of the transmission signal at the current delay time and the latched value obtained based on the sampling edge at the current delay time belongs to a first set, or record the detection result as a second flag if the sampling edge is not in the stable region of the transmission signal at the current delay time or the latched value obtained based on the sampling edge at the current delay time does not belong to the first set; wherein the preset training code is a binary number with an even bit length, the first set is composed of values obtained by cyclically shifting the training code by an even number of bits or an odd number of bits, and the values obtained by cyclically shifting the training code by the even number of bits and the odd number of bits are not overlapped; and the stable region represents a delay time range in which the latched value obtained based on the sampling edge is constant.

[0028] a logo sorting module, configured to sort the first logo of each data channel according to the order of the delay time, to obtain a first continuous interval formed by the continuous first logos;

[0029] an interval judging module, configured to judge whether there is a common delay time interval in the first continuous intervals in all the data channels; if yes, the common delay time interval is obtained as a first common interval;

[0030] a deviation correcting module, configured to delay the clock signal based on the delay time at the center of the first common interval, to correct the phase deviation of any data channel in the transmission link.

[0031] Optionally, after judging whether there is a common delay time interval in the first continuous intervals in all the data channels, the interval judging module further comprises:

[0032] if no, the delay time interval between adjacent first continuous intervals is obtained as a second continuous interval;

[0033] The data alignment system further comprises:

[0034] an interval dividing module, configured to, for each data channel, obtain the delay time range of any first continuous interval in the data channel, and divide an interval equal in length to the delay time range at the center region of each second continuous interval as a third continuous interval;

[0035] an interval obtaining module, configured to obtain a delay time interval common to the first continuous intervals and / or the third continuous intervals in all the data channels as a second common interval;

[0036] a clock delaying module, configured to delay the clock signal based on the delay time at the center of the second common interval, to correct the phase deviation of any data channel in the transmission link.

[0037] In a third aspect of the present application, an electronic device is provided, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus;

[0038] the memory is configured to store a computer program;

[0039] the processor is configured to execute the program stored on the memory, to implement the data alignment method of any one of the first aspect.

[0040] In a fourth aspect of the present application, a computer readable storage medium is provided, the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the data alignment method of any one of the first aspect.

[0041] The beneficial effects of the present application are as follows:

[0042] The present application provides a data alignment method applied to a transmission link with multiple data channels, comprising

[0043] For each data channel, at different delay times, it is detected whether the sampling edge of the clock signal based on the preset training code is in the stable region of the transmission signal; if yes, and the latched value based on the sampling edge at the current delay time belongs to the first set, the detection result is recorded as the first flag; otherwise, the detection result is recorded as the second flag; wherein the preset training code has an even binary bit length; the first set is composed of the values after the training code is cyclically shifted by an even number of bits, or composed of the values after the training code is cyclically shifted by an odd number of bits, and the values after the training code is cyclically shifted by an even number of bits and an odd number of bits do not overlap; the stable region represents the delay time range in which the latched value based on the sampling edge is constant; the first flags of the respective data channels are sorted according to the order of the delay times, to obtain a first continuous interval formed by consecutive first flags; it is judged whether there is a common delay time interval in the first continuous intervals of all data channels; if yes, the common delay time interval is obtained as a first common interval; and the clock signal is delayed based on the delay time at the center of the first common interval, to correct the phase deviation of any data channel in the transmission link.

[0044] Based on the above processing, in the alignment method provided by the present application, the two judgment methods of stable region and latched value are combined to obtain the corresponding determination result at each delay time. Compared with the prior art, the present application additionally sets a judgment means for whether the latched value belongs to the first set, which can make the detection result flags corresponding to the stable regions in the adjacent two signal periods in the transmission link different.

[0045] Meanwhile, according to the limitation condition of the elements in the first set and the data latching characteristics of the transmission link, it can be known that the first continuous interval formed by consecutive first flags has a stable time window that completely falls in the stable region of the transmission link and does not contain the transition region.

[0046] For the first continuous interval formed by the intersection of the first continuous intervals of all data channels, the interval also definitely does not contain the transition region, and after the clock signal is delayed based on the delay time at the center of the first common interval, it can be ensured that the sampling edge of the clock signal is in the stable region in any data channel, and the phase deviation between the clock signal and the transmission signal is corrected.

[0047] Therefore, for the transmission link containing multiple data channels, the technical solution provided by the present application avoids the error that the sampling edge of the clock signal is in the transition region, on the basis of correcting the phase deviation between the clock signal and the transmission signal. BRIEF DESCRIPTION OF DRAWINGS

[0048] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0049] Figure 1 This is a schematic diagram of a differential signal provided in this application;

[0050] Figure 2 This is a schematic diagram of a single-ended signal provided in this application;

[0051] Figure 3 This is a schematic diagram of data sampling within a single data channel provided in this application;

[0052] Figure 4 This application provides a schematic diagram of existing data sampling for a differential link under different delay times;

[0053] Figure 5 This is a flowchart illustrating a data alignment method provided in this application;

[0054] Figure 6 This is a schematic diagram of a continuous interval provided in this application;

[0055] Figure 7 This is a schematic diagram illustrating the division of a first common area provided in this application;

[0056] Figure 8 This is a flowchart illustrating another data alignment method provided in this application;

[0057] Figure 9 This is a schematic diagram of a third continuous interval division provided in this application;

[0058] Figure 10 This is a schematic diagram illustrating the division of a second common area provided in this application;

[0059] Figure 11 This is a schematic diagram of the structure of a data alignment system provided in this application;

[0060] Figure 12 This is a structural diagram of an electronic device provided in this application. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.

[0062] For each data channel, the voltage change process on the two lines of the transmitted signal takes a certain amount of time. This results in two voltage change regions at the two ends and a constant voltage region in the middle within one signal cycle of the differential signal, which are respectively regarded as the transition region and the stable region. Figure 1 , 2 As shown. The transmitted signals in this application include differential signals and single-ended signals. In practical work, to reduce environmental noise interference, differential signals are usually used as the transmitted signals. The following description uses differential signals as an example to illustrate this application.

[0063] By utilizing the rising or falling edge of the clock signal, the signal receiver can stably acquire logic "1" and logic "0" states from a constant voltage region.

[0064] In the field of machine vision, most image sensors employ differential links containing multiple data channels for high-speed data transmission. Due to factors such as trace delays and process variations, skew exists between the data channels and clock channels at the receiving end of the differential link (i.e., a phase difference exists between the differential signal and the clock signal), and the degree of skew may vary. This causes the sampling edge of the clock signal to fall within the transition region of the differential signal in the differential link, leading to the risk of bit errors in data latching. The differential link provided in this application represents a communication link for data transmission based on differential signals.

[0065] Before performing effective data latching, the receiver of a differential link typically needs to align the differential link skew of each data channel to avoid the sampling edge of the clock signal being in the transition region of the differential signal in the differential link. This is known as link training.

[0066] A common link training method involves inputting a fixed training pattern into the differential link. The receiving end (e.g., FPGA) adjusts the idelay of the link channel or clock channel and determines whether the data is stable. This is followed by window scanning, and the idelay window interval from which stable data is obtained after scanning is used as the stable time window. Finally, considering that changes in temperature, voltage, and other factors can cause the stable time window to shift, the delay time of the differential signal or clock signal needs to be fixed at the center of the aforementioned stable time window interval. This improves the anti-interference capability of the trained differential link while obtaining stable latch values.

[0067] With the continuous development of signal transmission technology, the transition region width of differential signals in existing signal transmission systems is relatively narrow (i.e., the data transition time is shorter). However, the delay time setting at the differential link receiver has certain precision limitations; that is, there is a minimum delay step size for adjusting the delay time. For example... Figure 3As shown, in the link training process, there is a case that the delay step size exceeds the jump region.

[0068] When the unit delay step size for adjusting the delay time exceeds the jump region, in the process of scanning the stable time window, there may be a problem that the jump region cannot be scanned, resulting in that the stable time window scanned by the delay time contains the jump region, as shown. Figure 4 Specifically, Figure 4 The latch result represents the judgment result under the current delay amount in the link training mode by the delay clock signal. In the latch result, 1 corresponds to a flag that the data can be stably sampled based on the clock signal (i.e., the sampling edge falls in the stable region of the differential link) under the current delay time, and 0 corresponds to a flag that the data cannot be stably sampled based on the clock signal (i.e., the sampling edge falls in the jump region of the differential link) under the current delay time.

[0069] In the foregoing case, for the differential link containing multiple data channels, when aligned to the center of the data stable window, the sampling edge of the clock signal is extremely likely to be in the jump region, resulting in the failure of the differential link training, and the result of the data alignment has an error.

[0070] In order to avoid the existence of the above error, the present application provides a data alignment method applied to a transmission link with multiple data channels, as shown. Figure 5 The data alignment method comprises the following steps:

[0071] S1, for each data channel, under different delay times, it is detected whether the sampling edge of the clock signal is in the stable region of the transmission signal based on a preset training code; if yes, and the latch value obtained based on the sampling edge under the current delay time belongs to a first set, the detection result is recorded as a first flag; otherwise, the detection result is recorded as a second flag.

[0072] The preset training code is a binary value with an even bit length; the first set is composed of values after the training code is cyclically moved by an even number of bit positions, or composed of values after the training code is cyclically moved by an odd number of bit positions, and the values after the training code is cyclically moved by an even number of bit positions and an odd number of bit positions are not overlapped; and the stable region represents a delay time range in which the latch value obtained based on the sampling edge is constant.

[0073] S2, the first flags of the respective data channels are sorted according to the order of the delay times, to obtain a first continuous interval formed by the continuous first flags.

[0074] S3, it is judged whether there is a delay time interval common to the first continuous intervals in all the data channels. If yes, go to step S4.

[0075] S4, obtain the common delay time interval as a first common interval.

[0076] S5, delay the clock signal based on the delay time at the center of the first common interval to correct the phase deviation of any data channel in the transmission link.

[0077] Based on the above processing, in the alignment method provided by the application, the two judgment methods of stable region and latch value are combined to obtain the corresponding determination result under each delay time. Compared with the prior art, the application additionally sets a judgment means for whether the latch value belongs to the first set, which can make the detection results of the stable region in the adjacent two signal periods in the transmission link different.

[0078] At the same time, according to the limitation condition of the elements in the first set and the data latch characteristics of the transmission link, it can be known that the first continuous interval formed by the continuous first flags corresponds to a stable time window that completely falls in the stable region of the differential link and does not contain the transition region.

[0079] For the first continuous interval formed by the intersection of the first continuous intervals in all data channels, the interval does not contain the transition region, and after delaying the clock signal based on the delay time at the center of the first common interval, the sampling edge of the clock signal can be ensured to be in the stable region of any data channel, and the phase deviation between the clock signal and the transmission signal is corrected.

[0080] Therefore, for the transmission link containing multiple data channels, the technical solution provided by the application avoids the error that the sampling edge of the clock signal is in the transition region on the basis of correcting the phase deviation between the clock signal and the transmission signal.

[0081] For step S1, in order to ensure the accuracy of the delay scanning result, the delay interval between adjacent delay times is fixed. Specifically, different delay times can be obtained by increasing the fixed delay step length one by one, that is, the delay time of the application can be represented as the delay amount.

[0082] In one implementation, before step S1, the data alignment method provided by the application further includes the following contents:

[0083] Step one, based on the fixed delay step length, the clock signal in the transmission link is sequentially delayed. Thus, the working scene of different delay times is constructed. Wherein, sequentially delaying means increasing the delay time in units of delay step length according to the signal input order.

[0084] Meanwhile, the maximum delay time is not less than 3 signal periods, which is used to form at least one first continuous interval and at least one second continuous interval in each data channel during data alignment, so as to ensure the existence of the first common interval or the second common interval, and achieve the purpose of correcting the phase deviation. The signal period represents the clock period of the transmission signal in the transmission link. For example, in a differential link, the signal period represents the clock period of the differential signal, and can also be referred to as a unit interval, which can be directly calculated by the transmission rate of the differential link.

[0085] The training code is a binary number with multiple bits. For example, with 12 bits, the training code can be 101110101101; and for example, with 4 bits, the training code can be 1010.

[0086] In the present application, the bit length of the training code is even, i.e., the training code has an even number of bits, such as 4 bits, 8 bits, and 12 bits. The values of the training code after cyclic shift of even bits and odd bits do not overlap, i.e., the values of the training code after cyclic shift of even bits do not coincide with the values of the training code after cyclic shift of odd bits. For example, with a 12-bit training code 101110101101 and even-bit cyclic shift, the first set consists of the values after cyclic shift of 2 bits, 4 bits, 6 bits, 8 bits, 10 bits, and 12 bits, i.e., the elements in the first set are (111010110110, 101011011011, 101101101110, 110110111010, 011011101011, 101110101101).

[0087] In some embodiments, step S1 can include the following contents:

[0088] S101, for each data channel, at different delay times, whether the sampling edge of the clock signal is in the stable region of the differential signal is detected based on the preset training code; if yes, go to step S102; if no, go to step S103.

[0089] S102, whether the latch value obtained based on the sampling edge at the current delay time belongs to the first set is judged; if yes, go to step S104; if no, go to step S103.

[0090] S103, the detection result of the current delay time is recorded as the second flag.

[0091] S104, the detection result of the current delay time is recorded as the first flag.

[0092] The detection result is used to mark the data latch state at the current delay time. The first flag and the second flag can be represented by two different numbers or high and low levels. In this application, the first flag is represented by the number 1, and the second flag is represented by the number 0.

[0093] In step S101, for each data channel, the step of determining whether the sampling edge of the clock signal is in the stable region of the transmission link at different delay times based on the training code can include:

[0094] Step a: input the fixed training code into each data channel at different delay times.

[0095] Step b: based on the sampling edge of the clock signal, the training code is sampled multiple times at the receiving end of the transmission link to obtain multiple latch values. The sampling edge is the rising edge or the falling edge of the clock signal.

[0096] Step c: determine whether the multiple latch values are consistent; if yes, it indicates that the sampling edge of the clock signal is in the stable region of the transmission signal in the current data channel; if not, it indicates that the sampling edge of the clock signal is not in the stable region of the transmission signal in the current data channel.

[0097] Taking the differential link and the training code 101110101101 as an example, when the delay step is 0, the input end of the differential link is input into each data channel at different delay times formed by the fixed delay step. Then, based on the clock signal, the training code of each data channel is sampled multiple times continuously at the receiving end of the differential link, and multiple latch values corresponding to the training code can be obtained. The number of latch values is higher than the preset threshold, which can be 1000 or 2000, and the specific number is not limited in this application. Then, it is determined whether the multiple latch values are completely consistent. If yes, it indicates that the clock signal can be stably sampled, and it is in a stable state. If not, it indicates that the clock signal cannot be stably sampled, and the sampling edge is in the transition region.

[0098] It should be noted that the transmission link based on the clock signal has the following data latch characteristics: for two different delay times, if the clock signal can be stably sampled, and the delay times fall in two adjacent signal periods, then the difference between the latch value obtained at the latter delay time and the latch value obtained at the former delay time is that the former is cyclically shifted left by 1 bit. Specifically, taking the aforementioned 12-bit training code as an example, the latch value stably sampled at the former delay time is 101101110101, and the latch value stably sampled at the latter delay time is 110110111010.

[0099] Based on the data latch characteristics of the aforementioned differential link, step S1 adds a judgment process of whether the latch value belongs to the first set on the basis of the detection means of the conventional stable region. The elements in the aforementioned first set are set (obtained by cyclically shifting the training code by an even or odd number of bits, and the values of the training code cyclically shifted by an odd number of bits and the training code cyclically shifted by an even number of bits do not coincide). Therefore, for two adjacent signal periods of the stable region, different intervals are respectively corresponded, and the first continuous interval does not contain a jump region, as shown in FIG. 2. Figure 6 As can be understood, if the jump region is contained, the detection result is the second flag, which belongs to the second continuous interval.

[0100] For step S2, the first flags corresponding to the delay times are arranged in order from small to large according to the number of delay steps contained in the delay time, and the first continuous interval is obtained, as shown in FIG. 3. Figure 6 As shown in FIG. 3, the high level 1 represents the first flag, and the low level 0 represents the second flag.

[0101] For step S3, it is judged whether there is an intersection interval (i.e., a common delay time interval) of the first continuous intervals in all data channels of the differential link. If there is, go to step S4 to obtain the intersection interval as the first common interval. As shown in FIG. 4, the first common interval is shown. Figure 7

[0102] Based on the foregoing, it can be known that the first continuous interval in each channel in the present application does not contain a jump region, and therefore the intersection interval of all data channels does not contain a jump region. In the subsequent step S5, after the delay time of the center of the first common interval is used to delay the clock signal, the sampling edges of the clock signal will be aligned with the stable regions of the transmission signals in each data channel, so as to correct the phase deviation of any data channel in the transmission link.

[0103] In some embodiments, for a transmission link containing multiple data channels, in addition to the implementation manner of delaying the clock signal, the phase deviation can also be corrected by delaying the transmission signals of each data channel. Specifically, after step S2, the data alignment method provided by the present application further includes the following steps:

[0104] Step S6, for each data channel, the transmission signal is delayed according to the delay time corresponding to the first flag at the center of any first continuous interval in the data channel, so as to correct the phase deviation of any data channel in the transmission link. In addition, the delay of the training code, the clock signal or the differential signal in the present application can be realized by using the head delay chain method or the PLL (phase-locked loop) method. ​

[0105] In some embodiments, if there is no common delay time interval in the first continuous intervals of all data channels, after step S3, the method further comprises the following steps: Figure 8

[0106] S7, obtaining the delay time interval between the adjacent first continuous intervals as a second continuous interval. As shown in the following figure, the delay time range composed of the last delay time of the previous first continuous interval and the first delay time of the next first continuous interval is taken as the second continuous interval of the present application. Figure 6

[0107] S8, for each data channel, obtaining the maximum delay time range of any first continuous interval in the data channel, and dividing the central region of each second continuous interval into an interval with the same length as the delay time range, as a third continuous interval.

[0108] For step S8, the delay time range corresponding to any one first continuous interval is obtained, and then, based on the range, an interval with the same delay time range is divided in the central region of the second continuous interval in the same data channel, as a third continuous interval, as shown in the following figure. The central region represents the region formed by extending the same distance from the center of the interval to both ends. Accordingly, the center point of the third continuous interval is consistent with the center point of the second continuous interval. Figure 9

[0109] Since the delay time corresponding to the first continuous interval belongs to the stable region, the delay time range thereof is not higher than the length of the stable region. Accordingly, according to the processing procedure of the foregoing step S1, it can be known that the second continuous interval contains the jump region, but the jump region is on both sides of the second continuous interval, and the central region is still the stable region. Therefore, the time length of the stable region can be obtained by using the delay time range corresponding to the first continuous interval, and an interval with the same time length is divided along the central region of the second continuous interval to obtain a third continuous interval that does not contain the jump region.

[0110] In actual work, the maximum delay time range corresponding to the first continuous interval can be obtained, which is beneficial to expand the delay time range of the second common interval in the subsequent step S9. Alternatively, when the noise interference in the differential link working environment is high, the minimum delay time range corresponding to the first continuous interval can be selected to construct the third continuous interval, so as to improve the anti-interference ability of the subsequent data alignment result.

[0111] ​​​For each data channel, the second marks can also be sorted according to the order of the delay time, and the interval formed by the continuous second marks is taken as the second continuous interval. In this case, there can be a problem that the length of the second continuous interval is less than that of the first continuous interval. Therefore, the shortest first continuous interval can be selected as a reference to divide the third continuous interval. Alternatively, the determination method of the second continuous interval in the foregoing step S7 is adopted to ensure that the length of any second continuous interval exceeds that of the first continuous interval.

[0112] S9, obtaining the delay time interval common to the first continuous intervals and / or the third continuous intervals in all data channels as the second common interval.

[0113] As shown in Figure 10 , the intersection interval of the first continuous intervals and the third continuous intervals in all channels is obtained as the second common interval. In some scenarios, after obtaining the third continuous intervals of each data channel, the intersection interval between the third continuous intervals in all data channels can also be obtained as the second common interval.

[0114] S10, delaying the clock signal based on the delay time at the center of the second common interval to correct the phase deviation of any data channel in the transmission link.

[0115] Since the delay time range corresponding to the third continuous interval belongs to the stable region of the differential signal, the second common interval obtained by step S9 belongs to the stable region, so after delaying the clock signal using the delay time at the center of the second common interval, the sampling edge of the clock signal will be aligned in the stable region of the differential signal in each data channel, and the phase deviation of any data channel in the differential link is corrected.

[0116] In some embodiments, as shown in Figure 11 , the application also provides a data alignment system applied to a differential link having a plurality of data channels, comprising:

[0117] The mark recording module 1101 is configured to, for each data channel, detect whether the sampling edge of the clock signal is in the stable region of the transmission signal based on a preset training code at different delay times; if yes, and the latched value obtained based on the sampling edge at the current delay time belongs to the first set, record the detection result as the first mark; otherwise, record the detection result as the second mark.

[0118] The preset training code is a binary value with an even bit length, the first set is composed of values obtained by cyclically shifting the training code by an even number of bits, or composed of values obtained by cyclically shifting the training code by an odd number of bits, and the values obtained by cyclically shifting the training code by an even number of bits and an odd number of bits are not overlapped; and the stable region represents the delay time range in which the latched value obtained based on the sampling edge is constant.

[0119] The flag sorting module 1102 is used to sort the first flags of each data channel according to the order of the delay time, so as to obtain a first continuous interval formed by consecutive first flags.

[0120] The interval judgment module 1103 is used to determine whether there is a common delay time interval in the first continuous interval of all data channels; if so, the common delay time interval is obtained as the first common interval.

[0121] The deviation correction module 1104 is used to delay the clock signal based on the delay time at the center of the first common interval in order to correct the phase deviation of any data channel in the differential link.

[0122] In some embodiments, after determining whether there is a common delay time interval in the first continuous interval across all data channels, the interval determination module further includes:

[0123] If not, then obtain the delay time interval between adjacent first continuous intervals as the second continuous interval.

[0124] The data alignment system also includes the following modules:

[0125] The interval division module is used to obtain the delay time range of any first continuous interval in each data channel, and divide the central area of ​​each second continuous interval into an interval of the same length as the delay time range, as a third continuous interval.

[0126] The interval acquisition module is used to acquire the delay time interval shared by the first continuous interval and / or the third continuous interval in all data channels, as the second common interval.

[0127] The clock delay module is used to delay the clock signal based on the delay time at the center of the second common interval in order to correct the phase deviation of any data channel in the transmission link.

[0128] This application also provides an electronic device, such as... Figure 12 As shown, it includes a processor 1201, a communication interface 1202, a memory 1203, and a communication bus 1204. The processor 1201, the communication interface 1202, and the memory 1203 communicate with each other through the communication bus 1204.

[0129] Memory 1203 is used to store computer programs;

[0130] The processor 1201, when executing a program stored in the memory 1203, implements any of the above-mentioned data alignment methods.

[0131] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0132] The communication interface is used for communication between the above electronic device and other devices.

[0133] The memory can include a Random Access Memory (RAM) and can also include a Non-Volatile Memory (NVM), for example, at least one disk memory. Optionally, the memory can also be at least one storage device located away from the aforementioned processor.

[0134] The processor mentioned above can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

[0135] In another embodiment provided in the present application, a computer readable storage medium is also provided, and the computer readable storage medium stores a computer program. The computer program is executed by a processor to implement any of the above data alignment method steps.

[0136] In another embodiment provided in the present application, a computer program product containing instructions is also provided, and when the computer program product is run on a computer, the computer is caused to execute any of the data alignment method steps in the above embodiments.

[0137] The above examples are only used to illustrate the technical solutions of the present application, but not to limit the same; although the present application has been described in detail with reference to the foregoing examples, it should be understood by those of ordinary skill in the art that: it can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A data alignment method, characterized in that, Applied to transmission links with multiple data channels, including For each data channel, under different delay times, the sampling edge of the clock signal is detected based on the preset training code to see if it is in the stable region of the transmitted signal; If yes, and the latch value obtained based on the sampling edge under the current delay time belongs to the first set, the detection result is recorded as the first flag; otherwise, the detection result is recorded as the second flag; wherein, the preset training code bit length is an even number of binary values; the first set consists of the values ​​after the training code is cyclically shifted by an even number of bits, or the values ​​after the training code is cyclically shifted by an odd number of bits, and the values ​​after the training code is cyclically shifted by an even number of bits and an odd number of bits do not overlap; the stable region represents the range of delay time where the latch value obtained based on the sampling edge is constant; The first flags of each data channel are sorted according to the order of their delay times to obtain the first continuous interval formed by consecutive first flags; Determine whether there is a common delay time interval in the first consecutive interval within all data channels; If so, then obtain the shared delay time interval as the first shared interval; Based on the delay time at the center of the first shared interval, the clock signal is delayed to correct the phase deviation of any data channel in the transmission link.

2. The data alignment method according to claim 1, characterized in that, After determining whether there is a common delay time interval in the first consecutive interval across all data channels, the data alignment method further includes: If not, then obtain the delay time interval between adjacent first consecutive intervals as the second consecutive interval; For each data channel, obtain the delay time range of any first continuous interval in the data channel, and divide the central region of each second continuous interval into an interval of the same length as the delay time range, as a third continuous interval; Obtain the delay time interval shared by the first and / or third consecutive intervals within all data channels, and use it as the second common interval; Based on the delay time at the center of the second shared interval, the clock signal is delayed to correct the phase deviation of any data channel in the transmission link.

3. The data alignment method according to claim 1 or 2, characterized in that, After sorting the first flags of each data channel according to the order of their delay times to obtain a first continuous interval formed by consecutive first flags, the data alignment method further includes: For each data channel, the transmitted signal is delayed according to the delay time corresponding to the first marker at the center of any first continuous interval within that data channel, in order to correct the phase deviation of any data channel in the transmission link.

4. The data alignment method according to claim 1, characterized in that, The step of detecting whether the sampling edge of the clock signal based on the preset training code is in the stable region of the differential signal includes: At different delay times, fixed training codes are input into each data channel respectively; Based on the sampling edge of the clock signal, the training code of each data channel is sampled multiple times at the receiving end of the transmission link to obtain multiple latch values; wherein, the sampling edge is the upper edge or the lower edge of the clock signal. Determine whether the multiple latch values ​​of each data channel are consistent; if yes, it indicates that the sampling edge of the clock signal is in the stable region of the transmitted signal in the current data channel; if no, it indicates that the sampling edge of the clock signal is not in the stable region of the transmitted signal in the current data channel.

5. The data alignment method according to claim 4, characterized in that, Before inputting fixed training codes into each data channel at different delay times, the data alignment method further includes: Based on a fixed delay step, the clock signals in the transmission link are delayed sequentially; where sequential delay means that the delay time is increased in units of delay step according to the order of signal input.

6. The data alignment method according to claim 1, characterized in that, The delay interval between adjacent delay times is fixed, and the highest delay time is no less than 3 signal cycles of the transmitted signal.

7. A data alignment system, characterized in that, Applied to transmission links with multiple data channels, including The flag recording module is used to detect whether the sampling edge of the clock signal is in the stable region of the transmitted signal based on a preset training code for each data channel at different delay times. If yes, and the latch value obtained based on the sampling edge under the current delay time belongs to the first set, the detection result is recorded as the first flag; otherwise, the detection result is recorded as the second flag. The preset training code bit length is an even-numbered binary value. The first set consists of the values ​​after the training code is cyclically shifted an even number of bits, or the values ​​after the training code is cyclically shifted an odd number of bits, and the values ​​after the training code is cyclically shifted an even number of bits and an odd number of bits do not overlap. The stable region represents the range of delay times where the latch value obtained based on the sampling edge is constant. The flag sorting module is used to sort the first flags of each data channel according to the order of their delay times, so as to obtain a first continuous interval formed by consecutive first flags; The interval judgment module is used to determine whether there is a common delay time interval in the first continuous interval of all data channels; if so, the common delay time interval is obtained as the first common interval. The deviation correction module is used to delay the clock signal based on the delay time at the center of the first common interval in order to correct the phase deviation of any data channel in the transmission link.

8. The data alignment system according to claim 7, characterized in that, After determining whether there is a common delay time interval in the first continuous interval across all data channels, the interval determination module further includes: If not, then obtain the delay time interval between adjacent first consecutive intervals as the second consecutive interval; The data alignment system also includes: The interval division module is used to obtain the delay time range of any first continuous interval in each data channel, and divide the central area of ​​each second continuous interval into an interval of the same length as the delay time range, as a third continuous interval. The interval acquisition module is used to acquire the delay time interval shared by the first continuous interval and / or the third continuous interval in all data channels, as the second common interval; The clock delay module is used to delay the clock signal based on the delay time at the center of the second common interval in order to correct the phase deviation of any data channel in the transmission link.

9. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the data alignment method according to any one of claims 1-6.

10. A computer-readable storage medium, characterized in that, A computer-readable storage medium stores a computer program that, when executed by a processor, implements the data alignment method according to any one of claims 1-6.

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