Chip packaging structure
By designing distributed power pads and ground pads in the chip package structure and utilizing a specific routing layout in the redistribution layer, the ESD protection capability is improved, solving the problem of insufficient ESD protection capability in existing technologies without increasing costs.
Patent Information
- Application Number
- CN202411104109.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-12
- Publication Date
- 2026-02-24
AI Technical Summary
Existing chip packaging structures cannot meet system-level requirements in terms of ESD protection capabilities, and adding a redistribution layer to improve ESD protection capabilities will increase costs.
In the chip packaging structure, power pads and ground pads are distributed. Through the design of power and ground traces in the redistribution layer, the power pads are connected in series, and the ground traces are arranged around the edge of the redistribution layer. At least some of the power traces are located in the area enclosed by the ground traces, so as to realize the series connection of the power and ground pads.
It improves the ESD protection capability of the chip packaging structure, reaching the system-level ESD level, without increasing costs.
Smart Images
Figure CN121568575A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of packaging technology, and in particular to a chip packaging structure. Background Technology
[0002] From manufacturing, packaging, transportation, and assembly, and even in the finished IC product, chip packaging structures are constantly exposed to the impact of electrostatic discharge (ESD). When static charge accumulated in the external environment or inside the chip flows into or out of the chip through the chip's pins, the instantaneous current or voltage generated can damage the integrated circuit and cause the chip to malfunction.
[0003] In current chip packaging structures, the internal circuit design typically connects all power (VDD) lines together and all ground (VSS) lines together on the bottom metal layer, and the external redistribution layer brings out the power and ground pads on the chip surface as close as possible. However, such a design does not meet the system-level ESD requirements.
[0004] Figure 1 This is a circuit diagram of the rewiring layer in a WLCSP package structure. Figure 1 As shown, in this WLCSP package structure, the redistribution layer (RDL) includes a power trace 202 and a ground trace 201. This set of power traces 202 and ground traces 201 leads out a set of power pads and a set of ground pads nearby. As a result, the maximum electrostatic discharge voltage that the WLCSP package structure can withstand cannot reach the minimum requirement of 2KV. Figure 2 This is a circuit diagram of the redistribution layer in an FO-CSP package structure. Figure 2 As shown, in this FO-CSP package structure, the redistribution layer includes multiple sets of power traces 202 and ground traces 201. Each set of power traces 202 and ground traces 201 leads to a set of power pads and ground pads nearby, and the power traces 202 and ground traces 201 are disconnected from each other. Therefore, the ESD protection level of the FO-CSP package structure still cannot meet the requirements. Adding a separate redistribution layer to connect all the power pads and all the ground pads together could meet the system-level ESD requirements, but the cost would increase by 30% to 40%.
[0005] Therefore, it is urgent to solve the problem of how to improve the ESD protection capability of chip packaging structures at low cost. Summary of the Invention
[0006] One of the objectives of this invention is to improve the ESD protection capability of chip packaging structures without increasing costs.
[0007] To achieve the above objectives, the present invention provides a chip packaging structure. The chip packaging structure includes a chip and a redistribution layer. The front side of the chip has multiple power pads and multiple ground pads, which are distributed dispersedly on the front side of the chip. The redistribution layer is disposed on one side of the front side of the chip, and includes power traces and ground traces. The power traces are connected in series with multiple power pads, and the ground traces are connected in series with multiple ground pads. The ground traces are arranged around the edge region of the redistribution layer, and at least a portion of the power traces are disposed within the area enclosed by the ground traces.
[0008] Optionally, the redistribution layer further includes multiple signal traces; the ground trace is arranged around the power trace and the multiple signal traces; the power trace is interspersed among the multiple signal traces.
[0009] Optionally, the power traces, ground traces, and multiple signal traces in the redistribution layer are located in the same horizontal plane.
[0010] Optionally, the power traces separate the multiple signal traces into different areas.
[0011] Optionally, the power trace may surround the signal trace.
[0012] Optionally, all power supply lines are located within the area enclosed by the grounding lines.
[0013] Optionally, the power pads and the ground pads are distributed along multiple sides of the front side of the chip.
[0014] Optionally, in the redistribution layer, the grounding trace is a loop-type trace; the power trace includes multiple interconnected lines.
[0015] Optionally, a passivation layer is formed on the front side of the chip. The passivation layer has windows corresponding to the power pad and the ground pad. A first dielectric layer is formed on the passivation layer. The redistribution layer is formed on the first dielectric layer and passes through the first dielectric layer to be electrically connected to the power pad and the ground pad. A second dielectric layer and an external pad that penetrates the second dielectric layer are formed on the first dielectric layer. The external pad is electrically connected to the redistribution layer and has solder balls formed on it.
[0016] Optionally, the chip packaging structure further includes a molding compound, a metal under the bump layer, and solder balls. The molding compound at least covers the outer edge of the chip, and a portion of the redistribution layer is located on the surface of the molding compound on the same side as the front of the chip. The metal under the bump layer is electrically connected to the redistribution layer, and the solder balls are disposed above the metal under the bump layer.
[0017] Optionally, the chip packaging structure is a WLCSP packaging structure or an FO-CSP packaging structure, wherein in the WLCSP packaging structure, the edge region around which the ground trace is arranged is located between the inner edge of the chip and the ground pad, and / or in the FO-CSP packaging structure, the edge region around which the ground trace is arranged is located between the outer edge of the chip and the inner side of the molding compound.
[0018] In the chip packaging structure provided by this invention, multiple power pads and multiple ground pads are distributed on the front side of the chip. A redistribution layer is disposed on one side of the front side of the chip. The redistribution layer includes power traces and ground traces. The power traces are connected in series with multiple power pads, and the ground traces are connected in series with multiple ground pads. The ground traces are arranged around the edge area of the redistribution layer, and at least some of the power traces are disposed within the area enclosed by the ground traces. By changing the design of the power traces and ground traces in the redistribution layer, multiple power pads and multiple ground pads are led out in series through the redistribution layer, which can improve the ESD protection capability of the chip packaging structure and achieve the goal of the chip packaging structure reaching the system-level ESD level without increasing costs. Attached Figure Description
[0019] Figure 1 This is a circuit diagram of the redistribution layer of a WLCSP package structure.
[0020] Figure 2 This is a circuit diagram of the redistribution layer of an FO-CSP package structure.
[0021] Figure 3 This is a circuit diagram of the redistribution layer of a chip packaging structure provided in an embodiment of the present invention.
[0022] Figure 4 This is a cross-sectional schematic diagram of a chip packaging structure provided in an embodiment of the present invention.
[0023] Figure 5 A circuit diagram of the rewiring layer of a chip packaging structure provided in another embodiment of the present invention.
[0024] Figure 6 This is a cross-sectional schematic diagram of a chip packaging structure provided in another embodiment of the present invention.
[0025] Figure labeling: 10-Chip; 11-IO pad; 111-Ground pad; 112-Power pad; 12-Passivation layer; 13-First insulating layer; 20-Rerouting layer; 201-Ground trace; 202-Power trace; 203-Signal trace; 21-Second insulating layer; 22-Under-the-bump metal layer; 23-Third insulating layer; 24-Solder ball; 25-First dielectric layer; 26-Second dielectric layer; 27-External pad. Detailed Implementation
[0026] To improve the ESD protection capability of chip packaging structures at low cost, this invention provides a chip packaging structure. The chip packaging structure includes a chip and a redistribution layer. The front side of the chip has multiple power pads and multiple ground pads, which are distributed on the front side of the chip. The redistribution layer is disposed on one side of the front side of the chip. The redistribution layer includes power traces and ground traces. The power traces are connected in series with multiple power pads, and the ground traces are connected in series with multiple ground pads. The ground traces are arranged around the edge region of the redistribution layer, and at least a portion of the power traces are located within the area enclosed by the ground traces.
[0027] The chip packaging structure proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0028] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly stated. As used herein, the term “or” is generally used to include the meaning of “and / or” unless otherwise expressly stated. As used herein, the term “a number” is generally used to include the meaning of “at least one” unless otherwise expressly stated. As used herein, the term “multiple” is generally used to include the meaning of “two or more” unless otherwise expressly stated. Furthermore, spatial relative terms, such as “below,” “under,” “down,” “above,” “up,” etc., are used to simply describe the relationship between one element and another element of this disclosure. Spatial relative terms are used to cover different orientations of a device containing elements. Spatial relative terms are used to include different orientations of a device in use or operation, as well as the orientations described in the accompanying drawings. When the chip package structure is rotated to different orientations (rotated 90 degrees or other orientations), the spatial relative adjectives used therein will also be interpreted according to the orientation after rotation.
[0029] The chip packaging structure provided in this application may be a wafer-level chip-scale packaging (WLCSP) structure or a fan-out chip-scale packaging (FO-CSP) structure, but is not limited to these.
[0030] Figure 3 This is a circuit diagram of the redistribution layer of a chip packaging structure provided in an embodiment of the present invention. Figure 4 This is a cross-sectional schematic diagram of a chip packaging structure provided in an embodiment of the present invention. Figure 3 The circuitry of the rewiring layer in the WLCSP package structure is shown. Figure 4 A cross-sectional view of the WLCSP package structure is shown. The following description uses a WLCSP-type chip package structure as an example to illustrate the chip package structure of this application.
[0031] refer to Figure 3 and Figure 4 As shown, the WLCSP package structure includes a chip 10 and a redistribution layer 20. The front side of the chip 10 has multiple IO (input / output) pads 11, which include multiple power pads 112 and multiple ground pads 111, and the power pads 112 and the ground pads 111 are distributed on the front side of the chip 10.
[0032] Chip 10 may have multiple sides; for example, chip 10 may be a rectangular chip with four sides. Correspondingly, the overall layout of the redistribution layer 20 may be rectangular. Multiple ground pads 111 and multiple power pads 112 may be distributed along multiple sides of the front side of chip 10; for example, refer to... Figure 3 As shown, multiple ground pads 111 and multiple power pads 112 are distributed along the four sides of the chip 10.
[0033] For example, chip 10 may include a semiconductor substrate on which a plurality of I / O pads 11 may be formed. The material of the semiconductor substrate may include silicon (Si). In addition, the material of the semiconductor substrate may also include semiconductor elements such as germanium (Ge) and / or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) and / or indium phosphide (InP).
[0034] The material of the IO pad 11 may be a metal including copper (Cu), nickel (Ni), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga) and / or ruthenium (Ru) and / or alloys of the above metals.
[0035] refer to Figure 3 and Figure 4 As shown, the redistribution layer 20 is disposed on one side of the front side of the chip 10. The redistribution layer 20 includes power traces 202 and ground traces 201. The power traces 202 are connected in series with a plurality of power pads 112, and the ground traces 201 are connected in series with a plurality of ground pads 111. The ground traces 201 are arranged around the edge region of the redistribution layer 20, and at least a portion of the power traces 202 are disposed within the area enclosed by the ground traces 201.
[0036] refer to Figure 3 As shown, in the redistribution layer 20, the grounding trace 201 is a loop-type trace; the power trace 202 includes multiple interconnected lines.
[0037] refer to Figure 3 As shown, the redistribution layer 20 also includes multiple signal traces 203, which are electrically connected to corresponding I / O pads. The ground trace 201 surrounds the power trace 202 and the multiple signal traces 203. In this embodiment, the power trace 202, ground trace 201, and multiple signal traces 203 of the redistribution layer 20 are located in the same horizontal plane, that is, the power trace 202, ground trace 201, and multiple signal traces 203 are located at the same height on the chip 10.
[0038] In this embodiment, the grounding trace 201 is the outermost trace among all traces in the redistribution layer 20, and some of the signal traces 203 and some of the power traces 202 are located in the area enclosed by the grounding trace 201.
[0039] The power traces 202 are interspersed among the multiple signal traces 203. The multiple lines of the power traces 202 separate the multiple signal traces 203 into different areas. This can achieve partitioned shielding between the signal traces, which helps to reduce signal interference and improve the performance of the chip packaging structure.
[0040] For signal traces with significant signal interference, refer to Figure 3 As shown in the dashed box, the power supply trace 202 can also wrap around part of the signal trace, that is, it can wrap around the signal trace 203 with greater interference, which can further reduce the signal interference of the chip package structure.
[0041] For example, the materials used for the traces in the redistribution layer include, but are not limited to, one or more of the following: silver (Ag), gold (Au), copper (Cu), palladium (Pd), platinum (Pt), chromium (Cr), molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al).
[0042] refer to Figure 3 and Figure 4 As shown, in the WLCSP package structure, the redistribution layer 20 is formed directly above the chip 10, and the edge of the redistribution layer 20 is located inside the edge of the chip 10. The edge region of the redistribution layer around which the ground trace 201 is disposed is located between the inside edge of the chip 10 and the ground pad 111.
[0043] refer to Figure 4 As shown, a passivation layer 12 may also be formed on the surface of the chip 10. Specifically, the passivation layer 12 is formed on the substrate surface of the chip 10, covering a portion of the substrate surface and having multiple openings exposing multiple I / O pads 11. The multiple I / O pads 11 include multiple power pads 112 and multiple ground pads 111. The passivation layer 12 has openings corresponding to the power pads 112 and the ground pads 111. The material of the passivation layer 12 includes, but is not limited to, silicon oxide.
[0044] A first dielectric layer 25 is formed on the passivation layer 12, the first dielectric layer 25 covers the passivation layer 12 and further defines the area where the IO pads 11 are exposed.
[0045] The redistribution layer 20 is formed on the first dielectric layer 25 and electrically connected to the IO pad 11. Specifically, the redistribution layer 20 passes through the first dielectric layer 25 and is electrically connected to the power pad 112 and the ground pad 111.
[0046] A second dielectric layer 26 may be formed on the redistribution layer 20, and through-holes are formed in the second dielectric layer 26 to expose a portion of the redistribution layer 20.
[0047] It should be noted that the reference Figure 4 As shown, this embodiment uses a chip package structure with a redistribution layer 20 as an example for illustration. In other embodiments, the chip package structure may include multiple interconnected redistribution layers 20, and the ground trace 201 and power trace 202 may be arranged in one of the redistribution layers 20 in the manner described above.
[0048] An external pad 27 extending through the second dielectric layer 26 may be formed on the second dielectric layer 26. The external pad 27 may cover the inner surface of the via in the second dielectric layer 26 and may also extend to cover part of the top surface of the second dielectric layer 26. The external pad 27 is electrically connected to the redistribution layer 20. For example, the first dielectric layer 25 and the second dielectric layer 26 may be made of the same material, and the materials of the first dielectric layer 25 and the second dielectric layer 26 include, but are not limited to, polyimide.
[0049] Solder balls 24 can be formed on the external pad 27, and each trace in the redistribution layer 20 can be led out through the corresponding solder balls 24. The material of the solder balls 24 includes tin (Sn) or tin-based alloys, such as SnAg, but is not limited to these.
[0050] Figure 5 A circuit diagram of the rewiring layer of a chip packaging structure provided in another embodiment of the present invention. Figure 6 This is a cross-sectional schematic diagram of a chip packaging structure provided in another embodiment of the present invention. Figure 5 The circuitry of the redistribution layer in the FO-CSP package structure is shown. Figure 6 A cross-sectional view of the FO-CSP package structure is shown. The following describes the chip package structure of the FO-CSP type.
[0051] refer to Figure 5 and Figure 6 As shown, the FO-CSP package structure includes a chip 10 and a redistribution layer 20.
[0052] The front side of the chip 10 has multiple I / O pads 11, including multiple power pads 112 and multiple ground pads 111, which are distributed on the front side of the chip 10. It should be noted that... Figure 5 The power pad 112 and ground pad 111 are not shown. The locations of the power pad 112 and ground pad 111 in the FO-CSP package structure can be found by referring to... Figure 3 The power pad 112 and ground pad 111 of the WLCSP package structure are positioned.
[0053] The redistribution layer 20 is disposed on one side of the front side of the chip 10. The redistribution layer 20 includes power traces 202 and ground traces 201. The power traces 202 are connected in series with a plurality of power pads 112, and the ground traces 201 are connected in series with a plurality of ground pads 111. The ground traces 201 are arranged around the edge region of the redistribution layer 20, and at least a portion of the power traces 202 are disposed within the area enclosed by the ground traces 201.
[0054] refer to Figure 5 As shown, in the redistribution layer 20, the grounding trace 201 is a loop-type trace; the power trace 202 includes multiple interconnected lines.
[0055] refer to Figure 5As shown, the redistribution layer 20 also includes multiple signal traces 203, which are electrically connected to corresponding IO pads 11. The ground trace 201 surrounds the power trace 202 and the multiple signal traces 203. In this embodiment, all the signal traces 203 and power traces 202 are located within the area enclosed by the ground trace 201; in other words, the ground trace 201 surrounds the signal traces 203 and power traces 202 in the redistribution layer 20.
[0056] The power traces 202 are interspersed among the multiple signal traces 203. The multiple lines of the power traces 202 separate the multiple signal traces 203 into different areas. This can achieve partitioned shielding between the signal traces, which helps to reduce signal interference and improve the formation of the chip packaging structure.
[0057] refer to Figure 6 As shown, a first insulating layer 13 can be formed on the front side of the chip 10. The first insulating layer 13 can have multiple vias, and these vias expose at least a portion of the surface of the IO pads 11 to bring out the IO pads 11. The first insulating layer 13 can protect the front side of the chip 10 during the packaging process.
[0058] refer to Figure 6 As shown, the FO-CSP type chip package structure also includes a molding compound 30, which at least covers the outer edge of the chip 10. Specifically, in this embodiment, the molding compound 30 covers the outer edge and the reverse side of the chip 10, and also covers the sidewalls of the first insulating layer 13. In other embodiments, to reduce the thickness of the chip package structure, the molding compound 30 may only cover the outer edge of the chip 10 and expose the reverse side of the chip 10. Exemplarily, the material of the molding compound 30 includes, but is not limited to, epoxy molding compound (EMC).
[0059] refer to Figure 6 As shown, a portion of the redistribution layer 20 can be formed on the surface of the molding compound 30 on the same side as the front side of the chip 10; in other words, the redistribution layer 20 can be formed on both the front sides of the molding compound 30 and the chip 10. (See reference...) Figure 5 and Figure 6 As shown, in the FO-CSP package structure, the edge region of the redistribution layer around which the ground trace 201 is disposed is located between the outer edge of the chip 10 and the inner side of the molding compound 30.
[0060] The redistribution layer 20 is electrically connected to the IO pads 11 on the front side of the chip through conductive plugs filled in the vias of the first insulating layer 13.
[0061] An under bump metallurgy (UBM) 22 and solder balls 24 may be formed on the redistribution layer 20. The under bump metallurgy 22 is electrically connected to the redistribution layer 20, and the solder balls 24 are disposed above the under bump metallurgy 22.
[0062] A second insulating layer 21 for isolation is formed between the redistribution layer 20 and the under-bump metal layer 22. The second insulating layer 21 also fills the gaps between the traces of the redistribution layer 20. A third insulating layer 23 is formed on the second insulating layer 21. The third insulating layer 23 covers the sidewalls of the under-bump metal layer 22 and the bottom sidewalls of the solder ball 24.
[0063] For example, the chip packaging structure provided in this application includes, but is not limited to, a microcontroller unit (MCU).
[0064] In the chip packaging structure provided by this invention, multiple power pads 112 and multiple ground pads 111 on the front side of chip 10 are dispersedly arranged on the front side of chip 10. A redistribution layer 20 is disposed on one side of the front side of chip 10. The redistribution layer 20 includes power traces 202 and ground traces 201. The power traces 202 are connected in series with multiple power pads 112, and the ground traces 201 are connected in series with multiple ground pads 111. The ground traces 201 are arranged around the edge area of the redistribution layer 20, and at least a portion of the power traces 202 are disposed within the area enclosed by the ground traces 201. By changing the design of the power traces 202 and ground traces 201 in the redistribution layer, multiple power pads 112 and multiple ground pads 111 are all led out in series through the redistribution layer 20, which can improve the ESD protection capability of the chip packaging structure and achieve the goal of the chip packaging structure reaching the system-level ESD level without increasing costs.
[0065] It should be noted that this specification describes the chip packaging structure of this application using WLCSP and FO-CSP chip packaging structures, but those skilled in the art should readily understand the details of this application and that this application can be applied to other packaging types with redistribution layers and their variations.
[0066] This manual uses a progressive approach. The FO-CSP type chip package structure described later focuses on the differences from the WLCSP type chip package structure described earlier. For similarities and similarities between the various parts, please refer to each other.
[0067] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A chip packaging structure, characterized in that, include: The chip has multiple power pads and multiple ground pads on its front side, and the power pads and multiple ground pads are distributed on the front side of the chip. as well as A redistribution layer is disposed on one side of the front side of the chip. The redistribution layer includes power traces and ground traces. The power traces are connected in series with multiple power pads, and the ground traces are connected in series with multiple ground pads. The ground traces are disposed around the edge area of the redistribution layer, and at least a portion of the power traces are disposed within the area enclosed by the ground traces.
2. The chip packaging structure as described in claim 1, characterized in that, The redistribution layer also includes multiple signal traces; the ground trace is arranged around the power trace and the multiple signal traces; the power trace is interspersed among the multiple signal traces.
3. The chip packaging structure as described in claim 2, characterized in that, The power traces, ground traces, and multiple signal traces in the redistribution layer are located in the same horizontal plane.
4. The chip packaging structure as described in claim 2, characterized in that, The power traces separate the multiple signal traces into different areas.
5. The chip packaging structure as described in claim 2, characterized in that, The power traces surround the signal traces.
6. The chip packaging structure as described in claim 1, characterized in that, All power supply lines are located within the area enclosed by the grounding lines.
7. The chip packaging structure as described in claim 1, characterized in that, The power pads and the ground pads are distributed along the multiple sides of the front side of the chip.
8. The chip packaging structure as described in claim 1, characterized in that, In the redistribution layer, the grounding trace is a loop-type trace; the power trace includes multiple interconnected lines.
9. The chip packaging structure as described in claim 1, characterized in that, A passivation layer is formed on the front side of the chip. The passivation layer has windows corresponding to the power pad and the ground pad. A first dielectric layer is formed on the passivation layer. A redistribution layer is formed on the first dielectric layer and passes through the first dielectric layer to be electrically connected to the power pad and the ground pad. A second dielectric layer and an external pad that penetrates the second dielectric layer are formed on the first dielectric layer. The external pad is electrically connected to the redistribution layer and has solder balls formed on it.
10. The chip packaging structure as described in claim 1, characterized in that, It also includes a molding compound, a metal under the bump layer, and solder balls. The molding compound at least covers the outer edge of the chip. A portion of the redistribution layer is located on the surface of the molding compound on the same side as the front of the chip. The metal under the bump layer is electrically connected to the redistribution layer. The solder balls are disposed above the metal under the bump layer.
11. The chip packaging structure as described in claim 1, characterized in that, The chip packaging structure is a WLCSP packaging structure or an FO-CSP packaging structure, wherein in the WLCSP packaging structure, the edge region around which the ground trace is arranged is located between the inner edge of the chip and the ground pad, and / or in the FO-CSP packaging structure, the edge region around which the ground trace is arranged is located between the outer edge of the chip and the inner side of the molding compound.