Memory management method, electronic device, and program product

Abstract

The present disclosure provides a memory management method, an electronic device and a program product, and relates to the technical field of computers. The memory management method comprises the following steps: dividing a DRAM cache into a plurality of cache sets, and dividing each cache set into a plurality of logical subsets, each logical subset containing a plurality of physical cache paths; constructing a metadata tree corresponding to each cache set; in response to a memory access request, determining a physical address corresponding to the memory access request; determining a cache set corresponding to the memory access request; determining whether the memory access request is a hit; in the case that the memory access request is not a hit and there is no idle physical cache path, locating a target logical subset from the metadata tree according to path indication information; selecting a target physical cache path according to a reference prediction value; replacing the storage content of the target physical cache path with request data, and updating the reference prediction value of the target physical cache path to an initial value.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, specifically to a memory management method, electronic device, and program product. Background Technology

[0002] With the evolution of the CXL (Compute Express Link) interconnect standard, data center architectures are moving towards memory pooling and memory tiering. Through CXL links, compute nodes can access large-capacity extended memory, forming a heterogeneous memory hierarchy consisting of local DRAM and CXL extended memory. However, CXL extended memory has significant disadvantages compared to local buses in terms of latency and bandwidth. As interconnect topologies become more complex, the latency penalty caused by cross-node access has become a key bottleneck restricting system performance.

[0003] To mitigate the high-latency access problem in CXL, existing systems deploy DRAM caches on local DRAM, employing both software and hardware management solutions. However, both have inherent drawbacks: software solutions migrate at 4KB page granularity, leading to traffic amplification, frequent page faults, and high kernel overhead. While hardware solutions support fine-grained (cache line or sub-block level) automatic management, they are limited by metadata overhead and often employ low associativity structures, making them prone to collision misses. In CXL scenarios, each miss triggers a high-cost cross-link access, significantly amplifying performance losses. Increasing associativity to reduce collisions would drastically increase tag comparison and metadata access overhead, introducing severe serial latency and bandwidth pressure, creating a dilemma of "low associativity, high collisions; high associativity, high overhead." Summary of the Invention

[0004] This disclosure provides a memory management method, an electronic device, and a program product.

[0005] According to one aspect of this disclosure, a memory management method is provided, comprising: dividing a DRAM cache into multiple cache sets, and further dividing each cache set into multiple logical subsets, each logical subset containing multiple physical cache paths; constructing a metadata tree corresponding to each cache set, the metadata tree including a root node, intermediate nodes, and leaf nodes, wherein the root node and the intermediate nodes are configured with path indication information, the path indication information being used to indicate the path of the most recently accessed subtree, the leaf nodes being used to record metadata of each physical cache path contained in the logical subset, and each leaf node corresponding to a logical subset, the metadata including a re-reference prediction value, the re-reference prediction value being used to indicate the priority of the corresponding physical cache path being accessed again; responding to a memory access request, determining the physical address corresponding to the memory access request; and based on the physical address, determining the cache path corresponding to the memory access request. The system stores a cache set; based on the cache set, it determines whether the memory access request is hit; if it is hit, it retrieves the request data from slow memory; if there is no free physical cache path in the cache set, it locates the target logical subset from the metadata tree according to the path indication information; based on the rereference prediction value of each physical cache path in the target logical subset, it selects a target physical cache path from the physical cache paths included in the target logical subset; and replaces the stored content of the target physical cache path with the request data, and updates the rereference prediction value of the target physical cache path to its initial value; if it is hit, it retrieves the request data based on the hit physical cache path, updates the rereference prediction value of the hit physical cache path to its minimum value, and updates the path indication information configured in the root node and the intermediate nodes of the metadata tree; and outputs the request data.

[0006] According to one technical solution, by increasing the granularity of cache replacement path location from a single physical cache path to a logical subset level, the storage and update complexity of replacement metadata in highly associative caches can be reduced, and a stable candidate range can be provided for subsequent replacement strategies. This ensures the accuracy of replacement decisions while avoiding replacement interference problems caused by local hotspot concentrations in traditional path-based replacement strategies in highly associative caches.

[0007] According to at least one embodiment of this disclosure, when there is an idle physical cache path in the cache set, the request data is written to the idle physical cache path, and the rereference prediction value of the idle physical cache path is updated to the initial value; and the request data is output.

[0008] According to the technical solution of this embodiment, it can be ensured that requested data is written to the idle physical cache path first.

[0009] According to at least one embodiment of this disclosure, locating a target logical subset from the metadata tree based on the path indication information includes: determining a target intermediate node based on the path indication information in the metadata tree; and determining a target logical subset based on the path indication information of the target intermediate node.

[0010] According to the technical solution of this embodiment, the location of the target logical subset can be completed with lower metadata overhead.

[0011] According to at least one embodiment of this disclosure, selecting a target physical cache path from the physical cache paths included in the target logical subset based on the rereference prediction value of each physical cache path in the target logical subset includes: determining whether there is a physical cache path in the target logical subset whose rereference prediction value is greater than or equal to an eviction threshold; and if there is a physical cache path whose rereference prediction value is greater than or equal to an eviction threshold, selecting one of the physical cache paths whose rereference prediction value is greater than or equal to an eviction threshold as the target physical cache path.

[0012] According to the technical solution of this embodiment, the physical cache path that has not been accessed for the longest time can be accurately located.

[0013] According to at least one embodiment of this disclosure, selecting a target physical cache path from the physical cache paths included in the target logical subset based on the rereference prediction value of each physical cache path in the target logical subset includes: determining whether there is a physical cache path in the target logical subset whose rereference prediction value is greater than or equal to an eviction threshold; if there is no physical cache path whose rereference prediction value is greater than or equal to an eviction threshold, incrementing the rereference prediction value of each physical cache path in the target logical subset until there is a physical cache path whose rereference prediction value is greater than or equal to an eviction threshold; and selecting one of the physical cache paths whose rereference prediction value is greater than or equal to an eviction threshold as the target physical cache path.

[0014] According to the technical solution of this embodiment, the target physical cache path can be quickly located through the active aging mechanism.

[0015] According to at least one embodiment of this disclosure, the process of determining the initial value of the re-reference prediction value includes: real-time monitoring of system operating status information, the system operating status information including last-level cache miss rate, local memory miss rate, change in local memory miss rate, DRAM cache miss rate, and change in DRAM cache miss rate; setting the initial value to A when the last-level cache miss rate is less than or equal to a first threshold; setting the initial value to B when the last-level cache miss rate is greater than the first threshold, the local memory miss rate is greater than the second threshold, and the change in local memory miss rate is greater than the third threshold; and setting the initial value to C when the last-level cache miss rate is greater than the first threshold, the local memory miss rate is greater than the second threshold, the change in local memory miss rate is greater than the third threshold, the DRAM cache miss rate is greater than the fourth threshold, and the change in DRAM cache miss rate is positive, where 0 < A < B < C ≤ the evictation threshold.

[0016] According to the technical solution of this embodiment, by using a step-by-step, state-aware initial value update method, fine-grained and adaptive adjustment of cache insertion priority can be achieved under different memory pressure levels, thereby improving the overall utilization efficiency and stability of DRAM cache space.

[0017] According to at least one embodiment of this disclosure, determining whether a memory access request is hit based on the cache set includes: determining whether a physical address is hit based on the labels of each physical cache path in the cache set; if the physical address is hit, determining a sub-block validity bitmap of the physical page corresponding to the physical address; and determining whether the memory access request is hit based on the sub-block validity bitmap.

[0018] According to the technical solution of this embodiment, accurate hit determination can be made when the requested data is a sub-block in a physical page.

[0019] According to at least one embodiment of this disclosure, determining the sub-block validity bitmap of the physical page corresponding to the physical address includes: searching in a page-level authoritative metadata table based on the physical page frame number in the physical address to obtain the sub-block validity bitmap of the physical page corresponding to the physical address, wherein the page-level authoritative metadata table records the mapping relationship between the physical page frame number and the corresponding sub-block validity bitmap of the physical page.

[0020] According to the technical solution of this embodiment, the effectiveness of the acquired sub-block validity bitmap can be improved.

[0021] According to at least one embodiment of this disclosure, determining whether the memory access request has been hit includes: when determining the physical address corresponding to the memory access request, if a TLB miss occurs and page table traversal is triggered, performing page table traversal and page table entry extension structure query in parallel, wherein the page table traversal is used to obtain the physical page frame number, and the page table entry extension structure query is used to determine the sub-block validity bitmap of the corresponding physical page based on the virtual address through the page table entry extension structure, wherein the page table entry extension structure is used to record the mapping relationship between the virtual address or the hash value of the virtual address and the sub-block validity bitmap of the corresponding physical page; if the physical page frame number is obtained based on the page table traversal, determining whether the sub-block validity bitmap is found; if the sub-block validity bitmap is not found, searching for the sub-block validity bitmap through the page-level authoritative metadata table based on the physical page frame number; and determining whether the memory access request has been hit based on the sub-block validity bitmap.

[0022] According to the technical solution of this embodiment, the accuracy of the hit determination can be guaranteed.

[0023] According to at least one embodiment of this disclosure, after determining whether the sub-block validity bitmap is found when the physical page frame number is obtained based on the page table traversal, the method further includes: if the sub-block validity bitmap is found, determining whether the memory access request is hit based on the sub-block validity bitmap.

[0024] According to the technical solution of this embodiment, the serial latency of sub-block metadata access can be hidden.

[0025] According to at least one embodiment of this disclosure, determining whether the memory access request has been hit includes: when determining the physical address corresponding to the memory access request, if a TLB hit occurs, searching a sub-block validity bitmap based on the page-level metadata cache, wherein the page-level metadata cache is used to store the mapping relationship between virtual addresses and corresponding physical page frame numbers; and determining whether the memory access request has been hit based on the sub-block validity bitmap.

[0026] According to the technical solution of this embodiment, the lookup of the sub-block validity bitmap is realized through page-level metadata caching, which can achieve low-latency decoupling of metadata access and address translation.

[0027] According to at least one embodiment of this disclosure, determining whether a memory access request is hit based on the sub-block validity bitmap includes: determining whether the target sub-block corresponding to the memory access request is valid based on the sub-block validity bitmap; and determining that the memory access request is hit if the target sub-block corresponding to the memory access request is valid.

[0028] According to the technical solution of this embodiment, accurate determination of memory access request hits can be achieved.

[0029] According to another aspect of this disclosure, an electronic device is provided, comprising: a memory storing execution instructions; and a processor executing the execution instructions stored in the memory, causing the processor to perform a memory management method according to any embodiment of this disclosure.

[0030] According to another aspect of this disclosure, a readable storage medium is provided, wherein executable instructions are stored therein, which, when executed by a processor, are used to implement a memory management method according to any embodiment of this disclosure.

[0031] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements a memory management method according to any embodiment of this disclosure.

[0032] This disclosure can significantly reduce the metadata access overhead and critical path latency of highly associative DRAM caches without sacrificing cache hit rate, thereby effectively alleviating the high-latency access bottleneck in CXL heterogeneous memory systems. Attached Figure Description

[0033] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0034] Figure 1 This is a flowchart illustrating a memory management method according to one embodiment of the present disclosure.

[0035] Figure 2 This is a flowchart illustrating a memory management method according to another embodiment of the present disclosure.

[0036] Figure 3 This is a flowchart illustrating a memory management method according to yet another embodiment of the present disclosure.

[0037] Figure 4 This is a flowchart illustrating the method corresponding to step S150 of another embodiment of this disclosure.

[0038] Figure 5 This is a flowchart illustrating a memory access request hit determination method according to one embodiment of the present disclosure.

[0039] Figure 6 This is a flowchart illustrating a memory access request hit determination method according to another embodiment of the present disclosure.

[0040] Figure 7 This is a flowchart illustrating a memory access request hit determination method according to yet another embodiment of this disclosure.

[0041] Figure 8 This is a flowchart illustrating a memory access request hit determination method according to another exemplary embodiment of the present disclosure.

[0042] Figure 9 This is a schematic diagram of the structure of a metadata tree according to one embodiment of the present disclosure.

[0043] Figure 10 This is a schematic block diagram of a memory management device according to one embodiment of the present disclosure.

[0044] Figure 11 This is a schematic structural block diagram of an electronic device employing a processor-based hardware implementation according to one embodiment of the present disclosure. Detailed Implementation

[0045] The present disclosure will now be described in further detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0046] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0047] To mitigate CXL access latency, existing systems typically introduce a caching mechanism (DRAM cache) on the local DRAM to cache data from the CXL extended memory. Based on different cache management methods, existing solutions can be mainly divided into two categories: software management and hardware management. However, both existing management solutions have inherent drawbacks.

[0048] Software management solutions typically perform cold and hot migrations at the operating system page level (e.g., 4KB). Since real-world applications often only access a portion of the cached lines within a page, page-level migrations lead to significant traffic amplification and frequent page faults. This results in high context switching and kernel path overhead, limiting their applicability in high-performance scenarios.

[0049] Hardware management solutions typically involve building hardware caches in local DRAM, with hardware automatically handling data placement and replacement. This usually supports finer-grained data management (such as cache line or sub-block level). To reduce the storage and access overhead of metadata such as address tags and replacement status, existing hardware DRAM caches mostly employ direct mapping or low-associativity structures. However, in the CXL heterogeneous memory hierarchy, this type of design is increasingly revealing significant limitations.

[0050] First, low-associative DRAM caches struggle to effectively accommodate ever-growing working set sizes, easily leading to numerous conflicting misses. In CXL systems, each DRAM cache miss often means a cross-link access to high-latency extended memory, which is significantly more costly than traditional local memory access. This amplifies the performance impact of conflicting misses, significantly affecting overall system performance.

[0051] Secondly, while increasing DRAM cache associativity helps reduce cache miss rates, it also introduces new scalability issues. Highly associative caches require multiple address tag comparisons along the access path and frequent access to and updates of related metadata. When this metadata cannot reside entirely within the processor's high-speed internal storage structure, or needs to be accessed via DRAM or even CXL links, it introduces significant serialization latency and additional data transfer overhead on critical access paths, and this problem worsens with increasing associativity.

[0052] To address these issues, this disclosure proposes the following technical solution. By dividing the DRAM cache into a multi-level structure (cache set → logical subset → physical cache path) and constructing a path-based metadata tree, the complexity of replacement decisions in highly associative caches can be significantly reduced, avoiding metadata traversal across the entire set. Maintaining path indication information in the root and intermediate nodes of the metadata tree enables access-hot-aware subtree guidance, quickly converging to low-hot logical subsets and improving replacement efficiency. Binding rereference prediction values ​​to logical subsets and performing replacements within those subsets effectively alleviates the "hot sibling interference" problem and improves cache space utilization. This disclosure significantly reduces metadata access overhead and critical path latency in highly associative DRAM caches without sacrificing cache hit rate, thereby effectively alleviating the high-latency access bottleneck in CXL heterogeneous memory systems.

[0053] To facilitate description and make the technical solutions of this disclosure easier to understand, the terminology of this disclosure will be explained before describing the technical solutions of this disclosure.

[0054] CXL (Compute Express Link) is an open standard high-speed interconnect protocol. The core function of CXL is to achieve efficient sharing and expansion of memory resources through a cache coherence protocol.

[0055] DRAM (Dynamic Random-Access Memory) is a volatile semiconductor memory that uses capacitors to store charge to represent data and requires periodic refresh to maintain the data.

[0056] DRAM cache associativity refers to the number of physical locations in the cache that can be occupied by a given memory address.

[0057] The Memory Management Unit (MMU) is a piece of computer hardware responsible for handling memory access requests. Its functions include virtual address to physical address translation (i.e., virtual memory management), memory protection, and control of the central processing unit cache.

[0058] The Page-Level Authoritative Metadata Table (PAMT) records the mapping between physical page frame numbers and the corresponding sub-block validity bitmaps of physical pages, and can be configured at the operating system software level.

[0059] The page table entry extension structure is used to record the mapping relationship between a virtual address (VPN) or the hash value of a virtual address and the validity bitmap of the corresponding physical page's sub-blocks, and can be stored in physical memory.

[0060] Page-level metadata cache is used to record the mapping relationship between physical page frame numbers and the corresponding sub-block validity bitmaps of physical pages, and can be integrated into the memory management unit.

[0061] The TLB (Translation Lookaside Buffer) is a tiny but extremely fast hardware cache in the processor, specifically designed to accelerate the translation process from virtual addresses to physical addresses.

[0062] The set index is a contiguous range of low-order bits in a physical address used to calculate which set of DRAM cache the address should fall into.

[0063] This disclosure applies to large-scale memory tiering and pooling scenarios.

[0064] Figure 1 A schematic diagram illustrating the overall flow of a memory management method according to one embodiment of this disclosure is shown. Figure 1 The method shown includes steps S110 to S170.

[0065] In step S110, the DRAM cache is divided into multiple cache sets, and each cache set is further divided into multiple logical subsets, with each logical subset containing multiple physical cache paths. This logical subset partitioning method reduces the complexity of subsequent replacement decisions.

[0066] One possible implementation is to build a DRAM cache on the processor side. The DRAM cache employs a set-associative cache organization, meaning the DRAM cache contains multiple cache sets, each consisting of multiple physical cache paths organized in a set-associative manner. All physical cache paths within each cache set are divided into several logical subsets, each containing a predetermined number of physical cache paths. For example, a cache set consisting of 16 set-associative physical cache paths can be divided into 4 logical subsets, each containing 4 physical cache paths.

[0067] In step S120, a metadata tree is constructed for each cache set. The metadata tree includes a root node, intermediate nodes, and leaf nodes.

[0068] Both the root node and intermediate nodes are configured with path indication information. This information indicates the path to the most recently visited subtree. As one possible implementation, path indication information can use path bits. The path bits can have values ​​of 0 and 1, corresponding to the direction of the two connected subtrees. In one example, a path bit value of 0 for the root node indicates that the left subtree connected to the root node is the most recently visited subtree; a path bit value of 1 indicates that the right subtree connected to the root node is the most recently visited subtree. In another example, a path bit value of 0 for an intermediate node indicates that the left subtree connected to the intermediate node is the most recently visited subtree; a path bit value of 1 indicates that the right subtree connected to the intermediate node is the most recently visited subtree. By configuring path indication information, the direction of the least recently visited (i.e., less frequently visited) subtree can be quickly identified, protecting currently popular paths.

[0069] Leaf nodes record the metadata of each physical cache path contained in the logical subset, and each leaf node corresponds to one logical subset. The metadata includes rereference prediction values, which indicate the priority of the corresponding physical cache path being accessed again. As one possible implementation, a higher rereference prediction value indicates a lower priority for the corresponding physical cache path to be accessed again; therefore, physical cache paths with higher rereference prediction values ​​can be prioritized for replacement during replacement. By configuring rereference prediction values, hot-sibling interference between adjacent physical cache paths in the same subtree can be eliminated.

[0070] As one possible implementation, the metadata may also include a tag and a validity bit. The tag corresponds to the data content stored in the physical cache path, which is typically stored in slow memory (such as CXL extended memory). The tag identifies the physical address of the data content stored in the physical cache path within the slow memory and can be used to determine whether a physical address has been hit. For example, the tag may be configured to store the high-order bits of the physical address in the slow memory (such as CXL extended memory) corresponding to the data content in the physical cache path. The validity bit can be used to indicate whether the corresponding physical cache path stores valid data (i.e., whether it is occupied).

[0071] As one possible implementation, metadata can be stored entirely in the processor's last-level cache to avoid frequent access to the external DRAM cache.

[0072] Figure 9 The diagram shown is a schematic representation of the metadata tree structure proposed in one embodiment of this disclosure. Figure 9 The metadata tree shown includes a root node, two intermediate nodes connected to the root node, and two leaf nodes connected to each intermediate node. Each intermediate node and its two connected leaf nodes are subtrees of the root node, and each intermediate node's subtree is a leaf node it connects to.

[0073] In other implementations, the cache set can be divided into more than four logical subsets. In this case, the metadata tree can be constructed by adding branch levels. For example, if the cache set is divided into eight logical subsets, it needs to include two levels of intermediate nodes. The first level of intermediate nodes consists of two intermediate nodes connected to the root node. The second level of intermediate nodes consists of two intermediate nodes connected to each of the first level intermediate nodes. Each second level intermediate node connects to two leaf nodes.

[0074] In the constructed metadata tree, leaf nodes no longer correspond to a single physical cache path, but rather to a logical subset containing multiple physical cache paths. This reduces the overall height of the metadata tree by decreasing the branch levels of the tree and mitigates the interference of hot (recently accessed) cache paths on cold (recently infrequently accessed) cache paths.

[0075] In step S130, in response to the memory access request, the physical address corresponding to the memory access request is determined.

[0076] As one possible implementation, the memory access request contains the virtual address of the DRAM cache to be accessed, and the corresponding physical address can be obtained through address translation by the Memory Management Unit (MMU).

[0077] In step S140, the cache set corresponding to the memory access request is determined based on the physical address.

[0078] As one possible implementation, the cache set index corresponding to the cache set of the memory access request can be determined first based on the physical address, and then the cache set can be determined based on the cache set index.

[0079] In step S150, based on the cache set, it is determined whether the memory access request has been hit.

[0080] As one possible implementation, physical address matching can be performed based on the tags corresponding to each physical cache path in the cache set. The result of the physical address matching is then used to determine whether the memory access request has been hit. If the physical address matching is successful, it means that the physical cache path corresponding to the tag stores the data at the corresponding physical address in the slow memory.

[0081] In step S160, in the event of a cache miss, the requested data is retrieved from slow memory. If no free physical cache path exists in the cache set, the target logical subset is located from the metadata tree based on the path indication information. Based on the rereference prediction values ​​of each physical cache path in the target logical subset, a target physical cache path is selected from the physical cache paths included in the target logical subset. The stored content of the target physical cache path is replaced with the requested data, and the rereference prediction value of the target physical cache path is updated to its initial value.

[0082] A miss indicates that the data at the corresponding physical address in the slow memory required by the memory access request does not exist in the DRAM cache. In this case, it is necessary to directly access the corresponding physical address in the slow memory and extract the data at that physical address as the requested data.

[0083] Since the DRAM cache is used to store data in the slow memory that is frequently accessed recently, the requested data also needs to be stored in the DRAM cache after it is retrieved from the slow memory.

[0084] Since the storage space of DRAM cache is limited, if there are no free physical cache paths in the cache set, the storage content of the least accessed physical cache path (i.e., the target physical cache path) in the cache set needs to be updated with the requested data (i.e., perform replacement), so that the storage content of DRAM cache is all data from the slow memory that is accessed most recently.

[0085] This implementation uses a metadata tree to locate the target physical cache path. As one possible implementation, the target logical subset is located from the metadata tree based on path indication information, including: determining the target intermediate node based on the path indication information in the metadata tree; and determining the target logical subset based on the path indication information of the target intermediate node. For example, starting from the root node, the target intermediate node is found based on the path indication information of the root node. Then, the target leaf node is found based on the path indication information of the target intermediate node. Finally, the logical subset corresponding to the target leaf node is taken as the target logical subset. This implementation uses a path-based cache metadata tree management structure based on logical subsets, which can complete the location of the target logical subset with lower metadata overhead.

[0086] The Re-Reference Prediction Value (RRPV) is used to indicate the priority of a corresponding physical cache path being accessed again. Therefore, based on the magnitude of the RRPV corresponding to each physical cache path in the target logical subset, the physical cache path that has not been accessed for the longest time can be selected from among the physical cache paths, and the selected physical cache path that has not been accessed for the longest time can be used as the target physical cache path.

[0087] After determining the target physical cache path, the stored content of the target physical cache path needs to be replaced with the requested data, and the rereference prediction value of the target physical cache path needs to be updated to the initial value.

[0088] As one possible implementation, determining whether the cache set has free physical cache paths can be achieved by setting a full status bit in the root node, such as... Figure 9 As shown. The full status bit is used to indicate whether there is a free physical cache path in the cache set corresponding to the metadata tree of the root node. In one example, the value of the full status bit can be 0 or 1. When the value of the full status bit is 0, it means that there is a free physical cache path in the cache set corresponding to the metadata tree of the root node. When the value of the full status bit is 1, it means that there is no free physical cache path in the cache set corresponding to the metadata tree of the root node.

[0089] It should be noted that when a DRAM cache is replaced or a sub-block becomes invalid, a page-level global eviction is performed. In this case, all sub-blocks within the page will become invalid simultaneously. The system gradually propagates state changes through unidirectional updates and delayed synchronization mechanisms, thereby ensuring stable system operation without introducing a global synchronization barrier.

[0090] In step S170, the request data is output.

[0091] This disclosure improves the granularity of cache replacement path location from a single physical cache path to a logical subset level, reducing the storage and update complexity of replacement metadata in highly associative caches and providing a stable candidate range for subsequent replacement strategies. This disclosure employs a rereference prediction replacement mechanism based on metadata trees, using rereference prediction values ​​to characterize the likelihood of the corresponding physical cache path being accessed again. This disclosure ensures the accuracy of replacement decisions while avoiding replacement interference caused by local hotspot concentrations in traditional path-based replacement strategies in highly associative caches. This disclosure can locate the target logical subset with lower metadata overhead. This disclosure effectively reduces slow memory access traffic and improves cache resource utilization.

[0092] Figure 2 The diagram shown is a schematic overall flow chart of a memory management method according to another embodiment of this disclosure. Figure 2 The method shown includes steps S210 to S270. Steps S210-S250 respectively correspond to... Figure 1 Steps S110-S150 of the implementation method, step S270 corresponds to Figure 1 Step S170 of the implementation method is detailed in the following article. Figure 1 The relevant descriptions of the implementation methods will not be repeated here.

[0093] In step S260, in the event of a cache miss, the requested data is retrieved from the slow memory. If there is a free physical cache path in the cache set, the requested data is written to the free physical cache path, and the rereference prediction value of the free physical cache path is updated to the initial value.

[0094] Figure 3 The diagram shown is a schematic representation of the overall flow of a memory management method according to yet another embodiment of this disclosure. Figure 3 The method shown includes steps S310 to S370. Steps S310-S350 respectively correspond to... Figure 1 Steps S110-S150 of the implementation method, step S370 corresponds to Figure 1 Step S370 of the implementation method is detailed in the following article. Figure 1 The relevant descriptions of the implementation methods will not be repeated here.

[0095] In step S360, if a hit occurs, the requested data is obtained based on the hit physical cache path, and the rereference prediction value of the hit physical cache path is updated to the minimum value. At the same time, the path indication information configured in the root node and intermediate nodes of the metadata tree is updated.

[0096] A hit indicates that the DRAM cache contains the data at the corresponding physical address in the slow memory that the memory access request needs to access. In this case, the requested data can be obtained by accessing the DRAM cache.

[0097] A minimum rereference prediction value indicates that the corresponding physical cache path has the highest priority for being accessed again and is least likely to be replaced during replacement. When request data is retrieved directly from a hit physical cache path, it means that the corresponding physical cache path has been frequently used recently and should not be used as the target physical cache path for replacement. Therefore, the rereference prediction value is set to the minimum. As one possible implementation, the minimum value can be set to 0.

[0098] As one possible implementation, during the process of updating the path indication information configured in the root and intermediate nodes of the metadata tree when a hit occurs, the logical subset to which the hit belongs is first determined based on the physical cache path. Then, the leaf node corresponding to the logical subset in the metadata tree is determined. Afterwards, starting from that leaf node, the path is traced back up the metadata tree to the root node, and the path indication information of the intermediate nodes and the root node traversed by the traversal path is updated sequentially. When the path indication information is represented by a path indication bit, the update method can be as follows: if the subtree traversed by the traversal path belongs to the left subtree of the root node or an intermediate node, the value of the path indication bit of the corresponding root node or intermediate node is updated to 0. If the subtree traversed by the traversal path belongs to the right subtree of the root node or an intermediate node, the value of the path indication bit of the corresponding root node or intermediate node is updated to 1.

[0099] As one possible implementation, selecting a target physical cache path from the physical cache paths included in the target logical subset based on the rereference prediction values ​​of each physical cache path in the target logical subset includes: determining whether there is a physical cache path in the target logical subset whose rereference prediction value is greater than or equal to the eviction threshold. If there is a physical cache path whose rereference prediction value is greater than or equal to the eviction threshold, one of the physical cache paths whose rereference prediction value is greater than or equal to the eviction threshold is selected as the target physical cache path.

[0100] The eviction threshold should be a relatively large value, with the eviction threshold > initial value > minimum value. The size of the eviction threshold can be set according to the actual application. If the rereference prediction value is greater than or equal to the eviction threshold, it means that the corresponding physical cache path is the least accessed physical cache path among all physical cache paths included in the target logical subset. Therefore, one of the physical cache paths with a rereference prediction value greater than or equal to the eviction threshold is selected as the target physical cache path. If there are multiple physical cache paths with a rereference prediction value greater than or equal to the eviction threshold, one can be randomly selected (or selected through round-robin) as the target physical cache path. If there is only one physical cache path with a rereference prediction value greater than or equal to the eviction threshold, the corresponding physical cache path is selected as the target physical cache path.

[0101] As another possible implementation, based on the rereference prediction values ​​of each physical cache path in the target logical subset, a target physical cache path is selected from the physical cache paths included in the target logical subset. This includes: determining whether there is a physical cache path in the target logical subset whose rereference prediction value is greater than or equal to the eviction threshold. If no physical cache path has a rereference prediction value greater than or equal to the eviction threshold, the rereference prediction values ​​of each physical cache path in the target logical subset are incremented until a physical cache path with a rereference prediction value greater than or equal to the eviction threshold is found. One of the physical cache paths with a rereference prediction value greater than or equal to the eviction threshold is selected as the target physical cache path.

[0102] If no physical cache path has a rereference prediction value greater than or equal to the eviction threshold, an active aging mechanism is triggered. This involves incrementing the rereference prediction value of each physical cache path in the target logical subset until a physical cache path with a rereference prediction value greater than or equal to the eviction threshold is found. The increment operation can be performed by adding 1 to the rereference prediction value each time.

[0103] As one possible implementation, the process of determining the initial value of the rereference prediction includes: real-time monitoring of system operating status information. This system operating status information includes the final-level cache miss rate, local memory miss rate, change in local memory miss rate, DRAM cache miss rate, and change in DRAM cache miss rate.

[0104] If the last-level cache miss rate is less than or equal to the first threshold, it indicates that the overall cache pressure of the current system is low. In this case, the initial value is updated to A (e.g., A=1), which represents high insertion priority, to extend the residence time of data blocks in the DRAM cache.

[0105] If the last-level cache miss rate exceeds the first threshold, the local memory miss rate exceeds the second threshold, and the change in the local memory miss rate exceeds the third threshold, it indicates that the current local memory access pressure is high and showing a continuous upward trend. In this case, the initial value is updated to B (e.g., B=2), which represents medium insertion priority.

[0106] When the final-level cache miss rate exceeds the first threshold, the local memory miss rate exceeds the second threshold, the change in local memory miss rate exceeds the third threshold, the DRAM cache miss rate exceeds the fourth threshold, and the change in DRAM cache miss rate is positive (i.e., showing an upward trend), it indicates that the DRAM cache is in a state of significant failure or severe congestion. In this case, updating the initial value to C (e.g., C=3), which represents a low insertion priority, ensures that newly inserted data blocks are preferentially evicted during subsequent replacement processes, thereby preventing low-value data from occupying cache space for extended periods.

[0107] During real-time monitoring of system operating status information, a fixed sampling time window can be set (e.g., every 1 million processor clock cycles or every 100,000 instructions). Within each sampling time window, key operating metrics of the processor and storage system (which may include last-level cache miss rate, local memory miss rate, DRAM cache miss rate, etc.) are statistically analyzed using a performance monitoring unit (PMU) or dedicated hardware counters. At the end of the sampling time window, the current values ​​of the above metrics are calculated relative to the previous sampling time window to show their changing trends (which may include changes in local memory miss rate, DRAM cache miss rate, etc.).

[0108] Initial values ​​A, B, and C correspond to high, medium, and low reuse states of the system, respectively. When data is stored in an idle physical cache path, the rereference prediction value for the corresponding idle physical cache path is set to the initial value A, B, or C. Assigning a smaller initial value in the high reuse state accelerates the retention of hot data (frequently accessed data). Assigning a larger initial value in the low reuse state encourages the earlier eviction of cold data (infrequently accessed data). The initial value is only updated at the sampling time window boundaries, ensuring rapid response to phased changes in workload while effectively reducing the hardware and system overhead of continuous online computing.

[0109] This implementation employs a dynamic re-reference prediction adjustment mechanism based on runtime state awareness. With the support of the operating system, this mechanism periodically collects and analyzes system runtime state information to identify the access and reuse characteristics of the current workload. Through a tiered, state-aware initial value update method, this implementation achieves fine-grained, adaptive adjustment of cache insertion priority under different memory pressure levels, thereby improving the overall utilization efficiency and stability of the DRAM cache space.

[0110] Regarding step S150, in some embodiments of this disclosure, it may include, for example... Figure 4 Steps S1501 to S1503 are shown.

[0111] In step S1501, the physical address is determined to be hit based on the label of each physical cache path in the cache set.

[0112] Tag-based methods can determine whether a physical address corresponds to a physical page hit.

[0113] In step S1502, if a physical address is hit, the validity bitmap of the sub-block of the physical page corresponding to the physical address is determined.

[0114] Since memory access requests do not need to access the entire physical page, but only the content of a specific sub-block within the physical page, it is also necessary to determine whether the corresponding sub-block is hit even if the physical address is hit.

[0115] As one possible implementation, determining the sub-block validity bitmap of the physical page corresponding to the physical address includes: searching the page-level authoritative metadata table based on the physical page frame number (PFN) in the physical address to obtain the sub-block validity bitmap of the physical page corresponding to the physical address. The page-level authoritative metadata table records the mapping relationship between the physical page frame number (PFN) and the corresponding sub-block validity bitmap of the physical page, and can serve as the final consistency judgment basis for the sub-block validity bitmap. The page-level authoritative metadata table can then be addressed using the physical page frame number, realizing the logical transformation from physical space index to fine-grained sub-block validity bitmap within the physical page.

[0116] In step S1503, based on the sub-block validity bitmap, it is determined whether the memory access request has been hit.

[0117] The sub-block validity bitmap is used to record the validity of each sub-block within a physical page. When a sub-block is determined to be valid based on the sub-block validity bitmap, it means that the physical cache path corresponding to the physical page stores the content of that sub-block, thus the memory access request is considered a hit. When a sub-block is determined to be invalid based on the sub-block validity bitmap, it means that the physical cache path corresponding to the physical page does not store the content of that sub-block, thus the memory access request is considered a miss.

[0118] Figure 5 A flowchart illustrating a memory access request hit determination method according to one embodiment of this disclosure is shown. Figure 5 The method shown includes steps S510 to S540.

[0119] In step S510, during the process of determining the physical address corresponding to the memory access request, when a TLB miss occurs and page table traversal is triggered, page table traversal and page table entry expansion structure lookup are performed in parallel.

[0120] Page table traversal is used to obtain the physical page frame number. As one possible implementation, the physical page frame number can be obtained by initiating a serial memory access through the memory management unit according to the standard four-level page table (such as CR3->PGD->PUD->PMD->PTE in x86-64 architecture).

[0121] Page table entry extension structure lookup is used to determine the sub-block validity bitmap of the corresponding physical page based on the virtual address. The page table entry extension structure records the mapping relationship between virtual addresses or their hash values ​​and the corresponding sub-block validity bitmaps of the physical page. It can be indexed using the hash value or linear mapping of the virtual address to match and retrieve the sub-block validity bitmap corresponding to the virtual address. As one possible implementation, while initiating a page table traversal, the memory management unit performs a sub-block validity bitmap lookup from the page table entry extension structure based on the virtual address.

[0122] In the example above using a standard four-level page table, the page table entry extension structure is used to record the mapping relationship between specific bits of the virtual address (such as bits (12, 19)) and the corresponding sub-block validity bitmap of the physical page. After outputting the specific bits of the virtual address in the PMD stage, PTE queries (i.e., page table traversal) and page table entry extension structure queries are performed based on these specific bits.

[0123] In step S520, if the physical page frame number is obtained based on page table traversal, it is determined whether a valid bitmap of the sub-block is found.

[0124] In step S530, if the sub-block validity bitmap is not found, the sub-block validity bitmap is searched through the page-level authoritative metadata table based on the physical page frame number.

[0125] If no valid sub-block bitmap is found, it means that the page table entry extended structure query timed out or returned an invalid value. The valid sub-block bitmap needs to be determined based on the physical page frame number obtained by traversing the page table.

[0126] In step S540, based on the sub-block validity bitmap, it is determined whether the memory access request has been hit.

[0127] Steps S510 to S540 can ensure the correctness of the hit determination.

[0128] Figure 6A flowchart illustrating a memory access request hit determination method according to another embodiment of this disclosure is shown. Figure 6 The method shown includes steps S610 to S630. Steps S610-S620 respectively correspond to... Figure 5 For details of steps S510-S520 of the implementation method, please refer to [link / reference]. Figure 5 The relevant descriptions of the implementation methods will not be repeated here.

[0129] In step S630, if the sub-block validity bitmap is found, it is determined whether the memory access request is hit based on the sub-block validity bitmap.

[0130] If a sub-block validity bitmap is found, it means the page table entry extension structure query is valid. You can directly determine whether the memory access request has been hit based on the sub-block validity bitmap obtained through the page table entry extension structure query, without having to perform the step of determining the sub-block validity bitmap based on the physical page frame number.

[0131] Steps S610 to S630 can hide the serial latency of sub-block metadata access.

[0132] Figure 7 A flowchart illustrating a memory access request hit determination method according to yet another embodiment of this disclosure is shown. Figure 7 The method shown includes steps S710 to S730.

[0133] In step S710, during the process of determining the physical address corresponding to the memory access request, when a TLB hit occurs, the sub-block validity bitmap is looked up based on the page-level metadata cache.

[0134] Page-level metadata cache is used to record the mapping relationship between physical page frame numbers and the corresponding sub-block validity bitmaps of physical pages. As one possible implementation, the page-level metadata cache can be a small static random access memory (SRAM) structure based on LRU (Least Recently Used) management, using a physical page frame number indexing mechanism.

[0135] In step S720, it is determined whether the sub-block validity bitmap is valid.

[0136] As one possible implementation, the sub-block validity bitmap can be determined to be the latest version based on its version number. If the sub-block validity bitmap is the latest version, it can be determined to be valid. If the sub-block validity bitmap is not the latest version, it can be determined to be invalid.

[0137] In step S730, if the sub-block validity bitmap is valid, the system determines whether the memory access request has been hit based on the sub-block validity bitmap.

[0138] This implementation achieves fast lookup of sub-block validity bitmaps through page-level metadata caching, enabling low-latency decoupling of metadata access and address translation.

[0139] Figure 8 A flowchart illustrating a memory access request hit determination method according to another embodiment of this disclosure is shown. Figure 8 The method shown includes steps S810 to S830. Steps S810-S820 respectively correspond to... Figure 7 For details of steps S710-S720 of the implementation method, please refer to [link / reference]. Figure 5 The relevant descriptions of the implementation methods will not be repeated here.

[0140] In step S830, if the sub-block validity bitmap is invalid, the memory access request is determined to be hit based on the sub-block validity bitmap obtained by looking up the page-level authoritative metadata table.

[0141] When generating the latest version of the sub-block validity bitmap, it is first written to the page-level authoritative metadata table. The sub-block validity bitmap obtained based on the page-level authoritative metadata table serves as the sole criterion for judgment.

[0142] While both the page-level metadata cache and the page-level authoritative metadata table are used to record the mapping between physical page frame numbers and the corresponding sub-block validity bitmaps of physical pages, they differ in their roles. The page-level authoritative metadata table serves as the final basis for ensuring the consistency of sub-block states. As the only writable source, the page-level authoritative metadata table is written to during sub-block validity bitmap updates via write operations. The sub-block validity bitmaps recorded in the page-level metadata cache and page table entry extension structure are maintained only as read-only copies or cached copies. Because the page-level metadata cache is located within the memory management unit, it can achieve zero-latency, no-serial-overhead retrieval of the sub-block validity bitmap within the TLB hit path, thus completely decoupling the sub-block-level cache hit determination from the memory access critical path.

[0143] It should be noted that while temporary inconsistencies are allowed between sub-block validity bitmaps stored in the page table entry extension structure, page-level metadata cache, and page-level authoritative metadata table, all write operations to the sub-block validity bitmap must strictly propagate downstream from the page-level authoritative metadata table. If data cleanup of an entire physical page occurs, it must first be marked as invalid in the page-level authoritative metadata table before data cleanup can be performed.

[0144] As one possible implementation, determining whether a memory access request has been hit based on a sub-block validity bitmap includes: determining whether the target sub-block corresponding to the memory access request is valid based on the sub-block validity bitmap. If the target sub-block corresponding to the memory access request is valid, the memory access request is determined to have been hit.

[0145] The sub-block validity bitmap records whether each sub-block contained in the corresponding physical page is valid, for example, by using 0 or 1 to indicate whether each sub-block is valid. When the flag is 0, it means that the corresponding target sub-block is invalid; when the flag is 1, it means that the corresponding target sub-block is valid. If the target sub-block is valid, it means that the data content of the target sub-block is stored in the corresponding physical cache. At this time, it can be determined that the memory access request has hit, and the data content of the target sub-block can be retrieved from the corresponding physical cache as the requested data.

[0146] According to any of the above embodiments, this disclosure also provides a memory management device 900. Figure 10 This is a schematic block diagram of a memory management device 900 according to one embodiment of this disclosure. Figure 10 As shown, the memory management device 900 includes a DRAM cache partitioning module 910, a metadata tree construction module 920, a physical address determination module 930, a cache set determination module 940, a hit judgment module 950, a request data acquisition module 960, and a request data output module 970.

[0147] The DRAM cache partitioning module 910 is used to divide the DRAM cache into multiple cache sets, and each cache set into multiple logical subsets, each logical subset containing multiple physical cache paths.

[0148] The metadata tree construction module 920 is used to construct the metadata tree corresponding to each cache set. The metadata tree includes a root node, intermediate nodes, and leaf nodes. The root node and intermediate nodes are configured with path indication information, which is used to indicate the path of the most recent access to the subtree. The leaf nodes are used to record the metadata of each physical cache path contained in the logical subset, and each leaf node corresponds to a logical subset. The metadata includes re-reference prediction values, which are used to indicate the priority of the corresponding physical cache path being accessed again.

[0149] The physical address determination module 930 is used to determine the physical address corresponding to the memory access request in response to the memory access request.

[0150] The cache set determination module 940 is used to determine the cache set corresponding to a memory access request based on the physical address.

[0151] The hit detection module 950 is used to determine whether a memory access request has a hit based on the cache set.

[0152] The request data acquisition module 960 is used to acquire request data from slow memory in the event of a cache miss; if no free physical cache path exists in the cache set, it locates the target logical subset from the metadata tree according to the path indication information; selects the target physical cache path from the physical cache paths included in the target logical subset based on the rereference prediction value of each physical cache path in the target logical subset; replaces the stored content of the target physical cache path with the request data, and updates the rereference prediction value of the target physical cache path to the initial value; in the event of a cache miss, it acquires the request data based on the hit physical cache path and updates the rereference prediction value of the hit physical cache path to the minimum value.

[0153] The request data output module 970 is used to output request data.

[0154] The memory management device 900 disclosed herein can be implemented through a computer software architecture.

[0155] According to further embodiments of this disclosure, an electronic device is also provided. Figure 11 This diagram illustrates a schematic block diagram of an electronic device employing a processor-based hardware implementation according to an embodiment of the present disclosure. The hardware structure of the electronic device of the present disclosure can be implemented using a bus architecture. The bus architecture can include any number of interconnect buses and bridges, depending on the specific application and overall design constraints of the hardware. Bus 1100 connects various circuits including one or more processors 1200, memory 1300, and / or hardware modules. Bus 1100 can also connect various other circuits 1400 such as peripheral devices, voltage regulators, power management circuits, external antennas, etc. Bus 1100 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Component (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, only one connecting line is used in this figure, but this does not indicate that there is only one bus or one type of bus.

[0156] This disclosure also provides a readable storage medium storing a computer program that, when executed by a processor, is used to implement the methods described above. A "readable storage medium" can be any means capable of containing, storing, communicating, propagating, or transmitting a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples of a readable storage medium include: an electrical connection with one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable read-only memory (CDROM), etc.

[0157] This disclosure also provides a computer program product, the methods of which can be implemented wholly or partially through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented wholly or partially as a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed, all or part of the processes or functions of this disclosure are performed.

[0158] Computer programs or instructions can be stored in a readable storage medium or transferred from one readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The readable storage medium can be any available medium capable of access, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; an optical medium, such as a digital video optical disc; or a semiconductor medium, such as a solid-state drive. The computer-readable storage medium can be a volatile or non-volatile storage medium, or it can include both volatile and non-volatile types of storage media.

[0159] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0160] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus, and computer program products according to this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0161] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0162] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0163] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., refer to specific features, structures, or characteristics described in connection with that embodiment / mode or example, which are included in at least one embodiment / mode or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0164] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A memory management method characterized by comprising: The method comprises the following steps: dividing a DRAM cache into a plurality of cache sets, and dividing each cache set into a plurality of logical subsets, each logical subset containing a plurality of physical cache ways; constructing a metadata tree corresponding to each cache set, the metadata tree comprising a root node, intermediate nodes and leaf nodes, the root node and the intermediate nodes each being configured with path indication information, the path indication information being used to indicate a path of a most recently accessed sub-tree, the leaf nodes being used to record metadata of each physical cache way contained in the logical subset, and each leaf node corresponding to a logical subset, the metadata comprising a refence prediction value, the reference prediction value being used to represent a priority of the corresponding physical cache way being accessed again; in response to a memory access request, determining a physical address corresponding to the memory access request; based on the physical address, determining a cache set corresponding to the memory access request; based on the cache set, determining whether the memory access request is a hit; in the case of a miss, obtaining request data from a slow memory, in the case that there is no idle physical cache way in the cache set, locating a target logical subset from the metadata tree according to the path indication information, selecting a target physical cache way from each physical cache way contained in the target logical subset based on the reference prediction value of each physical cache way in the target logical subset, and replacing storage content of the target physical cache way with the request data and updating the reference prediction value of the target physical cache way to an initial value; in the case of a hit, obtaining request data based on the hit physical cache way, updating the reference prediction value of the hit physical cache way to a minimum value, and updating the path indication information configured in the root node and the intermediate nodes of the metadata tree; and outputting the request data; wherein, based on the cache set, determining whether the memory access request is a hit comprises: based on the tags of each physical cache way in the cache set, determining whether the physical address is a hit; in the case that the physical address is a hit, determining a sub-block validity bitmap of a physical page corresponding to the physical address; and based on the sub-block validity bitmap, determining whether the memory access request is a hit. The determining whether the memory access request hits comprises: when a TLB miss occurs and triggers a page table walk in determining the physical address corresponding to the memory access request, performing the page table walk and a page table entry extension structure query in parallel, the page table walk is used to obtain a physical page frame number, and the page table entry extension structure query is used to obtain a sub-block validity bitmap of a corresponding physical page from the page table entry extension structure according to a virtual address, the page table entry extension structure is used to record a mapping relationship between a virtual address or a hash value of the virtual address and the sub-block validity bitmap of the corresponding physical page; judging whether the sub-block validity bitmap is found based on the physical page frame number obtained through the page table walk; when the sub-block validity bitmap is not found, finding the sub-block validity bitmap from a page-level authoritative metadata table based on the physical page frame number, the page-level authoritative metadata table records a mapping relationship between a physical page frame number and a sub-block validity bitmap of a corresponding physical page; and determining whether the memory access request hits based on the sub-block validity bitmap.

2. The memory management method of claim 1, wherein, The selecting the target physical cache way from the physical cache ways included in the target logical subset based on the reference prediction values of the physical cache ways in the target logical subset comprises: determining whether there is a physical cache way with a reference prediction value greater than or equal to an eviction threshold value in the target logical subset; and in a case where there is a physical cache way with a reference prediction value greater than or equal to the eviction threshold value, taking one of the physical cache ways with the reference prediction value greater than or equal to the eviction threshold value as the target physical cache way.

3. The memory management method of claim 1, wherein, The selecting the target physical cache way from the physical cache ways included in the target logical subset based on the reference prediction values of the physical cache ways in the target logical subset comprises: determining whether there is a physical cache way with a reference prediction value greater than or equal to an eviction threshold value in the target logical subset; and in a case where there is no physical cache way with a reference prediction value greater than or equal to the eviction threshold value, performing an increment operation on the reference prediction values of the physical cache ways in the target logical subset until there is a physical cache way with a reference prediction value greater than or equal to the eviction threshold value; and taking one of the physical cache ways with the reference prediction value greater than or equal to the eviction threshold value as the target physical cache way.

4. The memory management method of claim 1, wherein, The determination process of the initial value of the reference prediction value comprises: monitoring system running state information in real time, the system running state information comprises a last-level cache miss rate, a local memory miss rate, a local memory miss rate change amount, a DRAM cache miss rate and a DRAM cache miss rate change amount; in a case where the last-level cache miss rate is less than or equal to a first threshold value, setting the initial value as A; in a case where the last-level cache miss rate is greater than the first threshold value, the local memory miss rate is greater than a second threshold value, and the local memory miss rate change amount is greater than a third threshold value, setting the initial value as B; and in a case where the last-level cache miss rate is greater than the first threshold value, the local memory miss rate is greater than the second threshold value, and the local memory miss rate change amount is less than the third threshold value, setting the initial value as C. In a case where the last-level cache miss rate is greater than a first threshold, the local memory miss rate is greater than a second threshold, the local memory miss rate variation is greater than a third threshold, the DRAM cache miss rate is greater than a fourth threshold, and the DRAM cache miss rate variation is a positive number, the initial value is set as C, where 0 5. The memory management method of claim 1, wherein, The method comprises: Determining a sub-block validity bitmap of a physical page corresponding to the physical address comprises:

6. The memory management method of claim 1, wherein, Searching in a page-level authority metadata table based on a physical page frame number in the physical address to obtain the sub-block validity bitmap of the physical page corresponding to the physical address. Determining whether the memory access request hits comprises: In a case where a TLB hit occurs in the physical address corresponding to the memory access request, searching a sub-block validity bitmap according to a page-level metadata cache, the page-level metadata cache being used to store a mapping relationship between a virtual address and a corresponding physical page frame number; Determining whether the sub-block validity bitmap is valid; and 7. An electronic device, comprising: In a case where the sub-block validity bitmap is valid, determining whether the memory access request hits based on the sub-block validity bitmap; in a case where the sub-block validity bitmap is invalid, determining whether the memory access request hits based on the sub-block validity bitmap obtained by searching the page-level authority metadata table. The method comprises: a memory storing execution instructions; and 8. A computer program product comprising a computer program, characterized in that, a processor executing the execution instructions stored in the memory, so that the processor executes the memory management method in any one of claims 1 to 6. The computer program is executed by the processor to implement the memory management method in any one of claims 1 to 6. The computer program is executed by the processor to implement the memory management method in any one of claims 1 to 6.

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