A processing method and device of a multi-core processor, a storage medium and an electronic device

Abstract

Embodiments of the present disclosure provide a processing method and device of a multi-core processor, a storage medium and an electronic device, and relate to the technical field of computers. The multi-core processor includes a plurality of resource nodes in a network on a chip. The network on a chip adopts a mesh structure. The method comprises: in response to a setting instruction, setting a central region and a peripheral region for the plurality of resource nodes in the network on a chip; the central region includes at least two central resource nodes, and any two central resource nodes are directly connected; detecting a first priority and / or access demand of a process of each resource node in the plurality of resource nodes; determining at least one target process satisfying a first condition according to the first priority and / or access demand, and migrating the at least one target process to at least one central resource node of the central region. In this way, the delay of access of the target process is reduced, and the access efficiency between nodes is improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a processing method, apparatus, storage medium, and electronic device for a multi-core processor. Background Technology

[0002] In related technologies, the interconnect structure of multi-core processors (CPUs) generally adopts a mesh structure. Processor cores and routing nodes are arranged in a two-dimensional mesh. Each node is directly connected to its neighboring nodes, and data is transmitted hop-by-hop through links between adjacent nodes until it reaches the target node. Using simple routing algorithms (such as XY routing), in the two-dimensional mesh, data is first transmitted along the X-axis and then along the Y-axis. The traditional mesh interconnect structure of multi-core processors has significant advantages, such as high scalability; as the number of cores increases, the mesh structure can be easily expanded by simply adding more rows and columns; and modular design, as the mesh structure is easy to implement in a modular design, making it suitable for large-scale chip manufacturing.

[0003] Figure 1 This is a diagram of a traditional multi-core CPU architecture; such as... Figure 1 As shown, taking a 25-core CPU as an example, a MESH interconnect scheme is used to place the 25 processor cores in a 5×5 on-chip network. Each resource node includes a routing node (NODE) ​​and a compute node (i.e., a processor core (CORE)). The operating system distributes the processing processes across the 25 compute cores. If a compute node needs to access the resources of other compute nodes during the processing process, such as a process in CORE0 needing to access data in the cache of CORE24, an XY routing strategy is required. First, along the X direction, NODE0—NODE1—NODE2—NODE3—NODE4, then along the Y direction, NODE9—NODE14—NODE19—NODE24. After accessing the cache data in NODE24, if it is a write operation, the data is directly written to the cache space of NODE24. If it is a read operation, the data in the cache of NODE24 still needs to follow the above path and return to NODE0.

[0004] The above-mentioned MESH interconnection network structure based on the XY routing algorithm has the following drawbacks:

[0005] Latency issues: In large grids, data may need to go through multiple hops, leading to increased latency;

[0006] Uneven communication latency: Communication latency between different nodes in a mesh may be uneven. If nodes are adjacent in their topological structure, the latency is low; if nodes are far apart in their topological structure, the latency is high. For example... Figure 1 In the example, NODE0 accessing NODE24 requires 8 levels of routing nodes.

[0007] Due to the aforementioned drawbacks, multi-core CPUs suffer from reduced effectiveness in handling critical tasks, low efficiency in multi-threaded tasks with high cross-access frequency, and overall low chip performance, failing to truly unleash the optimal performance of multi-core processors. In particular, in scenarios with high inter-process access frequency, excessive inter-process access latency (such as when the system distributes processes across nodes that are far apart) leads to excessively low process processing efficiency, resulting in the inability to guarantee the real-time performance of critical processes. Summary of the Invention

[0008] This disclosure provides a multi-core processor processing method, apparatus, storage medium, and electronic device to at least solve the above-mentioned technical problems existing in the prior art.

[0009] The technical solution of this disclosure embodiment is implemented as follows:

[0010] In a first aspect, embodiments of this disclosure provide a processing method for a multi-core processor, the multi-core processor including multiple resource nodes in an on-chip network, the on-chip network adopting a mesh structure, the method comprising:

[0011] In response to a setting command, a central region and a peripheral region are set for multiple resource nodes in the on-chip network; the central region includes at least two central resource nodes, and any two central resource nodes are directly connected.

[0012] Detect the first priority and / or access requirements of the processes of each of the plurality of resource nodes;

[0013] Based on the first priority and / or access requirements, at least one target process that meets the first condition is determined, and the at least one target process is migrated to at least one central resource node in the central region.

[0014] Secondly, embodiments of this disclosure provide a processing apparatus for a multi-core processor, the multi-core processor including multiple resource nodes in an on-chip network, the on-chip network adopting a mesh structure, the apparatus comprising:

[0015] The first processing module is configured to, in response to a setting instruction, set a central region and a peripheral region for multiple resource nodes in the on-chip network; the central region includes at least two central resource nodes, and any two central resource nodes are directly connected.

[0016] The second processing module is used to detect the first priority and / or access requirements of the processes of each of the plurality of resource nodes;

[0017] The third processing module is used to determine at least one target process that meets the first condition based on the first priority and / or access requirements, and to migrate the at least one target process to at least one central resource node in the central region.

[0018] Thirdly, embodiments of this disclosure provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform any of the processing methods of a multi-core processor as described above.

[0019] Fourthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform a processing method according to any one of the multi-core processors.

[0020] The embodiments disclosed herein have the following beneficial effects:

[0021] The processing method, apparatus, storage medium, and electronic device of the multi-core processor provided in this disclosure include multiple resource nodes in an on-chip network, the on-chip network adopting a mesh structure. The method includes: in response to a setting instruction, setting a central region and a peripheral region for the multiple resource nodes in the on-chip network; the central region includes at least two central resource nodes, and any two central resource nodes are directly connected; detecting a first priority and / or access requirement of a process in each of the multiple resource nodes; determining at least one target process that meets a first condition based on the first priority and / or access requirement, and migrating the at least one target process to at least one central resource node in the central region. Thus, by determining the target process based on the first priority and / or access requirement and migrating the target process to a central resource node with higher communication efficiency, the access requirements between resource nodes are increased, significantly reducing the latency of target process access.

[0022] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0023] Figure 1 This is a diagram of a traditional multi-core CPU architecture;

[0024] Figure 2 A flowchart illustrating a multi-core processor processing method provided in an embodiment of this disclosure;

[0025] Figure 3 A schematic diagram of the central and peripheral regions of a multi-core processor provided in an embodiment of this disclosure;

[0026] Figure 4 This is a schematic diagram of the structure of a multi-core processor provided in an embodiment of the present disclosure;

[0027] Figure 5 This is a schematic diagram of the structure of a multi-core instruction and analysis module provided in an embodiment of the present disclosure;

[0028] Figure 6 A schematic diagram of the structure of an inter-core process hardware switching module provided in an embodiment of this disclosure;

[0029] Figure 7 A schematic diagram of the structure of a processing device for a core processor provided in an embodiment of this disclosure;

[0030] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0031] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0032] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0033] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0035] Figure 2 This is a flowchart illustrating a multi-core processor processing method provided in an embodiment of the present disclosure, as shown below. Figure 2 As shown, the method is applied to a multi-core processor, which includes multiple resource nodes in an on-chip network architecture. The on-chip network adopts a mesh structure, and the processing method of the multi-core processor includes:

[0036] Step 201: In response to the setting command, set a central region and a peripheral region for multiple resource nodes in the on-chip network; the central region includes at least two central resource nodes, and any two central resource nodes are directly connected;

[0037] Step 202: Detect the first priority and / or access requirements of the processes of each of the multiple resource nodes;

[0038] Step 203: Determine at least one target process that meets the first condition based on the first priority and / or access requirements, and migrate the at least one target process to at least one central resource node in the central region.

[0039] In some embodiments, the multi-core processor includes multiple resource nodes, each resource node including a routing node (NODE) ​​and a compute node (CORE). The routing node is responsible for data transmission between different compute cores; the compute node refers to the processor core (or processor core, etc.) that performs the actual computing tasks.

[0040] The multi-core processor employs a mesh interconnect scheme. In this embodiment, multiple resource nodes are divided into a central region and peripheral regions using configuration instructions. Resource nodes in the central region are fully interconnected; any two central resource nodes are directly connected. All other resource nodes, i.e., those in the peripheral regions, are referred to as peripheral resource nodes. The scope of the central region (i.e., its division) is configurable and modifiable. For example, it can be configured by the user according to specific application scenarios.

[0041] The first priority can reflect the importance or urgency of a process, while access requirements can reflect the time and / or frequency of access required for a process to access data.

[0042] The target process determined by the first priority refers to an important critical process. The target process determined by access requirements can refer to processes with high external core access frequency, processes with high inter-core cross-access frequency, etc. In this embodiment of the disclosure, based on the detected first priority and access requirements, at least one target process with high priority and / or high access requirements can be determined. By migrating the target processes (such as critical processes, processes with high external core access frequency, and processes with high inter-core cross-access frequency) to the first resource node in the fully connected central region for execution, and correspondingly deploying regular processes or processes with low inter-core cross-access frequency to peripheral resource nodes, the highest efficiency of the central resource node is achieved, greatly improving the inter-core data access rate of the target processes, reducing access latency, and improving the real-time performance of the target processes. This helps to achieve more efficient multi-core processing capabilities, especially in complex or multi-tasking environments.

[0043] The following provides an example of a structure after setting a central region and a peripheral region for multiple resource nodes in the on-chip network according to setting instructions. For example... Figure 3 As shown, Figure 3 This is a schematic diagram of a multi-core processor provided in an embodiment of the present disclosure. In the diagram, the central region includes 9 central resource nodes in a 3×3 configuration (of course, depending on the specific application scenario, the user can also choose central resource nodes of a 2×2 or 3×2 configuration as the fully connected central region). Figure 3 This is just one example, and is not intended to be limiting.

[0044] The term "fully interconnected" refers to a architecture where all central resource nodes are directly connected on the physical link, allowing direct access between any two central resource nodes without the need for cross-resource node access. For example, CORE6, CORE8, CORE15, CORE18, and CORE12 can directly access each other; CORE6 and CORE18, CORE6 and CORE8, CORE6 and CORE13, CORE6 and CORE16, and CORE6 and CORE17 can also directly access each other. Similarly, CORE7 and CORE11, CORE7 and CORE16, CORE7 and CORE17, CORE7 and CORE13, and CORE7 and CORE18 can also directly access each other. These connections will not be elaborated upon further here.

[0045] Here, a fully interconnected architecture is designed only in the central area. For peripheral resource nodes, such as CORE0, CORE5, CORE10, and CORE20, a mesh architecture is still used. Figure 1The example shown is the same. Based on the grid structure, the XY routing strategy is used for access. For example, if the process of compute node CORE0 wants to access the data in the cache of CORE4, the XY routing strategy is required. The process accesses the cache of CORE4 along the X direction: NODE0—NODE1—NODE2—NODE3—NODE4. This will not be elaborated on here.

[0046] In some embodiments, detecting the access requests of processes on each of the plurality of resource nodes includes:

[0047] Filter the process instructions for each resource node, and determine the target resource node to be interacted with for each instruction;

[0048] Based on the mesh structure of the on-chip network, and the destination resource node that each resource node and each instruction need to interact with, the total number of hops corresponding to the process of each resource node is determined; the total number of hops represents the access requirements corresponding to the process.

[0049] Accordingly, based on the access requirements, at least one target process that satisfies the first condition is determined, including:

[0050] Based on the total number of hops for each process of the resource node, select the N processes with the highest total hop count as the target processes; N is greater than or equal to 1.

[0051] Here, the resource node on which the process runs can be called the starting resource node, and the node that interacts with the starting resource node can be called the destination resource node. Furthermore, it can be understood that the execution of a process is actually implemented by the computing nodes of the resource nodes, i.e., the processor cores. Therefore, the interaction between resource nodes can be understood as the interaction between processor cores. The process of a resource node actually refers to the process running on its processor core, and the total number of hops corresponding to the process of a resource node can also be understood as the total number of hops corresponding to the process of a processor core.

[0052] For each resource node, the system can examine the instructions issued by its executing process. These instructions may involve access to other resource nodes (e.g., reading data from the cache of its own processor core or other processor cores, and writing data). Based on the nature of the instructions, it can identify which resource node is the target of the interaction required by that instruction, i.e., determine the destination resource node.

[0053] In a mesh architecture, resource nodes are arranged in a two-dimensional manner. Therefore, the access requirement can be reflected by the distance (i.e., the number of hops) between the current starting resource node (i.e., the resource node to which the process belongs) and the destination resource node. As the number of hops increases, the time consumed also increases, and correspondingly, the access efficiency decreases. That is, the fewer the hops, the higher the access efficiency; conversely, the more hops, the lower the access efficiency. Therefore, based on the access requirement of the number of hops, the target process with high access time and the need to improve access efficiency can be identified.

[0054] For each process currently running on a resource node, determine the total number of hops required for its execution, and select the N processes with the highest total number of hops as target processes. Here, "highest" means the process with the largest number of hops, i.e. the process with the lowest access efficiency. By migrating these poorly performing processes, the overall processing efficiency can be improved.

[0055] In some embodiments, the instructions include at least one of the following: a read instruction and a write instruction;

[0056] Based on the mesh structure of the on-chip network, and the destination resource node required for interaction between each resource node and each instruction, the total number of hops corresponding to the process of each resource node is determined, including:

[0057] If the instruction includes a read instruction, the first hop count from the starting resource node to the destination resource node is determined according to the grid structure and routing algorithm, and the first hop count is multiplied by 2 to obtain the second hop count;

[0058] If the instruction includes a write instruction, the third hop count of the process from the starting resource node to the destination resource node is determined according to the grid structure and routing algorithm;

[0059] The total number of hops is determined based on the second hop count and the third hop count.

[0060] Here, instructions from all processor cores can be obtained first. These instructions are distinguished according to processor cores and stored in DDR (Double Data Rate Synchronous Dynamic Random Memory) space. During processing, instructions are read from DDR in parallel (instructions from different cores are stored in different DDR spaces), and the read and write instructions are filtered out.

[0061] A read instruction indicates that the processor core needs to read data from the external cache (the cache space of this core or other cores) when executing the instruction; a write instruction indicates that the processor core needs to write data to the cache (the cache space of this core or other cores) when executing the instruction. It should be noted that during the instruction filtering process, when a branch jump instruction is encountered as the instruction read from DDR, subsequent instructions are filtered according to a 50 / 50 probability of jumping or not jumping (e.g., the first branch jump instruction is predicted to jump, the second branch jump instruction is predicted not to jump, the third branch jump instruction is predicted to jump, the fourth branch jump instruction is predicted not to jump, and so on). In this way, the instructions for the process of each resource node are filtered out, the destination resource node for each instruction's interaction is determined, and then, based on the on-chip network's mesh structure, and each resource node and the destination resource node for each instruction's interaction, the total number of hops corresponding to the process of each resource node is determined.

[0062] Here, the first hop count is the direct hop count from the starting resource node to the target resource node. This value is derived based on the actual grid structure and the routing algorithm used. Considering that read operations involve round trips, the first hop count is multiplied by 2 to obtain the second hop count. Write operations do not require round trips, so there is no need to double the hop count; the actual hop count is used as the third hop count. The second and third hop counts for all instructions are added together to obtain the final total hop count. The total hop count comprehensively considers the resource access requirements of both read and write instructions. The total hop count reflects the overall efficiency of the processor core in accessing other resource nodes by the instructions executed by the running processes.

[0063] In some embodiments, detecting the access requests of processes on each of the plurality of resource nodes includes:

[0064] Filter the process instructions for each resource node, and determine the target resource node to be interacted with for each instruction;

[0065] Based on the target resource node required for interaction for each instruction, determine the total number of times the process of each resource node accesses other resource nodes, where the total number of times represents the access requirements corresponding to the process;

[0066] Accordingly, based on the access requirements, at least one target process that satisfies the first condition is determined, including:

[0067] Based on the total number of times corresponding to each resource node, select the P processes with the highest total number of times as the target processes; where P is greater than or equal to 1.

[0068] Here, the total number of times a process of a resource node accesses other resource nodes actually refers to the total number of times the processor core of that resource node accesses other processor cores.

[0069] The total number of accesses represents the frequency with which a process accesses other resource nodes during execution. A higher total number of accesses is more likely to cause a performance bottleneck, resulting in lower access efficiency. Conversely, a lower total number of accesses results in higher access efficiency. Therefore, based on the total number of accesses, we can identify target processes with high access frequency and those that require improved access efficiency.

[0070] In some embodiments, the instructions include at least one of the following: a read instruction and a write instruction;

[0071] The step of determining the total number of times the process of each resource node accesses other resource nodes in accordance with the target resource node required for interaction according to each instruction includes:

[0072] If the instruction includes a read instruction, determine the first number of times the process travels from the starting resource node to the destination resource node, and multiply the first number by 2 to obtain the second number;

[0073] If the instruction includes a write instruction, determine the third time the process moves from the starting resource node to the destination resource node;

[0074] The total number of times is determined based on the second number and the third number.

[0075] Here, instructions from all processor cores can be obtained first. These instructions are distinguished according to processor cores and stored in DDR (Double Data Rate Synchronous Dynamic Random Memory) space. During processing, instructions are read from DDR in parallel (instructions from different cores are stored in different DDR spaces), and the read and write instructions are filtered out.

[0076] A read instruction indicates that the processor core needs to read data from the external cache (the cache space of this core or other cores) when executing the instruction; a write instruction indicates that the processor core needs to write data to the cache (the cache space of this core or other cores) when executing the instruction. It should be noted that during the instruction filtering process, when a branch jump instruction is encountered as the instruction read from DDR, subsequent instructions are filtered according to a 50 / 50 probability of jumping or not jumping (e.g., the first branch jump instruction is predicted to jump, the second branch jump instruction is predicted not to jump, the third branch jump instruction is predicted to jump, the fourth branch jump instruction is predicted not to jump, and so on). In this way, the instructions of the process for each resource node are filtered out, the target resource node for each instruction's interaction is determined, and thus the total number of times the process of each resource node accesses other resource nodes can be determined.

[0077] Specifically, the first count represents the number of inter-core accesses by the process from the starting resource node to the target resource node. Considering that read operations involve round trips, the first count is multiplied by 2 to obtain the second count. Write operations do not require round trips, so the actual number of accesses is used as the third count. Adding the second and third counts for all instructions yields the final total count. The total count comprehensively considers the resource access requirements of both read and write instructions, reflecting the overall efficiency of the processor core in accessing other resource nodes for the running processes.

[0078] It should be noted that the total number of jumps and the total number of attempts can be determined simultaneously. The following is an example of determining the total number of jumps and the total number of attempts.

[0079] like Figure 4 As shown, the multi-core processor has a multi-core instruction pre-analysis module, which can be used to pre-analyze the instructions used by the processes of each resource node (i.e. all processor cores) in the multi-core processor to obtain the access frequency (such as the total number of jumps and total number of times mentioned above) of all processor cores needing to access other processor cores.

[0080] like Figure 5 As shown, the multi-core instruction pre-analysis module may include: a multi-core instruction acquisition module, a read instruction pre-analysis module, a write instruction pre-analysis module, and an instruction pre-analysis information table creation module.

[0081] The multi-core instruction fetching module is used to fetch instructions from all processor cores. These instructions are stored in the DDR space according to the core. Internally, this module reads instructions from DDR in parallel (instructions from different cores are stored in different DDR spaces) and filters the read and write instructions. During the instruction filtering process, when a branch jump instruction is encountered when read from DDR, subsequent instructions are filtered according to the above-mentioned 50% probability of jumping and 50% probability of not jumping (e.g., the first branch jump instruction is predicted to jump, the second branch jump instruction is predicted not to jump, the third branch jump instruction is predicted to jump, the fourth branch jump instruction is predicted not to jump, and so on). The instructions are then passed to the read instruction pre-analysis module and the write instruction pre-analysis module respectively according to the core ID.

[0082] The instruction pre-analysis module is used to differentiate instructions based on core ID and perform multi-channel parallel processing, with each processor core corresponding to one processing channel. Each processing channel independently receives the read instructions with the corresponding ID selected by the multi-core instruction acquisition module.

[0083] For example, Figure 4 The architecture shown corresponds to 25 channels. Channel 0 receives read instructions from processor core 0 (i.e., CORE0 in the diagram), channel 1 receives read instructions from processor core 1 (i.e., CORE1 in the diagram), and so on. Each channel performs further preprocessing on the read instructions, identifying the processor core ID of the cache to be read under the corresponding read instruction, and passing this processor core ID information to the instruction pre-analysis information table creation module. The structure of the transmitted data can be: {SRC ID, DEST ID}, where SRC ID represents the starting processor core (i.e., the starting resource node), and DEST ID represents the target processor core (i.e., the destination resource node). For example, if the read instruction for CORE0 needs to read the cache of CORE7, the corresponding transmitted data is {0, 7}; similarly, if the read instruction for CORE1 needs to read the cache of CORE1 (i.e., read the cache of this core), the corresponding transmitted data is {1, 1}.

[0084] The write instruction pre-analysis module is used to differentiate instructions based on core ID and perform multi-channel parallel processing, with each processor core corresponding to one processing channel. Each processing channel independently receives write instructions with the corresponding ID selected by the preceding multi-core instruction acquisition module.

[0085] For example, Figure 3In the architecture shown, there are 25 channels. Channel 0 receives write instructions from processor core 0, channel 1 receives write instructions from processor core 1, and so on. Each channel performs further preprocessing on the write instructions, identifying the processor core ID of the cache to be read under the corresponding write instruction, and passing this processor core ID information to the instruction pre-analysis information table creation module. The format for transmitting data can be: {SRCID, DEST ID}, where SRC ID represents the starting processor core (i.e., the starting resource node), and DEST ID represents the destination processor core (i.e., the destination resource node). For example, if a write instruction from CORE0 needs to write to the cache of CORE3, the corresponding transmitted data is {0, 3}; another example is that if a write instruction from CORE0 needs to write to the cache of CORE0 (i.e., write to the cache of this core), the corresponding transmitted data is {0, 0}.

[0086] The instruction pre-analysis information table creation module receives the processing results of read instruction pre-processing and write instruction pre-processing for different processor cores generated by the read instruction pre-analysis module and the write instruction pre-analysis module. It calculates the number of read instruction jumps (denoted as RD_JUMP_CNT), the number of write instruction jumps (denoted as WR_JUMP_CNT), and the corresponding total number of jumps (denoted as ALL_JUMP) for each processor core, and creates an instruction pre-analysis information table based on the obtained jump counts. The instruction pre-analysis information can adopt the format shown in Table 1 below. Correspondingly, the instruction pre-analysis information table creation module also has multiple processing channels interconnected with the read instruction pre-analysis module and the write instruction pre-analysis module.

[0087] Table 1

[0088]

[0089] The calculation of the number of read instruction jumps (RD_JUMP_CNT) for each processor core includes:

[0090] Based on the received {SRC ID, DEST ID}, utilize Figure 3 The MESH structure shown (which does not include the fully connected structure of the central resource node at this time, that is, all processor cores are MESH structures in this calculation process), and the corresponding XY routing algorithm, calculate the first hop count from all read instructions SRC_ID to DEST_ID of the current processor core, and multiply the first hop count by 2 as the final read instruction hop count RD_JUMP_CNT of the current processor core (because the read data still needs to be returned from DEST_ID to SRC_ID).

[0091] For example, suppose CORE0 has a total of 5 read instructions, and the results of its corresponding read instruction pre-analysis module include: {0, 5}, {0, 11}, {0, 0}, {0, 7}, and {0, 21}. Calculate the results for each:

[0092] The hop count corresponding to {0, 5} is 1 × 2 = 2 (the route is NODE0-NODE5);

[0093] The hop count corresponding to {0, 11} is 3×2 (the route is NODE0-NODE1-NODE6-NODE11).

[0094] The hop count corresponding to {0, 0} is 0;

[0095] The hop count corresponding to {0, 7} is 3×2 (the route is NODE0-NODE1-NODE2-NODE7).

[0096] The hop count corresponding to {0, 21} is 5×2 (the route is NODE0-NODE1-NODE6-NODE11-NODE16-NODE21).

[0097] Therefore, the number of jumps for the CORE0 read instruction is determined as follows:

[0098] RD_JUMP_CNT =1×2+3×2+0+3×2+5×2=24.

[0099] The calculation of the write instruction hop count (WR_JUMP_CNT) for each processor core includes:

[0100] Based on the received {SRC_ID, DEST_ID}, utilize Figure 3 The MESH structure shown (which does not include the fully connected structure of the central resource node at this time, that is, all processor cores are MESH structures in this calculation process), and the corresponding XY routing algorithm, calculate the third hop number from all write instructions SRC_ID to DEST_ID of the current processor core, which is used as the final write instruction hop number WR_JUMP_CNT of the current processor core (because the read data still needs to be returned from DEST_ID to SRC_ID).

[0101] For example, suppose the results of the write instruction pre-analysis module corresponding to CORE12 include: {12, 24}, {12, 4}, {12, 0}, {12, 12}, {12, 20}, and calculate them respectively:

[0102] The hop count corresponding to {12, 24} is 4 (the route is NODE12-NODE13-NODE14-NODE19-NODE24).

[0103] The hop count corresponding to {12,4} is 4 (the route is NODE12-NODE13-NODE14-NODE9-NODE4).

[0104] The hop count corresponding to {12, 0} is 4 (the route is NODE12-NODE11-NODE10-NODE5-NODE0).

[0105] The jump count corresponding to {12, 12} is 0;

[0106] The hop count corresponding to {12, 20} is 4 (the route is NODE12-NODE17-NODE22-NODE21-NODE20).

[0107] Therefore, the number of jumps for the CORE12 write command is determined as follows:

[0108] WR_JUMP_CNT=4+4+4+0+4=16.

[0109] By analogy, we can obtain the second jump count (RD_JUMP_CNT) of read instructions, the third jump count (WR_JUMP_CNT) of write instructions, and the corresponding total jump count (ALL_JUMP) for all processor cores. Total jump count (ALL_JUMP) = number of read instruction jumps (RD_JUMP_CNT) + number of write instruction jumps (WR_JUMP_CNT).

[0110] The instruction pre-analysis information table creation module is also used to calculate the total number of times each processor core accesses other processor cores (MUTUAL_SRC_ID_DEST_ID) and create the instruction pre-analysis information table as shown in Table 2 below.

[0111] Table 2

[0112]

[0113] The value of MUTUAL_SRC_ID_DEST_ID is equal to the number of read instructions between the processor core and other processor cores × 2 + the number of write instructions.

[0114] For example, if the pre-analysis result of the CORE0 read instruction is 1 time {0, 11}, and the pre-analysis result of the write instruction is 2 times {0, 11}, then the total number of mutual accesses between CORE0 and CORE11 is MUTUAL_0_11 = 1×2 + 2×1 = 4.

[0115] For example, if the pre-analysis result of the CORE11 read instruction is 2 times {11, 0}, and the pre-analysis result of the write instruction is 3 times {11, 0}, then the total number of mutual accesses between CORE11 and CORE0 is MUTUAL_11_0 = 2×2 + 3×1 = 7.

[0116] It should be noted that after setting the central area, steps 202 and 203 can be executed in real time, periodically, or multiple times after a certain process has finished running; that is, the contents of Table 1 and Table 2 are also updated in real time, that is, process migration can be performed in real time according to the actual running process, process status, running conditions, user needs, etc.

[0117] In some embodiments, detecting the first priority of the process of each of the plurality of resource nodes includes:

[0118] The first priority of each currently running process on each resource node is issued by the receiving software.

[0119] Determining at least one target process that satisfies the first condition based on the first priority includes:

[0120] Based on the first priority of each process, the M processes with the highest first priority are selected as the target processes; M is greater than or equal to 1.

[0121] Here, the first priority can be used to determine which processes should be given priority when allocating and scheduling system resources. This first priority can be set by the user according to their needs.

[0122] When applied, the system can receive the first priority of the processes currently running on each resource node from the management software or scheduler, and select the M processes with the highest first priority as the target processes based on the first priority of each process.

[0123] It should be noted that M, N, and P can be set according to actual needs and can also be adjusted adaptively; there are no restrictions on their values.

[0124] In some embodiments, determining at least one target process that satisfies the first condition based on the first priority and / or access requirement includes:

[0125] Determine the initial total number of migrateable central resource nodes;

[0126] N first candidate nodes, P second candidate nodes, and / or M third candidate nodes are determined for the process to be migrated; the first candidate nodes are determined according to a first priority, the second candidate nodes are determined according to the total number of hops reflecting the access demand, and the third candidate nodes are determined according to the total number of times reflecting the access demand.

[0127] The second total number is determined based on N, M and / or P;

[0128] If the second total does not exceed the first total, the processes of the N first candidate nodes, P second candidate nodes and / or M third candidate nodes are taken as the target processes;

[0129] If the second total exceeds the first total, the target process is selected from the processes of the N first candidate nodes, P second candidate nodes and / or M third candidate nodes.

[0130] Here, if the second total does not exceed the first total, that is, if the number of candidate processes does not exceed the number of migrated resource nodes, then the processes of these N first candidate nodes, P second candidate nodes and M third candidate nodes are directly used as target processes, that is, all candidate processes can be migrated.

[0131] If the second total exceeds the first total, then a selection process needs to be made from the candidate processes to determine which processes will ultimately be used as the target processes.

[0132] Among them, the N first candidate nodes are selected according to the first priority of the process, that is, the process with the highest priority is selected as the candidate;

[0133] The P second-candidate nodes are determined based on the total number of hops accessed, meaning that the process with the highest total hop count is selected as the candidate with the second-highest priority.

[0134] The M third candidate nodes are determined based on the total number of inter-core accesses, with the process having the highest total number of accesses being selected as the final candidate.

[0135] In some embodiments, filtering a target process from the processes of the N first candidate nodes, P second candidate nodes, and / or M third candidate nodes includes:

[0136] Determine the filtering priority corresponding to the first candidate node, the second candidate node, and / or the third candidate node, respectively;

[0137] The target process for the first total number is determined based on the screening priorities corresponding to the first candidate node, the second candidate node, and / or the third candidate node, respectively.

[0138] The first candidate node has a higher screening priority than the second candidate node, and the second candidate node has a higher screening priority than the third candidate node.

[0139] Here, the processes of the N first candidate nodes are selected based on the first priority, which is of high importance. Therefore, they have the highest screening priority.

[0140] The processes of the P second candidate nodes are determined based on the total number of hops, and their screening priority is lower than that of the N first candidate nodes;

[0141] The M third candidate nodes are determined based on the total number of visits, and their degree of reflecting access frequency is lower than that of the total number of hops. Therefore, their screening priority is lower than that of the P second candidate nodes.

[0142] If the selected candidate nodes have the same selection priority, the selection is based on their respective first priority, total hop count, or total number of attempts. For example, if all selected candidate nodes are first-priority nodes, the higher the first priority, the more likely the process will be selected as the target process; if all selected candidate nodes are second-priority nodes, the higher the total hop count, the more likely the process will be selected as the target process; if all selected candidate nodes are third-priority nodes, the higher the total number of attempts, the more likely the process will be selected as the target process.

[0143] Processes are selected sequentially based on their screening priority to ensure that more important tasks are processed first. This helps improve the system's resource utilization efficiency and processing capacity, especially in multi-core processor environments, where it can effectively handle the scheduling needs of processes with different priorities.

[0144] In some embodiments, migrating the at least one target process to at least one central resource node in the central region includes:

[0145] Determine the target center resource node corresponding to each target process in the at least one target process; each target center resource node corresponds to a unique target process.

[0146] Each of the target processes will be migrated to the corresponding target central resource node.

[0147] Here, each resource node (i.e., processor core) executes only one process. Before the migration begins, a target central resource node can be determined for each target process, meaning that each target process will be assigned to a specific central resource node.

[0148] After identifying the target processes and their corresponding target central resource nodes, a migration operation is performed to migrate each target process to its corresponding central resource node. The target processes are then executed using the central resource nodes to improve the inter-core data access rate of the target processes, reduce access latency, enhance the real-time performance of critical processes, and improve the optimal performance of multi-core processors.

[0149] In some embodiments, migrating each target process to the corresponding target central resource node includes:

[0150] Before migration, wait for the instructions in the current pipeline of the target central resource node to finish processing, then pause the instruction fetching operation of the target central resource node and back up the state of the target central resource node.

[0151] The target process is migrated to the target central resource node, and the original process state of the target central resource node is migrated to the original resource node of the target process.

[0152] Here, migrating a process to a resource node specifically refers to migrating the process to the processor core of that resource node. Specifically, to achieve seamless software migration, the processor core state of the target resource node is backed up before migration. First, the process waits for the current instruction in the processor core's pipeline to complete processing, pauses the instruction fetch operation, and uses pre-defined cache resources to store the registers and cached instructions and data of the target resource node's processor core. Then, the target process state is migrated to the target resource node's processor core, and finally, the process state of the target process is migrated back to the target process's original processor core.

[0153] The following is an example, such as Figure 4 As shown, the multi-core processor has an inter-core process hardware switching module. This module is used to migrate the target process to the fully interconnected central resource node for execution in a software-seamless and hardware-adaptive manner, based on two instruction pre-analysis information tables (i.e., Table 1 and Table 2 above) created by the multi-core instruction pre-analysis module. This greatly improves the inter-core data access rate of the target process, reduces access latency, improves the real-time performance of critical processes, and maximizes the utilization of the central fully interconnected resource node.

[0154] like Figure 6 As shown, the inter-core process hardware switching module may include: a priority setting module, an information table 1 processing module, an information table 2 processing module, a scheduling and allocation module, a state backup module, and a state transition module.

[0155] The priority setting module is used to receive the first priority of the processes currently running on the processor cores from the software. The types of first priorities can be determined by the user. For example, the default is divided into 8 priorities. If the processes currently running on processor core 0, processor core 12, and processor core 21 have the highest priority, then the result output by the priority setting module is PRIORITY_ID=0 / 12 / 21. The number of cores with the highest priority is M. In the example above, M can be 3. Of course, the value of M can be other depending on other situations.

[0156] The Information Table 1 processing module is used to process the output of Information Table 1 of the instruction pre-analysis. Information Table 1 contains the total number of hops (ALL_JUMP) of all processor cores accessing other cores. It selects the top N processor cores with the highest total number of hops (N is the default value, but can also be adjusted adaptively). For example, the top 4 processor cores with the highest ALL_JUMP in Information Table 1 are processor core 3, processor core 16, processor core 20, and processor core 22. The output result is ALL_JUMP_ID=3 / 16 / 20 / 22.

[0157] The Information Table 2 processing module processes the output of Information Table 2 from the instruction pre-analysis. Information Table 2 contains the total number of inter-core accesses. Further processing of the total number of accesses in Information Table 2 yields the total number of accesses (MUTUAL_SRC_ID_DEST_ID_ALL).

[0158] MUTUAL_SRC_ID_DEST_ID_ALL=MUTUAL_SRC_ID_DEST_ID + MUTUAL_DEST_ID_SRC_ID

[0159] MUTUAL_SRC_ID_DEST_ID_ALL represents the total number of times the starting processor core and the destination processor core access each other; for example, MUTUAL_0_11_ALL = MUTUAL_0_11 + MUTUAL_11_0 represents the total number of times processor core 0 and processor core 11 access each other.

[0160] Select the top P with the most total counts (P is the default value, but can be adjusted adaptively). For example, the top 3 with the largest MUTUAL_SRC_ID_DEST_ID_ALL are processor core 17, processor core 3, and processor core 5. The output result is MUTUAL_JUMP_ID=17 / 3 / 5.

[0161] It should be noted that the total number of PRIORITY_ID, ALL_JUMP_ID, and MUTUAL_JUMP_ID cannot exceed the total number of central resource nodes in the fully interconnected network. If the total number exceeds the total number of central resource nodes, some processes will be retained based on a filtering priority, where the filtering priority is PRIORITY_ID > ALL_JUMP_ID > MUTUAL_JUMP_ID.

[0162] The scheduling and allocation module is used to map the PRIORITY_ID, ALL_JUMP_ID, and MUTUAL_JUMP_ID to the fully connected central resource nodes. The principle is to map PRIORITY_ID to the very center of the central resource node, such as... Figure 3The CORE11, CORE 12, CORE 13, etc. shown map ALL_JUMP_ID and MUTUAL_JUMP_ID to the secondary centers of the central resource nodes, such as... Figure 3 The CORE6, CORE7, CORE8, CORE16, CORE17, CORE18, etc. are shown.

[0163] The state backup module is used to back up the state (self-backup) of processes originally located at the central resource node. The process state mainly includes two types of information: register information within the processor core and instructions and data in the processor core's cache. Before process migration, the state of the processor core to be replaced at the central resource node is backed up. First, the module waits for the instructions in the current pipeline of the replaced processor core to complete processing, pauses the instruction fetch operation, and uses the cache resources in the state backup module to store the registers, instructions, and data in the cache of the replaced processor core. After the state migration module migrates the process state of the processor core to be migrated to the processor core to be replaced, the process state of the replaced processor core is then migrated back to the original processor core to be migrated. For example, after processing by the scheduling and allocation module, if the process of processor core 0 needs to be migrated to processor core 12, then processor core 0 is the processor core to be migrated, and processor core 12 is the processor core to be replaced.

[0164] The state transition module is used to migrate the process state (register and cache data) of the core to be migrated to the processor core to be replaced. This module's functionality is only enabled after the processor core to be replaced has completed its hardware state backup. It also needs to wait for the processor core to be migrated to complete the pipelined processing of the current instruction, pausing the instruction fetch module. After completing the process state transition for the processor core to be migrated, the instruction fetch module is restarted. This module also needs to migrate the state of the processor core to be replaced from the state backup module to the original processor core to be migrated, and then restart the instruction fetch module. Referring to the example above, the state backup module first waits for processor core 12 to complete the processing of the current instruction, pausing instruction fetching for processor core 12 and backing up its state. Then, the state transition module waits for processor core 0 to complete the processing of the current instruction, pausing instruction fetching for processor core 0, migrating / copying the state data of processor core 0 to processor core 12, and starting instruction fetching for processor core 12. Finally, it migrates / copys the state data of processor core 12 to processor core 0 and starts instruction fetching for processor core 0.

[0165] The processor core states in the corresponding mapping relationship set by the scheduling and allocation module are migrated sequentially. The entire process is completed autonomously by the hardware and is invisible to the software. That is, the software does not need to make any changes, and the hardware autonomously completes the optimal multi-core interconnect architecture adjustment.

[0166] In some embodiments, the method further includes:

[0167] According to the first rule, a link priority is set for the link between any two resource nodes, wherein the first rule includes: the link priority of the central resource node in the central area is higher than the link priority of the peripheral resource node in the peripheral area;

[0168] If multiple resource nodes access the same resource node at the same time, the data traffic of the physical link will be redirected according to the link priority.

[0169] The link priority of the central resource node is higher than that of the peripheral resource nodes in the peripheral area.

[0170] Here, considering the issue of link resource allocation caused by simultaneous access to the same resource node in practical applications, a first rule is provided to address this problem: link priority allocation. Specifically, if a central resource node and peripheral resource nodes access the same resource node simultaneously, the link priority of the central resource node is higher than that of the peripheral resource nodes. The central resource node should be given priority, for example, by allocating more traffic or using the link preferentially.

[0171] In some embodiments, the method further includes:

[0172] If multiple resource nodes access the same resource node simultaneously, and all of these resource nodes are central resource nodes, the link priority is adjusted according to the filtering priority of each central resource node.

[0173] Here, if multiple central resource nodes access the same resource node at the same time, the link priority of multiple central resource nodes can be further adjusted. This can be determined by combining the filtering priority when determining the target process corresponding to the central resource node. It should be noted that at this time, the central resource node is actually running the corresponding target process. Therefore, adjusting the link priority based on the target process ensures the priority and parallelism requirements when there are multiple processes.

[0174] The following provides an example of link management. Multi-core processors can also have a link control module, which manages the traffic of relevant links based on process priority.

[0175] To ensure Figure 3 Priority is given to link resources among the central resource nodes. When a central resource node and a non-central resource node (i.e., peripheral resource node) access the same resource node, priority is given to ensuring access to the central fully connected resource node. Figure 3If NODE6 and NODE10 simultaneously access NODE5, the link control module will manage the link status of NODE5, prioritizing data traffic on the physical link between NODE6 and NODE10. Access will proceed with NODE6 first, followed by NODE10.

[0176] Simultaneously, this module also guarantees the priority of link resources within fully connected resource nodes. Following the principle of PRIORITY_ID > ALL_JUMP_ID > MUTUAL_JUMP_ID, it prioritizes access to processor cores with higher priority in the aforementioned formula. For example, if NODE12 and NODE17 simultaneously access NODE18, and NODE12 corresponds to PRIORITY_ID while NODE17 corresponds to ALL_JUMP_ID, the link control module will control the link status of NODE8, prioritizing data traffic on the physical link from NODE12 to NODE18. Unlike the above situation, in this scenario, the link control module sets a traffic ratio, such as allocating 70% of the traffic to NODE12 accessing NODE18 and 30% of the traffic to NODE17 accessing NODE18.

[0177] This module enables relative priority access competition between high-priority resource nodes and absolute priority access competition between central resource nodes and non-central resource nodes (i.e., peripheral resource nodes) in a fully interconnected system, thus maximizing the priority and parallelism of processes on the central resource nodes of the fully interconnected system.

[0178] Figure 7 This is a schematic diagram of the structure of a multi-core processor processing device provided in an embodiment of the present disclosure; as shown below. Figure 7 As shown, the multi-core processor includes multiple resource nodes in an on-chip network, the on-chip network adopts a mesh structure, and the device includes:

[0179] The first processing module is configured to, in response to a setting instruction, set a central region and a peripheral region for multiple resource nodes in the on-chip network; the central region includes at least two central resource nodes, and any two central resource nodes are directly connected.

[0180] The second processing module is used to detect the first priority and / or access requirements of the processes of each of the plurality of resource nodes;

[0181] The third processing module is used to determine at least one target process that meets the first condition based on the first priority and / or access requirements, and to migrate the at least one target process to at least one central resource node in the central region.

[0182] In some embodiments, the second processing module is configured to filter the process instructions of each resource node and determine the target resource node to be interacted with for each instruction;

[0183] Based on the mesh structure of the on-chip network, and the destination resource node that each resource node and each instruction need to interact with, the total number of hops corresponding to the process of each resource node is determined; the total number of hops represents the access requirements corresponding to the process.

[0184] Accordingly, based on the access requirements, at least one target process that satisfies the first condition is determined, including:

[0185] Based on the total number of hops for each process of the resource node, select the N processes with the highest total hop count as the target processes; N is greater than or equal to 1.

[0186] In some embodiments, the instructions include at least one of the following: a read instruction and a write instruction;

[0187] The second processing module is configured to, if the instruction includes a read instruction, determine the first hop count of the process from the starting resource node to the destination resource node according to the grid structure and routing algorithm, and multiply the first hop count by 2 to obtain the second hop count;

[0188] If the instruction includes a write instruction, the third hop count of the process from the starting resource node to the destination resource node is determined according to the grid structure and routing algorithm;

[0189] The total number of hops is determined based on the second hop count and the third hop count.

[0190] In some embodiments, the second processing module is configured to filter the process instructions of each resource node and determine the target resource node to be interacted with for each instruction;

[0191] Based on the target resource node required for interaction for each instruction, determine the total number of times the process of each resource node accesses other resource nodes, where the total number of times represents the access requirements corresponding to the process;

[0192] Accordingly, based on the access requirements, at least one target process that satisfies the first condition is determined, including:

[0193] Based on the total number of times corresponding to each resource node, select the P processes with the highest total number of times as the target processes; where P is greater than or equal to 1.

[0194] In some embodiments, the instructions include at least one of the following: a read instruction and a write instruction;

[0195] The second processing module is configured to, if the instruction includes a read instruction, determine the first number of times the process travels from the starting resource node to the destination resource node, and multiply the first number by 2 to obtain the second number;

[0196] If the instruction includes a write instruction, determine the third time the process moves from the starting resource node to the destination resource node;

[0197] The total number of times is determined based on the second number and the third number.

[0198] In some embodiments, the second processing module is configured to receive the first priority of each process currently running on each resource node as issued by the software.

[0199] Determining at least one target process that satisfies the first condition based on the first priority includes:

[0200] Based on the first priority of each process, the M processes with the highest first priority are selected as the target processes; M is greater than or equal to 1.

[0201] In some embodiments, the second processing module is configured to determine a first total number of migrateable central resource nodes;

[0202] N first candidate nodes, P second candidate nodes, and / or M third candidate nodes are determined for the process to be migrated; the first candidate nodes are determined according to a first priority, the second candidate nodes are determined according to the total number of hops reflecting the access demand, and the third candidate nodes are determined according to the total number of times reflecting the access demand.

[0203] The second total number is determined based on N, M and / or P;

[0204] If the second total does not exceed the first total, the processes of the N first candidate nodes, P second candidate nodes and / or M third candidate nodes are taken as the target processes;

[0205] If the second total exceeds the first total, the target process is selected from the processes of the N first candidate nodes, P second candidate nodes and / or M third candidate nodes.

[0206] In some embodiments, the second processing module is configured to determine the filtering priorities corresponding to the first candidate node, the second candidate node, and / or the third candidate node, respectively.

[0207] The target process for the first total number is determined based on the screening priorities corresponding to the first candidate node, the second candidate node, and / or the third candidate node, respectively.

[0208] The first candidate node has a higher screening priority than the second candidate node, and the second candidate node has a higher screening priority than the third candidate node.

[0209] In some embodiments, the third processing module is configured to determine the target center resource node corresponding to each target process in the at least one target process; each target center resource node corresponds to a unique target process;

[0210] Each of the target processes will be migrated to the corresponding target central resource node.

[0211] In some embodiments, the third processing module is configured to wait for the instruction processing in the current pipeline of the target central resource node to be completed before migration, then pause the instruction fetching operation of the target central resource node and back up the state of the target central resource node.

[0212] The target process is migrated to the target central resource node, and the original process state of the target central resource node is migrated to the resource node of the target process.

[0213] In some embodiments, the apparatus further includes: a fourth processing module, configured to set a link priority for a link between any two resource nodes according to a first rule, wherein the first rule includes: the link priority of the central resource node in the central region is higher than the link priority of the peripheral resource node in the peripheral region;

[0214] If multiple resource nodes access the same resource node simultaneously, the data traffic of the physical link is adjusted according to the link priority.

[0215] In some embodiments, the fourth processing module is further configured to adjust the link priority according to the filtering priority of each central resource node when multiple resource nodes access the same resource node at the same time and the multiple resource nodes are all central resource nodes.

[0216] It is understood that, when implementing the corresponding multi-core processor processing method, the processing apparatus of the core processor provided in the above embodiments can allocate the above processing to different program modules as needed to complete all or part of the processing described above. Furthermore, the apparatus and the corresponding method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0217] This application provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a multi-core processor processing method.

[0218] This application provides a computer-readable storage medium storing executable instructions, wherein the executable instructions are stored and, when executed by a processor, will cause the processor to execute the processing method of the multi-core processor provided in this application.

[0219] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0220] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0221] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborating files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0222] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0223] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure; as shown below. Figure 8 As shown, the electronic device 80 includes: a processor 801, and a memory 802 communicatively connected to the processor 801; the memory 802 stores instructions executable by the processor 801. The instructions are executed by the processor 801 to enable the processor 801 to perform:

[0224] In response to a setting command, a central region and a peripheral region are set for multiple resource nodes in the on-chip network; the central region includes at least two central resource nodes, and any two central resource nodes are directly connected.

[0225] Detect the first priority and / or access requirements of the processes of each of the plurality of resource nodes;

[0226] Based on the first priority and / or access requirements, at least one target process that meets the first condition is determined, and the at least one target process is migrated to at least one central resource node in the central region.

[0227] The electronic devices and corresponding multi-core processor processing methods provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0228] In practical applications, the electronic device 80 may further include at least one network interface 803. The various components of the electronic device 80 are coupled together via a bus system 804. It is understood that the bus system 804 is used to implement communication between these components. In addition to a data bus, the bus system 804 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 8 All buses are labeled as bus system 804. The number of processors 801 can be at least one, and the number of memories 802 can be at least one. Network interface 803 is used for wired or wireless communication between electronic device 80 and other devices.

[0229] The memory 802 in this embodiment is used to store various types of data to support the operation of the electronic device 80.

[0230] The methods disclosed in the above embodiments of this disclosure can be applied to or implemented by processor 801. Processor 801 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 801 or by instructions in software form. The processor 801 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 801 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 802. Processor 801 reads the information in memory 802 and, in conjunction with its hardware, completes the steps of the aforementioned multi-core processor processing method.

[0231] In some embodiments, the electronic device 80 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to perform the aforementioned methods.

[0232] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0233] In the above description, the term "some embodiments" refers to a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0234] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0235] It should be understood that in the various embodiments of this disclosure, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0236] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0237] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A processing method of a multi-core processor, characterized by, The multi-core processor includes multiple resource nodes in an on-chip network, the on-chip network adopting a mesh structure, and the method includes: In response to a setting command, a central region and a peripheral region are set for multiple resource nodes in the on-chip network; the central region includes at least two central resource nodes, and any two central resource nodes are directly connected. Detect the first priority and / or access requirements of the processes of each of the plurality of resource nodes; Based on the first priority and / or access requirements, at least one target process that meets the first condition is determined, and the at least one target process is migrated to at least one central resource node in the central region; Based on the access requirements, at least one target process that meets the first condition is identified, including one of the following: Based on the total hop count of each process in the resource node, select the N processes with the highest total hop count as the target processes; N is greater than or equal to 1. Based on the total number of times corresponding to each resource node, select the P processes with the highest total number of times as the target processes; where P is greater than or equal to 1. or, Determining at least one target process that satisfies the first condition based on the first priority includes: Based on the first priority of each process, the M processes with the highest first priority are selected as the target processes; where M is greater than or equal to 1. or, Determining at least one target process that satisfies the first condition based on the first priority and / or access requirements includes: Determine the initial total number of migrateable central resource nodes; N first candidate nodes, P second candidate nodes, and / or M third candidate nodes are determined for the process to be migrated; the first candidate nodes are determined according to a first priority, the second candidate nodes are determined according to the total number of hops reflecting the access demand, and the third candidate nodes are determined according to the total number of times reflecting the access demand. The second total number is determined based on N, M and / or P; If the second total does not exceed the first total, the processes of the N first candidate nodes, P second candidate nodes and / or M third candidate nodes are taken as the target processes; If the second total exceeds the first total, the target process is selected from the processes of the N first candidate nodes, P second candidate nodes and / or M third candidate nodes.

2. The method of claim 1, wherein, Detecting the access requests of processes on each of the multiple resource nodes includes: Filter the process instructions for each resource node, and determine the target resource node to be interacted with for each instruction; Based on the mesh structure of the on-chip network, and the destination resource node that each resource node and each instruction need to interact with, the total number of hops corresponding to the process of each resource node is determined; the total number of hops represents the access requirements corresponding to the process.

3. The method of claim 2, wherein, The instructions include at least one of the following: a read instruction and a write instruction; Based on the mesh structure of the on-chip network, and the destination resource node required for interaction between each resource node and each instruction, the total number of hops corresponding to the process of each resource node is determined, including: If the instruction includes a read instruction, the first hop count from the starting resource node to the destination resource node is determined according to the grid structure and routing algorithm, and the first hop count is multiplied by 2 to obtain the second hop count; If the instruction includes a write instruction, the third hop count of the process from the starting resource node to the destination resource node is determined according to the grid structure and routing algorithm; The total number of hops is determined based on the second hop count and the third hop count.

4. The method of claim 1, wherein, Detecting the access requests of processes on each of the multiple resource nodes includes: Filter the process instructions for each resource node, and determine the target resource node to be interacted with for each instruction; Based on the target resource node required for interaction for each instruction, determine the total number of times the process of each resource node accesses other resource nodes, whereby the total number of times represents the access requirements corresponding to the process.

5. The method of claim 4, wherein, The instructions include at least one of the following: a read instruction and a write instruction; The step of determining the total number of times the process of each resource node accesses other resource nodes in accordance with the target resource node required for interaction according to each instruction includes: If the instruction includes a read instruction, determine the first number of times the process travels from the starting resource node to the destination resource node, and multiply the first number by 2 to obtain the second number; If the instruction includes a write instruction, determine the third time the process moves from the starting resource node to the destination resource node; The total number of times is determined based on the second number and the third number.

6. The method of claim 1, wherein, The first priority of the process detecting each of the plurality of resource nodes includes: The first priority of each process currently running on each resource node is issued by the receiving software.

7. The method of claim 1, wherein, The process of selecting a target process from the N first candidate nodes, P second candidate nodes, and / or M third candidate nodes includes: Determine the filtering priority corresponding to the first candidate node, the second candidate node, and / or the third candidate node, respectively; The target process for the first total number is determined based on the screening priorities corresponding to the first candidate node, the second candidate node, and / or the third candidate node, respectively. The first candidate node has a higher screening priority than the second candidate node, and the second candidate node has a higher screening priority than the third candidate node.

8. The method of claim 1, wherein, Migrating the at least one target process to at least one central resource node in the central region includes: Determine the target center resource node corresponding to each target process in the at least one target process; each target center resource node corresponds to a unique target process. Each of the target processes will be migrated to the corresponding target central resource node.

9. The method of claim 8, wherein, Migrating each of the target processes to the corresponding target central resource node includes: Before migration, wait for the instructions in the current pipeline of the target central resource node to finish processing, then pause the instruction fetching operation of the target central resource node and back up the state of the target central resource node. The target process is migrated to the target central resource node, and the original process state of the target central resource node is migrated to the original resource node of the target process.

10. The method of claim 1, wherein, The method further includes: According to the first rule, a link priority is set for the link between any two resource nodes, wherein the first rule includes: the link priority of the central resource node in the central area is higher than the link priority of the peripheral resource node in the peripheral area; If multiple resource nodes access the same resource node simultaneously, the data traffic of the physical link is adjusted according to the link priority.

11. The method of claim 10, wherein, The method further includes: If multiple resource nodes access the same resource node simultaneously, and all of these resource nodes are central resource nodes, the link priority is adjusted according to the filtering priority of each central resource node.

12. A processing device of a multi-core processor, comprising: The multi-core processor includes multiple resource nodes in an on-chip network, the on-chip network adopting a mesh structure, and the device includes: The first processing module is configured to, in response to a setting instruction, set a central region and a peripheral region for multiple resource nodes in the on-chip network; the central region includes at least two central resource nodes, and any two central resource nodes are directly connected. The second processing module is used to detect the first priority and / or access requirements of the processes of each of the plurality of resource nodes; The third processing module is used to determine at least one target process that meets the first condition based on the first priority and / or access requirements, and to migrate the at least one target process to at least one central resource node in the central area. Based on the access requirements, at least one target process that meets the first condition is identified, including one of the following: Based on the total hop count of each process in the resource node, select the N processes with the highest total hop count as the target processes; N is greater than or equal to 1. Based on the total number of times corresponding to each resource node, select the P processes with the highest total number of times as the target processes; where P is greater than or equal to 1. or, Determining at least one target process that satisfies the first condition based on the first priority includes: Based on the first priority of each process, the M processes with the highest first priority are selected as the target processes; where M is greater than or equal to 1. or, Determining at least one target process that satisfies the first condition based on the first priority and / or access requirements includes: Determine the initial total number of migrateable central resource nodes; N first candidate nodes, P second candidate nodes, and / or M third candidate nodes are determined for the process to be migrated; the first candidate nodes are determined according to a first priority, the second candidate nodes are determined according to the total number of hops reflecting the access demand, and the third candidate nodes are determined according to the total number of times reflecting the access demand. The second total number is determined based on N, M and / or P; If the second total does not exceed the first total, the processes of the N first candidate nodes, P second candidate nodes and / or M third candidate nodes are taken as the target processes; If the second total exceeds the first total, the target process is selected from the processes of the N first candidate nodes, P second candidate nodes and / or M third candidate nodes.

13. An electronic device, comprising: include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 11.

14. A non-transitory computer-readable storage medium having stored thereon computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 11.

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