Display apparatus, control method, and display apparatus

Abstract

The invention discloses a display device, a control method and display equipment, and relates to the field of display, the display device comprises a time schedule controller and an I2C bus, the time schedule controller is provided with a write protection end, and a bus control end of the time schedule controller is connected with the I2C bus; the time schedule controller is used for controlling the communication state of the I2C bus to be a communication stop state under the condition that the write protection end is detected to be at a preset protection level; and the time schedule controller is used for controlling the communication state of the I2C bus to be a communication allowing state under the condition that the write protection end is detected to be at a preset write level. According to the method and the device, the technical problem of abnormal display caused by the fact that the Code is easily rewritten by mistake is solved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and particularly relate to a display device, a control method and a display apparatus. BACKGROUND

[0002] In the field of TV (TeleVision) panel and display panel, the whole machine end usually needs to debug the Vcom (common voltage) in the driving chip through the I2C (Inter-Integrated Circuit) bus to achieve the best picture quality. However, during the running or transportation of the whole machine, due to signal interference or jitter and other factors, unexpected communication may occur on the I2C bus, which is easy to miswrite the Code (configuration data) of the IC (Integrated Circuit) connected on the I2C bus, and further cause display abnormalities. Therefore, there is currently a technical problem of display abnormalities caused by the Code being easily miswritten.

[0003] The above content is only used to assist in understanding the technical solutions of the embodiments of the present application, and does not represent the acknowledgement of the above content as prior art. SUMMARY

[0004] The main purpose of the embodiments of the present application is to provide a display device, a control method and a display apparatus, which aims to solve the technical problem of display abnormalities caused by the Code being easily miswritten.

[0005] To achieve the above purpose, the embodiments of the present application provide a display device, which comprises a timing controller and an I2C bus, the timing controller is configured with a write protection end, and a bus control end of the timing controller is connected with the I2C bus; The timing controller is configured to control the communication state of the I2C bus to be a stop communication state when it is detected that the write protection end is at a preset protection level; The timing controller is configured to control the communication state of the I2C bus to be an allowed communication state when it is detected that the write protection end is at a preset write level.

[0006] In an embodiment, the display device further comprises a pull-down resistor, and the pull-down resistor is connected with the write protection end; The pull-down resistor is configured to set the write protection end to the preset protection level when the write protection end does not receive a signal with a level state of the preset write level.

[0007] In an embodiment, the display device further comprises a bus pull-up module, the timing controller further comprises a control unit and a bus pull-down module, a pull-down control end of the control unit is connected to the bus pull-down module, the write protection end is connected to the control unit, and the bus pull-up module and the bus pull-down module are connected to the I2C bus. When the level of the write protection end is a preset protection level, the control unit controls the bus pull-down module to be turned on, and when the bus pull-down module is turned on, the bus pull-down module is configured to pull down the level of the I2C bus, so that the communication state of the I2C bus is in a stop communication state. When the level of the write protection end is a preset write level, the control unit controls the bus pull-down module to be turned off, and when the bus pull-down module is turned off, the bus pull-up module is configured to pull up the level of the I2C bus, so that the communication state of the I2C bus is in an allowed communication state.

[0008] In an embodiment, the bus pull-up module comprises a first pull-up resistor and a second pull-up resistor, and a first end of the first pull-up resistor and a first end of the second pull-up resistor are connected to a preset bus voltage. A second end of the first pull-up resistor is connected to an SCL bus in the I2C bus, and a second end of the second pull-up resistor is connected to an SDA bus in the I2C bus.

[0009] In an embodiment, the bus pull-down module comprises a first switch tube and a second switch tube, and a bus control end of the timing controller comprises a first control end and a second control end. The first end of the first switch tube is taken as the first control end, the first control end is connected to the SCL bus in the I2C bus, the first end of the second switch tube is taken as the second control end, and the second control end is connected to the SDA bus in the I2C bus. The second end of the first switch tube and the second end of the second switch tube are grounded, the third end of the first switch tube is taken as a first pull-down end of the pull-down control end in the control unit, and the third end of the second switch tube is taken as a second pull-down end of the pull-down control end.

[0010] In an embodiment, the display device further comprises a slave connected to the I2C bus, and the slave supports configuring the bus pull-down module.

[0011] In an embodiment, the resistance value of the first pull-up resistor in the bus pull-up module is greater than the resistance value of the conduction resistance of the first switch tube in the bus pull-down module. The resistance value of the second pull-up resistor in the bus pull-up module is greater than the resistance value of the conduction resistance of the second switch tube in the bus pull-down module.

[0012] In addition, to achieve the above object, the embodiment of the present application further provides a control method of a display device, which is applied to the display device as described above, and the control method comprises the following steps: monitoring a write protection terminal in the display device; controlling a communication state of the I2C bus to be a stop communication state when it is monitored that the write protection terminal is at a preset protection level; controlling the communication state of the I2C bus to be an allow communication state when it is monitored that the write protection terminal is at a preset write level.

[0013] In an embodiment, the control method further comprises the following steps: receiving, through the write protection terminal, a write protection signal with a preset write level sent by a host computer of the display device; writing, through the I2C bus, a preset optimal reference voltage into a memory of a preset source driver when the write protection signal sets the write protection terminal to the preset write level; receiving, after the preset optimal reference voltage is written into the memory, a write protection signal with a preset protection level sent by the host computer to set the write protection terminal to the preset protection level.

[0014] In addition, to achieve the above object, the embodiment of the present application further provides a display device, which is the display device as described above.

[0015] The one or more technical solutions provided by the embodiment of the present application have at least the following technical effects: the display device of the present application comprises a timing controller and an I2C bus, and the write protection terminal is configured on the timing controller, and the bus control terminal of the timing controller is connected to the I2C bus. Since the write protection terminal is configured on the timing controller, the timing controller can control the communication state of the I2C bus to be a stop communication state when it is detected that the write protection terminal is at a preset protection level, thereby avoiding communication on the I2C bus to avoid rewriting the Code of the IC connected to the I2C bus. The timing controller can also control the communication state of the I2C bus to be an allow communication state when it is detected that the write protection terminal is at a preset write level, thereby enabling the Vcom to be debugged by controlling the communication state of the I2C bus through the write protection terminal. Therefore, the present application can adjust the communication state of the I2C bus through the write protection terminal, thereby reducing the risk of miswriting the Code of the IC on the I2C bus in the case of Vcom debugging, thereby solving the technical problem of display abnormality caused by miswriting of the Code. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with those described herein and, together with the specification, serve to explain the principles of those embodiments.

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram showing a normal display on the display device; Figure 2 A schematic diagram illustrating a display device exhibiting color distortion; Figure 3 This is a circuit diagram for a standard switch configuration. Figure 4 This is a schematic diagram of a module in one embodiment of the display device according to the present application; Figure 5 This is a schematic diagram of a module in the display device of this application that has a pull-down resistor configured at the write protection terminal; Figure 6 This is a schematic diagram of a display device including a bus pull-down module and a bus pull-up module, as shown in the embodiments of this application. Figure 7 This is a circuit diagram of a display device including a bus pull-up module, as shown in an embodiment of this application. Figure 8 This is a circuit diagram of a display device including a bus pull-up module and a bus pull-down module, as shown in the embodiments of this application. Figure 9 This is a circuit diagram of an example display device according to an embodiment of this application; Figure 10 This is a circuit diagram of another example of a display device in an embodiment of this application; Figure 11 This is a waveform diagram of the I2C bus and write-protect terminal in the display device of the present application embodiment; Figure 12 This is a waveform diagram of the I2C bus in the display device of this application when the I2C bus is in a stopped communication state. Figure 13 This is a flowchart illustrating one embodiment of the control method for the display device in this application.

[0019] Explanation of icon numbers: 100, Timing Controller; 200, I2C Bus; WP, Write Protect Terminal; R1, Pull-down Resistor; 110, Control Unit; 120, Bus Pull-down Module; 300, Bus Pull-up Module; VDD, Preset Bus Voltage; Rp1~Rp2, First Pull-up Resistor~Second Pull-up Resistor; Q1~Q2, First Switching Transistor~Second Switching Transistor; SCL_k, First Pull-down Terminal; SDA_k, Second Pull-down Terminal; Ts1~Ts3, First Debugging Interface~Third Debugging Interface.

[0020] The objectives, features, and advantages of the embodiments described in this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of the embodiments of this application and are not intended to limit the embodiments of this application.

[0022] To better understand the technical solutions of the embodiments of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0023] In television (TV) and monitor (MNT) panels, each unit needs to be adjusted according to the requirements of OC (Optical Compensation) and Vcom (Common Voltage). OC product specifications typically provide Vcom adjustment methods based on the I2C (Inter-Integrated Circuit) bus for the unit to execute, in order to achieve optimal image quality.

[0024] However, during the operation or transportation of the entire device, factors such as signal interference or jitter may cause unexpected communication on the I2C bus, which can easily lead to accidental rewriting of the code of the IC connected to the I2C bus, resulting in display abnormalities. For example, panel manufacturers disclose the device address and register address corresponding to Vcom to the end user in the product specifications. The end user modifies the Vcom value to the optimal value through the I2C interface according to the debugging steps. After changing to the optimal Vcom value, since some ICs are not equipped with write protection, the internal code of the IC can easily be accidentally rewritten, resulting in abnormal image quality of the entire device. For example, if the P-gamma code is rewritten, color shift will occur. For example, refer to... Figure 1 and Figure 2 , Figure 1 This is a schematic diagram showing the correct display. Figure 2 This is a display illustration showing color distortion; comparison Figure 1 and Figure 2 It can be seen that, Figure 2Color cast, particularly a reddish tint, may occur. If the L / S (Level Shift / Scan Driver) code is rewritten, it may cause abnormal GOA (Gate Driver on Array) signal output or false triggering of OCP (Over-Current Protection). If the PMIC (Power Management Integrated Circuit) code is rewritten, it may cause the OC module in the entire device to fail to power on or display properly.

[0025] Due to frequent instances of accidental code rewriting, some high-end customers are requesting the introduction of a switch (integrated circuit) to achieve I2C signal isolation. For example, refer to... Figure 3 , Figure 3 The circuit diagram showing the setup of the Switch is displayed. Figure 3 In this configuration, the switch connects to the SCL bus and the SDA bus. The switch also connects to the write-protected port WP, as well as the debug interface SCL and debug interface SDA. The switch can transfer data received at the debug interface SCL to the SCL bus, and vice versa. Figure 3 Write protection can be implemented through a switch and a WP connected to the switch. While this can protect the IC from being rewritten to some extent, it also brings problems such as increased cost, more difficult PCB (Printed Circuit Board) layout, and increased risk of signal crosstalk. Furthermore, with the increasing integration of chips, the write pin protection function of most chips is often removed, making them more susceptible to accidental rewriting.

[0026] To address this issue, this embodiment provides a display device. This display device includes a timing controller and an I2C bus. A write-protection terminal is configured on the timing controller, and the bus control terminal of the timing controller is connected to the I2C bus. Because a write-protection terminal is configured on the timing controller, the timing controller can control the communication state of the I2C bus to a stopped communication state when it detects that the write-protection terminal is at a preset protection level. This avoids communication on the I2C bus and prevents rewriting of the code of the IC connected to the I2C bus. The timing controller can also control the communication state of the I2C bus to an enabled communication state when it detects that the write-protection terminal is at a preset write level. Therefore, when Vcom needs to be debugged, the communication state of the I2C bus can be controlled through the write-protection terminal to achieve Vcom debugging. Thus, this embodiment can adjust the communication state of the I2C bus through the write-protection terminal, thereby reducing the risk of accidental rewriting of the IC's code on the I2C bus during Vcom debugging, and solving the technical problem of display abnormalities caused by accidental code rewriting. Furthermore, without the need for additional hardware, write protection can be configured directly on the timing controller to control the I2C bus, thereby reducing the risk of the IC's code being rewritten.

[0027] Based on this, embodiments of this application provide a display device, referring to... Figure 4 , Figure 4 This is a schematic diagram of a display device module. The display device includes a timing controller 100 and an I2C bus 200. The timing controller 100 is equipped with a write-protection terminal WP, and the bus control terminal of the timing controller 100 is connected to the I2C bus 200. The timing controller 100 is used to control the communication state of the I2C bus 200 to a stopped communication state when it detects that the write protection terminal WP is at a preset protection level. The timing controller 100 is used to control the communication state of the I2C bus 200 to an enabled communication state when it detects that the write protection terminal WP is at a preset write level.

[0028] It should be noted that the write protection terminal WP can be a GPIO port with input function in the timing controller 100. The write protection terminal WP can be used to receive the write protection signal. The level state of the write protection signal can be divided into preset protection level and preset write level. The preset protection level and preset write level are different. The write protection signal can be sent by the host computer of the display device. For example, when VOCM debugging is required, the host computer needs to be used to find the optimal Vcom.

[0029] The timing controller 100 can monitor the write protection terminal WP. When it detects that the write protection terminal WP is at a preset protection level, it indicates that Vcom debugging is not required and communication on the I2C bus 200 is not needed. Therefore, the timing controller 100 can adjust the communication state of the I2C bus 200 to a stopped communication state. The stopped communication state indicates that communication is not supported on the I2C bus 200, and communication on the I2C bus 200 is invalid. Figure 4 The connection point of the timing controller 100 to the I2C bus 200 is the bus control terminal of the timing controller 100.

[0030] When the write protection pin WP is detected to be at the preset write level, it indicates that communication via I2C bus 200 is required. Therefore, the communication state of I2C bus 200 can be controlled to enable communication, indicating that communication on I2C bus 200 is supported. In the enabled communication state, communication can be performed on I2C bus 200 to find the optimal Vcom.

[0031] Therefore, this embodiment reduces the risk of the IC's code being easily rewritten at low cost by configuring a write protection terminal WP on the timing controller 100 and controlling the communication status of the I2C bus 200 through the timing controller 100, thereby making it easier to avoid display abnormalities on the display panel.

[0032] In one feasible embodiment, refer to Figure 5 The display device further includes a pull-down resistor R1, which is connected to the write protection terminal WP; If the write protection terminal WP does not receive a signal with a preset write level, the pull-down resistor R1 is used to set the write protection terminal WP to the preset protection level.

[0033] It should be noted that the value of the pull-down resistor R1 can be set based on actual conditions. For example, the value of the pull-down resistor R1 can be 4.7kΩ, etc. This embodiment does not impose a specific limitation on this. The pull-down resistor R1 can set the write protection terminal WP to the preset protection level when the write protection terminal WP does not receive a write protection signal with a level of the preset write level. This helps to ensure the stability of the write protection terminal WP in maintaining the preset protection level, thereby avoiding communication on the I2C bus 200. It also helps to provide a basic state for the write protection terminal WP, which is the preset protection level. For example, when the display device is powered on, the write protection terminal WP will be pulled down to the preset protection level by the pull-down resistor R1.

[0034] In this embodiment, the preset protection level can be low, and the preset write level can be high. In other embodiments, the preset protection level can also be high, and the preset write level can also be low. When the preset protection level is high, the pull-down resistor R1 needs to be adjusted to a pull-up resistor to ensure that the write protection terminal WP can stably maintain the preset protection level when it does not receive a write protection signal at the preset write level. Therefore, this embodiment can improve the reliability of the circuit.

[0035] In one feasible embodiment, please refer to Figure 6 The display device further includes a bus pull-up module 300, and the timing controller 100 further includes a control unit 110 and a bus pull-down module 120. The pull-down control terminal of the control unit 110 is connected to the bus pull-down module 120, and the write protection terminal WP is connected to the control unit 110. Both the bus pull-up module 300 and the bus pull-down module 120 are connected to the I2C bus 200. When the write protection terminal WP is at a preset protection level, the control unit 110 controls the bus pull-down module 120 to be turned on. When the bus pull-down module 120 is turned on, the bus pull-down module 120 is used to pull down the level of the I2C bus 200 so that the communication state of the I2C bus 200 is in a stopped communication state. When the write protection terminal WP is at a preset write level, the control unit 110 controls the bus pull-down module 120 to be turned off. When the bus pull-down module 120 is turned off, the bus pull-up module 300 is used to pull up the level of the I2C bus 200 so that the communication state of the I2C bus 200 is in the communication-enabled state.

[0036] It should be noted that both the bus pull-up module 300 and the bus pull-down module 120 are connected to the I2C bus 200. The bus pull-up module 300 can pull the I2C bus 200 high when the bus pull-down module 120 is off, thus enabling communication on the I2C bus 200. When the bus pull-down module 120 is on, it pulls the I2C bus 200 low, thus stopping communication on the I2C bus 200. For example, in this embodiment, when the I2C bus 200 is low, it indicates that communication on the I2C bus 200 is stopped; when the I2C bus 200 is high, it indicates that communication on the I2C bus 200 is enabled.

[0037] The control unit 110 in the timing controller 100 can control whether the bus pull-down module 120 is turned off or on. The control unit 110 can control the bus pull-down module 120 based on the level of the write protection terminal WP. For example, when the write protection terminal WP is at the preset protection level, the bus pull-down module 120 is on, and thus the bus pull-down module 120 can pull the I2C bus 200 low to protect the IC code on the I2C bus 200 from being rewritten. When the write protection terminal WP is at the preset write level, the bus pull-down module 120 is off, and thus the bus pull-up module 300 can pull the level of the I2C bus 200 high, thereby facilitating the debugging of the optimal Vcom.

[0038] This embodiment uses the bus pull-up module 300 and the bus pull-down module 120 to adjust the level of the I2C bus 200, thereby facilitating the adjustment of the communication state of the I2C bus 200 and reducing the risk of code rewriting.

[0039] In one feasible embodiment, please refer to Figure 7 The bus pull-up module 300 includes a first pull-up resistor Rp1 and a second pull-up resistor Rp2. The first end of the first pull-up resistor Rp1 and the first end of the second pull-up resistor Rp2 are both connected to a preset bus voltage VDD. The second end of the first pull-up resistor Rp1 is connected to the SCL bus in the I2C bus 200, and the second end of the second pull-up resistor Rp2 is connected to the SDA bus in the I2C bus 200.

[0040] It should be noted that I2C is a two-wire serial bus, consisting of an SDA (Serial Data Bus) and an SCL (Serial Clock Bus), which can send and receive data. The SDA bus is used for data transmission, and the SCL bus is used for synchronizing the timing of data transmission.

[0041] The resistance values ​​of the first pull-up resistor Rp1 and the second pull-up resistor Rp2 can be the same. For example, both the first pull-up resistor Rp1 and the second pull-up resistor Rp2 can be 4.7kΩ. Of course, other resistance values ​​are also possible, and the specific values ​​can be set based on actual conditions. This embodiment does not impose specific limitations on this. The preset bus voltage VDD can also be set based on actual conditions. This embodiment does not impose specific limitations on this. When the bus pull-up module 300 pulls up the I2C bus 200, the bus pull-up module 300 will pull the levels of the SDA bus and the SCL bus up to the preset bus voltage VDD, thereby raising the levels of the SDA bus and the SCL bus.

[0042] This embodiment uses a bus pull-up module 300 to facilitate the raising of the SDA and SCL bus levels when communication via the I2C bus 200 is required.

[0043] In one feasible embodiment, please refer to Figure 8 The bus pull-down module 120 includes a first switch Q1 and a second switch Q2, and the bus control terminal of the timing controller 100 includes a first control terminal and a second control terminal. The first terminal of the first switch Q1 is used as the first control terminal, and the first control terminal is connected to the SCL bus in the I2C bus 200. The first terminal of the second switch Q2 is used as the second control terminal, and the second control terminal is connected to the SDA bus in the I2C bus 200. The second terminals of the first switch Q1 and the second switch Q2 are both grounded. The third terminal of the first switch Q1 is used as the first pull-down terminal SCL_k of the pull-down control terminal in the control unit 110, and the third terminal of the second switch Q2 is used as the second pull-down terminal SDA_k of the pull-down control terminal.

[0044] It should be noted that both the first switching transistor Q1 and the second switching transistor Q2 are MOSFETs, for example, both could be NMOS transistors. The bus control terminals of the timing controller 100 include a first control terminal and a second control terminal. The first control terminal is connected to the SCL bus, and the second control terminal is connected to the SDA bus. The first terminal of the first switching transistor Q1 can be used as the first control terminal, and the second terminal of the second switching transistor Q2 can be used as the second control terminal. The first terminal of both the first switching transistor Q1 and the first terminal of the second switching transistor Q2 can be the drain.

[0045] The second terminal of the first switch Q1 and the second terminal of the second switch Q2 can both be the source, and the third terminal of the first switch Q1 and the third terminal of the second switch Q2 can both be the gate; the pull-down control terminal in the control unit 110 includes a first pull-down terminal SCL_k and a second pull-down terminal SDA_k, and the third terminal of the first switch Q1 can be used as the first pull-down terminal SCL_k, and the third terminal of the second switch Q2 can be used as the second pull-down terminal SDA_k.

[0046] When the write protection terminal WP is at the preset protection level, the control unit 110 outputs a high level to the third terminal of the first switch Q1 through the first pull-down terminal SCL_k and a high level to the third terminal of the second switch Q2 through the second pull-down terminal SDA_k, thereby turning on the first switch Q1 and the second switch Q2. This allows the first switch Q1 to pull the SCL bus level low and the second switch Q2 to pull the SDA bus level low. When the write protection terminal WP is at the preset write level, the control unit 110 outputs a low level to the third terminal of the first switch Q1 through the first pull-down terminal SCL_k and a low level to the third terminal of the second switch Q2 through the second pull-down terminal SDA_k, thereby turning off the first switch Q1 and the second switch Q2. This allows the bus pull-up module 300 to pull the SCL bus and the SDA bus level high.

[0047] In this embodiment, the conduction and cutoff of the first switch Q1 and the second switch Q2 can be controlled to facilitate the control of the I2C bus 200 level. This allows the I2C bus 200 level to be pulled low in time when communication is not required, so as to prevent the code from being rewritten.

[0048] To better understand this embodiment, please refer to Figure 9 , Figure 9 The diagram illustrates a circuit of the display device, including a timing controller 100, an I2C bus 200, and a bus pull-up module 300. Figure 9 The document also showcases a PMIC, P-gamma, and L / S module connected to I2C. The PMIC (Power Management Integrated Circuit) configures the voltage of each register; the L / S (Level Shift) configures the timing output of the GOA (Gross Orientation of Array) for each register; and the P-gamma module adjusts the gamma voltage curve. Figure 9 The document also showcases Ts1 to Ts3, all of which are debugging interfaces. Ts1 to Ts3 can be connected to a host computer, which can send data to them. For example, the host computer can send data to Ts1 and Ts2 to debug Vcom on the I2C bus 200. The host computer can also send a level signal to Ts3 to adjust the level of the write protection terminal WP.

[0049] In one feasible embodiment, please refer to Figure 10 The display device also includes a slave device connected to the I2C bus 200, which supports the configuration of the bus pull-down module 120.

[0050] It should be noted that the slave device can be a device connected to the I2C bus 200. A bus pull-down module 120 can also be configured in the slave device, thereby facilitating the control of the I2C bus 200 level through the bus pull-down module 120 in the slave device. When the bus pull-down module 120 in the timing controller 100 is turned on, or when the bus pull-down module 120 in the slave device is turned on, the I2C bus 200 level can be pulled low.

[0051] The slave device's bus pull-down module 120 also includes a first switch Q1 and a second switch Q2. The first terminal of the first switch Q1 is connected to the SCL bus, and the first terminal of the second switch Q2 is connected to the SDA bus. The second terminals of both the first and second switches Q1 are grounded. The third terminal of the first switch Q1 can also be connected to the first pull-down terminal SCL_k in the timing controller 100, and the third terminal of the second switch Q2 can also be connected to the second pull-down terminal SDA_k in the timing controller 100. For example, refer to... Figure 10 , Figure 10 The diagram shows two slave devices, namely slave 1 and slave 2. The master pull-down modules 120 inside slave 1 and slave 2 are connected to the I2C bus 200.

[0052] This embodiment can provide multiple ways to pull the I2C bus 200 level low, thereby improving the flexibility of pulling the I2C bus 200 level low and improving the flexibility of avoiding code rewriting.

[0053] In one feasible embodiment, the resistance value of the first pull-up resistor Rp1 in the bus pull-up module 300 is greater than the resistance value of the on-resistance of the first switch Q1 in the bus pull-down module 120. The resistance value of the second pull-up resistor Rp2 in the bus pull-up module 300 is greater than the resistance value of the on-resistance of the second switch Q2 in the bus pull-down module 120.

[0054] It should be noted that because the on-resistance of the MOSFET is much smaller than that of the pull-up resistors (the resistance of the first pull-up resistor Rp1 is greater than the on-resistance of the first switching transistor Q1, and the resistance of the second pull-up resistor Rp2 is greater than the on-resistance of the second switching transistor Q2), the pull-up capability of the bus pull-up module 300 is always less than the pull-down capability of the bus pull-down module 120. Therefore, when the bus pull-down module 120 is turned on, it can force the I2C bus 200 to a low level, thus ensuring circuit reliability and effectively preventing the IC code on the I2C bus 200 from being rewritten, thereby avoiding display abnormalities.

[0055] In this embodiment, the difference between the first pull-up resistor Rp1 and the on-resistance of the first switch Q1 can be greater than a preset threshold, so that the first pull-up resistor Rp1 is much larger than the on-resistance of the first switch Q1; similarly, the difference between the second pull-up resistor Rp2 and the on-resistance of the second switch Q2 can be greater than a preset threshold, so that the second pull-up resistor Rp2 is much larger than the on-resistance of the second switch Q2. The preset threshold can be set based on actual conditions, and this embodiment does not impose specific limitations on it.

[0056] To better understand this embodiment, please refer to Figure 11 , Figure 11 The diagram illustrates the waveforms of the write protection terminal WP, the SCL bus, and the SDA bus in this embodiment. The explanation uses an example where the preset protection level is low and the preset write level is high. Figure 10 In this configuration, when WP is low, both SCL and SDA will be low; when WP is high, SCL and SDA can communicate normally.

[0057] Furthermore, you can refer to Figure 12 , Figure 12 The diagram shows the waveform of the I2C bus 200 when the WP is at a low level, but the device connected to the I2C bus 200 is forced to communicate.

[0058] The device can be a device with an IC, etc. Figure 12 In the waveform diagram, c1 represents the waveform during normal communication on the SCL bus, c2 represents the waveform during normal communication on the SDA bus, b1 represents the waveform during forced communication when the SCL bus is in a stopped communication state, b2 represents the waveform during forced communication when the SDA bus is in a stopped communication state, yl refers to the minimum voltage threshold (low), and yh refers to the maximum voltage threshold (High). Figure 12 As can be seen, when WP is at a low level, if forced communication is performed on I2C, the highest voltage levels of b1 and b2 will not exceed High and low, respectively, which does not meet the conditions for I2C communication. Consequently, the IC connected to I2C bus 200 cannot recognize the data on I2C bus 200, resulting in communication failure and thus preventing accidental code rewriting.

[0059] Furthermore, based on the above embodiments of this application, in another embodiment of this application, the same or similar content as the above embodiments can be referred to the above description, and will not be repeated hereafter. Based on this, refer to... Figure 13 This embodiment provides a control method for a display device, the control method including steps S10 to S30: Step S10: Monitor the write protection terminal in the display device; Step S20: When the write protection terminal is detected to be at a preset protection level, the communication state of the I2C bus is controlled to be stopped. It should be noted that in this embodiment, the write protection terminal can be monitored in real time. For example, the timing controller in the display device can listen to the write protection terminal in real time, thereby facilitating timely adjustment of the I2C bus communication state based on changes in the write protection terminal's level. For instance, when the write protection terminal is at a preset protection level, the I2C bus communication state can be continuously controlled to a stopped communication state.

[0060] Step S30: When the write protection terminal is detected to be at a preset write level, the communication state of the I2C bus is controlled to be enabled.

[0061] It should be noted that when the write protection terminal is at the preset write level, it can continuously control the communication state of the I2C bus to the enabled communication state. When the level of the write protection terminal changes from the preset write level to the preset protection level, it can promptly pull down the level of the I2C bus, thereby promptly adjusting the communication state of the I2C bus to the stopped communication state. When the level of the write protection terminal changes from the preset protection level to the preset write level, it can promptly pull up the level of the I2C bus, thereby promptly adjusting the communication state of the I2C bus to the enabled communication state.

[0062] The write signal terminal can receive write protection signals sent from the host computer. The host computer can send a write protection signal with a preset protection level, or a protection signal with a preset write level. A write protection signal with a preset protection level will set the write signal terminal to the preset protection level, and a protection signal with a preset write level will set the write signal terminal to the preset write level. When the host computer does not send a write protection signal to the write signal terminal, the write signal terminal is at the preset protection level because a pull-down resistor is connected to the write signal terminal.

[0063] For example, the write protection terminal in the monitoring display device, when detecting that the write protection terminal is at a preset protection level, controls the communication state of the I2C bus to a stopped communication state; when detecting that the write protection terminal is at a preset write level, controls the communication state of the I2C bus to a enabled communication state. Specifically, the timing controller can respond to a write protection signal with a preset protection level sent by the host computer to the write protection terminal, controlling the communication state of the I2C bus to a stopped communication state; the timing controller can respond to a write protection signal with a preset write level sent by the host computer to the write protection terminal, controlling the communication state of the I2C bus to a enabled communication state.

[0064] In this embodiment, when the write protection terminal is detected to be at a preset protection level, the communication state of the I2C bus is controlled to a stopped communication state. This avoids communication on the I2C bus, preventing the rewriting of the IC's code connected to the I2C bus. Alternatively, when the write protection terminal is detected to be at a preset write level, the communication state of the I2C bus is controlled to a enabled communication state. This allows for VCOM debugging by controlling the I2C bus communication state through the write protection terminal. Therefore, this embodiment can adjust the I2C bus communication state through the write protection terminal, thereby reducing the risk of accidental rewriting of the IC's code on the I2C bus during VCOM debugging. This solves the technical problem of display anomalies caused by easily rewritten code. Furthermore, no additional hardware is required; the write protection terminal can be configured directly on the timing controller to control the I2C bus and reduce the risk of IC code rewriting.

[0065] In a feasible embodiment, the control method further includes steps A10 to A30: Step A10: Receive a write protection signal with a preset write level sent by the host computer of the display device through the write protection terminal; Step A20: When the write protection signal sets the write protection terminal to a preset write level, the preset optimal reference voltage is written to the memory of the preset source driver via the I2C bus. It should be noted that when the optimal Vcom needs to be found, the host computer can send a write protection signal with a preset write level to the write protection terminal of the display device. When the write protection terminal is at the preset write level, the I2C bus is at a high level and I2C is in the communication enabled state. Therefore, the preset optimal reference voltage can be written to the memory of the preset source driver through the I2C bus, which makes it easier to adjust the Vcom of the display device to the preset optimal reference voltage. The preset optimal reference voltage can be the optimal Vcom obtained in advance. The memory of the preset source driver can be non-volatile memory. The preset source driver can obtain the preset optimal reference voltage from the memory to drive the display device to display, thereby enabling the display device to achieve good image quality.

[0066] To better understand this embodiment, the process of finding the best Vcom is briefly described, including 5 steps, which are x10~x50 respectively.

[0067] x10: Initializes the configuration for devices that need to determine the optimal Vcom. For example, the corresponding initialization instruction could be "7 Bits Device Address E8h; RAM Register Address 00h; RAM Register Data 12h". This instruction indicates that the device address is E8h, and the data 12h is written to the device's 00h register. x20 writes the Vcom data 00h to the DAC. The corresponding instruction could be "Set Vcom data 00h to DAC". Specifically, it could write the data 00h to the device's 01h register, which is equivalent to initially setting the Vcom voltage to zero for subsequent Vcom determination.

[0068] x30 scans from 0x00 to 0xFE to find the best Vcom and writes it to the DAC. For example, the instruction could be "Search bestVcom data from 0x00 to 0xFE to DAC". Specifically, this involves sequentially writing all values ​​from 00h to FEh (decimal 0 to 254) to the device's 01h register. After each value is written, the operator observes the screen quality to determine which value provides the best image quality. x40 writes the best Vcom from the DAC to the EEPROM. For example, the instruction could be "Write final Vcom from DAC to EEPROM". x50 reloads the Vcom data from the EEPROM to the DAC. For example, the instruction could be "Re-load Vcomdata to DAC from EEPROM". This completes the search and configuration of the best Vcom.

[0069] Step A30: After the preset optimal reference voltage is written to the memory, a write protection signal with a preset protection level sent by the host computer is received, so as to set the write protection terminal to the preset protection level.

[0070] It should be noted that after the preset optimal reference voltage is written to the memory, communication on the I2C bus is no longer required. Therefore, the I2C bus needs to be set to a low level to stop communication and prevent accidental code modification. Thus, a write protection signal with a preset protection level sent by the host computer can be used to set the write protection terminal to the preset protection level.

[0071] For example, the timing controller can respond to a write protection signal with a preset write level sent by the host computer to the write protection terminal, thereby setting the write protection terminal to the preset write level. The timing controller can then set the I2C to a high level, and write a preset optimal reference voltage to the memory of the preset source driver via I2C. After writing the preset optimal reference voltage to the memory, the timing controller responds to a write protection signal with a preset protection level sent by the host computer, sets the write protection terminal to the preset protection level, and adjusts the communication state of the I2C bus to a stopped communication state.

[0072] This embodiment can adjust the communication state of the I2C bus to the communication-enabled state when a preset optimal reference voltage needs to be written, and then adjust the communication state of the I2C bus to the communication-stopped state after the preset optimal reference voltage is written. This can reduce the risk of code being accidentally rewritten while writing the optimal Vcom, thereby facilitating the assurance of the display device's display reliability.

[0073] This application also provides a display device, which employs the display apparatus described in the above embodiments, and aims to solve the technical problem of display anomalies caused by the easy miswriting of code. Compared with the prior art, the beneficial effects of the display device provided in this application are the same as those of the display apparatus provided in the above embodiments, and will not be repeated here.

[0074] The above are merely preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structural or procedural transformations made using the description and drawings of the present application, or direct or indirect applications in other related technical fields, are similarly included within the patent processing scope of the present application.

Claims

1. A display device, characterized in that, The display device includes a timing controller and an I2C bus. The timing controller is configured with a write-protection terminal, and the bus control terminal of the timing controller is connected to the I2C bus. The timing controller is used to control the communication state of the I2C bus to a stopped communication state when the write protection terminal is detected to be at a preset protection level. The timing controller is used to control the communication state of the I2C bus to the enabled communication state when the write protection terminal is detected to be at a preset write level.

2. The display device as claimed in claim 1, characterized in that, The display device further includes a pull-down resistor, which is connected to the write protection terminal; If the write protection terminal does not receive a signal with a preset write level, the pull-down resistor is used to set the write protection terminal to the preset protection level.

3. The display device as claimed in claim 1, characterized in that, The display device further includes a bus pull-up module, and the timing controller further includes a control unit and a bus pull-down module. The pull-down control terminal of the control unit is connected to the bus pull-down module, and the write protection terminal is connected to the control unit. Both the bus pull-up module and the bus pull-down module are connected to the I2C bus. When the write protection terminal is at a preset protection level, the control unit controls the bus pull-down module to turn on. When the bus pull-down module is turned on, the bus pull-down module is used to pull down the level of the I2C bus so that the communication state of the I2C bus is in a stopped communication state. When the write protection terminal is at a preset write level, the control unit controls the bus pull-down module to be turned off. When the bus pull-down module is turned off, the bus pull-up module is used to pull up the level of the I2C bus so that the communication state of the I2C bus is in the communication-enabled state.

4. The display device as claimed in claim 3, characterized in that, The bus pull-up module includes a first pull-up resistor and a second pull-up resistor, and the first end of the first pull-up resistor and the first end of the second pull-up resistor are both connected to a preset bus voltage. The second end of the first pull-up resistor is connected to the SCL bus in the I2C bus, and the second end of the second pull-up resistor is connected to the SDA bus in the I2C bus.

5. The display device as claimed in claim 3, characterized in that, The bus pull-down module includes a first switching transistor and a second switching transistor, and the bus control terminal of the timing controller includes a first control terminal and a second control terminal. The first terminal of the first switching transistor is used as the first control terminal, and the first control terminal is connected to the SCL bus in the I2C bus. The first terminal of the second switching transistor is used as the second control terminal, and the second control terminal is connected to the SDA bus in the I2C bus. The second terminals of the first and second switching transistors are both grounded. The third terminal of the first switching transistor is used as the first pull-down terminal of the pull-down control terminal in the control unit, and the third terminal of the second switching transistor is used as the second pull-down terminal of the pull-down control terminal.

6. The display device as claimed in claim 3, characterized in that, The display device also includes a slave device connected to the I2C bus, and the slave device supports the configuration of the bus pull-down module.

7. The display device according to any one of claims 3-6, characterized in that, The resistance value of the first pull-up resistor in the bus pull-up module is greater than the resistance value of the on-state resistance of the first switching transistor in the bus pull-down module. The resistance value of the second pull-up resistor in the bus pull-up module is greater than the resistance value of the on-state resistance of the second switching transistor in the bus pull-down module.

8. A control method for a display device, characterized in that, The control method, applied to the display device as described in any one of claims 1-7, comprises: Monitor the write-protect pin in the display device; If the write protection terminal is detected to be at a preset protection level, the communication state of the I2C bus is controlled to be stopped. When the write protection terminal is detected to be at a preset write level, the communication state of the I2C bus is controlled to be enabled.

9. The control method for the display device as described in claim 8, characterized in that, The control method further includes: The write protection terminal receives a write protection signal with a preset write level sent by the host computer of the display device. When the write protection signal sets the write protection terminal to a preset write level, the preset optimal reference voltage is written to the memory of the preset source driver via the I2C bus. After the preset optimal reference voltage is written to the memory, a write protection signal with a preset protection level sent by the host computer is received to set the write protection terminal to the preset protection level.

10. A display device, characterized in that, The display device includes the display apparatus as described in any one of claims 1-7.

Images