Operating method of split-gate memory array

Abstract

The invention provides an operation method of a split-gate memory array. The method is applied to a mirror image type memory cell array consisting of a selection tube and memory tubes on two sides. The core is that the erasing operation is realized through grid current carrier tunneling, and positive voltage is applied to a storage tube grid, so that a grid hole is injected into a charge storage layer; write-in operation is achieved through channel hot carrier injection (HCI), a selection tube is weakly turned on to generate nA-level electric leakage, and hot electron injection is formed at the drain end. In the whole operation process, the well region is kept grounded, and a deep N-well (DNW) process is not needed. The invention also provides a refined write suppression bias scheme for three architectures, i.e., an independent source line (DSL), a shared source line (SSL), and a common source line (CSL), to avoid perturbations of non-selected cells. The method has the advantages of high-speed writing, ultra-low power consumption, simplified process and the like, and the operation reliability of the storage array is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly to an operating method of split-gate memory array. BACKGROUND

[0002] Non-volatile memory technology is a core component of modern electronic devices. Among them, the SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) type memory has attracted widespread attention due to its good compatibility with standard CMOS process, simple structure, and relatively low operating voltage. The traditional SONOS memory usually uses the Fowler-Nordheim (F-N) tunneling effect to perform erase and write operations on electrons and holes in the channel. The advantage of this method is that the channel current during the erase and write process is almost zero, and the power consumption is extremely low. However, its main disadvantage is that the erase and write speed is slow, usually in the order of milliseconds (ms), which is difficult to meet the demand of high-speed data storage. At the same time, the traditional erase operation often needs to apply a positive voltage in the P-type well. In order to isolate this positive voltage from the P-type substrate, an additional deep N-well (DNW) needs to be made below the P-type well. This not only increases the complexity of the process, but also requires the introduction of additional photolithography masks and ion implantation steps, thereby increasing the manufacturing cost.

[0003] In order to improve the storage density, the industry has developed a mirror split-gate SONOS structure, that is, two storage tubes are shared on both sides of a selection tube. Although this structure effectively increases the number of storage bits per unit area, it also introduces new challenges, such as how to effectively suppress the crosstalk problem when reading the target cell.

[0004] In order to combine the advantages of different operation mechanisms, a new type of SONOS memory structure and its operation method are proposed. As shown in Figure 1 , it is a cross-sectional schematic diagram of this new type of memory cell. The memory cell is built on the P-type well 1 and adopts a mirror split-gate structure. The center is a selection tube, whose gate is a selection tube polysilicon 4, and the gate dielectric is a selection tube gate oxide 2. On both sides of the selection tube are two storage tubes, whose gate is a storage tube polysilicon 3. The source-drain implantation region 5 is formed on both sides of the gate structure in the P-type well 1. Among them, the storage tube adopts a special "gate carrier tunneling type ONO" dielectric layer. The ONO dielectric layer includes a relatively thick blocking oxide layer 8 close to the channel, a charge storage layer 7 in the middle, and a relatively thin tunneling oxide layer 6 close to the storage tube polysilicon 3. In addition, the structure also includes a lightly doped drain (LDD) region 9 and a side wall structure (ONO spacer) 10.

[0005] Based on this structure, a hybrid mode of operation can be realized. As shown in Figure 2The diagram illustrates the principle of the write operation. During data writing, Channel Hot Carrier Injection (HCI) is employed. Specifically, a weak turn-on voltage is applied to the word line (WL) of the select transistor, placing it in a subthreshold conducting state. Simultaneously, a positive voltage is applied to the word line (e.g., WLS) and the corresponding drain (e.g., BL) of the memory transistor to be written, while the source (SL) is grounded. This generates a weak leakage current in the channel, forming high-energy "hot" electrons (e-) in the strong electric field region near the drain. These hot electrons have sufficient energy to penetrate the thicker resistive oxide layer 8 and are injected into the charge storage layer 7, thus achieving fast data writing (e.g., on the order of 5-10 microseconds).

[0006] like Figure 3 The diagram illustrates the principle of the erase operation. Data erasure utilizes gate carrier tunneling. Specifically, a positive erase voltage is applied to the word lines (e.g., WLS and WLS*) of the target memory transistor, while all other terminals (WL, PW, SL, BL) remain grounded. This creates a strong electric field between the polysilicon gate 3 and the charge storage layer 7 of the memory transistor. Because the tunneling oxide layer 6 is very thin, holes (h+) in the gate can tunnel through this thin oxide layer via the Fowler-Nordheim (FN) tunneling effect and be injected into the charge storage layer 7, where they recombine with previously stored electrons, thus completing the erase operation.

[0007] This hybrid operation mode offers significant advantages: it achieves microsecond-level fast writing using HCI, while controlling the write current to the nA level through a weak turn-on selector, thus solving the problem of high power consumption in traditional HCI; it utilizes gate hole tunneling for erasure, and since a positive voltage is applied to the gate of the memory transistor during both erasure and writing, while the P-type well is always grounded, it fundamentally eliminates the need for a deep N-well (DNW), simplifying the process and reducing costs. Furthermore, the thicker barrier oxide layer naturally enhances the device's durability and read interference immunity.

[0008] However, despite the great potential of this new structure and operation mode, how to effectively apply it to large-scale, high-density storage arrays (such as independent source line DSL, shared source line SSL, and common source line CSL architectures) and design a complete, reliable array-level operation bias scheme that can effectively suppress various disturbances are key issues that urgently need to be addressed in this field. Summary of the Invention

[0009] In view of the above-mentioned disadvantages of the prior art, the present application aims to provide an operating method of a split-gate memory array, which can solve the problems of the prior art, such as the slow writing speed of the conventional SONOS memory, the need to introduce a complex deep N-well (DNW) process for the erase operation, and the high power consumption of the conventional hot carrier injection (HCI) writing mode, and provide a reliable operating scheme under a high-density array.

[0010] To achieve the above-mentioned and other related purposes, the present application provides an operating method of a split-gate memory array, which adopts an independent source line architecture, wherein each column of memory cells has its own independent bit line and source line, and each memory cell is composed of one select transistor and first and second storage transistors arranged on both sides of the select transistor, and the operating method comprises:

[0011] An erase operation is realized by a gate carrier tunneling mode, i.e. a positive voltage is applied to the gate of the storage transistor, so that holes pass through the tunneling oxide layer in the gate dielectric from the gate polysilicon of the storage transistor and are injected into the charge storage layer;

[0012] A write operation is realized by a channel hot carrier injection mode;

[0013] Write inhibition is performed by applying an inhibition bias to inhibit the write disturbance to non-selected cells.

[0014] Preferably, the specific bias of the erase operation is that all select transistor gates are grounded, the well region is grounded, all bit lines and dedicated source lines are floating or grounded; for the selected row, a positive erase voltage is applied to at least one storage transistor gate, so that holes are injected into the charge storage layer via the Fowler-Nordheim tunneling effect, while electrons in the channel are difficult to tunnel; for the non-selected row, the storage transistor gate is grounded.

[0015] Preferably, the specific bias of the write operation and write inhibition is that for the selected cell, the well region is grounded, a weak turn-on voltage is applied to the select transistor gate, a positive write assist voltage is applied to the storage transistor gate to be written, a write voltage is applied to the drain terminal, the source terminal is grounded, and another storage transistor gate sharing the select transistor with the selected cell is connected to a turn-on voltage; for the non-selected cell in the same row, the corresponding bit line and dedicated source line are both applied with the same voltage as the write voltage; for the non-selected row, the select transistor gate is grounded, and the storage transistor gate is connected to a non-selected write assist voltage.

[0016] Preferably, the operation method further comprises a read operation, the bias of which is that: the well region is grounded; for the selected cell, the gate of the memory transistor thereof to be read is grounded, the gate of the select transistor thereof is connected to a positive read voltage, the drain thereof is connected to a positive read limit voltage, and the source thereof is grounded; meanwhile, the gate of the memory transistor of another cell sharing the select transistor with the selected cell is connected to a turn-on voltage; for the unselected cells in the same row, both the bit line and the dedicated source line thereof are grounded; and for the unselected row, the gate of the select transistor thereof is grounded.

[0017] Preferably, during the write and erase operations, the well region where the memory transistor is located is always kept at a ground potential, so that a deep N-well is not needed.

[0018] Preferably, the operation method adopts a dual charge pump positive and negative voltage mode, and all the applied voltages during the erase and write operations are superimposed with a negative voltage difference by a charge pump applying a negative voltage.

[0019] Preferably, the negative voltage difference is -3 to -5 V.

[0020] Preferably, in the operation voltages, the erase voltage is 7 to 9 V, the turn-on voltage is 3 to 4 V, the read voltage is 2 to 4 V, the unselected write auxiliary voltage is 1 to 2 V, the write voltage is 4 V, the weak-on voltage is 0 to 1 V, and the read limit voltage is 0.1 to 0.85 V.

[0021] To achieve the above object and other related objects, the present application further provides an operation method of a split-gate memory array, the array adopting a shared source line architecture, wherein two adjacent columns of memory cells share one source line and are respectively connected to bit lines, and each memory cell is composed of one select transistor and first and second memory transistors arranged on both sides of the select transistor, the operation method comprising:

[0022] The erase operation is realized by means of gate carrier tunneling, that is, a positive voltage is applied to the gate of the memory transistor, so that holes pass through the tunneling oxide layer in the gate dielectric from the gate polysilicon of the memory transistor and are injected into the charge storage layer;

[0023] The write operation is realized by means of channel hot carrier injection;

[0024] The write inhibition is realized by applying an inhibition bias to inhibit the write disturbance to the unselected cells.

[0025] Preferably, the specific bias of the erase operation is that: all the gates of the select transistors are grounded, the well region is grounded, and all the bit lines and shared source lines are floating or grounded; for the selected row, a positive erase voltage is applied to at least one gate of the memory transistor thereof, so that holes are injected into the charge storage layer via the Fowler-Nordheim tunneling effect, while electrons in the channel are difficult to tunnel; and for the unselected row, the gate of the memory transistor thereof is grounded.

[0026] Preferably, the specific bias of the write operation and write inhibition is: for the selected cell, the well region is grounded, a weak turn-on voltage is applied to its select tube gate, a positive write assist voltage is applied to its storage tube gate to be written, a write voltage is applied to the drain terminal, the source terminal is grounded, and the other storage tube gate sharing the select tube with the selected cell is connected to a turn-on voltage; for the same row of non-selected cells, two cases are distinguished: when programming the storage tube close to the shared source line, the same voltage as the write voltage is applied to the bit line and the shared source line of all non-selected cells in the row; when programming the storage tube close to the bit line, for the non-selected cells sharing the same source line with the selected cell, the bit line is applied with a non-selected inhibition voltage smaller than the write voltage, and the shared source line is grounded; for other non-selected cells not sharing the source line with the selected cell, the same voltage as the write voltage is applied to the bit line and the source line connected thereto; for the non-selected row, the select tube gate is grounded, and the storage tube gate is connected to a non-selected write assist voltage.

[0027] Preferably, the operation method further includes a read operation, and the bias of the read operation is: the well region is grounded; for the selected cell, the storage tube gate to be read is grounded, the select tube gate is connected to a positive read voltage, the drain terminal is connected to a positive read limit voltage, and the source terminal is grounded; for the other storage tube gate sharing the select tube with the selected cell, the gate is connected to a turn-on voltage; for the same row of non-selected cells, the bit line and the shared source line are both grounded; for the non-selected row, the select tube gate is grounded.

[0028] Preferably, during the write and erase operations, the well region where the storage tube is located is always kept at a ground potential, so that a deep N-well is not needed.

[0029] Preferably, the operation method adopts a dual charge pump positive and negative voltage mode, and all the applied voltages are superimposed with a negative voltage difference during the erase and write operations by a charge pump applying a negative voltage.

[0030] Preferably, the negative voltage difference is -3 to -5V.

[0031] Preferably, in the operation voltages, the erase voltage is 7 to 9V, the turn-on voltage is 3 to 4V, the read voltage is 2 to 4V, the non-selected write assist voltage is 1 to 2V, the write voltage is 4V, the non-selected inhibition voltage is 1 to 3V, the weak turn-on voltage is 0 to 1V, and the read limit voltage is 0.1 to 0.85V.

[0032] To achieve the above object and other related objects, the present application also provides an operating method of a split-gate memory array, which adopts a common source line architecture, wherein all the memory cells in a column share a common source line and are connected to a respective bit line, and each memory cell is composed of a select transistor and a first memory transistor and a second memory transistor arranged on both sides of the select transistor, the operating method comprising:

[0033] an erase operation, which is realized by means of carrier tunneling through the gate, i.e. a positive voltage is applied to the gate of the memory transistor, so that holes pass through the tunneling oxide layer in the gate dielectric from the gate polysilicon of the memory transistor and are injected into the charge storage layer;

[0034] a write operation, which is realized by means of hot carrier injection through the channel;

[0035] write inhibition, which is realized by applying an inhibition bias to inhibit write disturbance to non-selected cells.

[0036] Preferably, the specific bias for the erase operation is that all select transistor gates are grounded, the well region is grounded, all bit lines and the common source line are floating or grounded; for the selected row, a positive erase voltage is applied to at least one memory transistor gate, so that holes are injected into the charge storage layer via the Fowler-Nordheim tunneling effect, while electrons in the channel are difficult to tunnel; for the non-selected row, the memory transistor gate is grounded.

[0037] Preferably, the specific bias for the write operation and write inhibition is that, for the selected cell, the well region is grounded, a weak turn-on voltage is applied to the select transistor gate, a positive write assist voltage is applied to the memory transistor gate to be written, a write voltage is applied to the drain terminal, the source terminal is grounded, and the other memory transistor gate sharing the select transistor is applied with a turn-on voltage; for the non-selected cell in the same row, two cases are distinguished: when programming the memory transistor close to the common source line, the same voltage as the write voltage is applied to the bit line and the common source line of all non-selected cells in the row; when programming the memory transistor close to the bit line, a non-selected inhibition voltage smaller than the write voltage is applied to the bit line of all non-selected cells in the row, while the common source line is grounded; for the non-selected row, the select transistor gate is grounded, and the memory transistor gate is applied with a non-selected write assist voltage.

[0038] Preferably, the operating method further comprises a read operation, the bias of which is that the well region is grounded; for the selected cell, the memory transistor gate to be read is grounded, the select transistor gate is applied with a positive read voltage, the drain terminal is applied with a positive read limit voltage, and the source terminal is grounded, while the other memory transistor gate sharing the select transistor is applied with a turn-on voltage; for the non-selected cell in the same row, the bit line and the common source line are both grounded; for the non-selected row, the select transistor gate is grounded.

[0039] Preferably, during the write and erase operations, the well region where the storage tube is located is always kept at ground potential, thus there is no need to use deep N-well.

[0040] Preferably, the operation method adopts a double charge pump positive and negative voltage mode, and all the applied voltages during the erase and write operations are superimposed with a negative voltage difference by a charge pump applying a negative voltage.

[0041] Preferably, the negative voltage difference is -3 to -5V.

[0042] Preferably, in the operation voltages, the erase voltage is 7 to 9V, the on voltage is 3 to 4V, the read voltage is 2 to 4V, the non-selected write auxiliary voltage is 1 to 2V, the write voltage is 4V, the non-selected inhibition voltage is 1 to 3V, the weak on voltage is 0 to 1V, and the read limit voltage is 0.1 to 0.85V.

[0043] As described above, the operation method of the split gate memory array of the present application has the following beneficial effects:

[0044] First, it has the advantages of high-speed writing and low power consumption. The microsecond-level fast writing is realized by adopting the channel hot carrier injection method, and the write current is innovatively controlled at the nA level by using the weak on mode of the selection tube, which is significantly lower than the traditional HCI technology, thus solving the problem that speed and power consumption are difficult to balance.

[0045] Second, the manufacturing process is greatly simplified and the cost is reduced. The erase and write operations of the present application are performed by applying a positive voltage to the gate of the storage tube, and the well region is always kept at ground, thus completely avoiding the deep N-well (DNW) process which must be introduced in the traditional scheme to isolate the positive bias of the well region, reducing the photolithography mask and ion implantation steps.

[0046] Third, the reliability and flexibility of the operation are improved. The present application provides a complete and refined write inhibition bias scheme for different high-density array architectures such as independent source line (DSL), shared source line (SSL) and common source line (CSL), effectively solving the write disturbance problem under complex connection relationship, and ensuring the accuracy of data operation. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 A cross-sectional structure schematic diagram of a SONOS storage unit based on gate carrier tunneling and channel hot carrier injection according to the present application is shown.

[0048] Figure 2 A physical principle schematic diagram of the write operation according to the present application is shown.

[0049] Figure 3 A physical principle schematic diagram of the erase operation according to the present application is shown.

[0050] Figure 4 Circuit schematic showing three different memory array architectures (DSL, SSL, CSL) applicable to the present invention;

[0051] Figure 5 Schematic showing an example of operating bias for the present invention under the DSL architecture;

[0052] Figure 6 Schematic showing an example of array bias for the present invention under the DSL architecture for a write operation;

[0053] Figure 7 Schematic showing an example of operating bias for the present invention under the SSL architecture for programming a memory cell near a bit line (BL);

[0054] Figure 8 Schematic showing an example of array bias for the present invention under the SSL architecture for programming a memory cell near a bit line (BL);

[0055] Figure 9 Schematic showing an example of operating bias for the present invention under the SSL architecture for programming a memory cell near a shared source line (SSL);

[0056] Figure 10 Schematic showing an example of array bias for the present invention under the SSL architecture for programming a memory cell near a shared source line (SSL);

[0057] Figure 11 Schematic showing an example of operating bias for the present invention under the CSL architecture for programming a memory cell near a bit line (BL);

[0058] Figure 12 Schematic showing an example of array bias for the present invention under the CSL architecture for programming a memory cell near a bit line (BL);

[0059] Figure 13 Schematic showing an example of operating bias for the present invention under the CSL architecture for programming a memory cell near a common source line (CSL);

[0060] Figure 14 Schematic showing an example of array bias for the present invention under the CSL architecture for programming a memory cell near a common source line (CSL);

[0061] Figure 15 Schematic showing an example of page erase operation for the present invention under the DSL architecture;

[0062] Figure 16 Schematic showing an example of byte program operation for the present invention under the DSL architecture;

[0063] Figure 17 Figure 1 shows a specific example of read operation in DSL architecture. DETAILED DESCRIPTION

[0064] Other advantages and benefits of the present application will become apparent to those skilled in the art upon consideration of the disclosure herein. The application can be implemented or applied in other different embodiments and its details can be modified in various obvious ways without departing from the spirit of the application.

[0065] The operation method proposed in this application is applicable to various memory array architectures. As shown in Figure 1, three typical array connection methods are illustrated. The first one is dedicated source line (DSL) architecture, in which each column of memory cells has its own independent bit line (e.g. BL1, BL2) and dedicated source line (e.g. SL1, SL2). This architecture is simple to control, but it requires two metal lines per column, which results in relatively large layout area. The second one is shared source line (SSL) architecture, in which two adjacent columns of memory cells (e.g. column A and column B) share one source line (e.g. SSL1), while each column has its own independent bit line (e.g. BL1, BL2). This architecture requires 1.5 metal lines per column on average, which can save layout area compared with DSL architecture. The third one is common source line (CSL) architecture, in which all columns of memory cells share one common source line (CSL), while each column has its own independent bit line (e.g. BL1, BL2). This architecture requires only one metal line per column on average, which results in the highest layout density. In the following description, the cells with and without asterisk (e.g. Al and Al*) indicate that they share the same select transistor and belong to the same mirror cell. The cells with the same letter (e.g. Al and A2) belong to the same column, and the cells with the same number (e.g. Al and Bl) belong to the same row. The operation method proposed in this application is compatible with these three and similar array architectures, and solves the disturbance problem in different architectures through specific biasing scheme. Figure 4 Figure 4

[0066] ​​The present application provides a method for operating a split-gate memory array with a separate source line (DSL) architecture, in which each column of memory cells has its own separate bit line and source line, and each memory cell is composed of a select transistor and first and second storage transistors on either side of the select transistor. The method includes: an erase operation, which is performed by a gate carrier tunneling method, i.e. a positive voltage is applied to the gate of the storage transistor, so that the holes pass through the tunneling oxide layer in the gate dielectric from the gate polysilicon of the storage transistor and are injected into the charge storage layer; a write operation, which is performed by a channel hot carrier injection (HCI) method; and a write inhibition, which is performed by applying an inhibition bias to inhibit write disturbance to non-selected cells.

[0067] Figure 5 A specific bias example for performing erase, write and read operations on the array under the DSL architecture is shown.

[0068] In some embodiments, the specific bias for the erase operation is that all select transistor gates (WL) are grounded, the well region (PW) is grounded, and all bit lines (BL) and dedicated source lines (SL) are floating or grounded; for the selected row, a positive erase voltage (Vpos) is applied to at least one of the storage transistor gates (WLS or WLS*), so that the holes are injected into the charge storage layer via the Fowler-Nordheim (FN) tunneling effect, while the electrons in the channel are difficult to tunnel; and for the non-selected rows, the storage transistor gates are grounded. Figure 15 A specific example of performing page erase under the DSL architecture is shown in detail. In this example, the goal is to erase all memory cells (A1, B1, A1*, B1*, etc.) in the first row (Row 1). As shown, the storage transistor word line WLS1 of the selected row is applied with a positive voltage of 7V, while the corresponding select transistor word line WL1 and the storage transistor word line WLS1* on the other side are both grounded (0V). For all non-selected rows (such as the second row and subsequent rows), all of their word lines (WLS2, WL2, WLS2*, etc.) are kept grounded (0V). At the same time, the well region (PW) of the entire array, as well as all bit lines (BL1, BL2,...) and source lines (SL1, SL2,...) are also grounded (0V). Under this bias, only the gate and channel of the storage transistors (A1, B1, etc.) controlled by the first row WLS1 form a strong electric field sufficient to trigger FN tunneling, so that the gate holes are injected and the erase is completed. The non-selected rows and other storage transistors do not meet the tunneling conditions and remain unchanged. The time for the entire page erase process is about 2.5 to 5 milliseconds. This erase method utilizes the mechanism of gate injection of holes, which is different from the traditional channel injection. Since a positive voltage is applied to the gate, the well region can be kept grounded, thereby avoiding the need for a deep N-well (DNW) process to isolate the positive bias of the well region, which significantly simplifies the manufacturing process, reduces production costs, and improves the integration density of the device.

[0069] In some embodiments, the specific bias for write operation and write inhibition is as follows: for the selected cell: the well region (PW) is grounded, a weak-on voltage (Vwl) is applied to its select gate (WL), a positive write assist voltage (Vpos) is applied to its storage gate (WLS or WLS*), a write voltage (Vbl) is applied to the drain terminal (BL or SL), the source terminal (SL or BL) is grounded, and the other storage gate (WLS* or WLS) sharing the select gate with the selected cell is applied with a turn-on voltage (Vso); for the unselected cell in the same row: both the bit line (BL) and the dedicated source line (SL) are applied with the same voltage as the write voltage (Vbl); for the unselected row: the select gate (WL) is grounded, and the storage gate is applied with an unselected write assist voltage (VposU). As shown in Figure 6 and Figure 16 The bias conditions for programming the selected cell A1 under the DSL architecture are shown in detail, with reference to the Program operation in Figure 5 In the selected cell A1, WL1 is applied with Vwl (e.g. 0.1V), WLS1 is applied with Vpos (e.g. 7V), BL1 is applied with Vbl (e.g. 4V), and SL1 is grounded, while A1* on the non-program side is turned on (WLS1* is applied with Vso, e.g. 3V), so as to generate hot electron injection at the drain terminal of A1. For the unselected cell B1 in the same row, although its WL1 and WLS1 are also applied with the same voltage, its BL2 and SL2 are both applied with Vbl voltage (4V), and there is no potential difference across the channel, so no current flows through, and no hot electron is generated, thus effectively inhibiting the write disturbance. For the unselected row (e.g. A2 / B2), its WL2 is grounded, and the select gate is completely turned off, even if its storage gate WLS2 / WLS2* is applied with a lower inhibition voltage (e.g. 1.1V), no write will occur. By weakly turning on the select gate during writing, only nA-level leakage current is generated in the channel, which is much lower than the μA-level current required in the conventional HCI write method, and the power consumption of the present application is greatly reduced. The time for the entire write process is about 5 to 10 microseconds.

[0070] In some embodiments, a read operation is also included, which is biased as follows: the well region (PW) is grounded; for the selected cell, its storage tube gate (WLS or WLS*) is grounded, its select tube gate (WL) is connected to a positive read voltage (Vpwr), its drain end (BL or SL) is connected to a positive read limit voltage (Vlim), its source end (SL or BL) is grounded, while the gate of another storage tube sharing the select tube with the selected cell (WLS* or WLS) is connected to a turn-on voltage (Vso); for the same row of unselected cells, both the bit line (BL) and the dedicated source line (SL) are grounded; for the unselected row, the select tube gate (WL) is grounded. Referring to the Read operation section in Figure 5 and Figure 17 When reading the A1 cell, only a read-out voltage difference is applied between BL1 and SL1 (BL1 = 0.85V, SL1 = 0V), while the BL and SL of all other rows of unselected cells (such as B1) are grounded, ensuring that only the selected cell has current flowing through it. The selected row WL1 is applied with Vpwr (such as 3V), WLS1 is grounded, and WLS1* is applied with Vso (such as 3V). The unselected row WL2 is grounded. This reading method precisely isolates the unselected cells, effectively avoiding read disturbance and misreading, and improving the reliability of array reading.

[0071] In some embodiments, during the write and erase operations, the well region (PW) in which the storage tube is located is always kept at a ground potential, so that a deep N-well (DNW) is not needed.

[0072] In some embodiments, the operation method can also use a dual charge pump positive and negative voltage mode, in which a negative voltage is applied by a charge pump, and during the erase and write operations, all applied voltages are superimposed with a negative voltage difference (Vneg). Using the dual pump positive and negative voltage operation, the peak value of all positive operating voltages can be reduced while keeping the effective electric field strength between the gate and the channel unchanged, which is beneficial for reducing the voltage requirements of the high-voltage generation circuit and the peripheral driving circuit, improving the reliability and compatibility of the circuit, and further optimizing power consumption.

[0073] In some embodiments, the negative voltage difference Vneg is -3 to -5V.

[0074] In some embodiments, the operating voltage Vpos is 7 to 9V, Vso is 3 to 4V, Vpwr is 2 to 4V, VposU is 1 to 2V, Vbl is 3 to 4V, Vwl is 0 to 1V, and Vlim is 0.1 to 0.85V.

[0075] The application also provides an operating method of a split-gate memory array adopting a shared source line (SSL) architecture, in which two adjacent columns of memory cells share one source line and are connected to respective bit lines, and each memory cell is composed of one select transistor and first and second storage transistors arranged on both sides of the select transistor, the operating method comprising: an erase operation realized by means of gate carrier tunneling, i.e. a positive voltage is applied to the gate of the storage transistor, so that holes pass through the tunneling oxide layer in the gate dielectric from the gate polysilicon of the storage transistor and are injected into the charge storage layer; a write operation realized by means of channel hot carrier injection (HCI); and write inhibition, i.e. an inhibition bias is applied to inhibit write disturbance to non-selected cells.

[0076] In some embodiments, the specific bias of the erase operation is that all select transistor gates (WL) are grounded, all well regions (PW) are grounded, and all bit lines (BL) and shared source lines (SSL) are floating or grounded; for the selected row, a positive erase voltage (Vpos) is applied to at least one storage transistor gate (WLS or WLS*) of the selected row, so that holes are injected into the charge storage layer via the Fowler-Nordheim (FN) tunneling effect, while electrons in the channel are difficult to tunnel; and for the non-selected row, the storage transistor gate is grounded. As shown in the Erase operation in Figure 7 and Figure 9 As shown in the Erase operation in the above-mentioned embodiments, the page erase operation in the SSL architecture is similar to that in the DSL architecture, and does not require a deep N-well process, thereby realizing process simplification and cost saving in the more compact SSL array.

[0077] In some embodiments, the specific biasing for write operation and write inhibition is as follows: for the selected cell: the well region (PW) is grounded, a weak turn-on voltage (Vwl) is applied to its select gate (WL), a positive write assist voltage (Vpos) is applied to its storage gate (WLS or WLS*), a write voltage (Vbl) is applied to the drain terminal, the source terminal is grounded, and the other storage gate (WLS* or WLS) sharing the select gate of the selected cell is connected to a turn-on voltage (Vso); for the non-selected cells in the same row, two cases are distinguished: when programming the storage tube close to the shared source line (SSL), for all non-selected cells in the row, both the corresponding bit line (BL) and the shared source line (SSL) are applied with the same voltage as the write voltage (Vbl); when programming the storage tube close to the bit line (BL), for the non-selected cells sharing the same source line with the selected cell, the corresponding bit line (BL) is applied with a non-selected inhibition voltage (VblU) smaller than the write voltage Vbl while the shared source line is grounded; for other non-selected cells not sharing the source line with the selected cell, both the corresponding bit line (BL) and the source line connected thereto are applied with the same voltage as the write voltage (Vbl); for the non-selected row, the select gate (WL) is grounded and the storage gate is connected to a non-selected write assist voltage (VposU). This refined write inhibition scheme for the SSL architecture design is an important aspect of the present application. For details, please refer to Figure 7 and Figure 8 When programming the storage tube Al close to the bit line BL1, the non-selected cell Bl sharing the source line SSL1 with Al has its bit line BL2 applied with a lower voltage VblU, and since its source line SSL1 is grounded, the voltage difference across the channel of Bl (VblU) is much smaller than that of the selected cell Al (Vbl), thus insufficient to generate effective hot electron injection, and Bl is inhibited. For the non-selected cell Cl not sharing the source line, both its bit line BL3 and source line SSL2 are applied with Vbl, and there is no voltage difference across the channel, so Cl is also inhibited. For details, please refer to Figure 9 and Figure 10 When programming the storage tube Al* close to the shared source line SSL1, the situation becomes different. At this time, SSL1 is applied with Vbl as the drain terminal and BL1 is grounded as the source terminal. For all non-selected cells (such as Bl*, Cl*) in the row, both their bit lines (BL2, BL3) and corresponding source lines (SSL1, SSL2) are applied with Vbl voltage, and there is no potential difference across the channel, so they are all effectively inhibited. This flexible biasing strategy can effectively prevent write disturbance, and ensure the accuracy of data writing even under the complex connection relationship of shared source lines.

[0078] In some embodiments, a read operation is also included, which is biased as follows: the well region (PW) is grounded; for the selected cell, its storage tube gate (WLS or WLS*) is grounded, its select tube gate (WL) is connected to a positive read voltage (Vpwr), its drain end (BL or SSL) is connected to a positive read limit voltage (Vlim), its source end (SSL or BL) is grounded, and the gate of another storage tube sharing the select tube of the selected cell (WLS* or WLS) is connected to a turn-on voltage (Vso); for the unselected cells in the same row, both the bit line (BL) and the shared source line (SSL) are grounded; and for the unselected row, the select tube gate (WL) is grounded. As shown in the Read operation in Figure 7 and Figure 9 During read, only the bit line and the shared source line of the selected cell are connected and have a voltage difference, while all the unselected cells have no voltage difference, thus ensuring the accuracy of the read operation.

[0079] In some embodiments, during the write and erase operations, the well region (PW) where the storage tube is located is always kept at ground potential, thus eliminating the need to use a deep N-well (DNW).

[0080] In some embodiments, the operation method can also use a dual charge pump positive and negative voltage mode, in which a negative voltage is applied by a charge pump, and during the erase and write operations, all the applied voltages are superimposed with a negative voltage difference (Vneg).

[0081] In some embodiments, the negative voltage difference Vneg is -3 to -5 V.

[0082] In some embodiments, the operation voltages are as follows: Vpos is 7 to 9 V, Vso is 3 to 4 V, Vpwr is 2 to 4 V, VposU is 1 to 2 V, Vbl is 3 to 4 V, VblU is 1 to 3 V, Vwl is 0 to 1 V, and Vlim is 0.1 to 0.85 V.

[0083] The present application also provides an operation method for a split-gate memory array, which uses a common source line (CSL) architecture in which all the storage cells in a column share the same source line and are connected to respective bit lines, and each storage cell is composed of a select tube and first and second storage tubes arranged on both sides of the select tube, the operation method including: an erase operation, which is realized by a gate carrier tunneling method, i.e., a positive voltage is applied to the gate of the storage tube, so that holes pass through the tunneling oxide layer in the gate dielectric from the gate polysilicon of the storage tube and are injected into the charge storage layer; a write operation, which is realized by a channel hot carrier injection (HCI) method; and a write inhibition, which is realized by applying an inhibition bias to inhibit write disturbance to unselected cells.

[0084] In some embodiments, the specific bias for the erase operation is: all select gate (WL) grounded, well (PW) grounded, all bit lines (BL) and common source line (CSL) floating or grounded; for the selected row, a positive erase voltage (Vpos) is applied to at least one of the storage gate (WLS or WLS*) such that holes are injected into the charge storage layer via the Fowler-Nordheim (FN) tunneling effect while electrons in the channel are unable to tunnel; for the unselected row, the storage gate is grounded. As shown in the Erase operation in Figure 11 and Figure 13 In the CSL architecture with the highest layout density, the erase method proposed by the present application still maintains its advantages of simplified process and no need for DNW, which is of great significance for the implementation of large-scale and high-density memory chips.

[0085] In some embodiments, the specific bias for the write operation and write inhibition is: for the selected cell: well (PW) grounded, weak on voltage (Vwl) applied to the select gate (WL), positive write assist voltage (Vpos) applied to the storage gate (WLS or WLS*) to be written, write voltage (Vbl) applied to the drain end (BL or CSL), source end (CSL or BL) grounded, and the other storage gate (WLS* or WLS) sharing the select gate of the selected cell is connected to a conduction voltage (Vso); for the unselected cell in the same row, two cases are distinguished: when programming the storage tube close to the common source line (CSL), the same voltage as the write voltage (Vbl) is applied to the corresponding bit line (BL) and common source line (CSL) of all unselected cells in the row; when programming the storage tube close to the bit line (BL), a non-selected inhibition voltage (VblU) smaller than the write voltage Vbl is applied to the corresponding bit line (BL) of all unselected cells in the row, while the common source line (CSL) is grounded; for the unselected row, the select gate (WL) is grounded and the storage gate is connected to a non-selected write assist voltage (VposU). This inhibition scheme also considers the scenario of programming storage tubes at different positions in the CSL architecture. For details, please refer to Figure 11 and Figure 12 When programming the storage tube Al close to the bit line BL1, the bit line BL2 of all unselected columns (such as column B) is applied with a lower voltage VblU. Since the common source line CSL is grounded, the voltage difference across the channel of all unselected cells (such as B1) is VblU, which is not enough to generate effective hot electron injection, thereby achieving inhibition of all unselected cells in the entire row. For details, please refer to Figure 13 and Figure 14When programming the memory cell A1* near the common source line CSL, the CSL is applied as the drain with Vbl, and the BL1 is grounded as the source. At this time, for all non-selected cells (e.g. B1*) in the same row, their bit line (BL2) and common source line (CSL) are both applied with Vbl voltage, and there is no potential difference across the channel, so they are all effectively inhibited. Through this flexible biasing strategy, it is ensured that the write operation is still accurate and reliable under high-density shared lines, and cross-talk between cells is avoided.

[0086] In some embodiments, a read operation is also included, which is biased as follows: the well region (PW) is grounded; for the selected cell, the memory cell gate (WLS or WLS*) to be read is grounded, the select gate (WL) is connected to a positive read voltage (Vpwr), the drain end (BL or CSL) is connected to a positive read limit voltage (Vlim), and the source end (CSL or BL) is grounded, while the gate (WLS* or WLS) of another memory cell sharing the select gate of the selected cell is connected to a turn-on voltage (Vso); for non-selected cells in the same row, their bit line (BL) and common source line (CSL) are both grounded; for non-selected rows, the select gate (WL) is grounded. As shown in the Read operation in Figure 11 and Figure 13 As shown in the Read operation in, only a path and a pressure difference are established between the bit line and the common source line of the selected cell during reading, and no pressure difference is applied to all non-selected cells, ensuring the accuracy of reading.

[0087] In some embodiments, during the write and erase operations, the well region (PW) where the memory cell is located is always kept at ground potential, so that a deep N-well (DNW) is not needed.

[0088] In some embodiments, the operation method can also use a dual charge pump positive and negative voltage mode, through a charge pump applying a negative voltage, during the erase and write operations, all applied voltages are superimposed with a negative voltage difference (Vneg).

[0089] In some embodiments, the negative voltage difference Vneg is -3 to -5V.

[0090] In some embodiments, the operating voltage Vpos is 7 to 9V, Vso is 3 to 4V, Vpwr is 2 to 4V, VposU is 1 to 2V, Vbl is 3 to 4V, VblU is 1 to 3V, Vwl is 0 to 1V, and Vlim is 0.1 to 0.85V.

[0091] In the above embodiments, the storage gate and select gate are typically formed of polysilicon. In other embodiments, these gate materials can also employ metal gate technology, such as using titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or a combination thereof, to improve the work function and electrical performance of the device. The method of forming the gate can include conventional deposition, photolithography, and etching processes, or can employ advanced gate-last or high-K metal gate process flows.

[0092] The tunneling oxide and blocking oxide in the gate dielectric layer are typically silicon dioxide (SiO2) and can be formed by thermal oxidation or chemical vapor deposition (CVD), etc. In some alternative embodiments, these layers can be replaced or combined with other high-K or low-K dielectric materials to optimize the tunneling efficiency and charge blocking capability. For example, the blocking oxide can employ aluminum oxide (Al2O3) or a composite oxide stack to enhance the binding capability of the charge and improve the data retention time. The tunneling oxide can also be designed as a multi-layer structure, such as silicon dioxide / silicon nitride / silicon dioxide (ONO), to optimize the tunneling process by band engineering.

[0093] The charge storage layer is typically silicon nitride (Si3N4), but can also employ other charge-trap-rich materials, such as silicon-rich nitride, nanocrystalline silicon-embedded dielectric, or defect states in high-K materials such as hafnium oxide (HfO2) to store the charge. The selection of these materials can be used to adjust the storage window and erase speed.

[0094] The implant regions of the source and drain are typically formed by ion implantation, followed by annealing activation. In forming the light-doped drain (LDD) structure, a specific implant angle and energy control can be employed to optimize the electric field distribution near the channel edge, thereby improving the efficiency of hot electron generation and reducing the short channel effect.

[0095] The above embodiments are illustrative only of the principles of the present application and are not intended to limit the scope of the present application. Any variations and modifications of the embodiments described will be apparent to those with ordinary skill in the art, without departing from the spirit and scope of the present application. Accordingly, all such variations and modifications are intended to be included within the scope of the present application as defined in the appended claims.

Claims

1. A method of operating a split-gate memory array, said array employing a separate source line (DSL) architecture in which each column of memory cells has its own separate bit line and source line, and each memory cell is formed from one select transistor and first and second storage transistors disposed on either side thereof, characterized by, At least comprising: an erase operation, realized by means of carrier tunneling through the gate, i.e. a positive voltage is applied to the gate of the memory tube, so that holes pass through the tunneling oxide in the gate dielectric from the gate polysilicon of the memory tube and are injected into the charge storage layer; a write operation, realized by means of hot carrier injection (HCI) through the channel; write inhibition, realized by applying an inhibition bias to inhibit write disturbance to non-selected cells.

2. The method of operating a split-gate memory array of claim 1, wherein: The specific bias for the erase operation is: all selected tube gates (WL) grounded, well region (PW) grounded, all bit lines (BL) and dedicated source lines (SL) floating or grounded; for the selected row, a positive erase voltage (Vpos) is applied to at least one of the memory tube gates (WLS or WLS*), so that holes are injected into the charge storage layer via the Fowler-Nordheim (FN) tunneling effect, while electrons in the channel are difficult to tunnel; for the non-selected row, the memory tube gate is grounded.

3. The method of operating a split-gate memory array of claim 1, wherein: The specific bias for the write operation and write inhibition is: for the selected cell: well region (PW) grounded, weak on voltage (Vwl) applied to the selected tube gate (WL), positive write assist voltage (Vpos) applied to the memory tube gate to be written (WLS or WLS*), write voltage (Vbl) applied to the drain end, source end grounded, while the other memory tube gate (WLS* or WLS) sharing the selected tube is applied with a conduction voltage (Vso); for the non-selected cell in the same row: weak on voltage (Vwl) applied to the selected tube gate, write assist voltage (Vpos) applied to the memory tube gate, but the corresponding bit line and dedicated source line are applied with the same voltage as the write voltage (Vbl); for the non-selected row: the selected tube gate is grounded, the memory tube gate is applied with a non-selected write assist voltage (VposU).

4. The method of operating a split-gate memory array of claim 1, wherein: It also includes a read operation, with the bias: well region (PW) grounded; for the selected cell, the memory tube gate to be read (WLS or WLS*) is grounded, the selected tube gate (WL) is applied with a positive read voltage (Vpwr), the drain end (BL or SL) is applied with a positive read limit voltage (Vlim), the source end (SL or BL) is grounded, while the other memory tube gate (WLS* or WLS) sharing the selected tube is applied with a conduction voltage (Vso); for the non-selected cell in the same row, both the bit line (BL) and the dedicated source line (SL) are grounded; for the non-selected row, the selected tube gate (WL) is grounded.

5. The method of operating a split-gate memory array of claim 1, wherein: During the write and erase operations, the well region (PW) where the memory tube is located is always kept at ground potential, so that a deep N well (DNW) is not needed.

6. The method of operating a split-gate memory array of claim 1, wherein: The operation method can also adopt a dual charge pump positive and negative voltage mode, by means of a charge pump applying a negative voltage, during the erase and write operations, all the applied voltages are superimposed with a negative voltage difference (Vneg).

7. The method of operating a split-gate memory array of claim 6, wherein: The negative voltage difference Vneg is -3 to -5V.

8. The method of operating a split-gate memory array of claim 1, wherein: The operating voltage Vpos is 7 to 9 V, Vso is 3 to 4 V, Vpwr is 2 to 4 V, VposU is 1 to 2 V, Vbl is 3 to 4 V, Vwl is 0 to 1 V, and Vlim is 0.1 to 0.85 V.

9. A method of operating a split-gate memory array, said array employing a shared source line (SSL) architecture in which two adjacent columns of memory cells share a source line and are connected to respective bit lines, and each memory cell is formed by a select transistor and first and second storage transistors disposed on either side thereof, characterized by, At least comprising: An erase operation is realized by means of carrier tunneling through the gate, i.e. a positive voltage is applied to the gate of the memory tube, so that holes pass through the tunneling oxide layer in the gate dielectric from the gate polysilicon of the memory tube and are injected into the charge storage layer; A write operation is realized by means of hot carrier injection (HCI) through the channel; Write inhibition is applied to inhibit write disturbance to non-selected cells.

10. The method of operating a split-gate memory array of claim 9, wherein: The specific bias of the erase operation is that all selected tube gates (WL) are grounded, the well region (PW) is grounded, and all bit lines (BL) and shared source lines (SSL) are floating or grounded; for the selected row, a positive erase voltage (Vpos) is applied to at least one of the memory tube gates (WLS or WLS*), so that holes are injected into the charge storage layer via the Fowler-Nordheim (FN) tunneling effect, while electrons in the channel are difficult to tunnel; for the non-selected row, the memory tube gate is grounded.

11. The method of operating a split-gate memory array of claim 9, wherein: For the selected cell: the well region (PW) is grounded, a weak turn-on voltage (Vwl) is applied to the selected tube gate (WL), a positive write assist voltage (Vpos) is applied to the memory tube gate (WLS or WLS*) to be written, a write voltage (Vbl) is applied to the drain terminal, the source terminal is grounded, and the other memory tube gate (WLS* or WLS) of the shared selected tube is connected to a turn-on voltage (Vso); for the non-selected cell in the same row, two cases are distinguished: when programming the memory tube close to the shared source line (SSL), for all non-selected cells in the row, the corresponding bit line (BL) and shared source line (SSL) are applied with the same voltage as the write voltage (Vbl); when programming the memory tube close to the bit line (BL), for the non-selected cell sharing the same source line with the selected cell, the corresponding bit line (BL) is applied with a non-selected inhibition voltage (VblU) smaller than the write voltage Vbl, and the shared source line is grounded; for other non-selected cells not sharing the source line with the selected cell, the corresponding bit line (BL) and the source line connected thereto are applied with the same voltage as the write voltage (Vbl); for the non-selected row, the selected tube gate (WL) is grounded, and the memory tube gate is connected to a non-selected write assist voltage (VposU).

12. The method of operating a split-gate memory array of claim 9, wherein: It also includes a read operation, the bias of which is: the well region (PW) is grounded; for the selected cell, the storage tube gate (WLS or WLS*) to be read is grounded, the selection tube gate (WL) is connected to a positive read voltage (Vpwr), the drain end (BL or SSL) is connected to a positive read limit voltage (Vlim), and the source end (SSL or BL) is grounded, while the gate (WLS* or WLS) of another storage tube sharing the selection tube of the selected cell is connected to a conduction voltage (Vso); for the non-selected cells in the same row, both the bit line (BL) and the shared source line (SSL) are grounded; and for the non-selected row, the selection tube gate (WL) is grounded.

13. The method of operating a split-gate memory array of claim 9, wherein: During the write and erase operations, the well region (PW) where the storage tube is located is always kept at a ground potential, so that a deep N-well (DNW) is not needed.

14. The method of operating a split-gate memory array of claim 9, wherein: The operation method can also use a dual charge pump positive and negative voltage mode, in which a negative voltage is applied by a charge pump, and during the erase and write operations, all applied voltages are superimposed with a negative voltage difference (Vneg).

15. The method of operating a split-gate memory array of claim 14, wherein: The negative voltage difference Vneg is -3 to -5V.

16. The method of operating a split-gate memory array of claim 9, wherein: The operation voltages Vpos is 7 to 9V, Vso is 3 to 4V, Vpwr is 2 to 4V, VposU is 1 to 2V, Vbl is 3 to 4V, VblU is 1 to 3V, Vwl is 0 to 1V, and Vlim is 0.1 to 0.85V.

17. A method of operating a split-gate memory array, said array employing a common source line (CSL) architecture in which the memory cells of all columns share a common source line and are connected to respective bit lines, and each memory cell is formed by a select transistor and first and second storage transistors disposed on either side thereof, characterized by, At least including: An erase operation is achieved by a gate carrier tunneling method, that is, a positive voltage is applied to the gate of the storage tube, so that holes pass through the tunneling oxide layer in the gate dielectric from the gate polysilicon of the storage tube and are injected into the charge storage layer; A write operation is achieved by a channel hot carrier injection (HCI) method; Write inhibition: an inhibition bias is applied to inhibit write disturbance to non-selected cells.

18. The method of operating a split-gate memory array of claim 17, wherein: The specific bias of the erase operation is: all selection tube gates (WL) are grounded, the well region (PW) is grounded, and all bit lines (BL) and common source lines (CSL) are floating or grounded; for the selected row, a positive erase voltage (Vpos) is applied to at least one storage tube gate (WLS or WLS*), so that holes are injected into the charge storage layer via the Fowler-Nordheim (FN) tunneling effect, while electrons in the channel are difficult to tunnel; for the non-selected row, the storage tube gate is grounded.

19. The method of operating a split-gate memory array of claim 17, wherein: The specific bias of the write operation and write inhibition is: for the selected cell, the well region (PW) is grounded, a weak turn-on voltage (Vwl) is applied to its selection tube gate (WL), a positive write auxiliary voltage (Vpos) is applied to its to-be-written storage tube gate (WLS or WLS*), a write voltage (Vbl) is applied to the drain end, the source end is grounded, and the other storage tube gate (WLS* or WLS) sharing the selection tube of the selected cell is connected to a turn-on voltage (Vso); for the non-selected cells in the same row, two cases are distinguished: when programming the storage tube close to the common source line (CSL), the corresponding bit line (BL) and common source line (CSL) of all non-selected cells in the row are applied with the same voltage as the write voltage (Vbl); when programming the storage tube close to the bit line (BL), the corresponding bit line (BL) of all non-selected cells in the row is applied with a non-selected inhibition voltage (VblU) smaller than the write voltage Vbl, and the common source line (CSL) is grounded; for the non-selected row, the selection tube gate (WL) is grounded, and the storage tube gate is connected to a non-selected write auxiliary voltage (VposU).

20. The method of operating a split-gate memory array of claim 17, wherein: The read operation also includes the bias: the well region (PW) is grounded; for the selected cell, the storage tube gate (WLS or WLS*) to be read is grounded, the selection tube gate (WL) is connected to a positive read voltage (Vpwr), the drain end (BL or CSL) is connected to a positive read limit voltage (Vlim), and the source end (CSL or BL) is grounded; for the non-selected cells in the same row, the bit line (BL) and common source line (CSL) are both grounded; for the non-selected row, the selection tube gate (WL) is grounded.

21. The method of operating a split-gate memory array of claim 17, wherein: During the write and erase operations, the well region (PW) where the storage tube is located is always kept at ground potential, so that a deep N-well (DNW) is not needed.

22. The method of operating a split-gate memory array of claim 17, wherein: The operation method can also use a dual charge pump positive and negative voltage mode, through a charge pump applying a negative voltage, during the erase and write operations, all the applied voltages are superimposed with a negative voltage difference (Vneg).

23. The method of operating a split-gate memory array of claim 22, wherein: The negative voltage difference Vneg is -3 to -5V.

24. The method of operating a split-gate memory array of claim 17, wherein: The operation voltages are Vpos 7 to 9V, Vso 3 to 4V, Vpwr 2 to 4V, VposU 1 to 2V, Vbl 3 to 4V, VblU 1 to 3V, Vwl 0 to 1V, and Vlim 0.1 to 0.85V.

Images