Display device and preparation method thereof

Abstract

A display device and a preparation method thereof. The display device comprises a display substrate, an opposite-side substrate and a liquid crystal layer arranged between the display substrate and the opposite-side substrate, wherein the display substrate and the opposite-side substrate are oppositely arranged. At least one of the display substrate and the opposite side substrate is provided with a supporting column. Wherein the display substrate comprises a first substrate, a second conducting layer, a second electrode and a first alignment layer, the second conducting layer, the second electrode and the first alignment layer are sequentially arranged in the direction away from the first substrate, the second electrode is connected with the second conducting layer through a first via hole, and in the direction perpendicular to the display device, the orthographic projection of the supporting column and the orthographic projection of the first via hole are not overlapped; a second alignment layer is arranged on one side, facing the display substrate, of the opposite-side substrate; the display substrate further comprises a filling layer, the filling layer is located in at least one first via hole between the second electrode and the first alignment layer, and the filling layer is arranged to enable the surface, facing the substrate on the opposite side, of the first alignment layer to be flat.

Description

Technical Field

[0001] This article relates to display technology, and in particular to a display device and its manufacturing method. Background Technology

[0002] Liquid crystal displays (LCDs) have seen rapid development due to their small size, low power consumption, and lack of radiation. An LCD consists of a thin-film transistor (TFT) array substrate and a color filter (CF) substrate. Liquid crystal (LC) molecules are disposed between the array substrate and the color filter substrate. By controlling the common electrode and pixel electrode, an electric field is formed to drive the liquid crystal deflection, achieving grayscale display.

[0003] However, liquid crystal displays are prone to slight light leakage in the dark, which is known as a Zara defect. Summary of the Invention

[0004] This disclosure provides a display device and its manufacturing method to solve the problem of defects in liquid crystal display devices (LCDs) caused by Zara.

[0005] On one hand, this disclosure provides a display device, including: a display substrate and a counter-side substrate disposed opposite each other, and a liquid crystal layer disposed between the display substrate and the counter-side substrate; at least one of the display substrate and the counter-side substrate is provided with a support pillar; wherein, the display substrate includes a first substrate and a second conductive layer, a second electrode, and a first alignment layer disposed sequentially along a direction away from the first substrate, the second electrode being connected to the second conductive layer through a first via, and in a direction perpendicular to the display device, the orthographic projection of the support pillar does not overlap with the orthographic projection of the first via; the counter-side substrate is provided with a second alignment layer on the side facing the display substrate; the display substrate further includes a filling layer, the filling layer being located within at least one first via between the second electrode and the first alignment layer, the filling layer being configured to make the surface of the first alignment layer facing the counter-side substrate flat.

[0006] In an exemplary embodiment, within the plane of the display substrate, the minimum distance between the contour edge of the support post that contacts the display substrate and the contour edge of the first via is greater than or equal to 9 micrometers.

[0007] In an exemplary embodiment, at least one of the display substrate and the opposite substrate is provided with a support post, including: the support post is disposed on the opposite substrate, and the support post is in contact with the display substrate through the second alignment layer.

[0008] In an exemplary embodiment, at least one of the display substrate and the opposite substrate is provided with a support pillar, including: the support pillar includes a first sub-support pillar and a second sub-support pillar arranged in pairs, the first sub-support pillar being located on the display substrate and the second sub-support pillar being located on the opposite substrate; in a direction perpendicular to the display device, the orthographic projections of the opposite side surfaces of the first sub-support pillar and the second sub-support pillar at least partially overlap.

[0009] In an exemplary embodiment, the display substrate further includes a first electrode, a plurality of first transistors, a plurality of common power lines, a plurality of gate lines, and a plurality of data lines, wherein the plurality of gate lines and the plurality of data lines intersect to define a plurality of sub-pixel regions; a single first transistor is located within a single sub-pixel region; the first electrode is located on the side of the second conductive layer near the second electrode; the gate electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, one of the first electrode and the second electrode is electrically connected to the second electrode of the first transistor; and the other of the first electrode and the second electrode is electrically connected to the common power line.

[0010] In an exemplary embodiment, the display substrate further includes a first conductive layer located on the side of the second conductive layer near the first substrate, and a first insulating layer located between the first conductive layer and the second conductive layer; the gate electrode of the first transistor and the gate line are located on the first conductive layer; the data line, the first electrode of the first transistor, the second electrode of the first transistor, and the common power line are located on the second conductive layer.

[0011] In an exemplary embodiment, the display substrate further includes a second insulating layer, a first organic layer, a first electrode, and a third insulating layer disposed sequentially along a direction away from the second conductive layer, wherein the second electrode is located on the side of the third insulating layer away from the first substrate; the first via penetrates the third insulating layer, the first organic layer, and the second insulating layer to expose the second electrode of the first transistor or the common power line.

[0012] In an exemplary embodiment, the depth of the first via is greater than or equal to 1.3 micrometers and less than or equal to 4.2 micrometers in a direction perpendicular to the display device.

[0013] In an exemplary embodiment, the first via exposes the surface of the common power line; the second electrode is connected to the second conductive layer through the first via, including: the second electrode is connected to the common power line through the first via.

[0014] In an exemplary embodiment, the first via exposes the surface of the second electrode of the first transistor; the second electrode is connected to the second conductive layer through the first via, including: the second electrode is connected to the second electrode of the first transistor through the first via.

[0015] In an exemplary embodiment, the material of the filling layer includes photoresist, or the material of the filling layer is the same as the material of the support pillar, or the material of the filling layer is the same as the material of the first organic layer.

[0016] On the other hand, this disclosure provides a method for fabricating a display device, comprising: sequentially forming a second conductive layer, a second electrode, a filling layer, and a first alignment layer on a first substrate to form a display substrate; wherein the second electrode is connected to the second conductive layer through a first via; the filling layer is located within at least one of the first vias between the second electrode and the first alignment layer, and the filling layer is configured to make the surface of the first alignment layer facing the opposite substrate flat; forming the opposite substrate, wherein a second alignment layer is disposed on the side of the opposite substrate facing the display substrate; at least one of the display substrate and the opposite substrate is provided with a support pillar; aligning the display substrate and the opposite substrate, and forming a liquid crystal layer between the display substrate and the opposite substrate; wherein, in a direction perpendicular to the display device, the orthographic projection of the support pillar and the first via does not overlap.

[0017] In an exemplary embodiment, forming the second electrode and the filling layer on the first substrate includes: forming a second transparent conductive layer on the first substrate; coating a side of the second transparent conductive layer away from the first substrate with photoresist or the material of the support pillar, wherein the photoresist or the material of the support pillar fills the first via; using a mask to form the second electrode from the second transparent conductive layer; and retaining the photoresist or the material of the support pillar filled in the first via to form the filling layer.

[0018] In an exemplary embodiment, before forming the second electrode, the method further includes: sequentially forming a second insulating layer, a first organic layer, a first electrode, and a third insulating layer on the second conductive layer; forming a first via in a direction perpendicular to the first substrate; and exposing the surface of the second conductive layer after the first via penetrates the third insulating layer, the first organic layer, and the second insulating layer.

[0019] In an exemplary embodiment, forming the filling layer on the first substrate includes: forming the second electrode on the first substrate, and then forming the filling layer on the second electrode; the material of the filling layer includes at least one of photoresist, the material of the support pillar, and the material of the first organic layer.

[0020] The display device provided in this embodiment provides a filling layer in at least one first via of the display substrate. The filling layer provides support to the first alignment layer, making the surface of the first alignment layer facing the opposite substrate flat. This eliminates the step difference of the first alignment layer at the corresponding first via, reduces the probability of the first alignment layer being scratched after being subjected to force, and thus reduces the probability of the display device experiencing Zara defects.

[0021] Other features and advantages of this disclosure will be set forth in the following description, or may be learned by practicing this disclosure. Other advantages of this disclosure may be realized and obtained by means of the solutions described in the specification and accompanying drawings. Attached Figure Description

[0022] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0023] Figure 1 This is a schematic cross-sectional view of a display device;

[0024] Figure 2 This is a schematic diagram of the planar structure of a display substrate in an exemplary embodiment;

[0025] Figure 3 In an exemplary embodiment Figure 2 A cross-sectional view of the display substrate along the CC direction;

[0026] Figure 4 To adopt Figure 3 The scan image shows a liquid crystal display device on the display substrate where a Zara defect occurs at the first via.

[0027] Figure 5 A scan image showing damage to the first alignment layer near the support column location;

[0028] Figure 6 In yet another exemplary embodiment Figure 2 A cross-sectional view of the display substrate along the CC direction;

[0029] Figure 7 In an exemplary embodiment Figure 6 A top view of the minimum distance between the outline edge of the support column that contacts the display substrate and the outline edge of the first via.

[0030] Figure 8 In yet another exemplary embodiment Figure 2 A cross-sectional view of the display substrate along the CC direction;

[0031] Figure 9 This is a cross-sectional view of a display device in an exemplary embodiment;

[0032] Figure 10 This is a cross-sectional view of the display device in yet another exemplary embodiment;

[0033] Figure 11 This is a schematic diagram of the orthographic projection of the opposite side surfaces of the first sub-support column and the second sub-support column onto the display device in an exemplary embodiment. Detailed Implementation

[0034] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0035] In the accompanying drawings, the size, thickness, or area of ​​one or more components is sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings. The scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of channels, the thickness and spacing of film layers, and the width and spacing of signal lines can be adjusted according to actual needs.

[0036] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0037] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0038] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Electrical connection" includes situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the term "component having some electrical function," as long as it allows for the transmission of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0039] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain) and the source electrode (source terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0040] In this specification, to distinguish the two terminals of a transistor other than the gate, one electrode is referred to as the first terminal and the other as the second terminal. For example, the first terminal can be the drain electrode and the second terminal can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0041] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0042] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfered corners, curved edges, and other variations.

[0043] In this specification, “about” means a value that is not strictly limited and is within the allowable range of process and measurement errors.

[0044] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main part of A extends along direction B".

[0045] In this specification, "A and B are set in the same layer" means that A and B are formed simultaneously through the same patterning process during the fabrication of the display substrate.

[0046] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0047] LCDs are generally made by aligning two substrates and filling the space between them with a liquid crystal layer. An electric field drives the liquid crystal molecules to twist, allowing light to selectively pass through and displaying images of different grayscale levels. The electric field driving the twisting of the liquid crystal molecules is formed through pixel electrodes and a common electrode. Polyimide (PI) films are coated on the surfaces of the two substrates facing the liquid crystal layer, and an alignment layer is formed through a tribological process to induce the molecules to align as required.

[0048] Figure 1This is a schematic cross-sectional view of a display device. Figure 1 As shown, the display device may include a display substrate 100 and a counter-side substrate 200 disposed opposite to each other, and a liquid crystal layer 300 disposed between the display substrate 100 and the counter-side substrate 200. The display substrate 100 may be referred to as an array substrate, and the counter-side substrate 200 may be referred to as a color filter substrate. The display substrate 100 may include a first structural layer 102 disposed on the side of the first substrate 101 facing the counter-side substrate 200, and a first alignment layer 103 located on the side of the first structural layer 102 facing the counter-side substrate 200. Pixel electrodes and common electrodes may be located on the first structural layer 102. The counter-side substrate 200 may include a color filter layer 202 disposed on the side of the second substrate 201 facing the display substrate 100, a support pillar 204 located on the side of the color filter layer 202 facing the first substrate 100, and a second alignment layer 205 located on the side of the support pillar 204 facing the first substrate 100. The color filter layer 202 may include a black matrix 20 and filter units of different colors. These filter units may include, for example, a red filter unit 21, a green filter unit 22, and a blue filter unit 23; this disclosure is not limiting in this regard. A support pillar 204 is disposed between the display substrate 100 and the opposite substrate 200, providing support and maintaining a suitable distance between them. A second planarization layer 203 may be disposed between the support pillar 204 and the color filter layer 202 to make the surface of the support pillar 204 near the second planarization layer 203 flat, ensuring the support performance of the support pillar 204.

[0049] In some examples, the display device also includes a cover plate (not shown), which may be located on the side of the opposite substrate 200 away from the display substrate 100, allowing the user to perform touch operations on the display device from the cover plate side. Before the display device leaves the factory, a click test is required to detect whether display abnormalities will occur under a large number of clicks. During the click test, it was found that the alignment layer of the display device is easily damaged, leading to Zara defects in the display device.

[0050] In other embodiments, the cover plate may be disposed on the side of the display substrate 100 away from the opposite substrate 200, and this disclosure does not limit this.

[0051] LCDs can be categorized by display mode into Twisted Nematic (TN) display mode, In-Plane Switching (IPS) display mode, Fringe Field Switching (FFS) display mode, and Advanced Super Dimension Switching (ADS) display mode. For the ADS display mode, in an exemplary embodiment, the first structural layer 102 may include a common voltage line, a gate line, a data line, a first transistor, a first electrode, and a second electrode. One of the first electrode and the second electrode can be a pixel electrode, and the other can be the common electrode. The common electrode is connected to the common voltage line to receive a common voltage signal from the common voltage line. The first electrode and the second electrode are used to generate an electric field that controls the deflection of liquid crystal molecules in the liquid crystal layer, thereby achieving the display of specific grayscale levels. The first transistor can be electrically connected to the pixel electrode, the data line, and the gate line respectively. The scan signal transmitted through the gate line can control the on / off state of the first transistor. When the first transistor is turned on, the pixel voltage transmitted on the data line can be output to the pixel electrode to achieve image display.

[0052] Figure 2 This is a schematic diagram of the planar structure of a display substrate in an exemplary embodiment, illustrating the connection relationship between some signal lines and sub-pixels (Pxij). Figure 2 As shown, in an exemplary embodiment, the display substrate 100 may include a display area AA and a non-display area, with the non-display area disposed on at least one side of the display area AA. In an exemplary embodiment, the non-display area may surround the display area AA. The non-display area may include a circuit area, which may include a first circuit area BB1 and a second circuit area BB2. The first circuit area BB1 may be located on one side of the display area AA along the second direction Y, and the second circuit area BB2 may be located on the opposite side of the display area AA along the second direction Y. The display area AA may include at least one first trace extending along the second direction Y and at least one second trace extending along the first direction X. The first trace may be, for example, a gate line, and the second trace may be, for example, a data line. The second direction Y may intersect the first direction X, for example, they may be perpendicular to each other. A first scan driver may be disposed in the first circuit area BB1, and a second scan driver may be disposed in the second circuit area BB2. The first and second scan drivers may provide scan signals to the gate lines in the display area AA. The data driver may provide data signals to the data lines in the display area AA.

[0053] In an exemplary embodiment, such as Figure 2As shown, multiple gate lines (S1 to Sm) and multiple data lines (D1 to Dn) can intersect to define multiple sub-pixel regions. Each sub-pixel region contains one sub-pixel, which includes a first electrode, a second electrode, and a driving circuit connected to the first electrode. The driving circuit may include at least one first transistor. Taking an oxide thin-film transistor as an example, the drain electrode of the oxide thin-film transistor can be electrically connected to the pixel electrode, the source electrode can be electrically connected to the data line, and the gate electrode can be electrically connected to the gate line. The scan signal transmitted through the gate line controls the first transistor to turn on, thereby illuminating the corresponding sub-pixel on the display substrate. The multiple sub-pixels within the display area AA can be arranged in an array, including multiple sub-pixel columns arranged along the first direction X and multiple sub-pixel rows arranged along the second direction Y.

[0054] In an exemplary embodiment, such as Figure 2 As shown, timing signal lines, common voltage lines, high-voltage power lines, and low-voltage power lines (not shown) can be provided on the side of the first scan driver away from the display area AA and the side of the second scan driver away from the display area AA. The first scan driver and the second scan driver can control the sub-pixels of the display area AA to display according to the timing signals from the timing signal lines. The high-voltage power lines can provide high-voltage signals, and the low-voltage power lines can provide low-voltage signals to enable the display device to display normally.

[0055] Figure 3 In an exemplary embodiment Figure 2 A cross-sectional view of the display substrate along the CC direction. Figure 3 The dashed lines in the diagram illustrate the support pillar 204 and part of the second alignment layer 205 disposed on the opposite substrate, showing the positions where the support pillar 204 and the second alignment layer 205 contact the display substrate. Figure 3 As shown, the display substrate may include a first substrate 101, a common voltage line 35 disposed on the first substrate 101, a first transistor, a gate line S, a data line D, a first electrode 51, a second electrode 61, and a first alignment layer 103. Along a direction away from the first substrate 101, the display substrate may include a first conductive layer, a first insulating layer 11, a semiconductor layer, a second conductive layer, a second insulating layer 12, a first organic layer 41, a first transparent conductive layer, a third insulating layer 13, a second transparent conductive layer, and the first alignment layer 103. The first insulating layer 11, the second insulating layer 12, and the third insulating layer 13 are inorganic insulating layers. The first insulating layer 11 may be referred to as a gate insulating (GI) layer, and the second insulating layer 12 and the third insulating layer 13 may be referred to as passivation layers (PVX). In an exemplary embodiment, the first conductive layer and the second conductive layer may be made of conductive materials such as metals, and the first transparent conductive layer and the second transparent conductive layer may be made of transparent conductive materials.

[0056] In an exemplary embodiment, such as Figure 3 As shown, the first conductive layer includes at least: a gate electrode 31 and a gate line S of the first transistor. The semiconductor layer includes at least: an active layer 32 of the first transistor. The active layer 32 may include: a channel region, a first doped region, and a second doped region. The channel region may be undoped and has semiconductor characteristics. The first doped region and the second doped region may be on opposite sides of the channel region and are doped with impurities, thus having conductivity. The impurities may vary depending on the type of transistor (e.g., N-type or P-type). The gate electrode 31 of the first transistor and the corresponding gate line S may be configured as an integral structure, and the portion of the gate line S and the active layer 32 overlapping in the direction perpendicular to the first substrate 101 may be used as the gate electrode 31 of the first transistor. The second conductive layer includes at least: a first electrode 33, a second electrode 34, a data line D, and a common voltage line 35 of the first transistor. The first transparent conductive layer includes at least: a first electrode 51. The first electrode 33 of the first transistor overlaps with and is directly connected to the first doped region of the active layer 32, and the second electrode 34 overlaps with and is directly connected to the second doped region of the active layer 32. The first electrode 33 of the first transistor and the adjacent data line D can be an integral structure. The first electrode 33 can be, for example, a source electrode. The orthographic projection of the second electrode 34 of the first transistor on the first substrate 101 overlaps with the first electrode 51. The second electrode 34 of the first transistor and the first electrode 51 are interconnected (not shown). The second electrode 34 can be, for example, a drain electrode. For example, the first electrode 51 can be a sheet electrode, or the first electrode 51 can have multiple slits. The extension direction of the multiple slits can intersect with the first direction X. The first electrode 51 can have slits in two different directions, thereby forming a dual-domain structure. However, this embodiment is not limited to this. For example, the first electrode 51 can form a single-domain or multi-domain structure. The second transparent conductive layer includes at least a plurality of second electrodes 61. The second electrodes 61 can be sheet electrodes, or the second electrodes 61 can form a single-domain or multi-domain structure. The orthographic projections of the second electrodes 61 and the first electrode 51 on the first substrate 101 can overlap each other. The second electrodes 61 of different sub-pixels can be interconnected. The second electrode 61 and the first electrode 51 are located within the sub-pixel region defined by the intersection of the data line 43 and the gate line 21. A first via T1 can expose the surface of the common voltage line 35, and the second electrode 61 can be connected to the common voltage line 35 through the first via T1 to receive the common voltage signal. A first alignment layer 103 can be located on the side of the second electrode 61 away from the first substrate 101 and cover the first substrate 101.

[0057] Figure 4 To adopt Figure 3 The scan image shows a liquid crystal display device on a display substrate that has a Zara defect at the first via. Figure 5 This is a scan image showing damage to the first alignment layer near the support column location. (Example:) Figure 4As shown, in dark conditions, tiny light spots Z appear on the screen, negatively impacting the display effect and user experience. Figure 5 As shown, the dashed circle indicates the contact position between the support post 204 and the display substrate. The inventors of this application have discovered through research that during click testing, the support post 204 is prone to damaging the alignment layer. The first alignment layer 103 located near the support post 204 is prone to scratches L under stress. Figure 3 As shown, the first alignment layer 103 has a large step at the first via T1, making it more susceptible to deformation under external forces. Furthermore, with the increasing demand for thinner and lighter display devices, the cover plate is becoming thinner, resulting in poorer protection. During operation, the force transmitted from the support column 204 to the first alignment layer 103 is greater, making it more prone to scratches at the first via T1. Figure 4 The shape of the Zara shown is defective.

[0058] This disclosure provides a display device, including: a display substrate and a counter-side substrate disposed opposite to each other, and a liquid crystal layer disposed between the display substrate and the counter-side substrate; at least one of the display substrate and the counter-side substrate is provided with a support pillar; wherein, the display substrate includes a first substrate and a second conductive layer, a second electrode, and a first alignment layer disposed sequentially along a direction away from the first substrate, the second electrode being connected to the second conductive layer through a first via; in a direction perpendicular to the display device, the orthographic projection of the support pillar does not overlap with the orthographic projection of the first via; a second alignment layer is disposed on the side of the counter-side substrate facing the display substrate; the display substrate further includes a filling layer, the filling layer being located within at least one first via between the second electrode and the first alignment layer, the filling layer being configured to make the surface of the first alignment layer facing the counter-side substrate flat.

[0059] The display device provided in this disclosure provides a filling layer within at least one first via of the display substrate. This filling layer supports the first alignment layer, making the surface of the first alignment layer flat towards the opposite substrate. This eliminates the step difference in the first alignment layer at the corresponding first via, reducing the probability of scratches on the first alignment layer under stress, and thus lowering the probability of Zara defects in the display device. In an exemplary embodiment, within the plane of the display substrate, the minimum distance between the contour edge of the support post contacting the display substrate and the contour edge of the first via is greater than or equal to 9 micrometers.

[0060] In an exemplary embodiment, in a direction perpendicular to the display device, there is a first distance between the surface of the first alignment layer facing the opposite substrate and the surface of the fill layer facing the opposite substrate; around the first via, there is a second distance between the surface of the first alignment layer facing the opposite substrate and the surface of the second electrode facing the opposite substrate. "The fill layer is configured to make the surface of the first alignment layer facing the opposite substrate flat" means that the difference between the first distance and the second distance is less than or equal to 10%, for example, the difference between the first distance and the second distance can be less than or equal to 5%, making the step size of the first alignment layer around the first via smaller. The difference between the first distance and the second distance can be set as needed, and this disclosure does not limit this.

[0061] In an exemplary embodiment, the filling layer may be provided only in the first through hole around the support column, which can effectively prevent the display device from malfunctioning. Alternatively, the filling layer may be provided in all the first through holes in the display device. This disclosure does not limit this.

[0062] In an exemplary embodiment, the material of the filling layer includes photoresist, or the material of the filling layer is the same as the material of the support pillar, or the material of the filling layer is the same as the material of the first organic layer, and this disclosure does not limit this.

[0063] In an exemplary embodiment, at least one of the display substrate and the opposite substrate is provided with a support post, including: the support post is disposed on the opposite substrate, and the support post is in contact with the display substrate through the second alignment layer.

[0064] In an exemplary embodiment, at least one of the display substrate and the opposite substrate is provided with a support pillar, including: the support pillar includes a first sub-support pillar and a second sub-support pillar arranged in pairs, the first sub-support pillar being located on the display substrate and the second sub-support pillar being located on the opposite substrate; in a direction perpendicular to the display device, the orthographic projections of the opposite side surfaces of the first sub-support pillar and the second sub-support pillar at least partially overlap.

[0065] In an exemplary embodiment, the opposite substrate further includes a color filter layer located on the side of the support pillar near the second substrate, or the color filter layer is located on the side of the second sub-support pillar near the second substrate.

[0066] Figure 6 In yet another exemplary embodiment Figure 2 A cross-sectional view of the display substrate along the CC direction. Figure 6 and Figure 3 The difference lies in the inclusion of a filling layer 71 within the first via T1; the remaining structure can be referenced above. Figure 3The description will not be repeated here.

[0067] like Figure 6 As shown, after the first via T1 penetrates the third insulating layer 13, the first organic layer 41, and the second insulating layer 12, it exposes the surface of the common power line 35. The second electrode 61 is connected to the common power line 35 through the first via T1. The filling layer 71 is located on the side of the second electrode 61 away from the first substrate 101, and the orthographic projection of the filling layer 71 on the first substrate 101 is within the range of the first via T1. The surface of the filling layer 71 away from the first substrate 101 is approximately flush with the surface of the second electrode 61 away from the first substrate 101, making the surface of the first alignment layer 103 near the first via T1 flat. In the direction perpendicular to the first substrate 101, the depth H of the first via T1 can be greater than or equal to 1.3 micrometers and less than or equal to 4.2 micrometers. For example, the depth H of the first via T1 can be greater than or equal to 1.5 micrometers and less than or equal to 4 micrometers. The depth H of the first via T1 can be the second conductive layer exposed by the first via T1 ( Figure 6 The distance between the surface of the second power line 35 and the surface of the third conductive layer 13 on the side away from the first substrate 101 is not limited in this disclosure.

[0068] like Figure 6 As shown, in a direction perpendicular to the display device, there is a first distance a1 between the surface of the first alignment layer 103 facing the opposite substrate and the surface of the filling layer 71 facing the opposite substrate; around the first via T1, there is a second distance a2 between the surface of the first alignment layer 103 facing the opposite substrate and the surface of the second electrode 61 facing the opposite substrate. The difference between the first distance a1 and the second distance a2 may be less than or equal to 10%, and this disclosure does not limit this.

[0069] Figure 7 In an exemplary embodiment Figure 6 A top view showing the minimum distance between the outline edge of the support pillar contacting the display substrate and the outline edge of the first via, omitting the rest of the structure. In an exemplary embodiment, combined with Figure 6 and Figure 7 As shown, in a plane parallel to the first substrate 101, the minimum distance R between the contour edge of the support post 204 contacting the display substrate and the contour edge of the first via T1 can be greater than or equal to 9 micrometers, for example, R can be greater than or equal to 10 micrometers, and this disclosure does not impose any limitation thereon. Since the support post 204 contacts the first alignment layer 103 of the display substrate through the second alignment layer 205, the contour shape of the second alignment layer 205 contacting the display substrate is related to the shape of the side of the support post 204 away from the second substrate 201. Figure 7The illustration uses a circular shape as an example, representing the outline shape of the cross-section of the support pillar 204 away from the second substrate 201, the outline shape of the second alignment layer 205 in contact with the display substrate, and the shape of the first via T1. The outline shape of the cross-section of the support pillar 204 away from the second substrate 201 and the shape of the first via T1 can be set as needed; this disclosure does not impose any limitations on these aspects. By setting the minimum distance R between the outline edge of the support pillar 204 in contact with the display substrate and the outline edge of the first via T1 to be greater than or equal to 9 micrometers, a certain distance can be maintained between the support pillar 204 and the first via T1. At this distance, even if the support pillar 204 scratches the first alignment layer 103, because the distance between the first via T1 and the support pillar 204 is relatively far, the scratches on the first alignment layer 103 will not affect the first via T1, thus preventing Zara defects in the display device.

[0070] In an exemplary implementation, such as Figure 6 As shown, the outline edge of the first via T1 can be the outline edge of the first via T1 located in the first organic layer 41, and this disclosure does not limit this.

[0071] Table 1 presents statistics compiled by the inventors of this application, showing whether the display device exhibits Zara defects near the first via under multiple sets of comparative experiments with different values ​​for the support column size, the first via size, and the minimum distance R. The support column size refers to the dimension of the end of the support column 204 furthest from the second substrate, and the first via size refers to the dimension of the first via T1 located in the first organic layer 41. The units for dimensions and distances in Table 1 are micrometers. Values ​​in "a*b" format indicate a rectangular shape with dimensions a and b for adjacent sides, while values ​​in single-digit format indicate a circular shape for the first via T1.

[0072] Table 1

[0073]

[0074]

[0075] As can be seen from the data of experiments 1, 5, and 6 in Table 1, by setting the minimum distance R to be greater than or equal to 10 micrometers, the display device will not exhibit Zara defects regardless of whether the dimensions of the support pillar and the first via are both small and similar (No. 1), whether the dimensions of the support pillar and the first via are both large (No. 5), or whether the dimensions of the support pillar are larger than the dimensions of the first via (No. 6). In contrast, as can be seen from the data of experiment 3 in Table 1, even when the dimensions of the support pillar and the first via are both small and similar, setting the minimum distance R to less than 9 micrometers will result in Zara defects in the display device. Furthermore, when the minimum distance R is less than 9 micrometers, Zara defects will occur regardless of whether the dimensions of the support pillar and the first via are larger than the dimensions of the first via (No. 2) or smaller than the dimensions of the support pillar and the first via (No. 4). Therefore, regardless of the settings of the support pillar and the first via dimensions, as long as the minimum distance R is greater than or equal to 9 micrometers, it is possible to effectively prevent the scratches on the first alignment layer 103 caused by the support pillar 204 from spreading to the first via T1, thereby preventing Zara defects in the display device.

[0076] In an exemplary embodiment, the material of the filling layer 71 may include photoresist. During the formation of the display substrate, a second electrode 61 with a predetermined morphology needs to be formed in the second transparent conductive layer using processes such as photolithography and etching. The first via T1 can be filled with photoresist, and this portion of photoresist located within the first via T1 can be retained in subsequent processing, thereby enabling the filling layer 71 and the second electrode 61 to be formed simultaneously. In this way, the filling layer 71 can be formed without increasing the number of process steps, which helps to reduce costs and lower process complexity while ensuring the display effect of the display device.

[0077] In an exemplary embodiment, the material of the filler layer 71 can be the same as the material of the support pillar 204, or the material of the filler layer 204 can be the same as the material of the first organic layer 41. For example, the filler layer 71 can be formed in the first via T1 using the material of the support pillar 204 after the second electrode 61 is formed, without increasing the material cost during the manufacturing process. In other embodiments, the material of the filler layer 71 can be other materials, and this disclosure does not limit this.

[0078] Figure 8 In yet another exemplary embodiment Figure 2 A cross-sectional view of the display substrate along the CC direction. Figure 8 and Figure 6 The difference lies in that the first via T1 exposes the surface of the second electrode 34 of the first transistor, and the second electrode 61 is connected to the second electrode 34 of the first transistor through the first via T1. The common voltage line 35 is omitted from the diagram. The remaining structure can be referenced to the above description. Figure 6The description will not be repeated here.

[0079] In an exemplary embodiment, the second electrode 61 can be a pixel electrode, and the first electrode 51 can be a common electrode, which can be connected to the common voltage line 35. Figure 8 As shown, the first via T1 exposes the surface of the second electrode 34. The second electrode 61 is connected to the second electrode 34 of the first transistor through the first via T1. The filling layer 71 is located on the side of the second electrode 61 away from the first substrate 101, and the orthographic projection of the filling layer 71 on the first substrate 101 is within the range of the first via T1. The surface of the filling layer 71 away from the first substrate 101 is approximately flush with the surface of the second electrode 61 on the side away from the first substrate 101, making the surface of the first alignment layer 103 flat near the first via T1.

[0080] Figure 9 This is a cross-sectional view of a display device in an exemplary embodiment. Figure 9 The display substrate in the middle can be referred to as Figure 6 The description of the opposite substrate can be referenced. Figure 1 The description will not be repeated here; the difference lies in... Figure 9 The display device also includes a sealant 301 and a cover plate 501. When assembling the display substrate 100 and the opposite substrate 200, the sealant 301 can be applied around the display area and circuit area to seal the display substrate 100 and the opposite substrate 200, preventing liquid crystal leakage. The cover plate 501 can be disposed on the side of the second substrate 201 away from the display substrate 100; this disclosure is not limiting in this regard. In other embodiments, other methods may be used, such as... Figure 8 The display substrate with the structure shown forms a display device, which will not be described in detail here.

[0081] In an exemplary embodiment, the support post 204 may be provided only on the opposite substrate 200. In the direction perpendicular to the display device, the height L of the support post 204 may be greater than or equal to 2.3 micrometers and less than or equal to 4.2 micrometers. For example, the height L of the support post 204 may be greater than or equal to 2.5 micrometers and less than or equal to 4 micrometers. This disclosure does not limit this.

[0082] Figure 10 This is a cross-sectional view of a display device in yet another exemplary embodiment. Figure 10 and Figure 9 The difference lies in the fact that the support columns include a pair of first sub-support columns 91 and second sub-support columns 92, while the rest of the structure is the same. Figure 9 The same applies here, so I will not repeat it further.

[0083] like Figure 10As shown, the first sub-support pillar 91 is located on the display substrate 100. The first sub-support pillar 91 can be located between the second electrode 61 and the first alignment layer 103. The orthographic projection of the first sub-support pillar 91 on the first substrate 101 and the orthographic projection of the second electrode 61 on the first substrate 101 at least partially overlap. The second sub-support pillar 92 is located on the opposite substrate 200. The second sub-support pillar 92 can be located between the second alignment layer 205 and the color filter layer 202. In the direction perpendicular to the display device, the orthographic projections of the first sub-support pillar 91 and the second sub-support pillar 92 at least partially overlap. The first sub-support pillar 91 and the second sub-support pillar 92 are in contact with each other through the alignment layer, and together they provide support between the display substrate 100 and the opposite substrate 200. In this embodiment, by providing a first sub-support post 91 and a second sub-support post 92 in pairs on the display substrate 100 and the opposite substrate 200, the contact surfaces of the first sub-support post 91 and the second sub-support post 92 are further away from the first via T1. This ensures that even if relative displacement occurs between the first sub-support post 91 and the second sub-support post 92, causing scratches on the alignment layer, the scratches can be confined to the contact surfaces of the first sub-support post 91 and the second sub-support post 92, and are less likely to spread to the vicinity of the first via T1. This helps to avoid Zara defects in the display device.

[0084] In an exemplary implementation, such as Figure 10 As shown, in the direction perpendicular to the display device, the first sub-support column 91 may have a first height L1, and the second sub-support column 92 may have a second height L2. The sum of the first height L1 and the second height L2 may be greater than or equal to 2.3 micrometers and less than or equal to 4.2 micrometers. For example, the sum of the first height L1 and the second height L2 may be greater than or equal to 2.5 micrometers and less than or equal to 4 micrometers. The size of the first height L1 and the second height L2 may be set as needed, and this disclosure does not limit this.

[0085] Figure 11 This is a schematic diagram of the orthographic projection of the opposing side surfaces of the first and second sub-support columns onto the display device in an exemplary embodiment; other structures are omitted. Figure 11 As shown, the opposite side surfaces of the first sub-support column 91 and the second sub-support column 92 can be circular. The area of ​​the first sub-support column 91 facing the second sub-support column 92 can be larger than the area of ​​the second sub-support column 92 facing the first sub-support column 91. The orthographic projection of the second sub-support column 92 on the display device can be located at the orthographic projection of the first sub-support column 91 on the display device. By setting the opposite side surfaces of the first sub-support column 91 and the second sub-support column 92 to be different, the alignment accuracy of the display substrate 100 and the opposite substrate 200 during cell alignment can be reduced, making it easier to align the first sub-support column 91 and the second sub-support column 92.

[0086] In an exemplary embodiment, the opposite side surfaces of the first sub-support column 91 and the second sub-support column 92 can be other shapes, such as triangles, ellipses, rectangles, other shapes of quadrilaterals and polygons, irregular shapes, etc. The opposite side surfaces of the first sub-support column 91 and the second sub-support column 92 can intersect each other to form different mating forms, and this disclosure does not limit them.

[0087] The technical solution of this embodiment is further explained below through the fabrication process of the display device of this exemplary embodiment. The "patterning process" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more methods selected from sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more methods selected from spraying and spin coating; and etching can be performed using any one or more methods selected from dry etching and wet etching. A "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0088] The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process. "Same layer" does not always mean that the layer thickness or layer height is the same in the cross-sectional view.

[0089] To form Figure 9 Taking the display device shown as an example, the manufacturing method of this disclosure embodiment may include:

[0090] (1) Preparation of display substrate.

[0091] A first substrate 101 is provided, and a first conductive thin film is deposited on the first substrate 101. The first conductive thin film is patterned using a patterning process to form a first conductive layer pattern. The first conductive layer pattern includes at least the gate electrode 31 and the gate line S of the first transistor. The gate electrode 31 and the gate line S of the first transistor can be interconnected.

[0092] In some examples, the first substrate 101 can be a transparent substrate, such as a quartz substrate, a glass substrate, or an organic resin substrate. However, this embodiment is not limited to this. The first conductive film can be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti.

[0093] Subsequently, a first insulating film and a semiconductor film are sequentially deposited on the first substrate 101 on which the aforementioned pattern is formed. The semiconductor film is patterned by a patterning process to form a first insulating layer 11 and a semiconductor layer pattern. The first insulating layer 11 can cover the first substrate 101, and the semiconductor layer pattern includes at least the active layer 32 of the first transistor.

[0094] In some examples, the first insulating film can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or a composite layer. The semiconductor thin film can be one or more of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, etc., meaning this disclosure applies to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0095] Subsequently, a second conductive film is deposited on the first substrate 101 on which the aforementioned pattern is formed. The second conductive film is patterned using a patterning process to form a second conductive layer pattern. The second conductive layer pattern includes at least the first electrode 33, the second electrode 34 of the first transistor, the data line D, and the common voltage line 35. The material of the second conductive film can be referred to the description of the first conductive film, and will not be repeated here. The first electrode 33 of the first transistor and the adjacent data line D can be an integral structure. The first electrode 33 and the second electrode 34 of the first transistor are directly connected to the two ends of the active layer 32, respectively.

[0096] Subsequently, a second insulating film is deposited on the first substrate 101 where the aforementioned pattern is formed, and an organic material is coated on it to form a second insulating layer 12 and a first organic layer 41 covering the first substrate 101. A first transparent conductive film is then deposited, and a patterning process is used to pattern the first transparent conductive film to form a first transparent conductive layer pattern. The first transparent conductive layer pattern includes at least a plurality of first electrodes 51. The first electrodes 51 can be pixel electrodes.

[0097] In some examples, the material of the second insulating film can refer to the foregoing description of the first insulating film, and will not be repeated here. The material of the first transparent conductive film can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0098] Subsequently, a third insulating film is deposited on the first substrate 101 that forms the aforementioned pattern to form a third insulating layer 13 covering the first substrate 101. A first via T1 is opened on the surface of the third insulating layer 13. The third insulating layer 13, the first organic layer 41 and the second insulating layer 12 inside the first via T1 are removed to expose the surface of the common voltage line 35.

[0099] In some examples, the material of the third insulating film can be referred to the foregoing description of the first insulating film, and will not be repeated here.

[0100] Subsequently, a second transparent conductive film is deposited on the first substrate 101 where the aforementioned pattern is formed. Photoresist is then coated onto the second transparent conductive film, filling the first via T1. The second transparent conductive film is patterned using a patterning process, retaining the photoresist filling the first via T1, thus forming a second transparent conductive layer pattern and a filling layer pattern. The second transparent conductive layer pattern includes at least a plurality of second electrodes 61, which can be common electrodes. The second electrodes 61 can be connected to a common voltage line 35 through corresponding first via T1. The filling layer pattern includes at least a plurality of filling layers 71. The surface of the filling layer 71 away from the first substrate 101 is flush with the surface of the plurality of second electrodes 61 away from the first substrate 101, so that the surface of the subsequently formed first alignment layer near the first via T1 is flat. In other embodiments, the material of the support pillars 204 can be coated onto the second transparent conductive film, which can not only form a filling layer but also act as photoresist.

[0101] In some examples, the material of the second transparent conductive film can be referred to the foregoing description of the first transparent conductive film, and will not be repeated here.

[0102] Subsequently, a transparent first alignment film is coated on the first substrate 101 forming the aforementioned pattern, the first alignment film is cured, and the cured first alignment film is aligned using alignment technology to obtain a transparent first alignment layer 103.

[0103] In some examples, the alignment techniques may include rubbing alignment and ultraviolet light alignment. These techniques can form trenches on the surface of the first alignment layer 103 to align the liquid crystal molecules, causing them to align in a specific direction. The material of the first alignment film can be polyimide, polyamide, polyethylene, polystyrene, or polyvinyl alcohol. However, this embodiment is not limited to this.

[0104] (2) Prepare the opposite side substrate.

[0105] A second substrate 201 is provided, on which a black pigment is coated or a black chromium (Cr) film is deposited. The black pigment or black chromium film is patterned by a patterning process to form a black matrix 20 pattern. Then, filter units of different colors are sequentially formed in the sub-pixel areas defined by the black matrix 20.

[0106] In some examples, such as Figure 9 As shown, the filter units of different colors may include periodically arranged red filter units 21, green filter units 22, and blue filter units 23. Taking the formation of red filter unit 21 as an example, red resin can be coated on the second substrate 201 on which the black matrix 20 has been formed. After baking and curing, red color film unit 21 is formed by masking, exposure, and development. The formation process of green color film unit and blue color film unit is similar and will not be described in detail here.

[0107] Subsequently, an organic material is coated onto the second substrate 201 on which the aforementioned pattern is formed to form a second planar layer 203 covering the second substrate 201.

[0108] Subsequently, a spacer film is deposited on the second substrate 201 where the aforementioned pattern is formed, and a patterning process is used to pattern the spacer film to form a plurality of support pillars 204. Suitable materials can be selected to form the support pillars 204 as needed; this embodiment does not impose any limitations on this. In other embodiments, the support pillars 204 can be formed directly on the color filter layer 202; this embodiment does not impose any limitations on this either.

[0109] Subsequently, a transparent second alignment film is coated on the second substrate 201 forming the aforementioned pattern, the second alignment film is cured, and the cured second alignment film is aligned using alignment technology to obtain a transparent second alignment layer 205. The material and preparation method of the second alignment layer 205 can be referred to the aforementioned description of the first alignment layer 103, and will not be repeated here.

[0110] (3) The display substrate and the opposite substrate are assembled and liquid crystal material is injected.

[0111] In an exemplary embodiment, a sealing adhesive 301 is applied to the surrounding display area and circuit area of ​​the display substrate. Then, the display substrate and the opposite substrate are assembled, with the first alignment layer 103 of the display substrate facing the second alignment layer 205 of the opposite substrate. Support pillars 204 are used to maintain the distance between the display substrate and the opposite substrate. After liquid crystal material is injected and the cover plate 501 is attached, a structure is formed as shown... Figure 9 The display device shown.

[0112] In the exemplary embodiment, the fabrication process of display devices with other structures can be referred to the example above. Figure 9 The manufacturing process of the display device shown is described in detail here.

[0113] This disclosure provides a method for fabricating a display device, comprising: sequentially forming a second conductive layer, a second electrode, a filling layer, and a first alignment layer on a first substrate to form a display substrate; wherein the second electrode is connected to the second conductive layer through a first via; the filling layer is located within at least one of the first vias between the second electrode and the first alignment layer, and the filling layer is configured to make the surface of the first alignment layer facing the opposite substrate flat; forming the opposite substrate, wherein a second alignment layer is disposed on the side of the opposite substrate facing the display substrate; at least one of the display substrate and the opposite substrate is provided with a support pillar; aligning the display substrate and the opposite substrate, and forming a liquid crystal layer between the display substrate and the opposite substrate; wherein, in a direction perpendicular to the display device, the orthographic projection of the support pillar and the first via does not overlap.

[0114] In an exemplary embodiment, forming the second electrode and the filling layer on the first substrate includes: forming a second transparent conductive layer on the first substrate; coating a side of the second transparent conductive layer away from the first substrate with photoresist or the material of the support pillar, wherein the photoresist or the material of the support pillar fills the first via; using a mask to form the second electrode from the second transparent conductive layer; and retaining the photoresist or the material of the support pillar filled in the first via to form the filling layer.

[0115] In an exemplary embodiment, before forming the second electrode, the method further includes: sequentially forming a second insulating layer, a first organic layer, a first electrode, and a third insulating layer on the second conductive layer; forming a first via in a direction perpendicular to the first substrate; and exposing the surface of the second conductive layer after the first via penetrates the third insulating layer, the first organic layer, and the second insulating layer.

[0116] In an exemplary embodiment, forming the filling layer on the first substrate includes: forming the second electrode on the first substrate, and then forming the filling layer on the second electrode; the material of the filling layer includes at least one of photoresist, the material of the support pillar, and the material of the first organic layer.

[0117] Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A display device, characterized in that, include: A display substrate and a counter substrate are disposed opposite each other, and a liquid crystal layer is disposed between the display substrate and the counter substrate; at least one of the display substrate and the counter substrate is provided with a support pillar; The display substrate includes a first substrate and a second conductive layer, a second electrode, and a first alignment layer sequentially disposed along a direction away from the first substrate. The second electrode is connected to the second conductive layer through a first via. In a direction perpendicular to the display device, the orthographic projection of the support column does not overlap with the orthographic projection of the first via. A second alignment layer is provided on the side of the opposite substrate facing the display substrate; The display substrate further includes a filling layer located within at least one first via between the second electrode and the first alignment layer, the filling layer being configured to make the surface of the first alignment layer flat toward the opposite substrate.

2. The display device according to claim 1, characterized in that, Within the plane of the display substrate, the minimum distance between the contour edge of the support post that contacts the display substrate and the contour edge of the first via is greater than or equal to 9 micrometers.

3. The display device according to claim 1, characterized in that, At least one of the display substrate and the opposite substrate is provided with a support pillar, including: The support pillar is disposed on the opposite substrate, and the support pillar is in contact with the display substrate through the second alignment layer.

4. The display device according to claim 1, characterized in that, At least one of the display substrate and the opposite substrate is provided with a support pillar, including: The support column includes a first sub-support column and a second sub-support column arranged in pairs. The first sub-support column is located on the display substrate, and the second sub-support column is located on the opposite side substrate. In a direction perpendicular to the display device, the orthographic projections of the opposite side surfaces of the first sub-support column and the second sub-support column at least partially overlap.

5. The display device according to claim 1, characterized in that, The display substrate further includes a first electrode, a plurality of first transistors, a plurality of common power lines, a plurality of gate lines, and a plurality of data lines, wherein the plurality of gate lines and the plurality of data lines intersect to define a plurality of sub-pixel regions; a single first transistor is located within a single sub-pixel region; the first electrode is located on the side of the second conductive layer near the second electrode; The gate electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, one of the first electrode and the second electrode is electrically connected to the second electrode of the first transistor, and the other of the first electrode and the second electrode is electrically connected to the common power line.

6. The display device according to claim 5, characterized in that, The display substrate further includes a first conductive layer located on the side of the second conductive layer near the first substrate, and a first insulating layer located between the first conductive layer and the second conductive layer; the gate electrode of the first transistor and the gate line are located in the first conductive layer; The data line, the first electrode of the first transistor, the second electrode of the first transistor, and the common power line are located in the second conductive layer.

7. The display device according to claim 6, characterized in that, The display substrate further includes a second insulating layer, a first organic layer, a first electrode, and a third insulating layer disposed sequentially along a direction away from the second conductive layer. The second electrode is located on the side of the third insulating layer away from the first substrate. After the first via penetrates the third insulating layer, the first organic layer, and the second insulating layer, it exposes the second electrode of the first transistor or the common power line.

8. The display device according to claim 7, characterized in that, In a direction perpendicular to the display device, the depth of the first via is greater than or equal to 1.3 micrometers and less than or equal to 4.2 micrometers.

9. The display device according to claim 6, characterized in that, The first via exposes the surface of the common power line; the second electrode is connected to the second conductive layer through the first via, including: The second electrode is connected to the common power line through the first via.

10. The display device according to claim 6, characterized in that, The first via exposes the surface of the second electrode of the first transistor; The second electrode is connected to the second conductive layer through the first via, including: The second electrode is connected to the second terminal of the first transistor through the first via.

11. The display device according to claim 7, characterized in that, The filling layer is made of photoresist, or the filling layer is made of the same material as the support pillar, or the filling layer is made of the same material as the first organic layer.

12. A method for manufacturing a display device, characterized in that, include: A display substrate is formed by sequentially forming a second conductive layer, a second electrode, a fill layer, and a first alignment layer on a first substrate; wherein the second electrode is connected to the second conductive layer through a first via; the fill layer is located in at least one of the first vias between the second electrode and the first alignment layer, and the fill layer is configured to make the surface of the first alignment layer flat toward the opposite side of the substrate; The opposite substrate is formed, and a second alignment layer is disposed on the side of the opposite substrate facing the display substrate; at least one of the display substrate and the opposite substrate is provided with a support pillar; The display substrate and the opposite substrate are assembled together, and a liquid crystal layer is formed between the display substrate and the opposite substrate; wherein, in a direction perpendicular to the display device, the support post does not overlap with the orthographic projection of the first via.

13. The preparation method according to claim 12, characterized in that, Forming the second electrode and the filling layer on the first substrate includes: A second transparent conductive layer is formed on the first substrate, and photoresist or the material of the support pillar is coated on the side of the second transparent conductive layer away from the first substrate, wherein the photoresist or the material of the support pillar fills the first via. The second electrode is formed by using a mask to create the second transparent conductive layer; the photoresist or the material of the support pillar filled in the first via is retained to form the filling layer.

14. The preparation method according to claim 12, characterized in that, Before forming the second electrode, the method further includes: A second insulating layer, a first organic layer, a first electrode, and a third insulating layer are sequentially formed on the second conductive layer; The first via is formed in a direction perpendicular to the first substrate; the first via penetrates the third insulating layer, the first organic layer and the second insulating layer, and exposes the surface of the second conductive layer.

15. The preparation method according to claim 14, characterized in that, Forming the filling layer on the first substrate includes: After forming the second electrode on the first substrate, the filling layer is formed on the second electrode; the material of the filling layer includes at least one of photoresist, the material of the support pillar, and the material of the first organic layer.

Images