Data processing method and device, equipment, storage medium and computer program product

Abstract

The invention provides a data processing method and device, equipment, a storage medium and a computer program product. The method comprises the steps that under the condition that a first processor does not receive a dog feeding signal in a dog feeding period, first data are read from a first memory, and the first data comprise operation field data when a first computer program is operated; the dog feeding signal is sent under the condition that the first computer program runs normally; the first processor sends the first data to an upper computer and / or stores the first data to a second memory; wherein the first memory is a volatile memory; the second memory is a nonvolatile memory; the first processor controls the first computer program to run again after completing reading of the first data.

Description

Technical Field

[0001] This application relates to the field of embedded systems, including but not limited to data processing methods and apparatus, devices, storage media, and computer program products. Background Technology

[0002] For handling abnormal interrupts, the system captures the interrupt and then quickly records the CPU register values ​​to the local machine for subsequent analysis.

[0003] For handling software infinite loop exceptions, the usual approach is to use a watchdog timer, which restores the system by resetting it after a failure to feed the watchdog timer. Summary of the Invention

[0004] The data processing methods, apparatus, devices, storage media, and computer program products provided in this application.

[0005] In a first aspect, embodiments of this application provide a data processing method, comprising: a first processor reading first data from a first memory when no dog-feeding signal is received during a dog-feeding cycle; the first data including runtime data of a first computer program being run; wherein the dog-feeding signal is sent when the first computer program is running normally; the first processor sending the first data to a host computer and / or storing it in a second memory; wherein the first memory is a volatile memory; the second memory is a non-volatile memory; and after completing the reading of the first data, the first processor controlling the first computer program to restart.

[0006] It is understood that in this embodiment of the application, if the first processor does not receive a dog feeding signal during the dog feeding cycle, the first processor reads the running environment data generated when running the first computer program in the first memory; after completing the reading of the running environment data, it controls the first computer program to run again.

[0007] Thus, on the one hand, the first processor reads the runtime context data generated when the first computer program is running in the first memory, rather than reading the register values ​​of the processor running the first computer program. Since the runtime context data includes register values ​​and other information, that is, it contains more information than register values, it is helpful in locating the cause of abnormal interruption in the scenario where the first computer program is abnormally interrupted during operation. On the other hand, the first processor controls the first computer program to restart only after completing the reading of the runtime context data. This can avoid the destruction / modification / overwriting of the previous runtime context data caused by restarting the first computer program before or during the acquisition of the runtime context data. This ensures that the first processor can obtain complete runtime context data from the first memory, which is helpful in locating the cause of abnormal operation of the first computer program, such as the cause of interruption or infinite loop.

[0008] In some embodiments, the dog-feeding signal comes from a second processor, and the first data includes runtime data of the second processor running a first computer program in a first memory.

[0009] It is understood that, in this embodiment, since the dog-feed signal comes from the second processor, and the first data includes runtime data of the second processor running the first computer program in the first memory, if the first processor does not receive a dog-feed signal from the second processor during the dog-feeding cycle, the first processor reads the runtime data generated by the second processor running the first computer program in the first memory; after completing the reading of the runtime data, the first processor controls the second processor to reset.

[0010] Thus, on the one hand, the first processor reads the runtime context data generated when the second processor runs the first computer program in the first memory, rather than reading the register values ​​in the second processor. Since the runtime context data includes register values ​​and other information, meaning it contains more information than register values, it is helpful in locating the cause of the abnormal interruption in scenarios where the first computer program is abnormally interrupted during operation. On the other hand, the first processor sends a reset signal to the second processor only after completing the reading of the runtime context data. This avoids damage / modification / overwriting of the previous runtime context data caused by re-running the first computer program before or during the acquisition of the data. This ensures that the first processor can obtain complete runtime context data from the first memory, which is helpful in locating the cause of the abnormal operation of the first computer program, such as the cause of an interruption or infinite loop.

[0011] In some embodiments, the first processor reads first data from the first memory, including: the first processor disconnects a first path between the second processor and the first memory, and connects a second path between the first processor and the first memory; the first processor reads the first data from the first memory through the second path.

[0012] It is understood that in this embodiment, the first processor reads the first data through the second path by disconnecting the first path between the second processor and the first memory, and connecting the second path between the first processor and the first memory. This prevents the possibility of modification of the runtime data, making the runtime data read by the first processor more accurate and complete, thereby improving the efficiency of locating anomalies.

[0013] In some embodiments, runtime data includes a first computer program, data generated by running the first computer program, register values ​​of the processor running the first computer program, and / or exception types.

[0014] It is understood that, in the embodiments of this application, the runtime data includes a first computer program, data generated by running the first computer program, register values ​​of the processor running the first computer program, and / or exception types. This facilitates the reproduction of the runtime environment based on the first computer program, the data generated by running the first computer program, register values ​​of the processor running the first computer program, or exception types, thereby aiding in locating the cause of the exception.

[0015] In some embodiments, the first computer program includes functions; the data generated by running the first computer program includes stack data; and the first processor determines the cause of the abnormality in the operation of the first computer program based on the functions, the stack data, and the register values ​​of the processor running the first computer program.

[0016] It is understood that, in this embodiment of the application, the cause of the first computer program's execution exception is determined based on the function, stack data, and register values ​​of the processor running the first computer program; that is, the specific code location causing the first computer program's execution exception is located. Thus, effectively locating the cause of the first computer program's execution exception helps reduce the maintenance cost of the first computer program and improves exception handling efficiency.

[0017] In some embodiments, the method further includes: the exception type is an interrupt, and the register values ​​of the processor running the first computer program and the exception type are written to the first memory when the processor running the first computer program determines that the execution of the first computer program has been interrupted.

[0018] It is understood that, in this embodiment, the processor running the first computer program sends a dog-feed signal to the first processor when no exception occurs; when an abnormal interrupt occurs, the processor running the first computer program stores information indicating that the exception type of the first computer program is an interrupt and the value of the register of the processor running the first computer program in the first memory. This is beneficial for the first processor to monitor the operating status of the processor running the first computer program and to locate the cause of the exception when an exception occurs in the processor running the first computer program.

[0019] In some embodiments, the method further includes: after the first processor completes reading the first data, connecting the first path between the second processor and the first memory, and disconnecting the second path between the first processor and the first memory.

[0020] It is understood that, in this embodiment of the application, after the first processor completes reading the first data, it switches its access permission to the first memory back to the second processor. This allows the second processor to read and run the first computer program stored in the first memory.

[0021] In some embodiments, after the first processor completes reading the first data, it controls the first computer program to run again, including: after the first processor completes reading the first data and sends the first data to the host computer and / or stores it in the second memory, it controls the first computer program to run again.

[0022] It is understood that in this embodiment, after the first processor completes reading the first data and sending the first data to the host computer and / or storing it in the second memory, the first computer program is controlled to run again. This improves the efficiency of sending or storing the first data, thereby increasing the efficiency of determining the cause of the anomaly. Furthermore, compared to the first processor sending the first data to the host computer and / or storing it in the second memory while simultaneously controlling the first computer program to run again, it reduces the performance overhead of the first processor.

[0023] In other embodiments, after the first processor completes reading the first data, it controls the first computer program to run again, including: after the first processor completes reading the first data and before sending the first data to the host computer and / or storing it in the second memory, the first processor controls the first computer program to run again.

[0024] It is understood that, in this embodiment of the application, the first computer program is restarted before the first processor completes reading the first data and sending the first data to the host computer and / or storing it in the second memory. This is beneficial for application scenarios with high real-time requirements.

[0025] In some other embodiments, after the first processor completes reading the first data, it controls the first computer program to run again, including: after the first processor completes reading the first data and during the process of sending the first data to the host computer and / or storing it in the second memory, it controls the first computer program to run again.

[0026] It is understood that, in this embodiment of the application, during the process of the first processor completing the reading of the first data and sending the first data to the host computer and / or storing it in the second memory, the first computer program is controlled to restart. This is beneficial in meeting the requirements of application scenarios with high real-time requirements while improving the efficiency of sending or storing the first data, thereby improving the efficiency of determining the cause of the anomaly.

[0027] Secondly, embodiments of this application provide a data processing apparatus, comprising: a reading module configured to read first data from a first memory when a first processor does not receive a dog-feeding signal during a dog-feeding cycle, the first data including runtime data of a first computer program being run; wherein the dog-feeding signal is sent when the first computer program is running normally; a first sending module configured to send the first data to a host computer and / or store it in a second memory; wherein the first memory is a volatile memory; the second memory is a non-volatile memory; and a second sending module configured to control the first computer program to restart after the first processor has completed reading the first data.

[0028] Thirdly, embodiments of this application provide an electronic device, including a first processor and a first memory, characterized in that the first memory stores a first computer program, and the first processor implements the method of the first aspect when executing a second computer program.

[0029] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method of the first aspect.

[0030] Fifthly, embodiments of this application provide a computer program product, including a computer program or instructions, which, when executed by a processor, implement the method of the first aspect.

[0031] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0033] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0034] Figure 1 A schematic diagram illustrating the implementation flow of the embedded system crash location method provided in this application embodiment;

[0035] Figure 2 This is a schematic diagram of the structure of an embedded system crash location device provided in an embodiment of this application;

[0036] Figure 3 A schematic diagram of the implementation flow of a data processing method provided in this application embodiment. Figure 1 ;

[0037] Figure 4 This is a schematic diagram of a data processing structure provided in an embodiment of this application;

[0038] Figure 5 A schematic diagram of the implementation flow of a data processing method provided in this application embodiment. Figure 2 ;

[0039] Figure 6 A schematic diagram of the implementation flow of a data processing method provided in this application embodiment. Figure 3 ;

[0040] Figure 7 This application provides a schematic diagram of the structure of an embedded system according to an embodiment of the present application.

[0041] Figure 8 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application;

[0042] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0043] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] In the following description, references to “some embodiments” or “other embodiments” describe a subset of all possible embodiments. However, it is understood that “some embodiments” or “other embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0046] In the following description, the terms "first" and "second" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first" and "second" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0048] In a related technology, a method and apparatus for locating crashes in embedded systems are proposed. Figure 1 This is a schematic diagram illustrating the implementation flow of the embedded system crash location method provided in the embodiments of this application, as shown below. Figure 1 As shown, the method includes the following steps 101 to 102:

[0049] Step 101: When a trigger signal for a target exception is detected, the target exception handling function is called. The target exception handling function is used to obtain the function stack pointer array of the current thread, query the compact function name string array corresponding to the function stack pointer array, convert each compact function name string in the compact function name string array into the corresponding standard function name string, and output each standard function name string to the crash log file.

[0050] Step 102: Output the crash log file and stop the embedded system.

[0051] Figure 2 This is a schematic diagram of the structure of an embedded system crash location device provided in an embodiment of this application, as shown below. Figure 2As shown, the embedded system crash location device 20 includes an exception handling unit 201, a crash handling unit 202, a registration unit 203, and an association unit 204; wherein the crash handling unit includes a restoration unit 2011 and a program stop unit 2012. The exception response unit 201 is used to call the target exception handling function when a trigger signal of a target exception is detected. The crash handling unit 202 is used to output a crash log file and stop the operation of the embedded system. The registration unit 203 is used to register the target exception handling function. The association unit 204 is used to associate at least one target exception with the target exception handling function. The restoration unit 2011 is used to restore the trigger function of the target exception to the default exception handling function. The program stop unit 2012 is used to re-invoke the trigger signal and call the default exception handling function to stop the operation of the embedded system.

[0052] According to this technical solution, the compact function name string of an embedded system can be converted into a pre-defined standard function name string through the target exception handling function. This allows the name of the function causing the bug and its call path to be directly seen in the crash log file, improving the efficiency of crash localization. This method is suitable for crash localization in embedded systems but cannot be applied to recording the runtime environment under abnormal conditions in embedded systems.

[0053] For embedded systems, software often encounters exceptions during operation, such as abnormal interruptions, entering infinite loops, or memory overflows.

[0054] In another related technology, an interrupt is captured by the system, and then the CPU register values ​​are quickly recorded locally in the central processing unit (CPU) for subsequent analysis.

[0055] The limitation of using exception capture record registers for defect localization in handling abnormal interrupts is the limited information recorded. Typically, only information from CPU general-purpose registers R0-R15, the stack register, jump register, status register, and the program counter (PC) pointer can be recorded. This information is too low-level, and the recording process itself can modify it, making it difficult to pinpoint the problem in many cases. Furthermore, exceptions like infinite loops do not generate interrupts, so this method cannot handle infinite loop exceptions.

[0056] In another related technology, the common practice for handling software infinite loops is to use a watchdog timer to restore the system by resetting it after a failure to feed the watchdog.

[0057] However, restoring the system using a watchdog timer is a passive process. During the process from the watchdog failure to the reset, the system cannot record the abnormal situation, and therefore cannot locate the cause of the abnormality.

[0058] Therefore, the above method has the following drawbacks:

[0059] (1) The recorded information is limited, and the information in the registers may not necessarily help software engineers locate the problem.

[0060] It is understood that, in the embodiments of this application, the operation of the program, from the perspective of microcomputer principle, is to complete pipeline instructions by operating the CPU registers. However, this is an abstract process, that is, the information in the registers is very low-level, so it is difficult to locate the cause of the abnormality through the information in the registers.

[0061] (2) Using the watchdog timer to restore the system cannot record the abnormal situation, so it is impossible to locate the cause of the abnormality.

[0062] Based on the above analysis, this application provides a data processing method. Figure 3 A schematic diagram of the implementation flow of a data processing method provided in this application embodiment. Figure 1 ,like Figure 3 As shown, the method may include steps 301 to 303.

[0063] Step 301: If the first processor does not receive a dog-feeding signal during the dog-feeding cycle, it reads first data from the first memory. The first data includes runtime data of the first computer program being run. The dog-feeding signal is sent when the first computer program is running normally.

[0064] Step 302: The first processor sends the first data to the host computer and / or stores it in the second memory; wherein the first memory is volatile memory; and the second memory is non-volatile memory.

[0065] Step 303: After completing the reading of the first data, the first processor controls the first computer program to run again.

[0066] It is understood that in this embodiment of the application, if the first processor does not receive a dog feeding signal during the dog feeding cycle, the first processor reads the running environment data generated when running the first computer program in the first memory; after completing the reading of the running environment data, it controls the first computer program to run again.

[0067] Thus, on the one hand, the first processor reads the runtime context data generated when the first computer program is running in the first memory, rather than reading the register values ​​of the processor running the first computer program. Since the runtime context data includes register values ​​and other information, that is, it contains more information than register values, it is helpful in locating the cause of abnormal interruption in the scenario where the first computer program is abnormally interrupted during operation. On the other hand, the first processor controls the first computer program to restart only after completing the reading of the runtime context data. This can avoid the destruction / modification / overwriting of the previous runtime context data caused by restarting the first computer program before or during the acquisition of the runtime context data. This ensures that the first processor can obtain complete runtime context data from the first memory, which is helpful in locating the cause of abnormal operation of the first computer program, such as the cause of interruption or infinite loop.

[0068] It is understood that in this embodiment of the application, the reception of the dog-feeding signal is not only used to trigger the control of the first computer program to restart, but also to trigger the acquisition of the running status data of the first computer program from the first memory. Since the running first computer program is stored in the first memory, and the running status data of the first computer program is also acquired from the first memory when the dog-feeding signal is not received, it is helpful to quickly locate the cause of the abnormal operation of the first computer program.

[0069] The following sections will describe further optional implementation methods for each of the above steps, as well as related terms.

[0070] In step 301, if the first processor does not receive a dog-feeding signal during the dog-feeding cycle, it reads first data from the first memory. The first data includes runtime data of the first computer program being run. The dog-feeding signal is sent when the first computer program is running normally.

[0071] It should be understood that the source of the dog-feeding signal received by the first processor is not limited in the embodiments of this application. In some embodiments, the dog-feeding signal comes from the first processor, and the first data includes runtime data of the first processor running a first computer program in the first memory. In other embodiments, the dog-feeding signal comes from a second processor, and the first data includes runtime data of the second processor running a first computer program in the first memory.

[0072] It is understood that, in this embodiment, since the dog-feed signal comes from the second processor, and the first data includes runtime data of the second processor running the first computer program in the first memory, if the first processor does not receive a dog-feed signal from the second processor during the dog-feeding cycle, the first processor reads the runtime data generated by the second processor running the first computer program in the first memory; after completing the reading of the runtime data, the first processor controls the second processor to reset.

[0073] Thus, on the one hand, the first processor reads the runtime context data generated when the second processor runs the first computer program in the first memory, rather than reading the register values ​​in the second processor. Since the runtime context data includes register values ​​and other information, meaning it contains more information than register values, it is helpful in locating the cause of the abnormal interruption in scenarios where the first computer program is abnormally interrupted during operation. On the other hand, the first processor sends a reset signal to the second processor only after completing the reading of the runtime context data. This avoids damage / modification / overwriting of the previous runtime context data caused by re-running the first computer program before or during the acquisition of the data. This ensures that the first processor can obtain complete runtime context data from the first memory, which is helpful in locating the cause of the abnormal operation of the first computer program, such as the cause of an interruption or infinite loop.

[0074] It should be understood that, in the embodiments of this application, the first processor and the second processor are not limited. The second processor is used to run the first computer program stored in the first memory; the first processor is used to monitor the operating status of the second processor.

[0075] In some embodiments, the first processor is a microcontroller unit (MCU) and the second processor is a CPU.

[0076] It is understood that in the embodiments of this application, the first processor is an MCU and the second processor is a CPU. Compared with the first processor and the second processor being a CPU or a System on Chip (SOC), this is beneficial to saving hardware costs.

[0077] It should be understood that the device on which the first processor, the second processor, and the first memory reside are not limited in the embodiments of this application. In some embodiments, the first processor is on a first device; the second processor and the first memory are on a second device. In other embodiments, the first processor, the second processor, and the first memory are on different printed circuit boards of the same device. In still other embodiments, the first processor, the second processor, and the first memory are on the same printed circuit board of the same device.

[0078] Exemplarily, as one possible implementation, Figure 4 This is a schematic diagram of a data processing structure provided in an embodiment of this application, such as... Figure 4 As shown, the second processor 401 sends a dog-feed signal to the first processor 402. If the first processor 402 does not receive a dog-feed signal from the second processor 401 during the dog-feeding cycle, the first processor 402 switches access to the first memory 403 to the first processor 402 via a switching signal. The access path between the second processor 401 and the first memory 403 is 1, and the access path between the first processor 402 and the first memory 403 is 2. The first processor 402 reads the data stored in the first memory 403 through path 2. The first processor 402 sends the read data stored in the first memory 403 to the host computer and / or stores it in the second memory 404. After completing the reading of the data stored in the first memory 403, the first processor 402 sends a reset signal to the second processor 401.

[0079] Regarding the aforementioned "watchdog signal," it can be understood that in this embodiment, the watchdog signal refers to a signal sent to the watchdog timer (WDT) in the embedded system. The watchdog timer is a mechanism used to monitor the running status of a program. It waits for a watchdog signal from the program during the watchdog cycle interval to confirm that the program is still running normally. When the program is running normally, it sends a watchdog signal to the watchdog timer during the watchdog cycle interval. This signal can be written to a specific register, sent as a pulse signal, or perform other predetermined operations. If the program fails to send the watchdog signal on time for some reason (such as a software error, hardware failure, or infinite loop), the watchdog timer will consider that the program may have encountered an error.

[0080] It should be understood that in the embodiments of this application, the first processor is used to implement the function of a watchdog timer. The first processor will wait for a watchdog signal from the first computer program during the watchdog feeding cycle interval to confirm that the first computer program is running normally. If the first processor does not receive a watchdog signal during the watchdog feeding cycle, it is considered that the operation of the first computer program has malfunctioned.

[0081] Regarding the situation where "the first processor does not receive a watchdog signal from the second processor within the watchdog cycle," it should be understood that the specific value of the watchdog cycle is not limited in this embodiment. Furthermore, in some embodiments, the watchdog cycle should be set according to the specific requirements and performance of the embedded system to ensure that the embedded system does not suffer increased burden due to excessively short watchdog cycle intervals, nor does it fail to respond promptly to abnormal situations due to excessively long watchdog cycle intervals.

[0082] Regarding the "running context data when the second processor runs the first computer program in the first memory," it should be noted that, in this embodiment, running context data refers to additional data such as processor memory information generated during processor operation. This data is used for diagnosing and resolving embedded system problems.

[0083] In some embodiments, runtime data includes a first computer program, data generated by running the first computer program, register values ​​of the processor running the first computer program, and / or exception types.

[0084] It is understood that, in the embodiments of this application, the runtime data includes a first computer program, data generated by running the first computer program, register values ​​of the processor running the first computer program, and / or exception types. This facilitates the reproduction of the runtime environment based on the first computer program, the data generated by running the first computer program, register values ​​of the processor running the first computer program, or exception types, thereby aiding in locating the cause of the exception.

[0085] It should be understood that, in the embodiments of this application, the first computer program includes: instruction sequence, data structure, algorithm, variables, constants, library files, functions, and other information. The data generated by running the first computer program includes: stack information (i.e., stack data), heap information, register information, global variable information, static variable information, file descriptors, socket information, environment variables, performance metrics, and other information.

[0086] In some embodiments, the runtime context data further includes the contents of the program counter of the processor running the first computer program. Additionally, if the processor running the first computer program needs to interact with external devices, the runtime context data of the processor running the first computer program also includes status information related to these devices, such as the status of input / output ports, communication protocols, etc. The runtime context data also includes the addresses of interrupt service routines, etc.

[0087] It should be understood that, in the embodiments of this application, a register is a high-speed storage unit inside the processor, used to temporarily store information such as instructions, data, and addresses. As the program runs, the processor running the first computer program reads instructions and data from memory and stores them in registers for processing. Therefore, the value of the register changes continuously according to the program's instructions and data. During data processing, the register temporarily stores information such as operands, intermediate results, and final results. These values ​​are continuously updated as the operation progresses.

[0088] In some embodiments, the first computer program includes functions; the data generated by running the first computer program includes stack data; and the first processor determines the cause of the abnormality in the operation of the first computer program based on the functions, the stack data, and the register values ​​of the processor running the first computer program.

[0089] It is understood that, in this embodiment of the application, the cause of the first computer program's execution exception is determined based on the function, stack data, and register values ​​of the processor running the first computer program; that is, the specific code location causing the first computer program's execution exception is located. Thus, effectively locating the cause of the first computer program's execution exception helps reduce the maintenance cost of the first computer program and improves exception handling efficiency.

[0090] It should be understood that, in the embodiments of this application, determining the cause of the abnormal operation of the first computer program refers to locating which line of code the first computer program reached where the abnormality occurred, rather than determining the type of abnormality, i.e., determining whether the first computer program's operation was interrupted or whether the first computer program entered an infinite loop. For example, in some embodiments, if the first computer program enters an infinite loop, and if, based on functions, stack data, and the register values ​​of the processor running the first computer program, it is determined that the infinite loop occurred at line 158 of the first computer program, then line 158 of the first computer program is the determined cause of the abnormal operation of the first computer program.

[0091] In this application embodiment, the specific implementation method for determining the cause of an abnormality in the execution of the first computer program based on functions, stack data, and register values ​​of the processor running the first computer program is not limited. In some embodiments, the cause of the abnormality in the execution of the first computer program is determined by analyzing and comparing functions, stack data, and register values ​​of the processor running the first computer program.

[0092] In some embodiments, the first processor reads first data from the first memory, including: the first processor disconnects a first path between the second processor and the first memory, and connects a second path between the first processor and the first memory; the first processor reads the first data from the first memory through the second path.

[0093] It is understood that in this embodiment, the first processor reads the first data through the second path by disconnecting the first path between the second processor and the first memory and connecting the second path between the first processor and the first memory. This prevents the possibility of modification of the runtime data, making the runtime data read by the first processor more accurate and complete, thereby improving the efficiency of locating anomalies.

[0094] It should be understood that, in the embodiments of this application, the specific implementation methods for the first processor to disconnect the first path between the second processor and the first memory, and to connect the second path between the first processor and the first memory, are not limited. For example, in some embodiments, the first processor can disconnect the first path or connect the second path by pulling down or pulling up input / output (IO) pins; or, the first processor can disconnect the first path or connect the second path by software code.

[0095] In some embodiments, the exception type is an interrupt, and the register values ​​and exception type of the processor running the first computer program are written to the first memory when the processor running the first computer program determines that the execution of the first computer program has been interrupted.

[0096] It is understood that, in this embodiment, the processor running the first computer program sends a dog-feed signal to the first processor when no exception occurs; when an abnormal interrupt occurs, the processor running the first computer program stores information indicating that the exception type of the first computer program is an interrupt and the value of the register of the processor running the first computer program in the first memory. This is beneficial for the first processor to monitor the operating status of the processor running the first computer program and to locate the cause of the exception when an exception occurs in the processor running the first computer program.

[0097] It should be understood that in the embodiments of this application, when the processor running the first computer program is the first processor, the processor monitoring the running status of the first processor is the first processor itself. That is, different threads of the first processor monitor the running status of the first processor and the running of the first computer program respectively.

[0098] When the processor running the first computer program is the second processor, the register values ​​and exception types of the second processor are written to the first memory when the second processor determines that the execution of the first computer program has been interrupted. Therefore, the first processor monitors the operating status of the second processor; that is, the first processor monitors the operating status of the second processor, and the second processor runs the first computer program.

[0099] It should be understood that, in the embodiments of this application, "reset timer" refers to the operation of restoring the timer to its initial or starting state. This operation is typically used to clear the current timing value of the timer and reset it to a state where a new round of timing can begin.

[0100] In this application, the specific implementation method for the second processor to determine that the execution of the first computer program has been interrupted is not limited. Exemplarily, in some embodiments, the second processor determines that the execution of the first computer program has been interrupted upon capturing an interrupt signal.

[0101] Exemplary, in some embodiments, Figure 5 A schematic diagram of the implementation flow of a data processing method provided in this application embodiment. Figure 2 ,like Figure 5 As shown, the method includes the following steps 501 to 505.

[0102] Step 501: The second processor starts the dog-feeding thread or timer;

[0103] Step 502: The second processor determines whether it is time to feed the dog; if so, proceed to step 503; otherwise, proceed to step 504.

[0104] Step 503: The second processor operates the IO pin to send a dog feed signal;

[0105] Step 504: The second processor determines whether an abnormal interrupt has occurred; if yes, proceed to step 505; otherwise, proceed to step 502.

[0106] Step 505: The second processor writes the exception type and register value into RAM.

[0107] In some embodiments, the CPU program periodically sends a watchdog signal during execution, which is achieved by pulling the I / O pin high or low. If an exception interrupt occurs, the interrupt signal is captured, and the exception type and the current value of the CPU register are recorded in a designated area of ​​RAM.

[0108] In some embodiments, the method further includes: after the first processor completes reading the first data, connecting the first path between the second processor and the first memory, and disconnecting the second path between the first processor and the first memory.

[0109] It is understood that, in this embodiment of the application, after the first processor completes reading the first data, it switches its access permission to the first memory back to the second processor. This allows the second processor to read and run the first computer program stored in the first memory.

[0110] It should be understood that, in the embodiments of this application, the specific implementation of the first processor connecting the first path between the second processor and the first memory, and disconnecting the second path between the first processor and the first memory, is not limited. For example, in some embodiments, the first processor can connect the first path or disconnect the second path by pulling down or raising input / output (IO) pins; or, the first processor can connect the first path or disconnect the second path through software code.

[0111] Exemplary, in some embodiments, Figure 6 A schematic diagram of the implementation flow of a data processing method provided in this application embodiment. Figure 3 ,like Figure 6 As shown, the method includes the following steps 601 to 609.

[0112] Step 601: The first processor listens for the dog-feeding signal.

[0113] Step 602: The first processor determines that no dog-feeding signal has been received within a certain period of time; if so, proceed to step 601; otherwise, proceed to step 603.

[0114] Specifically, in some embodiments, the MCU monitors the dog feed signal in real time and starts a timeout counter. If the dog feed signal is not received within a certain period of time, the CPU is determined to have entered an abnormal state (abnormal interruption or program dead loop).

[0115] Step 603: The first processor switches to MCU to access RAM.

[0116] Step 604: The first processor MCU reads the data from the RAM in batches.

[0117] Step 605: The first processor stores the data in RAM into NVM.

[0118] Specifically, in some embodiments, RAM access is switched to the MCU, which reads all the data in RAM in batches and stores it in the NVM as files.

[0119] Step 606: The first processor determines whether it is connected to the host computer; if so, proceed to step 607; otherwise, proceed to step 608.

[0120] Step 607: The first processor sends the RAM data to the host computer for backup and analysis.

[0121] It should be understood that in the embodiments of this application, if the MCU is connected to the host computer, it simultaneously sends the data from the RAM to the host computer for backup and analysis; if the RAM has a large space and a lot of data, the above storage and uploading actions are performed multiple times.

[0122] In some embodiments, abnormal data stored in NVM can also be sent up for analysis after a request is initiated by the host computer.

[0123] Step 608: The first processor switches to CPU accessing RAM.

[0124] Step 609: The first processor sends a reset signal to the CPU to reset it.

[0125] In some embodiments, after storing and uploading RAM data, the RAM access permissions are first switched to the CPU, and then the MCU resets the CPU.

[0126] In step 302, the first processor sends the first data to the host computer and / or stores it in the second memory; wherein the first memory is volatile memory and the second memory is non-volatile memory.

[0127] It should be understood that, in the embodiments of this application, the first memory and the second memory are not limited. The first memory only needs to ensure that the stored content is not lost when the power supply is continuous; the second memory only needs to be able to retain the stored content for a long time when there is no power supply.

[0128] In some embodiments, the first memory may be one of the following: Random Access Memory (RAM), Synchronous Dynamic Random Access Memory (SDRAM), or Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM).

[0129] In some embodiments, the second memory may be one of the following: read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory (FM); wherein FM includes: Nor flash memory (NorFlash) and NAND flash memory (NANDFlash).

[0130] In some embodiments, the first processor sending the first data to the host computer includes:

[0131] The first processor responds to a first request sent by the host computer; wherein the first request is used to request the acquisition of first data;

[0132] The first processor, based on the first request, sends the first data to the host computer; or,

[0133] The first processor establishes a third communication channel with the host computer;

[0134] The first processor sends the first data to the host computer through the third channel.

[0135] In step 303, after the first processor completes the reading of the first data, it controls the first computer program to run again.

[0136] It should be noted that, in this embodiment of the application, there is no limitation on the specific time when the first processor controls the first computer program to run again. The first processor only needs to control the first computer program to run again after completing the reading of the first data.

[0137] In some embodiments, after the first processor completes reading the first data, it controls the first computer program to run again, including: after the first processor completes reading the first data and sends the first data to the host computer and / or stores it in the second memory, it controls the first computer program to run again.

[0138] It is understood that in this embodiment, after the first processor completes reading the first data and sending the first data to the host computer and / or storing it in the second memory, the first computer program is controlled to run again. This improves the efficiency of sending or storing the first data, thereby increasing the efficiency of determining the cause of the anomaly. Furthermore, compared to the first processor sending the first data to the host computer and / or storing it in the second memory while simultaneously controlling the first computer program to run again, it reduces the performance overhead of the first processor.

[0139] In other embodiments, after the first processor completes reading the first data, it controls the first computer program to run again, including: after the first processor completes reading the first data and before sending the first data to the host computer and / or storing it in the second memory, the first processor controls the first computer program to run again.

[0140] It is understood that, in this embodiment of the application, the first computer program is restarted before the first processor completes reading the first data and sending the first data to the host computer and / or storing it in the second memory. This is beneficial for application scenarios with high real-time requirements.

[0141] In some other embodiments, after the first processor completes reading the first data, it controls the first computer program to run again, including: after the first processor completes reading the first data and during the process of sending the first data to the host computer and / or storing it in the second memory, it controls the first computer program to run again.

[0142] It is understood that, in this embodiment of the application, during the process of the first processor completing the reading of the first data and sending the first data to the host computer and / or storing it in the second memory, the first computer program is controlled to restart. This is beneficial in meeting the requirements of application scenarios with high real-time requirements while improving the efficiency of sending or storing the first data, thereby improving the efficiency of determining the cause of the anomaly.

[0143] It should be understood that, in the embodiments of this application, when the processor running the first computer program is the first processor, controlling the first computer program to run again means that the thread in the first processor that monitors the running status of the first processor sends a reset signal to the thread running the first computer program.

[0144] If the processor running the first computer program is the second processor, the first computer program is restarted, that is, the first processor sends a reset signal to the second processor.

[0145] It should be understood that, in this embodiment, the reset signal is a specific electrical signal used to trigger a reset operation of the second processor. When the second processor receives the reset signal, it stops all currently running operations, clears internal registers and status flags, and then restarts its startup program or initialization sequence. In abnormal situations such as system crashes, program crashes, or entering infinite loops, the reset signal can force the system to return to its initial state, thereby preventing the system from being stuck for extended periods or malfunctioning. By sending a reset signal in a timely manner, errors or abnormal states in the system can be detected and corrected, thereby improving the reliability and stability of the system.

[0146] In this embodiment, the reset signal is generated by a first processor, and the specific implementation of the first processor generating the reset signal is not limited. Specifically, in some embodiments, the first processor generates the reset signal through a resistor-capacitor (RC) circuit; or the first processor generates the reset signal through a reset chip.

[0147] Based on this, the following will describe an exemplary application of the embodiments of this application in a practical application scenario.

[0148] This application proposes a data processing method that records all information from memory (i.e., an example of a first memory) after a software exception occurs. All memory information preserves the runtime context, and parsing the memory information at the time of the error assists software engineers in locating the problem. This method monitors the running status of the embedded system software using an MCU and records runtime context data when an exception occurs (abnormal interruption or software infinite loop) to help pinpoint the cause of the exception.

[0149] Figure 7 This application provides a schematic diagram of the structure of an embedded system, as shown in the embodiment of the present application. Figure 7 As shown, the embedded system 70 includes a CPU 701 (an example of a second processor), a monitoring MCU 702 (an example of a first processor), logic control switches 703 and 704, RAM 705 (an example of a first memory), and NVM 706 (an example of a second memory).

[0150] The monitoring MCU 702 replaces the watchdog function and is connected to the CPU 701 and RAM 705. When an anomaly occurs, it records the operational data by reading the data from RAM 705.

[0151] Specifically, the running CPU 701 is connected to the monitoring MCU 702 via I / O pins and periodically sends a watchdog signal by pulling the pins high and low. The control pin of the monitoring MCU 702 is connected to the reset pin of the CPU 701 to reset the CPU 701 after an exception occurs. The running CPU 701 and the monitoring MCU 702 are both connected to RAM 705. Under normal circumstances, only the CPU 701 accesses RAM 705 for program execution; under abnormal circumstances, the monitoring MCU 702 operates RAM 705 to read data and record the context. The switching of RAM 705 access rights is implemented in hardware through added logic circuitry, controlled by the monitoring MCU 702. The monitoring MCU 702's own program runs in its internal RAM (an example of a third memory) and does not use the shared RAM 705.

[0152] It should be understood that, in this embodiment of the application, the monitoring MCU 702 is connected to the NVM 706 for recording data of RAM 705 in abnormal situations. Therefore, the capacity of the NVM 706 should be greater than the capacity of RAM 705 to ensure that all memory data can be stored.

[0153] The monitoring MCU 702 can be connected to the host computer via Ethernet. In case of an anomaly, the data read from RAM 705 (i.e., an example of the first data) can be sent to the host computer for backup and analysis via Transmission Control Protocol (TCP) or User Datagram Protocol (UDP) messages.

[0154] RAM 705 is a random access memory, an internal memory that directly exchanges data with the CPU 701. It can be read and written at any time (except during refresh) and is very fast, typically serving as temporary data storage for the operating system or other running programs. Specifically, in some embodiments, RAM 705 can be SDRAM or DDR SDRAM, etc.

[0155] The NVM 706 is a non-volatile memory, a type of computer memory that retains its data even after the power is turned off. It is typically used for data storage. Specifically, in some embodiments, the NVM 706 can be NorFlash or NANDFlash, etc.

[0156] The main functions of the monitoring MCU 702 include a fault monitoring module 7021, a memory data processing module 7022, a fault recording module 7023, a fault handling module 7024, and a recording and reporting module 7025.

[0157] The fault monitoring module 7021 periodically monitors whether it receives a dog-feeding signal from the CPU 701. If no dog-feeding signal is received within a certain period of time (configurable), the abnormal handling process is initiated.

[0158] The memory data processing module 7022 controls the access permissions of RAM 705 by sending control signals to logic control switches 703 and 704. Specifically, when the first processor is operating normally, RAM 705 is accessed by CPU 701; when the first processor malfunctions, RAM 705 is accessed by monitoring MCU 702. Thus, data from RAM 705 can be read by monitoring MCU 702 to preserve operational data.

[0159] The memory data processing module 7022 is also used to send a reset command to the fault handling module 7024 after completing the reading of data from RAM 705, and to switch CPU 701 to access RAM 705. The reset command instructs the fault handling module 7024 to send a reset signal to CPU 701.

[0160] The fault handling module 7024 is used to send a reset signal to the CPU 701 upon receiving a reset command. The reset signal instructs the CPU 701 to trigger a reset operation.

[0161] The fault recording module 7023 is used to save the data in RAM 705 in NVM 706 as a file after an anomaly occurs. At the same time, after receiving the instruction from the host computer to retrieve the fault record, it reads the running field data from NVM 706 and sends it to the record reporting module 7025.

[0162] The 7025 recording and reporting module uploads fault record data (i.e., an example of on-site operational data) to the host computer via Ethernet, so that the host computer can back up and analyze the received fault record data.

[0163] This application proposes a hardware connection method that uses a monitoring MCU 702 to capture operational anomalies in the embedded system. An anomaly handling mechanism is designed so that when an anomaly occurs, the monitoring MCU 702 retrieves data (i.e., operational context data) from the memory (an example of the first memory) and records the operational context of the CPU 701 by saving or uploading it. In this way, on the one hand, when an anomaly occurs in the embedded system, the monitoring MCU 702 can read more operational context data, thereby improving the efficiency of problem localization; on the other hand, for low-probability anomalies, recording the data in RAM 705 can effectively restore the context, thereby helping to solve the cause of the anomaly and reducing the time cost of reproduction.

[0164] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this application without departing from the spirit and scope of the technical solutions of this application, and all such modifications or substitutions should be covered within the protection scope of this application.

[0165] It should be noted that although the steps of the method in this application are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps; or steps from different embodiments may be combined into a new technical solution. Based on the foregoing embodiments, this application provides an apparatus comprising the included modules and the units included in each module, which can be implemented by a processor; of course, it can also be implemented by specific logic circuits; in implementation, the processor can be an AI acceleration engine (such as an NPU), a graphics processing unit (GPU), a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field-programmable gate array (FPGA), etc.

[0166] Figure 8 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application, as shown below. Figure 8 As shown, the data processing device 80 includes a reading module 801, a first sending module 802, and a second sending module 803, wherein:

[0167] The reading module 801 is configured to read first data from the first memory when the first processor does not receive a dog-feeding signal during the dog-feeding cycle. The first data includes runtime data of the first computer program being run. The dog-feeding signal is sent when the first computer program is running normally.

[0168] The first transmitting module 802 is configured to send the first data to a host computer and / or store it in a second memory; wherein the first memory is a volatile memory and the second memory is a non-volatile memory.

[0169] The second sending module 803 is configured to control the first computer program to run again after the first processor has finished reading the first data.

[0170] In some embodiments, the dog-feeding signal comes from a second processor, and the first data includes runtime data of the second processor running a first computer program in a first memory.

[0171] In some embodiments, the read module 801 is configured such that the first processor disconnects the first path between the second processor and the first memory, and connects the second path between the first processor and the first memory; the first processor reads first data from the first memory through the second path.

[0172] In some embodiments, runtime data includes a first computer program, data generated by running the first computer program, register values ​​of the processor running the first computer program, and / or exception types.

[0173] In some embodiments, the first computer program includes functions; the data generated by running the first computer program includes stack data; and the first processor determines the cause of the abnormality in the operation of the first computer program based on the functions, the stack data, and the register values ​​of the processor running the first computer program.

[0174] In some embodiments, the exception type is an interrupt, and the register values ​​and exception type of the processor running the first computer program are written to the first memory when the processor running the first computer program determines that the execution of the first computer program has been interrupted.

[0175] In some embodiments, the data processing apparatus 80 further includes a switching module; wherein the switching module is configured to, after the first processor completes reading the first data, switch on a first path between the second processor and the first memory, and disconnect a second path between the first processor and the first memory.

[0176] In some embodiments, the second sending module 803 is specifically configured such that after the first processor completes reading the first data and sends the first data to the host computer and / or stores it in the second memory, it controls the first computer program to run again; or, after the first processor completes reading the first data and before sending the first data to the host computer and / or storing it in the second memory, it controls the first computer program to run again; or, after the first processor completes reading the first data and during the process of sending the first data to the host computer and / or storing it in the second memory, it controls the first computer program to run again.

[0177] The descriptions of the above device embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0178] It should be noted that the module division in the embodiments of this application is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, exist as separate physical units, or have two or more units integrated into one unit. The integrated units can be implemented in hardware, as software functional units, or a combination of software and hardware.

[0179] It should be noted that, in the embodiments of this application, if the above methods are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device to execute all or part of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware and software combination.

[0180] This application provides an electronic device. Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 9 As shown, the electronic device 90 includes a first processor 901 and a first memory 902. The first memory 902 stores a first computer program, and the first processor 901 implements the steps in the method provided in the embodiments of this application when executing the second computer program.

[0181] It should be noted that the second processor 901 can also cache data to be processed or already processed by the first processor 901 and various modules in the electronic device 90, which can be achieved through flash memory or random access memory (RAM).

[0182] It should be understood that the storage location of the second computer program is not limited in the embodiments of this application. In some embodiments, the second computer program is stored in the first memory 902. In other embodiments, the second computer program is stored in the first processor 901. In still other embodiments, the second computer program is stored in a third memory.

[0183] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the method provided in the above embodiments.

[0184] This application provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the steps in the method provided in the above-described method embodiments.

[0185] It should be noted that the descriptions of the storage medium and device embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0186] It should be understood that the phrases "one embodiment," "an embodiment," or "some embodiments" mentioned throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment," "in one embodiment," or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely for descriptive purposes and do not represent the superiority or inferiority of the embodiments. The descriptions of the various embodiments above tend to emphasize the differences between the various embodiments; their similarities or commonalities can be referred to mutually, and for the sake of brevity, they will not be repeated here.

[0187] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three kinds of relationships. For example, object A and / or object B can represent three situations: object A exists alone, object A and object B exist simultaneously, and object B exists alone.

[0188] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0189] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple modules or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or modules can be electrical, mechanical, or other forms.

[0190] The modules described above as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules. They may be located in one place or distributed across multiple network units. Some or all of the modules may be selected to achieve the purpose of this embodiment according to actual needs.

[0191] In addition, each functional module in the various embodiments of this application can be integrated into one processing unit, or each module can be a separate unit, or two or more modules can be integrated into one unit; the integrated modules can be implemented in hardware or in the form of hardware plus software functional units.

[0192] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0193] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device to execute all or part of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0194] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. Similarly, the features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict.

[0195] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0196] The above are merely embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A data processing method, characterized in that, The method includes: If the first processor does not receive a dog-feeding signal during the dog-feeding cycle, it reads first data from the first memory. The first data includes runtime data of the first computer program being run. The dog-feeding signal is sent when the first computer program is running normally. The first processor sends the first data to the host computer and / or stores it in the second memory; wherein the first memory is volatile memory; and the second memory is non-volatile memory. After the first processor finishes reading the first data, it controls the first computer program to run again.

2. The method according to claim 1, characterized in that, The dog-feeding signal comes from the second processor, and the first data includes runtime data of the second processor running the first computer program in the first memory.

3. The method according to claim 2, characterized in that, The first processor reads first data from the first memory, including: The first processor disconnects the first path between the second processor and the first memory, and connects the second path between the first processor and the first memory; The first processor reads the first data from the first memory through the second path.

4. The method according to claim 1, wherein, The operational data includes the first computer program, the data generated by running the first computer program, the register values ​​of the processor running the first computer program, and / or the exception type.

5. The method according to claim 4, wherein, The first computer program includes functions; the data generated by running the first computer program includes stack data; the method further includes: The first processor determines the cause of the abnormal operation of the first computer program based on the function, the stack data, and the register values ​​of the processor running the first computer program.

6. The method according to claim 4, characterized in that, The exception type is an interrupt, and the register value of the processor running the first computer program and the exception type are written to the first memory when the processor running the first computer program determines that the execution of the first computer program has been interrupted.

7. The method according to claim 3, characterized in that, The method further includes: After the first processor completes reading the first data, it connects the first path between the second processor and the first memory, and disconnects the second path between the first processor and the first memory.

8. The method according to any one of claims 1 to 7, characterized in that, After the first processor completes reading the first data, it controls the first computer program to restart, including: After the first processor completes reading the first data and sends the first data to the host computer and / or stores it in the second memory, it controls the first computer program to restart; or, After the first processor finishes reading the first data and before sending the first data to the host computer and / or storing it in the second memory, it controls the first computer program to restart; or, After the first processor finishes reading the first data and during the process of sending the first data to the host computer and / or storing it in the second memory, it controls the first computer program to run again.

9. A data processing apparatus, characterized in that, include: The reading module is configured to read first data from the first memory when the first processor does not receive a dog-feeding signal during the dog-feeding cycle. The first data includes runtime data of the first computer program being run. The dog-feeding signal is sent when the first computer program is running normally. The first sending module is configured so that the first processor sends the first data to a host computer and / or stores it in a second memory; wherein the first memory is a volatile memory; and the second memory is a non-volatile memory. The second sending module is configured to control the first computer program to run again after the first processor has finished reading the first data.

10. An electronic device, comprising a first processor and a first memory, characterized in that, The first memory stores a first computer program, and the first processor implements the method according to any one of claims 1 to 8 when executing the second computer program.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 8.

12. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by a processor, they implement the method described in any one of claims 1 to 8.

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