Driving substrate, display panel and display device

Abstract

The invention relates to a driving substrate, a display panel and a display device. The driving substrate comprises a substrate, a first signal line, a driving layer and an inorganic dielectric layer. The first signal line is located on the substrate. The driving layer is located on the side, away from the substrate, of the first signal line and comprises a plurality of conducting layers, and the conducting layers at least form a driving circuit. The inorganic dielectric layer is located between the adjacent conductive layers and between the driving layer and the first signal line. Phenomena such as corrosion of the first signal line can be effectively prevented.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving substrate, a display panel, and a display device. Background Technology

[0002] Currently, display products are widely used in people's production and daily life. The packaging reliability of display products is a crucial performance characteristic affecting product quality.

[0003] However, existing display products often suffer from display abnormalities due to the intrusion of water, oxygen, or metal ions. Summary of the Invention

[0004] Therefore, it is necessary to provide a driving substrate, display panel, and display device that can effectively prevent corrosion and other phenomena of the first signal line in order to address the above-mentioned technical problems.

[0005] A driving substrate, comprising:

[0006] Substrate;

[0007] The first signal line is located on the substrate.

[0008] A driving layer, located on the side of the first signal line away from the substrate, includes multiple conductive layers, the multiple conductive layers forming at least a driving circuit;

[0009] An inorganic dielectric layer is located between adjacent conductive layers and between the driving layer and the first signal line.

[0010] In one embodiment, the driving substrate has a display area and a non-display area, and the first signal line is located at least in the non-display area.

[0011] In one embodiment, the non-display area includes a transition area and a bend area, the transition area being located between the display area and the bend area, and the first signal line being at least partially located in the transition area.

[0012] In one embodiment, the driving substrate includes:

[0013] A shielding layer is located between the substrate and the driving layer, and includes a shielding pattern;

[0014] Optionally, the first signal line is located in the shielding layer;

[0015] Optionally, the first signal line includes a negative power supply line.

[0016] In one embodiment, the material of the first signal line is different from the material of the shielding pattern;

[0017] Optionally, the impedance of the first signal line is less than the impedance of the shielding pattern;

[0018] Optionally, the first signal line includes a stacked titanium layer, an aluminum layer, and a titanium layer, and / or the shielding pattern includes a molybdenum layer.

[0019] In one embodiment, the material of the first signal line is the same as the material of the shielding pattern;

[0020] Optionally, both the first signal line and the shielding pattern include a layer of molybdenum, an aluminum layer, and a titanium layer stacked together.

[0021] In one embodiment, the driving substrate includes:

[0022] A shielding layer is located between the substrate and the driving layer, and includes a shielding pattern;

[0023] A first wiring layer includes the first signal line, and the first wiring layer is located between the shielding layer and the driving layer, and / or the first wiring layer is located between the shielding layer and the substrate.

[0024] In one embodiment, the substrate includes a first flexible layer, a first barrier layer, a second flexible layer, and a second barrier layer;

[0025] Optionally, the second barrier layer includes a first sub-barrier layer and a second sub-barrier layer, wherein the material of the first sub-barrier layer is different from the material of the second sub-barrier layer;

[0026] Optionally, the inorganic dielectric layer includes a third barrier layer that covers the first signal line and the second barrier layer, and the material of the third barrier layer is different from the material of the second sub-barrier layer;

[0027] Optionally, the material of the third barrier layer and the material of the first sub-barrier layer both include silicon oxide, and / or the material of the second sub-barrier layer includes silicon nitride;

[0028] Optionally, the inorganic medium layer further includes a buffer layer located between the third barrier layer and the driving layer.

[0029] In one embodiment, the driving substrate further includes:

[0030] The second wiring layer includes a second signal line and is located on the side of the driving layer away from the substrate;

[0031] Optionally, the second signal line includes any one or more of a positive power line, a data line, and a reference signal line.

[0032] In one embodiment, the inorganic dielectric layer is further located between the second wiring layer and the driving layer, and the plurality of conductive layers further form fan-out traces, the orthographic projection of the fan-out traces on the substrate overlapping the orthographic projection of the first signal line on the substrate, wherein the inorganic dielectric layer comprises:

[0033] A first dielectric layer is located between the first signal line and the fan-out trace;

[0034] The second dielectric layer is located between the second wiring layer and the fan-out trace;

[0035] Wherein, the thickness of the first dielectric layer is greater than or equal to the thickness of the second dielectric layer.

[0036] In one embodiment, the driving substrate further includes a planarization layer located on the side of the driving layer away from the substrate.

[0037] A display panel, comprising:

[0038] The driving substrate of any of the above embodiments;

[0039] The pixel layer is located on the side of the driving layer away from the substrate;

[0040] The second inorganic encapsulation layer is located on the side of the pixel layer away from the driving substrate, and its orthogonal projection on the driving substrate covers the orthogonal projection of the pixel layer on the driving substrate.

[0041] In one embodiment, the driving substrate has a display area and a non-display area, and includes a first organic planarization layer located on the side of the driving layer away from the substrate and located in the display area. The pixel layer includes:

[0042] An isolation structure is located on the side of the first organic planarization layer away from the substrate and is configured to form an isolation opening, the isolation opening being located in the display area;

[0043] Multiple light-emitting structures are spaced apart, each light-emitting structure being at least partially located within the isolation opening. Each light-emitting structure includes a light-emitting unit and a first electrode, the first electrode covering the side of the light-emitting unit away from the driving substrate and connected to the isolation structure.

[0044] In one embodiment, the display panel further includes a first inorganic encapsulation layer, the first inorganic encapsulation layer including a plurality of encapsulation units spaced apart, the encapsulation units being at least partially located within the area defined by the isolation opening and covering the side of the first electrode away from the light-emitting unit;

[0045] The orthographic projection of the second inorganic encapsulation layer on the driving substrate covers the orthographic projections of the first inorganic encapsulation layer and the isolation structure on the driving substrate;

[0046] Optionally, the display panel further includes an organic encapsulation layer that covers the first inorganic encapsulation layer and the isolation structure, and a second inorganic encapsulation layer that covers the organic encapsulation layer.

[0047] Optionally, the pixel layer further includes a second electrode located between the first organic planarization layer and the isolation structure, and the isolation opening exposes the second electrode;

[0048] Optionally, the display panel further includes a pixel definition layer that covers the surface of the second electrode away from the driving substrate and forms a pixel opening that communicates with the isolation opening and exposes at least a portion of the second electrode.

[0049] Optionally, the orthographic projection of the pixel opening on the substrate lies within the orthographic projection of the isolation opening on the substrate.

[0050] In one embodiment, the isolation structure includes a first isolation layer and a second isolation layer, the first isolation layer being located on the side of the second isolation layer closer to the driving substrate, and the orthographic projection of the first isolation layer on the driving substrate being located within the orthographic projection of the second isolation layer on the driving substrate.

[0051] In one embodiment, the isolation structure includes a third isolation layer, a first isolation layer, and a second isolation layer arranged sequentially, wherein the orthographic projection of the first isolation layer on the driving substrate is located within the orthographic projection of the second isolation layer on the driving substrate, and the orthographic projection of the first isolation layer on the driving substrate is located within the orthographic projection of the third isolation layer on the driving substrate.

[0052] In one embodiment, the first insulating layer is made of aluminum, the second insulating layer is made of titanium, and the third insulating layer is made of molybdenum.

[0053] In one embodiment, the driving substrate has a display area and a non-display area, and includes a second organic planarization layer located on the side of the driving layer away from the substrate, extending from the display area to the non-display area, and the pixel layer includes:

[0054] The second electrode is located on the side of the second organic planarization layer away from the substrate;

[0055] A pixel definition layer covers the surface of the second electrode away from the substrate and is configured to form a pixel opening that exposes the second electrode;

[0056] The isolation pillars are located on the pixel definition layer;

[0057] The light-emitting unit is located within the pixel opening;

[0058] The first electrode covers the pixel definition layer, the isolation pillar, and the light-emitting unit.

[0059] In one embodiment, the first signal line includes a negative power supply line, and the display panel further includes:

[0060] The polarizer is located on the side of the second inorganic encapsulation layer away from the pixel layer.

[0061] A display panel, comprising:

[0062] The driving substrate of any of the above embodiments has a display area and a non-display area;

[0063] A pixel layer includes an isolation structure and a plurality of light-emitting structures spaced apart. The isolation structure is located on the side of the driving layer away from the substrate and forms an isolation opening. The isolation opening is located in the display area. The light-emitting structures are at least partially located within the isolation opening. Each light-emitting structure includes a light-emitting unit and a first electrode. The first electrode covers the side of the light-emitting unit away from the driving substrate and is connected to the isolation structure.

[0064] The first inorganic encapsulation layer includes a plurality of encapsulation units spaced apart, wherein the encapsulation units are at least partially located within the area defined by the isolation opening and cover the side of the first electrode away from the light-emitting unit;

[0065] The second inorganic encapsulation layer is located on the side of the pixel layer away from the driving substrate, and its orthogonal projection on the driving substrate covers the pixel layer and the orthogonal projection of the first inorganic encapsulation layer on the driving substrate.

[0066] A display device includes a display panel as described above.

[0067] The aforementioned driving substrate, display panel, and display device include a driving substrate comprising a substrate, a first signal line, an inorganic dielectric layer, and a driving layer sequentially disposed therefrom, wherein the inorganic dielectric layer protects the first signal line. In the display panel, the driving layer is located on the side of the first signal line away from the substrate, meaning the first signal line is positioned on the side of the driving layer away from the second inorganic encapsulation layer, thus keeping the first signal line away from the second inorganic encapsulation layer. Simultaneously, inorganic dielectric layers are provided between adjacent conductive layers of the driving layer and between the driving layer and the first signal line. Therefore, the inorganic dielectric layer forms an isolation between the second inorganic encapsulation layer and the first signal line, while simultaneously protecting the first signal line. Thus, even if cracks occur in the second inorganic encapsulation layer, the inorganic dielectric layer can prevent further intrusion of water, oxygen, or metal ions into the first signal line, effectively preventing corrosion of the first signal line. Attached Figure Description

[0068] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0069] Figures 1 to 5 This is a partial cross-sectional schematic diagram of the display panel in different embodiments of this application.

[0070] Explanation of reference numerals in the attached figures:

[0071] 100 - Driving substrate, 110 - Substrate, 111 - First flexible layer, 112 - First barrier layer, 113 - Second flexible layer, 114 - Second barrier layer, 1141 - First sub-barrier layer, 1142 - Second sub-barrier layer, 120 - First signal line, 130 - Driving layer, 131 - First conductive layer, 132 - Second conductive layer, 140 - Inorganic dielectric layer, 141 - Third barrier layer, 142 - Buffer layer, 1421 - First buffer sub-layer, 1422 - Second buffer sub-layer, 143 - Gate oxide layer, 144 - First interlayer dielectric layer, 145 - Second interlayer dielectric layer, 150 - Shielding layer, 151 - Shielding pattern, 160 - First wiring layer, 170 - Second wiring layer, 171 - First... 172-Second wiring sublayer, 181-First organic planarization layer, 182-Second organic planarization layer, 183-Third organic planarization layer, 200-Pixel layer, 210-Isolation structure, 211-First isolation layer, 212-Second isolation layer, 213-Third isolation layer, 220-Light emission structure, 221-Light emission unit, 222-First electrode, 230-Second electrode, 300-Second inorganic encapsulation layer, 400-First inorganic encapsulation layer, 410-Encapsulation unit, 500-Pixel definition layer, 600-Isolation pillar, 700-Polarizer, 800-Organic encapsulation layer, 900-Dyke, A1-Display area, A2-Non-display area, A21-Transition area, A22-Bending area. Detailed Implementation

[0072] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0073] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0074] It should be noted that when a component is said to be "fixed to" another component, it can be directly attached to the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0075] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It is understood that when a layer or element is referred to as "on" another layer or substrate, the layer or element may be directly on said other layer or substrate, or there may be intermediate layers. Furthermore, it is understood that when a layer is referred to as "between" two layers, the layer may be the only layer between said two layers, or there may be one or more intermediate layers. Additionally, the same reference numerals always denote the same elements.

[0076] In the following embodiments, when a layer, region, or element is “connected,” it can be interpreted as the layer, region, or element being connected not only directly but also through other constituent elements placed therebetween. For example, when a layer, region, element, etc., is described as being connected or electrically connected, the layer, region, element, etc., can not only be directly connected or directly electrically connected, but can also be connected or electrically connected through another layer, region, element, etc., placed therebetween.

[0077] In the following text, although terms such as “first” and “second” may be used to describe various components, these components are not necessarily limited to the terms above. The terms above are only used to distinguish one component from another. It will also be understood that expressions used in the singular form include plural expressions, unless the singular form has a distinctly different meaning in the context.

[0078] When a phrase such as “at least one of…” follows a list of elements, it modifies the entire list of elements, not individual elements within that list. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. As used in the application documents, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that terms such as “comprising / including” or “having” specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0079] Electronic or electrical devices and / or any other related devices or components (e.g., display devices including a display panel and a display panel driver, wherein the display panel driver further includes a drive controller, a gate driver, a gamma reference voltage generator, a data driver, and a transmit driver) according to embodiments of the concepts described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices may be formed on an integrated circuit (IC) chip or on a separate IC chip. Additionally, various components of these devices may be implemented on a flexible printed circuit film, a tape-on-a-package (TCP), a printed circuit board (PCB), or formed on a substrate. Furthermore, various components of these devices may be processes or threads running on one or more processors in one or more computing devices to execute computer program instructions and interact with other system components to perform the various functions described herein. Computer program instructions are stored in memory, which may be implemented in a computing device using standard storage devices such as random access memory (RAM). Computer program instructions may also be stored in other non-transitory computer-readable media such as CD-ROMs, flash drives, etc. Furthermore, those skilled in the art will recognize that the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices, without departing from the spirit and scope of the exemplary embodiments of the present application.

[0080] Patents CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, PCT / CN2024 / 098217, PCT / CN2024 / 099419, and PCT / CN2024 / 099072 describe relevant technical solutions for isolation structures, the contents of which are incorporated herein by reference.

[0081] In one embodiment, see Figure 1 or Figure 2 or Figure 4 A display panel is provided, which includes a driving substrate 100, a pixel layer 200 and a second inorganic encapsulation layer 300.

[0082] The driving substrate 100 can provide driving for the pixel layer 200.

[0083] The pixel layer 200 is located on the driving substrate 100. The pixel layer 200 may include multiple pixel units. Each pixel unit may include multiple sub-pixels. For example, each pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0084] The second inorganic encapsulation layer 300 is located on the side of the pixel layer 200 away from the driving substrate 100, and its orthographic projection on the driving substrate 100 covers the orthographic projection of the pixel layer 200 on the driving substrate 100. The material of the second inorganic encapsulation layer 300 is an inorganic material, used to prevent water, oxygen or metal ions from intruding into the interior of the display panel.

[0085] In one embodiment, the driving substrate 100 includes a substrate 110, a first signal line 120, a driving layer 130, and an inorganic dielectric layer 140.

[0086] The substrate 110 may be, but is not limited to, a flexible substrate.

[0087] The first signal line 120 is located on the substrate 110. The material of the first signal line 120 may include, but is not limited to, a metallic material. Furthermore, the first signal line 120 may be a multilayer structure or a single-layer structure. No restrictions are placed on either.

[0088] The driving layer 130 is located on the side of the first signal line 120 away from the substrate 110. The driving layer 130 may include multiple conductive layers. The multiple conductive layers may form a driving circuit. The driving circuit may include, but is not limited to, pixel driving circuits such as 7T1C, 8T1C, or 9T1C. It is understood that in this application, "multiple" may mean two or more.

[0089] The pixel layer 200 of the display panel is located on the side of the driving layer 130 away from the substrate 110. For each sub-pixel in the pixel layer 200, multiple driving circuits can be provided in the driving layer 130 to drive each sub-pixel to emit light.

[0090] In addition, as an example, each conductive layer of the driving layer 130 can also form some traces, such as fan-out traces.

[0091] The inorganic dielectric layer 140 is located between adjacent conductive layers and between the driving layer 130 and the first signal line 120. Specifically, the inorganic dielectric layer 140 may include multiple inorganic film layers. During the fabrication of the driving substrate 100, at least one inorganic film layer can be formed after the formation of the first signal line 120 and after the formation of each conductive layer of the driving layer 130, thereby isolating the different conductive layers from each other.

[0092] During reliability testing or application of the display panel, the second inorganic encapsulation layer 300 may develop cracks due to the film quality and / or various stress effects, which may cause water, oxygen, or metal ions to invade the interior of the panel.

[0093] In this embodiment, the driving layer 130 is located on the side of the first signal line 120 away from the substrate 110, that is, the first signal line 120 is disposed on the side of the driving layer 130 away from the second inorganic encapsulation layer 300, thereby keeping the first signal line 120 away from the second inorganic encapsulation layer 300. Simultaneously, an inorganic dielectric layer 140 is provided between adjacent conductive layers of the driving layer 130 and between the driving layer 130 and the first signal line 120. Therefore, the inorganic dielectric layer 140 can form an isolation between the second inorganic encapsulation layer 300 and the first signal line 120. Therefore, in the display panel formed based on the driving substrate 100 of this embodiment, even if cracks occur in the second inorganic encapsulation layer 300, the inorganic dielectric layer 140 can prevent water, oxygen, or metal ions from further intruding into the first signal line 120, thereby effectively preventing corrosion of the first signal line 120.

[0094] In one embodiment, see Figure 1 or Figure 2 or Figure 4 The driving substrate 100 has a display area A1 and a non-display area A2. The first signal line 120 is located at least in the non-display area A2.

[0095] Specifically, after the display panel is formed based on the driving substrate 100, the second inorganic encapsulation layer 300 is more likely to crack in the non-display area A2.

[0096] Therefore, by placing the first signal line 120 below the driving layer 130 in the non-display area A2, it is more effective to prevent the signal lines in the display panel from being attacked by water, oxygen or metal ions.

[0097] In one embodiment, the non-display area A2 includes a transition area A21 and a bending area A22.

[0098] Specifically, the non-display area A2 may also include a bonding area located on the side of the bending area A22 away from the transition area A21. The bonding area is used for bonding with ICs and FPCs, etc. The bending area A22 can be bent so that the bonding area bends to the back of the display panel, thereby reducing the bezel size of the display panel.

[0099] The transition area A21 is located between the display area A1 and the bending area A22, and the first signal line 120 is at least partially located in the transition area A21. Optionally, the first signal line 120 includes a negative power supply line.

[0100] The transition region A21 can have various boundaries, such as the polarizer 700 boundary, the organic layer boundary, the second inorganic package boundary, etc., which makes the signal lines in the transition region A21 more susceptible to corrosion by water, oxygen or metal ions.

[0101] At this time, placing at least part of the first signal line 120 located in the transition zone A21 below the driving layer 130 can more effectively prevent the signal lines in the display panel from being attacked by water, oxygen or metal ions.

[0102] In one embodiment, see Figure 1 or Figure 4 The driving substrate 100 includes a shielding layer 150. In one embodiment, a first signal line 120 is located in the shielding layer 150.

[0103] A shielding layer 150 is located between the substrate 110 and the driving layer 130. The shielding layer 150 includes a shielding pattern 151. The material of the shielding layer 150 includes a conductive material, thereby achieving ESD protection.

[0104] Specifically, the shielding pattern 151 may include a first shielding pattern and a second shielding pattern.

[0105] In display area A1, multiple first shielding patterns that are spaced apart and electrically connected to each other can be arranged. For each sub-pixel, a first shielding pattern can be provided opposite to it, thereby shielding each sub-pixel.

[0106] Meanwhile, the non-display area A2 may include multiple border areas. The second shielding graphic may be located within at least a portion of the border areas.

[0107] For example, the non-display area A2 may include a top border area, a bottom border area, a left border area, and a right border area. The bottom border area may include the aforementioned transition area A21. The top border area, left border area, and right border area may each have a second shielding graphic.

[0108] Furthermore, within the border area where the second shielding pattern is provided, the second shielding pattern can extend along the extension direction of the border area and connect with each of the first shielding patterns located in the display area A1, thereby making the shielding signal distribution more uniform.

[0109] The first signal line 120 can be located in the shielding layer 150.

[0110] As an example, the first signal line 120 may include a negative power supply line. The negative power supply line is used to provide a negative power supply voltage VSS.

[0111] The negative power line usually only needs to be set in the non-display area A2, so that the setting of the first signal line 120 can have little or no impact on the normal arrangement of the shielding pattern 151.

[0112] In this embodiment, the first signal line 120 and the shielding pattern 151 are simultaneously disposed on the shielding layer 150, so that the shielding layer 150 has both ESD protection function and signal transmission function.

[0113] In one embodiment, the material of the first signal line 120 is different from the material of the shielding pattern 151.

[0114] During the fabrication of the display panel, the first signal line 120 and the shielding pattern 151 can be formed through two different photolithography processes. The two photolithography processes use two different photomasks.

[0115] Specifically, a shielding material layer (or a first signal material layer) can first be formed on the substrate 110. Then, a first photoresist is coated on the shielding material layer (or the first signal material layer). Then, based on a first photomask, the first photoresist on the shielding material layer (or the first signal material layer) is exposed and developed to form a first patterned photoresist. Afterward, the shielding material layer (or the first signal material layer) is etched based on the first patterned photoresist to form a shielding pattern 151 (or a first signal line 120).

[0116] Then, a first signal material layer (or shielding material layer) can be coated on the substrate 110 where the shielding pattern 151 (or the first signal line 120) is formed. A second photoresist is then coated on the first signal material layer (or shielding material layer). The second photoresist on the first signal material layer (or shielding material layer) is then exposed and developed based on a second photomask to form a second patterned photoresist. Subsequently, the first signal material layer (or shielding material layer) is etched based on the second patterned photoresist to form the first signal line 120 (or shielding pattern 151).

[0117] The first and second masks can be a dark field mask and a bright field mask, respectively. Of course, the first and second masks can both be dark field masks, or both can be bright field masks.

[0118] At this time, the materials of the first signal line 120 and the shielding pattern 151 can be flexibly selected according to their respective functions.

[0119] As an example, the impedance of the first signal line 120 is less than the impedance of the shielding pattern 151, which can improve the display effect and at the same time provide good ESD protection.

[0120] For example, the first signal line 120 includes a stacked titanium layer, an aluminum layer, and a titanium layer, and the shielding pattern 151 includes a molybdenum layer.

[0121] The first signal line 120, which includes a titanium layer, an aluminum layer, and a titanium layer, is located below the driving layer 130. When the second inorganic encapsulation layer 300 is broken, the inorganic dielectric layer 140 can block the intrusion of water, oxygen, or metal ions, thereby preventing aluminum corrosion problems. It can also prevent aluminum migration problems caused by the breakage of the second inorganic encapsulation layer 300.

[0122] Meanwhile, the first signal line 120, which includes a titanium layer, an aluminum layer, and a titanium layer, has lower impedance, thereby reducing the voltage drop of signals transmitted to each sub-pixel in the display area A1 on the output path, resulting in better display performance. The shielding pattern 151, which includes a molybdenum layer, has higher impedance and effectively prevents ESD breakdown.

[0123] In one embodiment, the material of the first signal line 120 is the same as the material of the shielding pattern 151.

[0124] In the process of manufacturing the display panel, the first signal line 120 and the shielding pattern 151 can be formed using the same photomask and the same photolithography process, thereby reducing process costs and increasing production capacity.

[0125] Specifically, a conductive material layer can first be formed on the substrate 110. Then, a third photoresist is coated on the conductive material layer. Then, based on a third photomask, the third photoresist on the conductive material layer is exposed and developed to form a third patterned photoresist. Afterward, the conductive material layer is etched based on the third patterned photoresist to form the shielding pattern 151 and the first signal line 120.

[0126] As an example, both the first signal line 120 and the shielding pattern 151 include a molybdenum layer, an aluminum layer, and a titanium layer stacked together.

[0127] At this time, the first signal line 120 of the shielding layer 150 and the shielding pattern 151 are made of the same material, which can also serve as both ESD protection and signal channel.

[0128] Of course, in other embodiments, the first signal line 120 may not be provided in the shielding layer 150.

[0129] For example, in one embodiment, the driving substrate 100 includes a shielding layer 150 and a first wiring layer 160.

[0130] The shielding layer 150 is located between the substrate 110 and the driving layer 130. The shielding layer 150 includes a shielding pattern 151. The shielding pattern 151 is used for ESD shielding.

[0131] The first wiring layer 160 includes a first signal line 120. The first wiring layer 160 is located between the shielding layer 150 and the driving layer 130. (See also...) Figure 2 And / or, the first wiring layer 160 is located between the shielding layer 150 and the substrate 110, see [link to relevant documentation]. Figure 3 The first wiring layer 160 may include one or more wiring sublayers spaced apart.

[0132] At this time, the first signal line 120 may include any one or more of the following: a negative power supply line, a positive power supply line, a reference signal line, and a data line. The negative power supply line is used to provide the negative power supply voltage VSS, and the positive power supply line is used to provide the positive power supply voltage VDD. The reference signal line is used to provide the reference signal Vref. The data line is used to provide the data voltage VData.

[0133] Furthermore, positive power lines, reference signal lines, data lines, etc., can extend from the non-display area A2 to the display area A1. As an example, any one or more of the positive power lines, reference signal lines, data lines, etc., can be formed in multiple (e.g., two) wiring sub-layers of the first wiring layer 160, thereby being distributed in a mesh pattern in the display area A1.

[0134] In one embodiment, see Figure 1 or Figure 2 or Figure 4 or Figure 5 The substrate 110 includes a first flexible layer 111, a first barrier layer 112, a second flexible layer 113, and a second barrier layer 114.

[0135] The first flexible layer 111 and the second flexible layer 113 can be made of organic materials. Organic materials may include, but are not limited to, polyimide (PI). Meanwhile, the first barrier layer 112 and the second barrier layer 114 can be made of inorganic materials. Inorganic materials may include, but are not limited to, silicon oxide, silicon nitride, or silicon oxynitride.

[0136] The first flexible layer 111, the first barrier layer 112, the second flexible layer 113, and the second barrier layer 114 are stacked together, so that the substrate 110 has an alternating arrangement of organic and inorganic layers. At this time, on the one hand, the flexibility requirements can be met by the organic layers (the first flexible layer 111 and the second flexible layer 113), and on the other hand, the inorganic layers (the first barrier layer 112 and the second barrier layer 114) can block the intrusion of water, oxygen, or metal ions.

[0137] As an example, the second barrier layer 114 includes a first sub-barrier layer 1141 and a second sub-barrier layer 1142. The material of the first sub-barrier layer 1141 is different from that of the second sub-barrier layer 1142, thereby better preventing the intrusion of water, oxygen or metal ions.

[0138] As an example, the inorganic dielectric layer 140 includes a third barrier layer 141. The material of the third barrier layer 141 may also be an inorganic material.

[0139] The third barrier layer 141 covers the first signal line 120 and the second barrier layer 114. The material of the third barrier layer 141 is different from that of the second sub-barrier layer 1142, thereby enhancing the waterproof, oxygen-proof, or metal ion-proof functions of the second barrier layer 114.

[0140] Optionally, the material of the third barrier layer 141 and the material of the first sub-barrier layer 1141 both include silicon oxide, and / or the material of the second sub-barrier layer 1142 includes silicon nitride.

[0141] As an example, the inorganic dielectric layer 140 also includes a buffer layer 142. The buffer layer 142 is located between the third barrier layer 141 and the driving layer 130. A semiconductor active layer can be formed on the buffer layer 142. The material of the semiconductor active layer can be, but is not limited to, silicon. Specifically, the buffer layer 142 can also include a first buffer sublayer 1421 and a second buffer sublayer 1422. The first buffer sublayer 1421 and the second buffer sublayer 1422 can be sequentially stacked on the third barrier layer 141. And the material of the first buffer sublayer 1421 can be different from the material of the third barrier layer 141 and the material of the second buffer sublayer 1422.

[0142] For example, the material of the first buffer sublayer 1421 can be silicon nitride. The material of the second buffer sublayer 1422 can be silicon oxide.

[0143] In one embodiment, see Figure 1 or Figure 2 or Figure 4 or Figure 5 The driving substrate 100 also includes a second wiring layer 170. Specifically, the second wiring layer 170 may include one or more wiring sublayers that are spaced apart.

[0144] The second wiring layer 170 includes a second signal line, meaning that the second signal line can be formed in the second wiring layer 170. The second signal line can be, but is not limited to, any one or more of positive power lines, data lines, and reference signal lines.

[0145] The second wiring layer 170 is located on the side of the driving layer 130 away from the substrate 110. In the display panel, the second wiring layer 170 may be located between the driving layer 130 and the pixel layer 200, thereby connecting the driving substrate 100 and the pixel layer 200.

[0146] At this point, the second signal line is closer to the pixel layer 200, which reduces the voltage drop between them.

[0147] As an example, the second signal line can be located in display area A1. In this case, since the second inorganic package layer 300 corresponding to display area A1 is usually highly reliable, placing the second signal line in display area A1 can reduce the impedance on the signal transmission paths of traces such as positive power lines, data lines, and reference signal lines, and can also reduce problems such as corrosion caused by the intrusion of water, oxygen, or metal ions.

[0148] Of course, in other examples, the second signal line can also extend from display area A1 to non-display area A2.

[0149] Specifically, at this time, the first signal line 120 can be a signal line whose electrical parameters change significantly after cracks or other problems occur in the second inorganic encapsulation layer 300. The second signal line can be a signal line whose electrical parameters do not change significantly after cracks or other problems occur in the second inorganic encapsulation layer 300, such as a positive power supply line.

[0150] In different display products, the changes in electrical parameters of the same signal lines after problems such as cracks appearing in the second inorganic encapsulation layer 300 may vary. For example, in some display products, after cracks appear in the second inorganic encapsulation layer 300, the electrical parameters of the negative power supply line used to provide the negative power supply voltage VSS will change significantly, while the electrical parameters of other signal lines, such as the positive power supply line used to provide the positive power supply voltage VDD, will not change significantly. Conversely, in other display products, after cracks appear in the second inorganic encapsulation layer 300, the electrical parameters of the positive power supply line will change significantly, while the electrical parameters of other signal lines, such as the negative power supply line, will not change significantly.

[0151] In one embodiment, the inorganic dielectric layer 140 is also located between the second wiring layer 170 and the driver layer 130. The plurality of conductive layers of the driver layer 130 also form fan-out traces. As an example, the fan-out traces can be fan-out traces of data lines.

[0152] The orthographic projection of the fan-out trace on the substrate 110 overlaps with the orthographic projection of the first signal line 120 on the substrate 110. Therefore, there is a parasitic capacitance between the fan-out trace and the first signal line 120.

[0153] Meanwhile, the inorganic dielectric layer 140 includes a first dielectric layer and a second dielectric layer.

[0154] The first dielectric layer is located between the first signal line 120 and the fan-out trace. The second dielectric layer is located between the second wiring layer 170 and the fan-out trace. The thickness of the first dielectric layer is greater than or equal to the thickness of the second dielectric layer, thereby reducing the parasitic capacitance between the fan-out trace and the first signal line 120 and ensuring display quality.

[0155] For example, please refer to Figure 1 The driving layer 130 includes a first conductive layer 131 and a second conductive layer 132. The driving circuit in the driving layer 130 may include thin-film transistors and capacitors, etc. The gate of the thin-film transistor may be located in the first conductive layer 131. Meanwhile, the inorganic dielectric layer 140 may include the gate oxide layer 143 of the thin-film transistor.

[0156] Meanwhile, the second wiring layer 170 includes a first wiring sublayer 171 and a second wiring sublayer 172. The first wiring sublayer 171 is located on the side of the second wiring sublayer 172 closer to the drive layer 130.

[0157] When the fan-out trace is located in the first conductive layer 131, the first dielectric layer includes a third barrier layer 141, a buffer layer 142, and a gate oxide layer 143; the second dielectric layer includes a first interlayer dielectric layer 144 and a second interlayer dielectric layer 145 located between the first wiring sublayer 171 and the fan-out trace.

[0158] The thickness of the third barrier layer 141 can be 1200 Å-1400 Å, for example, 1200 Å, 1300 Å, and 1400 Å; the thickness of the buffer layer 142 can be 3000 Å-4000 Å, for example, 3000 Å, 3500 Å, and 4000 Å; the thickness of the gate oxide layer 143 can be 1200 Å-1400 Å, for example, 1200 Å, 1300 Å, and 1400 Å; the thickness of the first interlayer dielectric layer 144 can be 2500 Å-3500 Å, for example, 2500 Å, 2800 Å, 3000 Å, 3200 Å, and 3500 Å; and the thickness of the second interlayer dielectric layer 145 can be 2500 Å-3500 Å, for example, 2500 Å, 2800 Å, 3000 Å, 3200 Å, and 3500 Å.

[0159] Specifically, the thickness of the third barrier layer 141 can be 1300 Å, the thickness of the buffer layer 142 can be 3500 Å, and the thickness of the gate oxide layer 143 can be 1300 Å. Therefore, the total thickness of the first dielectric layer is 6100 Å. The total thickness of the first interlayer dielectric layer 144 and the second interlayer dielectric layer 145 can also be 6100 Å.

[0160] At this point, the thickness of the first dielectric layer and the second dielectric layer are the same. Therefore, placing the first signal line 120 below the driving layer 130, compared to placing it above the driving layer 130 or the first conductive layer 131, does not increase the parasitic capacitance between the fan-out trace and the first signal line 120.

[0161] When the fan-out trace is located in the second conductive layer 132, the first dielectric layer includes a third barrier layer 141, a buffer layer 142, a gate oxide layer 143, and a first interlayer dielectric layer 144. The second dielectric layer includes a second interlayer dielectric layer 145.

[0162] At this point, the thickness of the first dielectric layer is the same as that of the second dielectric layer. Therefore, placing the first signal line 120 below the driving layer 130, compared to placing it above the driving layer 130 or the first conductive layer 131, can reduce the parasitic capacitance between the fan-out trace and the first signal line 120, thereby resulting in a better display effect.

[0163] In one embodiment, the driving substrate 100 further includes a planarization layer. The number of planarization layers can be one or more.

[0164] As an example, the driving substrate 100 also includes a second wiring layer 170, which includes one or more wiring sublayers. In this case, during the display panel manufacturing process, a planarization layer can be formed for each wiring sublayer, so that subsequent wiring sublayers or pixel layers 200 can be formed on a flat surface, thereby improving product reliability.

[0165] As an example, the material of the planarization layer may include organic materials.

[0166] In one embodiment, see Figure 1 or Figure 2 or Figure 3 The driving substrate 100 has a display area A1 and a non-display area A2. The display area A1 and the non-display area A2 of the driving substrate 100 are the same as the display area A1 and the non-display area A2 of the display panel.

[0167] The driving substrate 100 includes a second organic planarization layer 182. The second organic planarization layer 182 is located on the side of the driving layer 130 away from the substrate 110 and extends from the display area A1 to the non-display area A2.

[0168] The pixel layer 200 of the display panel includes a second electrode 230, a pixel definition layer 500, isolation pillars 600, a light-emitting unit 221, and a first electrode 222. The first electrode 222 can be configured as a cathode and the second electrode 230 as an anode. Alternatively, the first electrode 222 can be configured as an anode and the second electrode 230 as a cathode.

[0169] The second electrode 230 is located on the side of the second organic planarization layer 182 away from the substrate 110. A pixel definition layer 500 covers the surface of the second electrode 230 away from the substrate 110. The pixel definition layer 500 forms a pixel opening that exposes the second electrode 230. An isolation pillar 600 is located on the pixel definition layer 500. A light-emitting unit 221 is located within the pixel opening. A first electrode 222 covers the pixel definition layer 500, the isolation pillar 600, and the light-emitting unit 221.

[0170] In the display panel fabrication process, a plurality of second electrodes 230 spaced apart can first be formed on the second organic planarization layer 182. Then, a pixel definition layer 500 and isolation pillars 600 are formed. Subsequently, based on a precision photomask (FMM), light-emitting units 221 of different colors can be formed within the pixel openings. Then, a first electrode 222 covering the display area A1 can be formed so that different light-emitting units 221 share the first electrode 222.

[0171] As an example, the display panel in this embodiment may include, but is not limited to, medium to large-sized display panels such as foldable phones, tablets, and laptops.

[0172] The larger the display panel size, the more prone the second inorganic encapsulation layer 300 is to crack due to stress, which in turn makes it more susceptible to intrusion of water, oxygen, or metal ions, leading to reliability issues.

[0173] In this embodiment, the first signal line 120 is disposed on the side of the driving layer 130 away from the second inorganic encapsulation layer 300, so that the inorganic dielectric layer 140 can effectively prevent water, oxygen or metal ions from invading the first signal line 120, thereby effectively protecting the first signal line 120 from corrosion and other problems.

[0174] In this embodiment, the first signal line 120 may include, for example, a positive power supply line for providing a positive power supply voltage VDD.

[0175] In one embodiment, see Figure 4 or Figure 5 The driving substrate 100 has a display area A1 and a non-display area A2. The display area A1 and the non-display area A2 of the driving substrate 100 are the same as the display area A1 and the non-display area A2 of the display panel.

[0176] The pixel layer 200 of the display panel includes an isolation structure 210 and a plurality of light-emitting structures 220 spaced apart.

[0177] The isolation structure 210 is configured to form an isolation opening, which is located in the display area A1.

[0178] For example, please refer to Figure 4 The isolation structure 210 includes a first isolation layer 211 and a second isolation layer 212. The first isolation layer 211 is located on the side of the second isolation layer 212 closer to the driving substrate 100, and the orthographic projection of the first isolation layer 211 on the driving substrate 100 is located within the orthographic projection of the second isolation layer 212 on the driving substrate 100.

[0179] As another example, please refer to Figure 5 The isolation structure 210 includes a third isolation layer 213, a first isolation layer 211, and a second isolation layer 212 sequentially disposed on the driving substrate 100. The orthographic projection of the first isolation layer 211 on the driving substrate 100 lies within the orthographic projection of the third isolation layer 213 on the driving substrate 100, and the orthographic projection of the first isolation layer 211 on the driving substrate 100 lies within the orthographic projection of the second isolation layer 212 on the driving substrate 100.

[0180] The light-emitting structure 220 is at least partially located within the isolation opening. The light-emitting structure 220 includes a light-emitting unit 221 and a first electrode 222.

[0181] The display panel may include various light-emitting structures 220 of different colors (such as red light-emitting structure 220, green light-emitting structure 220 and blue light-emitting structure 220). The light-emitting units 221 of the light-emitting structures 220 of different colors are made of different materials, so that they can emit different colors of light.

[0182] The first electrode 222 can be either a cathode or an anode.

[0183] The first electrode 222 covers the side of the light-emitting unit 221 away from the driving substrate 100. Simultaneously, the first electrode 222 is connected to the isolation structure 210. For example, the first electrode 222 may overlap with the sidewall of the isolation structure 210. The first electrodes 222 of each light-emitting structure 220 can be electrically connected through the isolation structure 210.

[0184] Meanwhile, the driving substrate 100 includes a first organic planarization layer 181. The first organic planarization layer 181 is located in the display area A1.

[0185] Furthermore, the first organic planarization layer 181 is located on the side of the driving layer 130 away from the substrate 110, and the isolation structure 210 is located on the side of the first organic planarization layer 181 away from the substrate 110. That is, the first organic planarization layer 181 is located between the driving layer 130 and the isolation structure 210.

[0186] At this time, the first organic planarization layer 181 is placed in the display area A1, not in the non-display area A2, so as to prevent the first organic planarization layer 181 from absorbing water in the non-display area A2 and affecting the performance of the isolation structure 210 in the display area A1.

[0187] During the formation of the first organic planarization layer 181, the first organic material layer can be formed over the entire surface first. Then, the first organic material layer located in the non-display area A2 is etched away, thereby forming the first organic planarization layer 181. During this process, if the first signal line 120 is positioned above the driving layer 130, the first signal line 120 may be covered by the first organic material layer. Therefore, when the first organic material layer is patterned and etched into the first organic planarization layer 181, a portion of the film layer of the first signal line 120 may be side-etched. For example, when the first signal line 120 includes a stacked titanium layer, an aluminum layer, and another titanium layer, the aluminum layer may be side-etched. This can lead to poor film formation on the sidewalls of the second inorganic encapsulation layer 300 formed subsequently. In this case, the second inorganic encapsulation layer 300 is prone to peeling or cracking during reliability testing or screen use, which can easily lead to corrosion problems (such as aluminum corrosion or aluminum migration) of the first signal line 120.

[0188] In this embodiment, the first signal line 120 is disposed on the side of the driving layer 130 away from the second inorganic encapsulation layer 300, so that the inorganic dielectric layer 140 can effectively prevent water, oxygen or metal ions from invading the first signal line 120, thereby effectively protecting the first signal line 120 from corrosion and other problems.

[0189] In this embodiment, the first signal line 120 may include, for example, a negative power supply line for providing a negative power supply voltage VSS.

[0190] Meanwhile, it can be understood that there may be multiple planarization layers between the driving layer 130 and the isolation structure 210, and the first organic planarization layer 181 in this embodiment may be at least a partial planarization layer.

[0191] In some embodiments, a third organic planarization layer 183 may also be included between the driving layer 130 and the isolation structure 210. The third organic planarization layer 183 may be located in both the display area A1 and the non-display area A2. Simultaneously, the third organic planarization layer in the non-display area A2 may be isolated by a dam 900 or similar structure to prevent water, oxygen, or metal ions from intruding into the display area A1. As an example, the third organic planarization layer 183 may be the topmost planarization layer near the pixel layer 200, and the first organic planarization layer 181 may be any other planarization layer below the third organic planarization layer 183.

[0192] In one embodiment, see Figure 4 The display panel also includes a first inorganic encapsulation layer 400. The first inorganic encapsulation layer includes a plurality of encapsulation units 410 spaced apart.

[0193] The encapsulation unit 410 is at least partially located within the area defined by the isolation opening and covers the side of the first electrode 222 away from the light-emitting unit 221.

[0194] During the manufacturing process of the display panel, after each color of light-emitting structure 220 is formed, an encapsulation unit 410 can be formed in the isolation opening corresponding to the light-emitting structure 220.

[0195] The orthographic projection of the second inorganic encapsulation layer 300 on the driving substrate 100 covers the orthographic projection of the first inorganic encapsulation layer and the isolation structure 210 on the driving substrate 100.

[0196] As an example, the display panel also includes an organic encapsulation layer 800.

[0197] The organic encapsulation layer 800 covers the first inorganic encapsulation layer and the isolation structure 210. The second inorganic encapsulation layer 300 covers the organic encapsulation layer 800. The surface of the organic encapsulation layer 800 away from the driving substrate 100 can be a flat surface, so that the second inorganic encapsulation layer 300 can be located on a flat surface.

[0198] As an example, pixel layer 200 also includes a second electrode 230. A corresponding set of second electrodes 230, light-emitting units 221, and first electrodes 222 form a sub-pixel.

[0199] The second electrode 230 is located between the first organic planarization layer 181 and the isolation structure 210. The isolation opening exposes the second electrode 230. The first electrode 222 can be configured as the cathode and the second electrode 230 as the anode. Alternatively, the first electrode 222 can be configured as the anode and the second electrode 230 as the cathode.

[0200] Optionally, the display panel further includes a pixel definition layer 500. The pixel definition layer 500 covers the surface of the second electrode 230 away from the driving substrate 100. The pixel definition layer 500 is configured to form a pixel opening.

[0201] Optionally, the orthographic projection of the pixel opening onto the substrate 110 lies within the orthographic projection of the isolation opening onto the substrate 110. The pixel opening communicates with the isolation opening and exposes at least a portion of the second electrode 230.

[0202] The pixel definition layer 500 may be made of inorganic materials, and the pixel definition layer 500 may extend from the display area A1 to the non-display area A2. In this case, the pixel definition layer 500 can enhance the encapsulation effect of the second inorganic encapsulation layer 300 in the non-display area A2.

[0203] In one embodiment, see Figure 1 The first signal line 120 may include a negative power supply line. The display panel also includes a polarizer 700. The polarizer 700 is located on the side of the second inorganic encapsulation layer 300 away from the pixel layer 200.

[0204] When the second inorganic encapsulation layer 300 peels off or cracks during reliability testing or screen use, potassium ions and other substances in the polarizer 700 may invade the negative power lines inside the display panel and corrode them.

[0205] In this embodiment, the first signal line 120 is disposed on the side of the driving layer 130 away from the second inorganic encapsulation layer 300. This allows the inorganic dielectric layer 140 to effectively prevent potassium ions and other particles in the polarizer 700 from invading the negative power line, thereby effectively protecting the first signal line 120 from corrosion and other problems.

[0206] In one embodiment, see Figure 4or Figure 5 A display panel is provided, including a driving substrate 100, a pixel layer 200, a first inorganic encapsulation layer 400 and a second inorganic encapsulation layer 300.

[0207] The driving substrate can be the driving substrate 100 as described in any of the above embodiments. The driving substrate 100 has a display area A1 and a non-display area A2.

[0208] The pixel layer 200 includes an isolation structure 210 and a plurality of light-emitting structures 220 spaced apart.

[0209] The isolation structure 210 is located on the side of the driving layer 130 away from the substrate 110. The isolation structure 210 is configured to form an isolation opening, which is located in the display area A1.

[0210] For example, please refer to Figure 4 The isolation structure 210 includes a first isolation layer 211 and a second isolation layer 212. The first isolation layer 211 is located on the side of the second isolation layer 212 closer to the driving substrate 100, and the orthographic projection of the first isolation layer 211 on the driving substrate 100 is located within the orthographic projection of the second isolation layer 212 on the driving substrate 100.

[0211] As another example, please refer to Figure 5 The isolation structure 210 includes a third isolation layer 213, a first isolation layer 211, and a second isolation layer 212 sequentially disposed on the driving substrate 100. The orthographic projection of the first isolation layer 211 on the driving substrate 100 lies within the orthographic projection of the third isolation layer 213 on the driving substrate 100, and the orthographic projection of the first isolation layer 211 on the driving substrate 100 lies within the orthographic projection of the second isolation layer 212 on the driving substrate 100.

[0212] The light-emitting structure 220 is at least partially located within the isolation opening.

[0213] The light-emitting structure 220 includes a light-emitting unit 221 and a first electrode 222. The first electrode 222 can be either a cathode or an anode.

[0214] The first electrode 222 covers the side of the light-emitting unit 221 away from the driving substrate 100. Simultaneously, the first electrode 222 is connected to the isolation structure 210. For example, the first electrode 222 may overlap with the sidewall of the isolation structure 210. The first electrodes 222 of each light-emitting structure 220 can be electrically connected through the isolation structure 210.

[0215] The first inorganic encapsulation layer 400 includes a plurality of encapsulation units 410 spaced apart.

[0216] The encapsulation unit 410 is at least partially located within the area defined by the isolation opening and covers the side of the first electrode 222 away from the light-emitting unit 221.

[0217] The second inorganic encapsulation layer 300 is located on the side of the pixel layer 200 away from the driving substrate 100, and its orthogonal projection on the driving substrate 100 covers the pixel layer 300 and the orthogonal projection of the first inorganic encapsulation layer 400 on the driving substrate 100.

[0218] Based on the same inventive concept, this application also provides a display device (not shown), which includes the display panel in the above embodiments.

[0219] It is understood that the display device in the embodiments of this application can be any product or component with display function, such as OLED display device, QLED display device, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, wearable device, Internet of Things device, etc., and the embodiments disclosed in this application do not limit this.

[0220] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0221] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0222] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A driving substrate, characterized in that, include: Substrate; The first signal line is located on the substrate; A driving layer, located on the side of the first signal line away from the substrate, includes multiple conductive layers, the multiple conductive layers forming at least a driving circuit; An inorganic dielectric layer is located between adjacent conductive layers and between the driving layer and the first signal line.

2. The driving substrate according to claim 1, characterized in that, The driving substrate has a display area and a non-display area, and the first signal line is located at least in the non-display area.

3. The driving substrate according to claim 2, characterized in that, The non-display area includes a transition area and a bend area, the transition area being located between the display area and the bend area, and the first signal line being at least partially located in the transition area.

4. The driving substrate according to any one of claims 1-3, characterized in that, The driving substrate includes: A shielding layer is located between the substrate and the driving layer, and includes a shielding pattern; Optionally, the first signal line is located in the shielding layer; Optionally, the first signal line includes a negative power supply line.

5. The driving substrate according to claim 4, characterized in that, The material of the first signal line is different from the material of the shielding pattern; Optionally, the impedance of the first signal line is less than the impedance of the shielding pattern; Optionally, the first signal line includes a stacked titanium layer, an aluminum layer, and a titanium layer, and / or the shielding pattern includes a molybdenum layer.

6. The driving substrate according to claim 4, characterized in that, The material of the first signal line is the same as the material of the shielding pattern; Optionally, both the first signal line and the shielding pattern include a layer of molybdenum, an aluminum layer, and a titanium layer stacked together.

7. The driving substrate according to claim 1, characterized in that, The driving substrate includes: A shielding layer is located between the substrate and the driving layer, and includes a shielding pattern; A first wiring layer includes the first signal line, and the first wiring layer is located between the shielding layer and the driving layer, and / or the first wiring layer is located between the shielding layer and the substrate.

8. The driving substrate according to claim 1, characterized in that, The substrate includes a first flexible layer, a first barrier layer, a second flexible layer, and a second barrier layer; Optionally, the second barrier layer includes a first sub-barrier layer and a second sub-barrier layer, wherein the material of the first sub-barrier layer is different from the material of the second sub-barrier layer; Optionally, the inorganic dielectric layer includes a third barrier layer that covers the first signal line and the second barrier layer, and the material of the third barrier layer is different from the material of the second sub-barrier layer; Optionally, the material of the third barrier layer and the material of the first sub-barrier layer both include silicon oxide, and / or the material of the second sub-barrier layer includes silicon nitride; Optionally, the inorganic medium layer further includes a buffer layer located between the third barrier layer and the driving layer.

9. The driving substrate according to claim 1, characterized in that, The driving substrate further includes: The second wiring layer includes a second signal line and is located on the side of the driving layer away from the substrate; Optionally, the second signal line includes any one or more of a positive power line, a data line, and a reference signal line.

10. The driving substrate according to claim 9, characterized in that, The inorganic dielectric layer is also located between the second wiring layer and the driving layer, and the plurality of conductive layers further form fan-out traces. The orthographic projection of the fan-out traces on the substrate overlaps with the orthographic projection of the first signal line on the substrate. The inorganic dielectric layer includes: A first dielectric layer is located between the first signal line and the fan-out trace; The second dielectric layer is located between the second wiring layer and the fan-out trace; Wherein, the thickness of the first dielectric layer is greater than or equal to the thickness of the second dielectric layer.

11. The driving substrate according to claim 1, characterized in that, The driving substrate further includes a planarization layer located on the side of the driving layer away from the substrate.

12. A display panel, characterized in that, include: The driving substrate according to any one of claims 1 to 11; The pixel layer is located on the side of the driving layer away from the substrate; The second inorganic encapsulation layer is located on the side of the pixel layer away from the driving substrate, and its orthogonal projection on the driving substrate covers the orthogonal projection of the pixel layer on the driving substrate.

13. The display panel according to claim 12, characterized in that, The driving substrate has a display area and a non-display area, and includes a first organic planarization layer. The first organic planarization layer is located on the side of the driving layer away from the substrate and is located in the display area. The pixel layer includes: An isolation structure is located on the side of the first organic planarization layer away from the substrate and is configured to form an isolation opening, the isolation opening being located in the display area; Multiple light-emitting structures are spaced apart, each light-emitting structure being at least partially located within the isolation opening. Each light-emitting structure includes a light-emitting unit and a first electrode, the first electrode covering the side of the light-emitting unit away from the driving substrate and connected to the isolation structure.

14. The display panel according to claim 13, characterized in that, The display panel further includes a first inorganic encapsulation layer, which includes a plurality of encapsulation units spaced apart. The encapsulation units are at least partially located within the area defined by the isolation opening and cover the side of the first electrode away from the light-emitting unit. The orthographic projection of the second inorganic encapsulation layer on the driving substrate covers the orthographic projections of the first inorganic encapsulation layer and the isolation structure on the driving substrate; Optionally, the display panel further includes an organic encapsulation layer that covers the first inorganic encapsulation layer and the isolation structure, and a second inorganic encapsulation layer that covers the organic encapsulation layer. Optionally, the pixel layer further includes a second electrode located between the first organic planarization layer and the isolation structure, and the isolation opening exposes the second electrode; Optionally, the display panel further includes a pixel definition layer that covers the surface of the second electrode away from the driving substrate and forms a pixel opening that communicates with the isolation opening and exposes at least a portion of the second electrode. Optionally, the orthographic projection of the pixel opening on the substrate lies within the orthographic projection of the isolation opening on the substrate.

15. The display panel according to claim 13, characterized in that, The isolation structure includes a first isolation layer and a second isolation layer. The first isolation layer is located on the side of the second isolation layer closer to the driving substrate, and the orthographic projection of the first isolation layer on the driving substrate is located within the orthographic projection of the second isolation layer on the driving substrate.

16. The display panel according to claim 13, characterized in that, The isolation structure includes a third isolation layer, a first isolation layer, and a second isolation layer arranged sequentially. The orthographic projection of the first isolation layer on the driving substrate is located within the orthographic projection of the second isolation layer on the driving substrate, and the orthographic projection of the first isolation layer on the driving substrate is located within the orthographic projection of the third isolation layer on the driving substrate. Optionally, the first insulating layer is made of aluminum, the second insulating layer is made of titanium, and the third insulating layer is made of molybdenum.

17. The display panel according to claim 12, characterized in that, The driving substrate has a display area and a non-display area, and includes a second organic planarization layer. The second organic planarization layer is located on the side of the driving layer away from the substrate and extends from the display area to the non-display area. The pixel layer includes: The second electrode is located on the side of the second organic planarization layer away from the substrate; A pixel definition layer covers the surface of the second electrode away from the substrate and is configured to form a pixel opening that exposes the second electrode; The isolation pillars are located on the pixel definition layer; The light-emitting unit is located within the pixel opening; The first electrode covers the pixel definition layer, the isolation pillar, and the light-emitting unit.

18. The display panel according to claim 12, characterized in that, The first signal line includes a negative power supply line, and the display panel also includes: The polarizer is located on the side of the second inorganic encapsulation layer away from the pixel layer.

19. A display panel, characterized in that, include: The driving substrate according to any one of claims 1 to 11, wherein the driving substrate has a display area and a non-display area; A pixel layer includes an isolation structure and a plurality of light-emitting structures spaced apart. The isolation structure is located on the side of the driving layer away from the substrate and forms an isolation opening. The isolation opening is located in the display area. The light-emitting structures are at least partially located within the isolation opening. Each light-emitting structure includes a light-emitting unit and a first electrode. The first electrode covers the side of the light-emitting unit away from the driving substrate and is connected to the isolation structure. The first inorganic encapsulation layer includes a plurality of encapsulation units spaced apart, wherein the encapsulation units are at least partially located within the area defined by the isolation opening and cover the side of the first electrode away from the light-emitting unit; The second inorganic encapsulation layer is located on the side of the pixel layer away from the driving substrate, and its orthogonal projection on the driving substrate covers the pixel layer and the orthogonal projection of the first inorganic encapsulation layer on the driving substrate.

20. A display device, characterized in that, Includes the display panel as described in any one of claims 12-19.

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