Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof, and relates to the technical field of semiconductors. Compared with a traditional semiconductor structure, the application divides a source region into three sub-regions, and a second doped region is arranged between the first sub-region and the second sub-region and between the second sub-region and the third sub-region in a second direction, the doping concentration of the second doped region is smaller than the doping concentration of the source region, and the doping height of the second doped region is smaller than the doping height of the source region in a direction perpendicular to the substrate. When the semiconductor structure is short-circuited, the arrangement of the second doped region is equivalent to introducing resistance into the semiconductor structure, the short-circuit bearing capacity of the structure is improved, and the possibility of structure damage is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) have been widely used in new energy vehicles, renewable energy power generation, photovoltaics, energy storage systems, rail transportation, and smart grids due to their excellent performance, such as high voltage resistance, high temperature resistance, low on-resistance, and high switching frequency.

[0003] However, under short-circuit conditions, due to the high current density and rapid heat rise of SiC MOSFETs, their short-circuit withstand capability is weak, making them extremely prone to device damage or even the burnout of the entire electrical equipment.

[0004] Therefore, improving the short-circuit time of devices has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] Therefore, it is necessary to provide a semiconductor structure and its fabrication method for improving the short-circuit time of the device.

[0006] To achieve the above objectives, in one respect, the present invention provides a method for preparing a semiconductor structure, comprising:

[0007] A substrate is provided, the substrate having a first doping type;

[0008] An epitaxial structure is formed on one side of the substrate. The epitaxial structure includes a drift region, a well region, a source region, a first doped region, and a second doped region. The well region is located on the side of the drift region away from the substrate. The source region, the first doped region, and the second doped region are located on the side of the well region away from the drift region. The source region includes a first sub-region, a second sub-region, and a third sub-region. The first sub-region and the third sub-region extend in a first direction and are disposed opposite each other in a second direction. A plurality of first doped regions are disposed in the epitaxial structure between the first sub-region and the third sub-region, spaced apart in the first direction. In the first direction, the second sub-region and the second doped region are located between two adjacent first doped regions. In the second direction, the second doped region is located on both sides of the second sub-region. The drift region, the source region, and the second doped region have the first doping type. The first doped region has the second doping type. The doping concentration of the second doped region is less than the doping concentration of the source region. In the direction perpendicular to the substrate, the doping height of the second doped region is less than the doping height of the source region. The first direction and the second direction are parallel to the substrate and intersect each other.

[0009] A gate structure is formed on the side of the epitaxial structure away from the substrate. The gate structure is located between the well regions in the second direction, covers a portion of the well regions and the source region, and extends in the first direction.

[0010] In one embodiment, forming an epitaxial structure on one side of the substrate includes:

[0011] An epitaxial initial layer is formed on one side of the substrate;

[0012] A first patterned mask layer is formed on the side of the epitaxial initial layer away from the substrate. The first patterned mask layer includes a first opening that extends in a first direction and is spaced apart in a second direction.

[0013] Based on the first patterned mask layer, a first ion implantation is performed on the epitaxial initial layer from the side of the epitaxial initial layer away from the substrate to form a first initial well region, and the remaining epitaxial initial layer forms the drift region;

[0014] A second patterned mask layer is formed within the first opening of the first patterned mask layer. The second patterned mask layer includes a second opening and a third opening, which extend in the first direction and are spaced apart in the second direction.

[0015] Based on the second patterned mask layer, a second ion implantation is performed on the first initial well region from the side of the epitaxial initial layer away from the substrate, forming the first sub-region in the first initial well region exposed by the second opening, forming the third sub-region in the first initial well region exposed by the third opening, and forming the second initial well region with the remaining first initial well region.

[0016] Remove the first patterned mask layer and the second patterned mask layer.

[0017] In one embodiment, after removing the first patterned mask layer and the second patterned mask layer, the process includes:

[0018] A third patterned mask layer is formed on the side of the epitaxial initial layer away from the substrate. The third patterned mask layer includes a fourth opening that exposes the second initial well region between the first sub-region and the second sub-region in the second direction, and the fourth opening is spaced apart in the first direction.

[0019] Based on the third patterned mask layer, a third ion implantation is performed on the second initial well region from the side of the epitaxial initial layer away from the substrate to form a second doped initial region, and the remaining second initial well region forms a third initial well region.

[0020] In one embodiment, after performing a third ion implantation on the second initial well region from the side of the epitaxial initial layer away from the substrate based on the third patterned mask layer, the process includes:

[0021] A fourth patterned mask layer is formed within the fourth opening of the third patterned mask layer. The fourth patterned mask layer includes a fifth opening, and the orthographic projection of the fifth opening on the substrate is located within the orthographic projection of the fourth opening on the substrate.

[0022] Based on the fourth patterned mask layer, a fourth ion implantation is performed on the second doped initial region from the side of the epitaxial initial layer away from the substrate to form the second sub-region, and the remaining third initial well region forms the fourth initial well region.

[0023] Remove the third patterned mask layer and the fourth patterned mask layer.

[0024] In one embodiment, after removing the third patterning mask layer and the fourth patterning mask layer, the process includes:

[0025] A fifth patterned mask layer is formed on the side of the epitaxial initial layer away from the substrate. The fifth patterned mask layer includes a sixth opening that exposes the fourth initial well region located between the first sub-region and the second sub-region in the second direction, and the sixth opening is spaced apart in the first direction.

[0026] Based on the fifth patterned mask layer, a fifth ion implantation is performed on the fourth initial well region from the side of the epitaxial initial layer away from the substrate to form the first doped region, the remaining second doped initial region forms the second doped region, and the remaining fourth initial well region forms the well region.

[0027] Remove the fifth patterned mask layer.

[0028] In one embodiment, forming a gate structure on the side of the epitaxial structure away from the substrate includes:

[0029] A gate oxide layer is formed on the side of the epitaxial structure away from the substrate;

[0030] A gate is formed on the side of the gate oxide layer away from the epitaxial structure.

[0031] In one embodiment, after forming the gate structure on the side of the epitaxial structure away from the substrate, the process includes:

[0032] A dielectric layer is formed on the side of the gate structure away from the epitaxial structure, the dielectric layer exposing the epitaxial structure between the first sub-region and the second sub-region.

[0033] In one embodiment, after forming a dielectric layer on the side of the gate structure away from the epitaxial structure, the process includes:

[0034] A source electrode is formed on the dielectric layer and on the exposed side of the epitaxial structure away from the substrate;

[0035] A drain electrode is formed on the side of the substrate away from the epitaxial structure.

[0036] In one embodiment, after forming the source on the dielectric layer and the exposed epitaxial structure on the side away from the substrate, the process includes:

[0037] A passivation layer is formed on the side of the source electrode away from the epitaxial structure. The passivation layer includes a first passivation layer and a second passivation layer sequentially disposed in a direction perpendicular to the substrate.

[0038] On the other hand, a semiconductor structure is also provided, including:

[0039] Substrate, the substrate having a first doping type;

[0040] An epitaxial structure is located on one side of the substrate. The epitaxial structure includes a drift region, a well region, a source region, a first doped region, and a second doped region. The well region is located on the side of the drift region away from the substrate. The source region, the first doped region, and the second doped region are located on the side of the well region away from the drift region. The source region includes a first sub-region, a second sub-region, and a third sub-region. The first sub-region and the third sub-region extend in a first direction and are disposed opposite each other in a second direction. A plurality of first doped regions are disposed in the epitaxial structure between the first sub-region and the third sub-region, spaced apart in the first direction. In the first direction, the second sub-region and the second doped region are located between two adjacent first doped regions, and in the second direction, the second doped region is located on both sides of the second sub-region. The drift region, the source region, and the second doped region have the first doping type, and the first doped region has the second doping type. The doping concentration of the second doped region is less than the doping concentration of the source region. In the direction perpendicular to the substrate, the doping height of the second doped region is less than the doping height of the source region. The first direction and the second direction are parallel to the substrate and intersect each other.

[0041] A gate structure is located on the side of the epitaxial structure away from the substrate.

[0042] Compared with existing technologies, the above technical solution has the following advantages:

[0043] In this semiconductor structure and its fabrication method, a substrate with a first conductivity type is first provided. An epitaxial structure is then formed on the substrate, and a gate structure is formed on the side of the epitaxial structure away from the substrate to form the semiconductor structure. The epitaxial structure includes a drift region, a well region, a source region, a first doped region, and a second doped region. The drift region, source region, and second doped region all have a first doping type, and the first doped region has a second doping type. The well region is located on the side of the drift region away from the substrate and surrounds the source region, the first doped region, and the second doped region. The source region includes a first sub-region, a second sub-region, and a third sub-region. The first and third sub-regions extend along a first direction and are positioned opposite each other along a second direction. The second sub-region is located between the first and third sub-regions in the second direction. A first doped region is also disposed between the first and third sub-regions. In the first direction, the second sub-region and the second doped region are located between adjacent first doped regions, and in the second direction, the second doped region is located on both sides of the second sub-region.

[0044] At this point, compared to the traditional semiconductor structure, this application divides the source region into three sub-regions, and in the second direction, a second doped region is set between the first sub-region and the second sub-region, and between the second sub-region and the third sub-region. The doping concentration of the second doped region is less than that of the source region, and in the direction perpendicular to the substrate, the doping height of the second doped region is less than that of the source region. When the semiconductor structure is short-circuited, the setting of the second doped region is equivalent to introducing resistance into the semiconductor structure, which improves the short-circuit withstand capability of the structure and reduces the possibility of structural damage. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application;

[0047] Figure 2 This is a schematic diagram of the structure of forming an epitaxial initial layer on a substrate according to an embodiment of this application;

[0048] Figure 3This is a schematic diagram of the structure for forming the first initial well region provided in an embodiment of this application;

[0049] Figure 4 A top view of the structure forming the first sub-region and the second sub-region provided in an embodiment of this application;

[0050] Figure 5 for Figure 4 Schematic diagram of the cross-sectional structure along AA';

[0051] Figure 6 This is a top view of the structure for forming the second doped initial region provided in an embodiment of this application;

[0052] Figure 7 for Figure 6 Schematic diagram of the cross-sectional structure along BB';

[0053] Figure 8 A top view of the structure forming the third sub-region provided in an embodiment of this application;

[0054] Figure 9 for Figure 8 Schematic diagram of the cross-sectional structure along CC';

[0055] Figure 10 This is a top view of the structure forming the first doped region provided in an embodiment of this application;

[0056] Figure 11 for Figure 10 Schematic diagram of the cross-sectional structure along DD';

[0057] Figure 12 This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this application.

[0058] Explanation of reference numerals in the attached figures: Substrate 01; Epitaxial structure 02; Initial epitaxial layer 02a; Drift region 021; Well region 022; First initial well region 022a; Second initial well region 022b; Third initial well region 022c; Source region 023; First sub-region 0231; Second sub-region 0232; Third sub-region 0233; First doped region 024; Second doped region 025; Second initial doped region 025a; Gate structure 03; Gate oxide layer 031; Gate 032; First patterned mask layer 04; First opening 041; Second patterned mask layer 05; Second opening 051; Third opening 052; Sidewall mask 053; Center mask 054; Third patterned mask layer 06; Fourth opening 061; Fourth patterned mask layer 07; Fifth opening 071; Fifth patterned mask layer 08; Sixth opening 081; Dielectric layer 09; Source 10; Drain 11; First direction Y; Second direction X. Detailed Implementation

[0059] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0061] It should be understood that when a layer is referred to as "on," "adjacent to," or "connected to" other layers, it can be directly on, adjacent to, or connected to other layers, or there can be intervening layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," or "directly connected to" other layers, there are no intervening layers.

[0062] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0063] To make the objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0064] refer to Figure 1 , Figure 1 This application provides a schematic flowchart of a method for fabricating a semiconductor structure; the fabrication steps include:

[0065] S10: Provide substrate 01, substrate 01 having a first doping type (e.g., ... Figure 2 (As shown).

[0066] In this step, the substrate 01 provided can be a silicon carbide substrate, and the doping type of the silicon carbide substrate is N-type doped.

[0067] S20: An epitaxial structure 02 is formed on one side of the substrate 01 (e.g., Figure 12 (As shown).

[0068] The epitaxial structure 02 includes a drift region 021, a well region 022, a source region 023, a first doped region 024, and a second doped region 025. The well region 022 is located on the side of the drift region 021 away from the substrate 01. The source region 023, the first doped region 024, and the second doped region 025 are located on the side of the well region 022 away from the drift region 021. The source region 023 includes a first sub-region 0231, a second sub-region 0232, and a third sub-region 0233. The first sub-region 0231 and the third sub-region 0233 extend in the first direction Y and are disposed opposite each other in the second direction X. The epitaxial structure 02 between the first sub-region 0231 and the third sub-region 0233 is provided with a doped region in the first direction X. Multiple first doped regions 024 are spaced apart on the Y-axis. In the first direction Y, a second sub-region 0232 and a second doped region 025 are located between two adjacent first doped regions 024, and in the second direction X, the second doped region 025 is located on both sides of the second sub-region 0232. The drift region 021, the source region 023, and the second doped region 025 have a first doping type, and the first doped regions 024 have a second doping type. The doping concentration of the second doped region 025 is less than that of the source region 023. In the direction perpendicular to the substrate 01, the doping height of the second doped region 025 is less than that of the source region 023. The first direction Y and the second direction X are parallel to the substrate 01 and intersect (e.g., ...). Figure 4 (As shown).

[0069] In this step, the material used to form the epitaxial structure 02 on one side of the substrate 01 is silicon carbide.

[0070] The epitaxial structure 02 can be formed by multiple doping processes to create a drift region 021, a well region 022, a source region 023, a first doped region 024, and a second doped region 025. Among them, the drift region 021, the source region 023, and the second doped region 025 have a first doping type, which is N-type doping, and the first doped region 024 has a second doping type, which is P-type doping.

[0071] Well region 022 is located on the side of drift region 021 away from substrate 01, surrounding source region 023, first doped region 024, and second doped region 025. Source region 023 is located on the side of well region 022 away from drift region 021, and source region 023 includes first sub-region 0231, second sub-region 0232, and third sub-region 0233. First sub-region 0231 and third sub-region 0233 extend along a first direction Y and are arranged opposite to each other along a second direction X, i.e., spaced apart. It should be noted that first sub-region 0231 and third sub-region 0233 are formed simultaneously, while second sub-region 0232 is formed later.

[0072] Within the epitaxial structure 02 between the first sub-region 0231 and the third sub-region 0233, first doped regions 024 are arranged at Y-intervals in the first direction. Second sub-regions 0232 and 025 are also disposed between adjacent first doped regions 024. In the second direction X, the second doped regions 025 are located on both sides of the second sub-region 0232. It should be noted that the doping height of the source region 023 and the second doped region 025 in the direction perpendicular to the substrate 01 is less than the doping height of the well region 022 in the direction perpendicular to the substrate 01. Furthermore, the doping height of the second doped region 025 in the direction perpendicular to the substrate 01 is less than the doping height of the source region 023 in the direction perpendicular to the substrate 01.

[0073] It should also be noted that the first direction Y and the second direction X are parallel to the substrate 01. In this embodiment, the first direction Y and the second direction X may intersect perpendicularly.

[0074] The source region 023 is N+ doped, and the second doped region 025 is N- doped. In this case, the second doped region 025 separates the source region 023. Compared with the traditional source region 023, this application introduces a second doped region 025, which introduces a resistor. When the SiC MOSFET is short-circuited, the short-circuit withstand capability of the structure is improved, reducing the possibility of structural damage.

[0075] S30: A gate structure 03 is formed on the side of the epitaxial structure 02 away from the substrate 01 (e.g., Figure 12 (As shown).

[0076] The gate structure 03 is located between the well regions 022 in the second direction X, covers part of the well region 022 and the source region 023, and extends in the first direction Y.

[0077] In this step, a gate structure 03 is also provided on the side of the epitaxial structure 02 away from the substrate 01. The gate structure 03 is used to switch the semiconductor structure.

[0078] In this embodiment, compared to a conventional semiconductor structure, the source region 023 is divided into three sub-regions. A second doped region 025 is provided in the second direction X, between the first sub-region 0231 and the second sub-region 0232, and between the second sub-region 0232 and the third sub-region 0233. The doping concentration of the second doped region 025 is less than that of the source region 023, and the doping height of the second doped region 025 is less than that of the source region 023 in the direction perpendicular to the substrate 01. When the semiconductor structure is short-circuited, the provision of the second doped region 025 is equivalent to introducing resistance into the semiconductor structure, improving the short-circuit withstand capability of the structure and reducing the possibility of structural damage.

[0079] In another embodiment of this application, an epitaxial structure 02 is formed on one side of the substrate 01, including:

[0080] S201: An epitaxial initial layer 02a is formed on one side of the substrate 01 (e.g., ...). Figure 2 (As shown).

[0081] In this step, an N-type doped silicon carbide epitaxial layer with nitrogen as the dopant can be provided first. Then, ion implantation is performed on the N-type doped silicon carbide epitaxial layer to form a transition layer (JFET layer) (not shown), which is used to adjust the carrier flow path, control the electric field distribution, and affect the on-resistance and breakdown voltage. The implantation method is plain implantation (i.e., implantation of the entire wafer without patterning), and the implanted element is nitrogen, with a doping concentration ranging from 1E16cm. -3 ~1E18cm -3 This includes endpoint values.

[0082] At this point, an epitaxial initial layer 02a with the first doping type is formed on one side of the substrate 01. The doping element of the epitaxial initial layer 02a can be nitrogen. It should be noted that the thickness and doping concentration of the epitaxial structure 02 required for devices with different performance characteristics are different. For example, the thickness of the epitaxial structure 02 for a 1200V device can range from 10μm to 12μm, and the doping concentration can range from 1E16 to 2E16cm. -3 This includes endpoint values.

[0083] S202: A first patterned mask layer 04 is formed on the side of the epitaxial initial layer 02a away from the substrate 01. The first patterned mask layer 04 includes a first opening 041, which extends in the first direction Y and is spaced apart in the second direction X (e.g., ...). Figure 3 (As shown).

[0084] In this step, a first patterned mask layer 04 is formed on one side of the epitaxial initial layer 02a. A silicon dioxide hard mask layer can be formed on one side of the epitaxial initial layer 02a first, and then photolithography and dry etching processes are performed to form the first patterned mask layer 04.

[0085] The first patterned mask layer 04 may include a first opening 041, which extends in the first direction Y and is spaced apart in the second direction X, thus exposing the locations where the well regions 022 will be formed subsequently. In other words, the well regions 022 may include multiple wells. Figure 3 Only one is shown in the image.

[0086] S203: Based on the first patterned mask layer 04, the epitaxial initial layer 02a is implanted with ions from the side away from the substrate 01 to form the first initial well region 022a. The remaining epitaxial initial layer 02a forms the drift region 021 (e.g., ...). Figure 3 (As shown).

[0087] In this step, based on the first patterned mask layer 04, a first ion implantation is performed on the epitaxial initial layer 02a. This first ion implantation is a high-temperature ion implantation. It should be noted that the doping element used in the first ion implantation is aluminum, and the doping concentration can range from 1E16cm⁻¹. -3 -1E17cm -3 This includes endpoint values.

[0088] S204: A second patterned mask layer 05 is formed within the first opening 041 of the first patterned mask layer 04. The second patterned mask layer 05 includes a second opening 051 and a third opening 052, which extend in the first direction Y and are spaced apart in the second direction X (e.g., ...). Figure 4 , Figure 5 (As shown).

[0089] In this step, the first patterned mask layer 04 is not removed, and the second patterned mask layer 05 is formed directly in the first opening 041 of the first patterned mask layer 04. At this time, a silicon dioxide hard mask layer is formed in the first opening 041, and then photolithography and dry etching processes are performed to form the second patterned mask layer 05.

[0090] It should be noted that the second patterned mask layer 05 includes a second opening 051 and a third opening 052, which divide the second patterned mask layer 05 into a sidewall mask 053 near the first patterned mask layer 04 and a center mask 054 located in the central area. The second opening 051 and the third opening 052 extend in the first direction Y and are spaced apart in the second direction X.

[0091] S205: Based on the second patterned mask layer 05, a second ion implantation is performed on the first initial well region 022a from the side of the epitaxial initial layer 02a away from the substrate 01. A first sub-region 0231 is formed in the first initial well region 022a exposed by the second opening 051, and a third sub-region 0233 is formed in the first initial well region 022a exposed by the third opening 052. The remaining first initial well region 022a forms the second initial well region 022b (e.g., ...). Figure 4 , Figure 5 (As shown).

[0092] In this step, based on the second patterned mask layer 05, a second ion implantation is performed on the first initial well region 022a from the side of the epitaxial initial layer 02a away from the substrate 01. This second ion implantation is a high-temperature ion implantation. It should be noted that the doping element used in the first ion implantation can be nitrogen or phosphorus, and the doping concentration can range from 1E19cm⁻¹. -3 -1E21cm -3 This includes endpoint values.

[0093] It should be noted that a first sub-region 0231 is formed within the first initial well region 022a exposed by the second opening 051, and a third sub-region 0233 is formed within the first initial well region 022a exposed by the third opening 052. The first sub-region 0231 and the second sub-region 0232 are doped in the same way and simultaneously. The remaining first initial well region 022a forms the second initial well region 022b.

[0094] S206: Remove the first patterned mask layer 04 and the second patterned mask layer 05.

[0095] Subsequently, wet etching was used to remove the first patterned mask layer 04 and the second patterned mask layer 05.

[0096] In this embodiment, the second patterned mask layer 05 is formed directly on the basis of the first patterned mask layer 04, which saves the material of the mask layer.

[0097] In another embodiment of this application, after removing the first patterned mask layer 04 and the second patterned mask layer 05, the process includes:

[0098] S207: A third patterned mask layer 06 is formed on the side of the epitaxial initial layer 02a away from the substrate 01. The third patterned mask layer 06 includes a fourth opening 061, which exposes the second initial well region 022b between the first sub-region 0231 and the second sub-region 0232 in the second direction X. The fourth openings 061 are spaced apart in the first direction Y (e.g., ...). Figure 6 , Figure 7 (As shown).

[0099] In this step, a third patterned mask layer 06 is formed on the side of the epitaxial initial layer 02a away from the substrate 01. A silicon dioxide hard mask layer can be formed on one side of the epitaxial initial layer 02a first, and then photolithography and dry etching processes are performed to form the third patterned mask layer 06.

[0100] S208: Based on the third patterned mask layer 06, a third ion implantation is performed on the second initial well region 022b from the side of the epitaxial initial layer 02a away from the substrate 01 to form the second doped initial region 025a. The remaining second initial well region 022b forms the third initial well region 022c (e.g., ...). Figure 6 , Figure 7 (As shown).

[0101] In this step, based on the third patterned mask layer 06, a third ion implantation is performed on the second initial well region 022b from the side of the epitaxial initial layer 02a away from the substrate 01. The third ion implantation is a high-temperature ion implantation. It should be noted that the doping element used in the first ion implantation can be nitrogen or phosphorus, and the doping concentration can be in the range of 1E18cm⁻¹. -3 -1E20cm-3 This includes endpoint values.

[0102] After the third ion implantation, the second initial doped region 025a is formed, and the remaining second initial well region 022b forms the third initial well region 022c. At this time, the second initial doped region 025a is the N-doped region.

[0103] In this embodiment, a second initial doping region 025a is formed based on the third patterned mask layer 06, that is, a resistor is introduced into the semiconductor structure, which provides a basis for improving the short-circuit withstand capability of the semiconductor structure in the future.

[0104] In another embodiment of this application, after performing a third ion implantation on the second initial well region 022b from the side of the epitaxial initial layer 02a away from the substrate 01, based on the third patterned mask layer 06, the process includes:

[0105] S209: A fourth patterned mask layer 07 is formed within the fourth opening 061 of the third patterned mask layer 06. The fourth patterned mask layer 07 includes a fifth opening 071, and the orthographic projection of the fifth opening 071 onto the substrate 01 lies within the orthographic projection of the fourth opening 061 onto the substrate 01 (e.g., ...). Figure 8 , Figure 9 (As shown).

[0106] In this step, the third patterned mask layer 06 is not removed, and the fourth patterned mask layer 07 is directly formed in the fourth opening 061 of the third patterned mask layer 06. At this time, a silicon dioxide hard mask layer is formed in the fourth opening 061, and then photolithography and dry etching processes are performed to form the fourth patterned mask layer 07.

[0107] It should be noted that the fourth patterned mask layer 07 includes a fifth opening 071, and the orthographic projection of the fifth opening 071 onto the substrate 01 lies within the orthographic projection of the fourth opening 061 onto the substrate 01. That is, the area of ​​the fifth opening 071 is smaller than the area of ​​the fourth opening 061.

[0108] S210: Based on the fourth patterned mask layer 07, the second doped initial region 025a is implanted with fourth ions from the side of the epitaxial initial layer 02a away from the substrate 01 to form the second sub-region 0232. The remaining third initial well region 022c forms the fourth initial well region 022d (e.g., ...). Figure 8 , Figure 9 (As shown).

[0109] In this step, based on the fourth patterned mask layer 07, a fourth ion implantation is performed on the second doped initial region 025a from the side of the epitaxial initial layer 02a away from the substrate 01. This fourth ion implantation is a high-temperature ion implantation. It should be noted that the doping element used for the fourth ion implantation can be nitrogen or phosphorus, and the doping concentration can range from 1E19cm⁻¹.-3 -1E21cm -3 This includes endpoint values.

[0110] At this point, the area of ​​the second sub-region 0232 is smaller than the area of ​​the first doped region 024, meaning that the first doped region 024 surrounds the second sub-region 0232, and the remaining third initial well region 022c forms the fourth initial well region 022d.

[0111] S211: Remove the third patterned mask layer 06 and the fourth patterned mask layer 07.

[0112] Subsequently, wet etching was used to remove the third patterned mask layer 06 and the fourth patterned mask layer 07.

[0113] In this embodiment, the fourth patterned mask layer 07 is formed on the basis of the third patterned mask layer 06, which can save the material of the mask layer and reduce the removal steps in the preparation process.

[0114] In another embodiment of this application, after removing the third patterned mask layer 06 and the fourth patterned mask layer 07, the process includes:

[0115] S212: A fifth patterned mask layer 08 is formed on the side of the epitaxial initial layer 02a away from the substrate 01. The fifth patterned mask layer 08 includes a sixth opening 081, which exposes a fourth initial well region 022d located between the first sub-region 0231 and the second sub-region 0232 in the second direction X. The sixth openings 081 are spaced apart in the first direction Y (e.g., ...). Figure 10 , Figure 11 (As shown).

[0116] In this step, a silicon dioxide hard mask layer can be formed on the side of the epitaxial initial layer 02a away from the substrate 01, and then a fifth patterned mask layer 08 can be formed by photolithography and dry etching processes.

[0117] S213: Based on the fifth patterned mask layer 08, fifth ion implantation is performed on the fourth initial well region 022d from the side of the epitaxial initial layer 02a away from the substrate 01 to form the first doped region 024. The remaining second doped initial region 025a forms the second doped region 025, and the remaining fourth initial well region 022d forms the well region 022 (e.g., ...). Figure 10 , Figure 11 (As shown).

[0118] In this step, based on the fifth patterned mask layer 08, a fifth ion implantation is performed on the fourth initial well region 022d from the side of the epitaxial initial layer 02a away from the substrate 01 to form the first doped region 024. Due to ion diffusion during doping, the first doped region 024 will partially cover the second doped initial region 025a. At this time, the remaining second doped initial region 025a forms the second doped region 025, and the remaining fourth initial well region 022d forms the well region 022, completing the doping of the epitaxial structure 02.

[0119] It should be noted that the fifth ion implantation can use aluminum as the doping element, and the doping concentration can range from 1E20cm⁻¹. -3 -1E21cm -3 This includes endpoint values.

[0120] S215: Remove the fifth patterned mask layer 08.

[0121] Then, the fifth patterned mask layer 08 can be removed using a wet process to form the subsequent structure.

[0122] It should be noted that after ion implantation, a carbon film can be formed on the side of the epitaxial structure 02 away from the substrate 01, and then high-temperature ion activation can be performed. The high-temperature activation temperature can be 1750°C, the time can be 30 minutes, and it can be performed in an Ar atmosphere.

[0123] A sacrificial oxide layer is then formed using an oxidation process, which is followed by wet etching to remove the oxide layer and eliminate surface damage, thereby improving the yield of the device.

[0124] In another embodiment of this application, a gate structure 03 is formed on the side of the epitaxial structure 02 away from the substrate 01, including:

[0125] S301: A gate oxide layer 031 is formed on the side of the epitaxial structure 02 away from the substrate 01;

[0126] S302: Gate 032 is formed on the side of gate oxide layer 031 away from epitaxial structure 02 (e.g., Figure 12 (As shown).

[0127] Specifically, the gate structure 03 includes a gate oxide layer 031 and a gate 032. The material of the gate oxide layer 031 can be silicon dioxide, and the material of the gate 032 can be polysilicon.

[0128] When fabricating the gate oxide layer 031, a gate oxide material layer can be formed using high-temperature thermal oxidation or chemical vapor deposition processes. Then, a gate material layer is formed on one side of the gate oxide material layer using low-pressure chemical vapor deposition. The gate material layer can be formed in a silane atmosphere at 620°C. Subsequently, the gate oxide material layer and the gate material layer between the first sub-region 0231 and the second sub-region 0232 of different well regions 022 in the second direction X are removed using photolithography and dry etching processes. The remaining gate oxide material layer serves as gate oxide layer 031, and the remaining gate material layer serves as gate 032.

[0129] In another embodiment of this application, after forming the gate structure 03 on the side of the epitaxial structure 02 away from the substrate 01, the process includes:

[0130] A dielectric layer 09 is formed on the side of the gate structure 03 away from the epitaxial structure 02, and the dielectric layer 09 exposes the epitaxial structure 02 between the first sub-region 0231 and the second sub-region 0232 (e.g., Figure 12 (As shown).

[0131] Specifically, after forming the gate structure 03, a dielectric material layer is formed on the side of the gate structure 03 away from the epitaxial structure 02 using a chemical vapor deposition process. The material of the dielectric material layer can be silicon dioxide, phosphorus-doped silicon dioxide, or boron- and phosphorus-doped silicon dioxide, etc.

[0132] Then, photolithography and dry etching processes are used to etch away part of the dielectric material layer to form dielectric layer 09. At this time, dielectric layer 09 exposes the epitaxial structure 02 between the first sub-region 0231 and the second sub-region 0232, which forms a contact hole for the subsequent source electrode 10.

[0133] Subsequently, an ohmic contact layer can be formed on one side of the epitaxial structure 02 exposed by the dielectric layer 09. Before forming the source 10, a metal layer can be sputtered on the side of the epitaxial structure 02 exposed by the dielectric layer 09 that is away from the substrate 01, and then the ohmic contact layer is formed after two annealing processes. The material of this metal can be Ni, Pt, nickel-platinum alloy, etc., and there is no specific limitation. The above materials are only examples.

[0134] It should be noted that the first annealing temperature can be 750°C, the time can be 5 minutes, and it can be performed in an N2 atmosphere. After the first annealing, unreacted metal can be removed by wet etching, and then a second annealing can be performed to form a metal silicide with low contact resistance. The second annealing temperature can be 950°C, the time can be 3 minutes, and it can be performed in an N2 atmosphere.

[0135] After annealing, metal silicides, or ohmic contact layers, are formed on the surface of silicon carbide. The low-resistance ohmic contacts can significantly reduce the heat dissipation generated by the semiconductor structure during operation, improve the efficiency and reliability of the semiconductor structure, and also help to reduce the size and weight of the semiconductor structure.

[0136] In another embodiment of this application, after forming a dielectric layer 09 on the side of the gate structure 03 away from the epitaxial structure 02, the following steps are included:

[0137] A source electrode 10 is formed on the side of the dielectric layer 09 and the exposed epitaxial structure 02 away from the substrate 01;

[0138] A drain 11 is formed on the side of substrate 01 away from epitaxial structure 02 (e.g. Figure 12 (As shown).

[0139] Specifically, after forming the ohmic contact layer, a source electrode 10 is formed on the side of the dielectric layer 09, the ohmic contact layer, and the epitaxial structure 02 away from the substrate 01. The source electrode 10 can be formed by physical vapor deposition (PVD), for example, by sequentially depositing an Al layer as the source electrode 10.

[0140] In addition, the side of the substrate 01 away from the epitaxial structure 02 can be thinned first, and then nickel can be sputtered to form an ohmic contact. Then, metals such as titanium, nickel, and silver can be used for the evaporation of the drain electrode 11.

[0141] In another embodiment of this application, after forming the source 10 on the side of the dielectric layer 09 and the exposed epitaxial structure 02 away from the substrate 01, the process includes:

[0142] A passivation layer is formed on the side of the source electrode 10 away from the epitaxial structure 02. The passivation layer includes a first passivation layer and a second passivation layer (not shown) sequentially disposed in a direction perpendicular to the substrate 01.

[0143] Specifically, a first passivation layer is deposited on the side of the source electrode 10 away from the epitaxial structure 02 by plasma chemical vapor deposition. It should be noted that the material of the first passivation layer can be SiN. Then, photolithography and dry etching are used to form the required pattern.

[0144] Then, a second passivation layer is formed through processes such as coating, exposure, development, and curing. The second passivation layer can be a polyimide passivation layer.

[0145] In this embodiment, the passivation layer can protect the device and improve the yield.

[0146] In another embodiment of this application, a semiconductor structure is also provided, comprising:

[0147] Substrate 01, substrate 01 has a first doping type;

[0148] Epitaxial structure 02 is located on one side of substrate 01. Epitaxial structure 02 includes a drift region 021, a well region 022, a source region 023, a first doped region 024, and a second doped region 025. The well region 022 is located on the side of the drift region 021 away from substrate 01. The source region 023, the first doped region 024, and the second doped region 025 are located on the side of the well region 022 away from the drift region 021. The source region 023 includes a first sub-region 0231, a second sub-region 0232, and a third sub-region 0233. The first sub-region 0231 and the third sub-region 0233 extend in the first direction Y and are disposed opposite each other in the second direction X. The epitaxial structure 02 between the first sub-region 0231 and the third sub-region 0233 is within... A plurality of first doped regions 024 are arranged at intervals in the first direction Y. In the first direction Y, the second sub-region 0232 and the second doped region 025 are located between two adjacent first doped regions 024, and in the second direction X, the second doped region 025 is located on both sides of the second sub-region 0232. The drift region 021, the source region 023 and the second doped region 025 have a first doping type, the first doped region 024 have a second doping type, the doping concentration of the second doped region 025 is less than the doping concentration of the source region 023, and in the direction perpendicular to the substrate 01, the doping height of the second doped region 025 is less than the doping height of the source region 023. The first direction Y and the second direction X are parallel to the substrate 01 and intersect.

[0149] Gate structure 03 is located on the side of epitaxial structure 02 away from substrate 01.

[0150] Specifically, substrate 01 can be a silicon carbide substrate, and the doping type of the silicon carbide substrate is N-type doped.

[0151] The epitaxial structure 02 can be formed by multiple doping processes to create a drift region 021, a well region 022, a source region 023, a first doped region 024, and a second doped region 025. Among them, the drift region 021, the source region 023, and the second doped region 025 have a first doping type, which is N-type doping, and the first doped region 024 has a second doping type, which is P-type doping.

[0152] Well region 022 is located on the side of drift region 021 away from substrate 01, surrounding source region 023, first doped region 024, and second doped region 025. Source region 023 is located on the side of well region 022 away from drift region 021, and source region 023 includes first sub-region 0231, second sub-region 0232, and third sub-region 0233. First sub-region 0231 and third sub-region 0233 extend along a first direction Y and are arranged opposite to each other along a second direction X, i.e., spaced apart. It should be noted that first sub-region 0231 and third sub-region 0233 are formed simultaneously, while second sub-region 0232 is formed later.

[0153] Within the epitaxial structure 02 between the first sub-region 0231 and the third sub-region 0233, first doped regions 024 are arranged at Y-intervals in the first direction. Second sub-regions 0232 and 025 are also disposed between adjacent first doped regions 024. In the second direction X, the second doped regions 025 are located on both sides of the second sub-region 0232. It should be noted that the doping height of the source region 023 and the second doped region 025 in the direction perpendicular to the substrate 01 is less than the doping height of the well region 022 in the direction perpendicular to the substrate 01. Furthermore, the doping height of the second doped region 025 in the direction perpendicular to the substrate 01 is less than the doping height of the source region 023 in the direction perpendicular to the substrate 01.

[0154] It should also be noted that the first direction Y and the second direction X are parallel to the substrate 01. In this embodiment, the first direction Y and the second direction X may intersect perpendicularly.

[0155] The source region 023 is N+ doped, and the second doped region 025 is N- doped. In this case, the second doped region 025 separates the source region 023. Compared with the traditional source region 023, this application introduces a second doped region 025, which introduces a resistor. When the SiC MOSFET is short-circuited, the short-circuit withstand capability of the structure is improved, reducing the possibility of structural damage.

[0156] A gate structure 03 is also provided on the side of the epitaxial structure 02 away from the substrate 01. The gate structure 03 is used to switch the semiconductor structure.

[0157] Compared to traditional semiconductor structures, this application divides the source region 023 into three sub-regions, and sets a second doped region 025 in the second direction X, between the first sub-region 0231 and the second sub-region 0232, and between the second sub-region 0232 and the third sub-region 0233. The doping concentration of the second doped region 025 is less than that of the source region 023, and the doping height of the second doped region 025 is less than that of the source region 023 in the direction perpendicular to the substrate 01. When the semiconductor structure is short-circuited, the setting of the second doped region 025 introduces resistance into the semiconductor structure, improves the short-circuit withstand capability of the structure, and reduces the possibility of structural damage.

[0158] In the description of this specification, references to terms such as "some embodiments," "another embodiment," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0159] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0160] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate having a first doping type; An epitaxial structure is formed on one side of the substrate. The epitaxial structure includes a drift region, a well region, a source region, a first doped region, and a second doped region. The well region is located on the side of the drift region away from the substrate. The source region, the first doped region, and the second doped region are located on the side of the well region away from the drift region. The source region includes a first sub-region, a second sub-region, and a third sub-region. The first sub-region and the third sub-region extend in a first direction and are disposed opposite each other in a second direction. A plurality of first doped regions are disposed in the epitaxial structure between the first sub-region and the third sub-region, spaced apart in the first direction. In the first direction, the second sub-region and the second doped region are located between two adjacent first doped regions. In the second direction, the second doped region is located on both sides of the second sub-region. The drift region, the source region, and the second doped region have the first doping type. The first doped region has the second doping type. The doping concentration of the second doped region is less than the doping concentration of the source region. In the direction perpendicular to the substrate, the doping height of the second doped region is less than the doping height of the source region. The first direction and the second direction are parallel to the substrate and intersect each other. A gate structure is formed on the side of the epitaxial structure away from the substrate. The gate structure is located between the well regions in the second direction, covers a portion of the well regions and the source region, and extends in the first direction.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of an epitaxial structure on one side of the substrate includes: An epitaxial initial layer is formed on one side of the substrate; A first patterned mask layer is formed on the side of the epitaxial initial layer away from the substrate. The first patterned mask layer includes a first opening that extends in a first direction and is spaced apart in a second direction. Based on the first patterned mask layer, a first ion implantation is performed on the epitaxial initial layer from the side of the epitaxial initial layer away from the substrate to form a first initial well region, and the remaining epitaxial initial layer forms the drift region; A second patterned mask layer is formed within the first opening of the first patterned mask layer. The second patterned mask layer includes a second opening and a third opening, which extend in the first direction and are spaced apart in the second direction. Based on the second patterned mask layer, a second ion implantation is performed on the first initial well region from the side of the epitaxial initial layer away from the substrate, forming the first sub-region in the first initial well region exposed by the second opening, forming the third sub-region in the first initial well region exposed by the third opening, and forming the second initial well region with the remaining first initial well region. Remove the first patterned mask layer and the second patterned mask layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, After removing the first patterned mask layer and the second patterned mask layer, the process includes: A third patterned mask layer is formed on the side of the epitaxial initial layer away from the substrate. The third patterned mask layer includes a fourth opening that exposes the second initial well region between the first sub-region and the second sub-region in the second direction, and the fourth opening is spaced apart in the first direction. Based on the third patterned mask layer, a third ion implantation is performed on the second initial well region from the side of the epitaxial initial layer away from the substrate to form a second doped initial region, and the remaining second initial well region forms a third initial well region.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, After performing a third ion implantation on the second initial well region from the side of the epitaxial initial layer away from the substrate, based on the third patterned mask layer, the process includes: A fourth patterned mask layer is formed within the fourth opening of the third patterned mask layer. The fourth patterned mask layer includes a fifth opening, and the orthographic projection of the fifth opening on the substrate is located within the orthographic projection of the fourth opening on the substrate. Based on the fourth patterned mask layer, a fourth ion implantation is performed on the second doped initial region from the side of the epitaxial initial layer away from the substrate to form the second sub-region, and the remaining third initial well region forms the fourth initial well region. Remove the third patterned mask layer and the fourth patterned mask layer.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, After removing the third patterned mask layer and the fourth patterned mask layer, the process includes: A fifth patterned mask layer is formed on the side of the epitaxial initial layer away from the substrate. The fifth patterned mask layer includes a sixth opening that exposes the fourth initial well region located between the first sub-region and the second sub-region in the second direction, and the sixth opening is spaced apart in the first direction. Based on the fifth patterned mask layer, a fifth ion implantation is performed on the fourth initial well region from the side of the epitaxial initial layer away from the substrate to form the first doped region, the remaining second doped initial region forms the second doped region, and the remaining fourth initial well region forms the well region. Remove the fifth patterned mask layer.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a gate structure on the side of the epitaxial structure away from the substrate includes: A gate oxide layer is formed on the side of the epitaxial structure away from the substrate; A gate is formed on the side of the gate oxide layer away from the epitaxial structure.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, After forming the gate structure on the side of the epitaxial structure away from the substrate, the process includes: A dielectric layer is formed on the side of the gate structure away from the epitaxial structure, the dielectric layer exposing the epitaxial structure between the first sub-region and the second sub-region.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, After forming a dielectric layer on the side of the gate structure away from the epitaxial structure, the process includes: A source electrode is formed on the dielectric layer and on the exposed side of the epitaxial structure away from the substrate; A drain electrode is formed on the side of the substrate away from the epitaxial structure.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, After forming the source electrode on the dielectric layer and the exposed epitaxial structure on the side away from the substrate, the process includes: A passivation layer is formed on the side of the source electrode away from the epitaxial structure. The passivation layer includes a first passivation layer and a second passivation layer sequentially disposed in a direction perpendicular to the substrate.

10. A semiconductor structure, characterized in that, include: Substrate, the substrate having a first doping type; An epitaxial structure is located on one side of the substrate. The epitaxial structure includes a drift region, a well region, a source region, a first doped region, and a second doped region. The well region is located on the side of the drift region away from the substrate. The source region, the first doped region, and the second doped region are located on the side of the well region away from the drift region. The source region includes a first sub-region, a second sub-region, and a third sub-region. The first sub-region and the third sub-region extend in a first direction and are disposed opposite each other in a second direction. A plurality of first doped regions are disposed in the epitaxial structure between the first sub-region and the third sub-region, spaced apart in the first direction. In the first direction, the second sub-region and the second doped region are located between two adjacent first doped regions, and in the second direction, the second doped region is located on both sides of the second sub-region. The drift region, the source region, and the second doped region have the first doping type, and the first doped region has the second doping type. The doping concentration of the second doped region is less than the doping concentration of the source region. In the direction perpendicular to the substrate, the doping height of the second doped region is less than the doping height of the source region. The first direction and the second direction are parallel to the substrate and intersect each other. A gate structure is located on the side of the epitaxial structure away from the substrate.

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