Image sensing device

Abstract

The invention relates to an image sensing device. The image sensing device includes single photon avalanche diodes (SPAD) disposed adjacent to each other and a connection region located between the SPADs. Each SPAD includes an output node that outputs a voltage pulse and a bias node that overlaps the output node and receives a bias voltage, and the connection region connects the bias nodes included in the corresponding SPAD.

Description

Technical Field

[0001] This disclosure relates to a single-photon avalanche diode and an image sensing device including the same. Background Technology

[0002] Time-of-flight (TOF) technology extracts distance by emitting pulses of light from a light source located inside or near the sensor, receiving the light reflected from the target being detected, and measuring the time elapsed between these pulses.

[0003] For accurate TOF measurements, detection needs to be performed immediately after the reflected light reaches the photoreceiving element, thus requiring a photoelectric conversion element with very high sensitivity.

[0004] Single-photon avalanche diodes (SPADs) are optical components that can be manufactured using CMOS technology. SPADs exhibit very high gain characteristics and high photoelectric conversion efficiency sufficient to detect a single photon.

[0005] Single-photon avalanche diodes can use the avalanche multiplication effect to amplify and identify emitted photons, thereby enabling accurate time-of-flight (TOF) measurements. Summary of the Invention

[0006] This disclosure has been made to address the aforementioned problems that occur in the related art while fully preserving the advantages achieved by the related art.

[0007] One aspect of this disclosure provides an image sensing apparatus for adjusting photon detection efficiency and / or resolution.

[0008] The technical problems to be solved by this disclosure are not limited to those described above, and any other technical problems not mentioned herein will be clearly understood by those skilled in the art to which this disclosure pertains based on the following description.

[0009] According to one aspect of this disclosure, an image sensing device includes single-photon avalanche diodes (SPADs) disposed adjacent to each other and a connection region located between the SPADs. Each SPAD includes an output node that outputs a voltage pulse and a bias node that overlaps with the output node and receives a bias voltage, and the connection region connects to the bias node included in the respective SPAD.

[0010] According to the implementation method, the output node can be a cathode, and the bias node can be an anode.

[0011] According to the implementation method, the output node can be an anode, and the bias node can be a cathode.

[0012] According to an embodiment, the image sensing device may further include a first partition structure located between the SPADs and a second partition structure surrounding the SPADs.

[0013] According to the implementation method, the first partition structure may overlap with the connecting area.

[0014] According to an embodiment, the second partition structure may include a protruding structure extending toward the first partition structure, and the connecting area may be located between the first partition structure and the protruding structure.

[0015] According to the implementation method, the bias node may have a circular shape.

[0016] According to the implementation method, the bias node can have a rounded rectangular shape.

[0017] According to the implementation method, the impurity doping type of the output node may be different from the impurity doping type of the bias node.

[0018] According to an embodiment, the depth of the first partition structure extending from one surface of a substrate including the first partition structure and the second partition structure toward the opposite surface of the substrate opposite to one surface of the substrate may be less than the depth of the second partition structure.

[0019] According to an embodiment, the depth of the first partition structure extending from one surface of a substrate including the first partition structure and the second partition structure toward the opposite surface of the substrate opposite to one surface of the substrate can be equal to the depth of the second partition structure.

[0020] According to the implementation, the bias voltage may be a first bias voltage from each SPAD output voltage pulse or a second bias voltage from only the SPAD output voltage pulse that provides the bias voltage thereto.

[0021] According to another aspect of this disclosure, an image sensing device includes: single-photon avalanche diodes (SPADs) located inside a substrate and adjacent to each other; a connection region connecting the SPADs; a first separation structure located between the SPADs; and a second separation structure surrounding the SPADs, wherein the first separation structure extends from a surface of the substrate on which arriving light is incident toward the connection region.

[0022] According to an implementation, each SPAD may include an output node that contacts an opposing surface of the substrate, and a bias node that overlaps with the output node and is located inside the substrate.

[0023] According to the implementation method, the doping type of the output node may be different from that of the bias node.

[0024] According to an embodiment, the second separation structure can extend from one surface of the substrate to an opposite surface of the substrate that is opposite to one surface of the substrate.

[0025] According to the implementation method, the connection area can have a smaller width than the SPAD.

[0026] According to the implementation method, the connection area can have a smaller thickness than the SPAD. Attached Figure Description

[0027] The above and other objects, features and advantages of this disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings:

[0028] Figure 1 This is a block diagram illustrating an imaging apparatus according to an embodiment of the present disclosure.

[0029] Figure 2 Examples include Figure 1 A diagram illustrating an implementation of a unit pixel in a pixel array.

[0030] Figure 3 Examples include Figure 1 A diagram illustrating an embodiment of the unit pixels in the pixel array shown.

[0031] Figure 4 Examples include Figure 1 A diagram illustrating an embodiment of the unit pixels in the pixel array shown.

[0032] Figure 5 This is an example along Figure 2 A diagram illustrating an embodiment of the cross-sectional structure cut by the first cutting line.

[0033] Figure 6 This is an example along Figure 2 A diagram illustrating an embodiment of the cross-sectional structure cut by the first cutting line.

[0034] Figure 7 Examples include Figure 1 A diagram illustrating an implementation of a unit pixel in a pixel array.

[0035] Figure 8 This is an example along Figure 7 A diagram illustrating an embodiment of the cross-sectional structure cut by the second cutting line.

[0036] Figure 9 This is an example along Figure 7 A diagram illustrating an implementation of the cross-sectional structure cut by the third cutting line.

[0037] Figure 10 Examples include Figure 1 A diagram illustrating an implementation of a unit pixel in a pixel array.

[0038] Figure 11 This is an example along Figure 10 A diagram illustrating an implementation of the cross-sectional structure cut by the fourth cutting line.

[0039] Figure 12 This is an example along Figure 10 A diagram illustrating an embodiment of the cross-sectional structure cut by the fifth cutting line. Detailed Implementation

[0040] In the following description, various embodiments of the present disclosure will be described with reference to the accompanying drawings. Therefore, those skilled in the art will recognize that modifications, equivalents, and / or substitutions can be made to the various embodiments described herein based on the content described or illustrated in this document.

[0041] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale of at least some structures shown in the figures may be enlarged to clearly depict the features of the embodiments. When a multilayer structure with two or more layers is disclosed in the accompanying drawings or detailed description, the relative positional relationship or arrangement order of the layers shown only reflects the specific embodiment, and this disclosure is not limited thereto. The relative positional relationship or arrangement order of the layers may vary. Furthermore, the drawings or detailed descriptions of the multilayer structure may not reflect all the layers present in a particular multilayer structure (e.g., one or more additional layers may exist between the two layers shown). For example, when the first layer is "on" or "above" the second layer or substrate in the multilayer structure shown in the drawings or detailed description, this may not only mean that the first layer is formed directly on the second layer or substrate, but also that one or more other layers exist between the first and second layers or between the first layer and the substrate.

[0042] In the following, a single-photon avalanche diode and an image sensing device including the same, according to embodiments of the present disclosure, will be described in detail with reference to the accompanying drawings.

[0043] Figure 1 This is a block diagram illustrating an imaging apparatus according to an embodiment of the present disclosure.

[0044] Reference Figure 1 The imaging device ID can refer to a device such as a digital still camera that captures still images or a digital video camera that captures moving images. For example, the imaging device ID can be implemented as a digital SLR (DSLR) camera, a mirrorless camera, or a smartphone, but is not limited to these. The imaging device ID can also be a concept that includes an imaging element and is capable of capturing an object and generating an image. In some embodiments, the imaging device ID can be a LiDAR sensor.

[0045] The imaging device ID may include an image sensing device 100 and an image signal processor (ISP) 150.

[0046] The image sensing device 100 may be a complementary metal-oxide-semiconductor image sensor (CIS) that converts incident light into electrical signals. The image sensing device 100 may include a light source 10, a lens module 20, a light source driver 30, a pixel array 110, a sensor driver 120, a readout circuit 130, and a timing controller 140.

[0047] The light source 10 can emit light toward the target object 1 under the control of the light source driver 30. The light source 10 can be a laser diode (LD), a light-emitting diode (LED), a near-infrared laser (NIR), a point light source, a monochromatic light source combining a white lamp and a monochromator, or a combination of other laser light sources that emit light of a specific wavelength band (e.g., near-infrared light, infrared light, or visible light). For example, the light of a specific wavelength band can be light in the infrared wavelength band with a wavelength of 800 nm to 1000 nm (hereinafter referred to as "infrared light"), and in this disclosure, it is assumed that the light source 10 emits infrared light. Furthermore, the light emitted from the light source 10 can be pulsed light with a predetermined period, amplitude, and pulse width. For ease of description, Figure 1 The example shows only one light source 10, but multiple light sources can be arranged around the lens module 20.

[0048] Lens module 20 can collect light reflected from target object 1 and focus the collected light onto pixels PX of pixel array 110. For example, lens module 20 may include a focusing lens with a glass or plastic surface or other cylindrical optical elements. Lens module 20 may include multiple lenses aligned with respect to the optical axis.

[0049] The light source driver 30 can drive the light source 10 under the control of the timing controller 140. Specifically, the light source driver 30 can control the waveform (period, amplitude, and pulse width) of the emitted light EL output from the light source 10.

[0050] The pixel array 110 may include a plurality of pixels PX arranged continuously in a two-dimensional matrix structure (e.g., continuously arranged in the column direction and / or row direction). Under the control of the sensor driver 120, each of the plurality of pixels PX can detect incident light incident through the lens module 20 and can generate a pixel signal.

[0051] Each pixel PX can be an infrared pixel that generates a pixel signal by detecting incident light, including arriving light RL incident on the pixel by reflection of emitted light EL from light source 10 reflected from target object 1. In this disclosure, it is assumed that the arriving light RL is incident on pixel PX by reflection of emitted light EL from target object 1. However, the spirit and scope of this disclosure are not limited thereto. For example, light source 10 may be located in a separate device other than image sensing device 100, and emitted light EL emitted from light source 10 may be directly incident on pixel array 110. In this disclosure, infrared pixels can be depth pixels for calculating the distance to target object 1, and according to embodiments, infrared pixels may include pixels for generating infrared images by simply detecting infrared light incident from the scene instead of arriving light. According to embodiments, pixel PX may include pixels for generating color images by detecting visible light incident from the scene. Hereinafter, it is assumed that each pixel PX is a single-photon avalanche diode (SPAD) pixel for detecting the distance to target object 1 according to a direct ToF method. Reference will be made below. Figure 2 The following figures illustrate the structure and operation of each unit pixel PX in more detail.

[0052] The sensor driver 120 can drive the pixels PX of the pixel array 110 in response to a timing signal output from the timing controller 140. For example, the sensor driver 120 can generate control signals to select and control the pixels PX included in at least one of the multiple row lines of the pixel array 110.

[0053] The readout circuit 130, under the control of the timing controller 140, processes the pixel signals output from the pixel array 110 to generate and store depth data for detecting the distance to the target object 1. Specifically, the readout circuit 130 can calculate a candidate time-of-flight corresponding to a SPAD pulse generated by each pixel through detecting incident light including arrival light, and can store the candidate time-of-flight corresponding to the SPAD pulse on a subframe basis. The readout circuit 130 can send the candidate time-of-flight stored on a subframe basis to the image signal processor 150 under the control of the timing controller 140. In this disclosure, for ease of description, candidate time-of-flight can be used interchangeably with time-of-flight.

[0054] The timing controller 140 can generate timing signals to control the operation of the light source driver 30, the sensor driver 120, and the readout circuit 130. According to one embodiment, the timing controller 140 can generate timing signals based on a pre-stored sequence, data transmitted from the readout circuit 130, and / or requests from the image signal processor 150. According to another embodiment, the timing controller 140 may include logic control circuitry, a phase-locked loop (PLL) circuit, timing control circuitry, and a communication interface circuit.

[0055] The image signal processor 150 can perform image signal processing on the image data IDATA received from the image sensing device 100 to generate processed image data. The image signal processor 150 can reduce noise in the image data IDATA and can perform image signal processing to improve image quality, such as interpolation of the image data IDATA and lens distortion correction.

[0056] Image data IDATA may include the aforementioned candidate times of flight stored in units of subframes. Image signal processor 150 may accumulate data in units of subframes to generate a histogram of a frame, and may determine the target time of flight of a frame based on the histogram. The target time of flight may be determined for each pixel PX, and image signal processor 150 may calculate the target distance based on the target time of flight of pixel PX, which is the distance to the target object 1 detected by each pixel PX. A set of target distances of pixels PX included in pixel array 110 may be referred to as a depth image and may be included in the processed image data.

[0057] The image signal processor 150 can send the processed image data to a host device (not illustrated). The host device (not illustrated) can be a processor (e.g., an application processor) that processes the processed image data received from the image signal processor 150, a memory (e.g., a non-volatile memory) that stores the image data, or a display device (e.g., a liquid crystal display (LCD)) that visually outputs the image data.

[0058] In addition, the image signal processor 150 can send control signals for controlling the operation of the image sensing device 100 (whether to operate, operation timing, and operation mode) to the image sensing device 100.

[0059] Figure 2 Examples include Figure 1 A diagram illustrating an embodiment of the unit pixel 200 in the pixel array shown.

[0060] Figure 2 An example is shown: a planar view of a unit pixel 200 taken from the direction of incident light on the pixel array.

[0061] Reference Figure 2 The unit pixels 200 included in the pixel array may include a first SPAD SPAD1a, a second SPAD SPAD2a, a third SPAD SPAD3a and a fourth SPAD SPAD4a arranged in a 2x2 matrix comprising two rows and two columns.

[0062] The first to fourth SPADs (SPAD1a, SPAD2a, SPAD3a and SPAD4a) can be arranged continuously in the row direction or column direction of the pixel array.

[0063] Each SPAD may include a bias node that receives the bias voltage and an output node that outputs the voltage pulse.

[0064] The first SPAD SPAD1a may include a first bias node BN1a and a first output node ON1a. The second SPAD SPAD2a may include a second bias node BN2a and a second output node ON2a. The third SPAD SPAD3a may include a third bias node BN3a and a third output node ON3a. The fourth SPAD SPAD4a may include a fourth bias node BN4a and a fourth output node ON4a.

[0065] In such Figure 2 In the example shown, SPAD, SPAD1a, SPAD2a, SPAD3a and SPAD4a may include bias nodes (BN1a, BN2a, BN3a and BN4a) each having a circular shape and output nodes (ON1a, ON2a, ON3a and ON4a) each having a circular shape.

[0066] Each of the first to fourth SPADs (SPAD1a, SPAD2a, SPAD3a and SPAD4a) can receive a bias voltage.

[0067] The bias voltage can be the voltage that enables each of the first through fourth SPADs (SPAD1a, SPAD2a, SPAD3a and SPAD4a) to operate in Geiger mode.

[0068] Geiger mode can refer to the operating mode in which a reverse bias voltage (where the voltage between the cathode and anode is higher than the breakdown voltage) is applied to a photodiode including a PN junction (SPAD).

[0069] In Geiger mode, avalanche breakdown can be triggered by a single photon incident on the SPAD and can output a voltage pulse.

[0070] The node that provides it with a reverse bias voltage for Geiger mode operation can be called a bias node, and the node from which the voltage pulse is output can be called an output node.

[0071] For example, the first SPAD SPAD1a may include a first bias node BN1a and a first output node ON1a. In this example, the shapes of the bias nodes and output nodes included in the SPADs (SPAD1a, SPAD2a, SPAD3a, and SPAD4a) may be substantially the same. Therefore, the first SPAD SPAD1a is described below as a representative example, and this description can be applied to the remaining SPADs, SPAD2a, SPAD3a, and SPAD4a, while repeated descriptions are omitted.

[0072] The first bias node BN1a may overlap with the first output node ON1a. The first output node ON1a may be located in the center of the first SPAD SPAD1a and may have a circular shape. The first bias node BN1a may be spaced a certain distance from the first output node ON1a and may have a shape that surrounds the first output node ON1a and is located outside the first output node ON1a. (Refer to...) Figure 5 and Figure 6 Describe in detail the specific shapes of the first output node ON1a and the first bias node BN1a.

[0073] Because the first bias node BN1a and the first output node ON1a are spaced apart by a certain distance, it can prevent the edge breakdown or tunneling phenomenon caused by the charge being directly transferred from the bias node to the output node.

[0074] The bias voltage can be applied individually to each of the first to fourth SPADs, SPAD1a, SPAD2a, SPAD3a, and SPAD4a.

[0075] The first bias node BN1a and the first output node ON1a can be doped with different types of impurities.

[0076] For example, the first bias node BN1a may be doped with N-type impurities, and the first output node ON1a may be doped with P-type impurities. In this case, the semiconductor substrate including the first bias node BN1a and the first output node ON1a may be a semiconductor substrate doped with N-type impurities.

[0077] The first bias node BN1a, doped with N-type impurities, can be the cathode of the first SPAD SPAD1a or operate as the cathode of the first SPAD SPAD1a. Furthermore, the first output node ON1a, doped with P-type impurities, can be the anode of the first SPAD SPAD1a or operate as the anode of the first SPAD SPAD1a. Therefore, the first SPAD SPAD1a, including the first bias node BN1a doped with N-type impurities, can be referred to as a cathode-biased SPAD.

[0078] According to an embodiment, the first bias node BN1a may be doped with P-type impurities, and the first output node ON1a may be doped with N-type impurities. In this case, the semiconductor substrate including the first bias node BN1a and the first output node ON1a may be or include a semiconductor substrate doped with P-type impurities.

[0079] The first bias node BN1a, doped with a P-type impurity, can be the anode of the first SPAD SPAD1a or operate as the anode of the first SPAD SPAD1a. Furthermore, the first output node ON1a, doped with an N-type impurity, can be the cathode of the first SPAD SPAD1a or operate as the cathode of the first SPAD SPAD1a. Therefore, the first SPAD SPAD1a, including the first bias node BN1a doped with a P-type impurity, can be referred to as an anode-biased SPAD.

[0080] The connection region can be set between two adjacent SPADs in the row direction (ROW) or column direction (COLUMN) of a 2x2 matrix.

[0081] The unit pixel 200 may include a first connection region IC12a connecting the first bias node BN1a and the second bias node BN2a, a second connection region IC13a connecting the first bias node BN1a and the third bias node BN3a, a third connection region IC24a connecting the second bias node BN2a and the fourth bias node BN4a, and a fourth connection region IC34a connecting the third bias node BN3a and the fourth bias node BN4a.

[0082] The connecting region is formed in a repeating shape within the unit pixel 200. Therefore, for ease of description, the description is set in the first connecting region IC12a between the first SPAD SPAD1a and the second SPAD SPAD2a, and the repeating description is omitted.

[0083] The first connection area IC12a can be located between the first SPAD SPAD1a and the second SPAD SPAD2a. More specifically, the first connection area IC12a can be electrically connected to the first bias node BN1a and the second bias node BN2a.

[0084] The first connection region IC12a may be a region doped with the same type of impurities as the first bias node BN1a and the second bias node BN2a.

[0085] When connecting regions (IC12a, IC13a, IC24a and IC34a) are formed, multiple SPADs (SPAD1a, SPAD2a, SPAD3a and SPAD4a) can be operated as a single SPAD or as separate SPAD operations.

[0086] In some implementations, depending on the magnitude of the bias voltage provided to one of the SPADs (SPAD1a, SPAD2a, SPAD3a, and SPAD4a) included in the unit pixel 200, multiple SPADs (SPAD1a, SPAD2a, SPAD3a, and SPAD4a) connected by the connection regions (IC12a, IC13a, IC24a, and IC34a) can operate as a single SPAD or operate individually.

[0087] As described above, the bias voltage can be a voltage that enables each of the first to fourth SPADs (SPAD1a, SPAD2a, SPAD3a, and SPAD4a) to operate in Geiger mode. In the example, the bias voltage can be a voltage randomly selected from those that satisfy the condition that the voltage between the cathode and anode of the photodiode SPAD is higher than the breakdown voltage.

[0088] In the image sensing apparatus according to an embodiment of the present disclosure, the first bias node to the fourth bias node (BN1a, BN2a, BN3a, and BN4a) are electrically connected via connection regions (IC12a, IC13a, IC24a, and IC34a). Depending on the magnitude of the voltage applied to the first bias node BN1a, a voltage higher than the noise range may or may not be generated in the remaining SPADs (SPAD2a, SPAD3a, and SPAD4a). For example, when a high voltage higher than or equal to a preset voltage is applied to the first bias node BN1a, additional voltage pulses exceeding the noise range may be generated in the second to fourth SPADs (SPAD2a, SPAD3a, and SPAD4a).

[0089] Conversely, when a low voltage below a preset voltage is applied to the first bias node BN1a, voltage pulses can be generated only in the first SPADs D1a, and voltage pulses exceeding the noise range can be avoided in the second to fourth SPADs (SPAD2a, SPAD3a and SPAD4a).

[0090] The preset voltage used to determine whether voltage pulses exceeding the noise range are generated in other SPADs (e.g., second to fourth SPADs, SPAD2a, SPAD3a, and SPAD4a) connected to the first SPAD (SPAD1a) to which the bias current is applied can vary depending on various factors, including at least one of the following: the shape of the connection regions (IC12a, IC13a, IC24a, and IC34a), the distance between bias nodes (BN1a, BN2a, BN3a, and BN4a), the doping concentration of the connection regions (IC12a, IC13a, IC24a, and IC34a), or the doping concentration of the bias nodes (BN1a, BN2a, BN3a, and BN4a).

[0091] For example, as the connection area and doping concentration of the connection regions (IC12a, IC13a, IC24a and IC34a) and bias nodes (BN1a, BN2a, BN3a and BN4a) increase, the preset voltage can be reduced.

[0092] When a high voltage higher than or equal to a preset voltage is applied to the first SPAD (SPAD1a) included in the unit pixel 200, photons can be detected in all the first to fourth SPADs (SPAD1a, SPAD2a, SPAD3a and SPAD4a) included in the unit pixel 200, and a voltage pulse corresponding to the detected photon can be output.

[0093] When a high voltage higher than or equal to a preset voltage is applied to any bias node (e.g., the first bias node BN1a) included in the unit pixel 200, all SPADs (SPAD1a, SPAD2a, SPAD3a, and SPAD4a) included in the unit pixel 200 can operate in Geiger mode, and thus photon detection efficiency (PDE) can be increased.

[0094] An operating mode in which a high voltage, greater than or equal to a preset voltage, is applied to any bias node (e.g., the first bias node BN1a) included in the unit pixel 200 to increase photon detection efficiency can be referred to as the first mode.

[0095] When a low voltage lower than a preset voltage is applied to the first SPAD (SPAD1a) included in the unit pixel 200, photons can be detected only in the first SPAD SPAD1a, and a voltage pulse corresponding to the detected photons can be output.

[0096] In the example, when a low voltage below a preset voltage is applied to any bias node (e.g., the first bias node BN1a) included in the unit pixel 200, only the SPAD (e.g., SPAD1a) to which the low voltage is applied can operate in Geiger mode.

[0097] Therefore, when a low bias voltage lower than a preset voltage is provided to a selected SPAD (e.g., SPAD1a) among the multiple SPADs (SPAD1a, SPAD2a, SPAD3a and SPAD4a) included in the unit pixel 200, only the selected SPAD can be allowed to operate in Geiger mode.

[0098] Voltage pulses can be output from SPADs operating in Geiger mode among the multiple SPADs (SPAD1a, SPAD2a, SPAD3a, and SPAD4a) included in unit pixel 200. Therefore, by selecting the SPAD to which a bias voltage is applied and adjusting the magnitude of the bias voltage applied to the selected SPAD, four different voltage pulses can be obtained from the multiple SPADs (SPAD1a, SPAD2a, SPAD3a, and SPAD4a) included in a unit pixel 200.

[0099] When the four SPADs (SPAD1a, SPAD2a, SPAD3a and SPAD4a) included in a unit pixel 200 operate individually, four different signals can be output from a unit pixel 200, and the resolution of the image sensing device can be increased.

[0100] The operation mode in which a low voltage below a preset voltage is applied to any bias node (e.g., the first bias node BN1a) included in the unit pixel 200, such that SPADs (SPAD1a, SPAD2a, SPAD3a, and SPAD4a) operate independently and the resolution is increased, can be referred to as the second mode.

[0101] Unit pixel 200 may include a first separating structure IS1a located between four SPADs (SPAD1a, SPAD2a, SPAD3a, and SPAD4a) and a second separating structure IS2a surrounding the four SPADs (SPAD1a, SPAD2a, SPAD3a, and SPAD4a). In the example, the second separating structure IS2a is located outside the four SPADs (SPAD1a, SPAD2a, SPAD3a, and SPAD4a). In the example, the second separating structure IS2a is placed outside the four SPADs, leaving a margin between the SPADs and the second separating structure IS2a.

[0102] The first separator structure IS1a may be located at the center of the unit pixel 200. The first separator structure IS1a may be a trench-type separator structure. The first separator structure IS1a may have a shape that extends from a surface onto which the arriving light RL is incident toward the connecting regions (IC12a, IC13a, IC24a and IC34a).

[0103] According to an embodiment, the first separating structure IS1a may overlap with the connecting regions IC12a, IC13a, IC24a, and IC34a. The first separating structure IS1a may be located between two adjacent bias nodes (e.g., BN1a and BN2a). Since the first separating structure IS1a is located between two adjacent bias nodes, charge movement between the two adjacent bias nodes can be partially isolated.

[0104] According to the embodiment, the first separating structure IS1a can extend from a surface onto which the arriving light RL is incident toward the connecting regions IC12a, IC13a, IC24a and IC34a.

[0105] The second separating structure IS2a can surround four adjacent SPADs (SPAD1a, SPAD2a, SPAD3a, and SPAD4a). In the example, the second separating structure IS2a can be positioned outside the four adjacent SPADs (SPAD1a, SPAD2a, SPAD3a, and SPAD4a). Furthermore, adjacent unit pixels 200 can be separated from each other by the second separating structure IS2a.

[0106] According to an embodiment, the second separating structure IS2a can extend from a surface onto which the arriving light RL is incident to an opposing surface. Furthermore, the second separating structure IS2a may include a deep trench structure extending from the opposing surface toward a surface.

[0107] Figure 3 Examples include Figure 1 A diagram illustrating an embodiment of the unit pixel 300 in the pixel array shown.

[0108] Similar to Figure 2 The unit pixel is 200. Figure 3 The unit pixel 300 is a planar view taken from the direction of incident light on the pixel array.

[0109] The unit pixel 300 may include a first SPAD (SPAD1b), a second SPAD (SPAD2b), a third SPAD (SPAD3b), and a fourth SPAD (SPAD4b) arranged in a 2x2 matrix comprising two rows and two columns.

[0110] Each SPAD may include a bias node that receives the bias voltage and an output node that outputs the voltage pulse.

[0111] The first SPAD (SPAD1b) may include a first bias node BN1b and a first output node ON1b. The second SPAD (SPAD2b) may include a second bias node BN2b and a second output node ON2b. The third SPAD (SPAD3b) may include a third bias node BN3b and a third output node ON3b. The fourth SPAD (SPAD4b) may include a fourth bias node BN4b and a fourth output node ON4b.

[0112] Additionally, unit pixel 300 may include multiple connection regions IC12b, IC13b, IC24b and IC34b that connect adjacent SPADs, SPAD1b, SPAD2b, SPAD3b and SPAD4b.

[0113] The unit pixel 300 may include a first connection region IC12b connecting the first bias node BN1b and the second bias node BN2b, a second connection region IC13b connecting the first bias node BN1b and the third bias node BN3b, a third connection region IC24b connecting the second bias node BN2b and the fourth bias node BN4b, and a fourth connection region IC34b connecting the third bias node BN3b and the fourth bias node BN4b.

[0114] The unit pixel 300 may include a first dividing structure IS1b located in the center and a second dividing structure IS2b surrounding the SPADs (SPAD1b, SPAD2b, SPAD3b and SPAD4b). The second dividing structure IS2b may be located outside the SPADs (SPAD1b, SPAD2b, SPAD3b and SPAD4b).

[0115] Although it has been referenced Figure 2 The characteristics of SPADs (SPAD1b, SPAD2b, SPAD3b, and SPAD4b), connecting regions IC12b, IC13b, IC24b, and IC34b, and separating structures IS1b and IS2b are described. However, such a description can be applied to, for example... Figure 3 The unit pixel is shown as 300. In the following text, the main descriptions and references will be as follows: Figure 2 The examples shown illustrate the differences in the content discussed.

[0116] Included Figure 3The SPADs (SPAD1b, SPAD2b, SPAD3b and SPAD4b) in the unit pixel 300 may include offset nodes (BN1b, BN2b, BN3b and BN4b) with rounded rectangular shapes and output nodes (ON1b, ON2b, ON3b and ON4b) with circular shapes.

[0117] Since the bias nodes (BN1b, BN2b, BN3b and BN4b) have rounded rectangular shapes, the area occupied by the bias nodes (BN1b, BN2b, BN3b and BN4b) in unit pixel 300 can be increased compared to the area occupied by bias nodes with circular shapes.

[0118] As the areas of bias nodes BN1b, BN2b, BN3b, and BN4b increase, the region within the SPAD to which the reverse bias voltage is applied can be increased, thus facilitating photon detection. Furthermore, by altering the shapes of bias nodes BN1b, BN2b, BN3b, and BN4b, the electric field generated within the SPADs SPAD1b, SPAD2b, SPAD3b, and SPAD4b by the reverse bias voltage can be adjusted to control photon detection.

[0119] Figure 4 Examples include Figure 1 A diagram illustrating an embodiment of the unit pixel 400 in the pixel array shown.

[0120] Similar to Figure 2 The unit pixel is 200. Figure 4 The unit pixel 400 is a planar view taken from the direction of incident light on the pixel array.

[0121] The unit pixel 400 may include a first SPAD (SPAD1c), a second SPAD (SPAD2c), a third SPAD (SPAD3c), and a fourth SPAD (SPAD4c) arranged in a 2x2 matrix comprising two rows and two columns.

[0122] Each SPAD may include a bias node that receives the bias voltage and an output node that outputs the voltage pulse.

[0123] The first SPAD SPAD1c may include a first bias node BN1c and a first output node ON1c. The second SPAD SPAD2c may include a second bias node BN2c and a second output node ON2c. The third SPAD SPAD3c may include a third bias node BN3c and a third output node ON3c. The fourth SPAD SPAD4c may include a fourth bias node BN4c and a fourth output node ON4c.

[0124] In addition, unit pixel 400 may include multiple connection regions IC12c, IC13c, IC24c and IC34c that connect adjacent SPAD SPAD1c, SPAD2c, SPAD3c and SPAD4c.

[0125] The unit pixel 400 may include a first connection region IC12c connecting the first bias node BN1c and the second bias node BN2c, a second connection region IC13c connecting the first bias node BN1c and the third bias node BN3c, a third connection region IC24c connecting the second bias node BN2c and the fourth bias node BN4c, and a fourth connection region IC34c connecting the third bias node BN3c and the fourth bias node BN4c.

[0126] Unit pixel 400 may include a first dividing structure IS1c located in the center and a second dividing structure IS2c surrounding the SPADs (SPAD1c, SPAD2c, SPAD3c and SPAD4c). The second dividing structure IS2c may be located outside the SPADs (SPAD1c, SPAD2c, SPAD3c and SPAD4c).

[0127] Focus on Figure 2 Different characteristics are used to describe the features of SPADs (SPAD1c, SPAD2c, SPAD3c and SPAD4c) included in unit pixel 400, connecting regions IC12c, IC13c, IC24c and IC34c, and separating structures IS1c and IS2c.

[0128] Included Figure 4 SPAD1c, SPAD2c, SPAD3c and SPAD4c in unit pixel 400 may include offset nodes BN1c, BN2c, BN3c and BN4c with rounded rectangle shapes and output nodes ON1c, ON2c, ON3c and ON4c with rounded rectangle shapes.

[0129] when Figure 3 The width of the output node ON1b is equal to Figure 4 When the width of the output node ON1c is... Figure 4 The area of ​​the output node ON1c can be greater than Figure 3 The area of ​​the output node ON1b.

[0130] The areas of output nodes ON1c, ON2c, ON3c, and ON4c can correspond to the areas of the active regions capable of detecting photons, and increasing the areas of output nodes ON1c, ON2c, ON3c, and ON4c can improve sensitivity. Conversely, increasing the areas of output nodes ON1c, ON2c, ON3c, and ON4c may increase the likelihood of noise due to background noise and the possibility of edge breakdown.

[0131] Figure 5 This is an example along Figure 2 A diagram illustrating an embodiment of the cross-sectional structure cut by the first cutting line A-A'.

[0132] Reference Figure 5 Examples along Figure 2 The first cross-section structure 200a is cut by the first cutting line A-A'.

[0133] The description will be based on the assumption that the first cross-sectional structure 200a is formed on an N-type substrate (N substrate) doped with N-type impurities (e.g., group V elements). Figure 5 The first cross-sectional structure 200a. However, other implementations are also possible. For example, the first cross-sectional structure 200a can be formed in a well region doped with N-type impurities inside a P-type substrate doped with P-type impurities (e.g., group III elements).

[0134] Referring to the first cross-sectional structure 200a, a unit pixel may include a microlens ML located on an N-type substrate (N substrate) and a grid structure GS located between adjacent microlenses ML.

[0135] In addition, the unit pixel may include a first output node 1000a, a second output node 1000b, a first connection region 1100, a first bias node 1200a, a second bias node 1200b, a first separation structure 1300, and a second separation structure 1400 located inside the N-type substrate (N substrate).

[0136] Microlenses (MLs) can be formed into a hemispherical shape on an N-type substrate (N substrate) and can increase the light collection capability for incident light, thereby improving the light receiving efficiency (the amount of light received per unit area).

[0137] The microlens ML may also include an outer coating (not shown) to prevent diffuse reflection of incident light.

[0138] The grid structure GS can be located between microlenses ML included in adjacent unit pixels. The grid structure GS can prevent crosstalk of incident light introduced between adjacent unit pixels.

[0139] According to one embodiment, the grid structure GS may include a metallic material such as tungsten. According to another embodiment, the grid structure GS may include an air layer comprising air and a cover film, and the cover film may include a silicon oxide film.

[0140] An N-type substrate (N-substrate) may be or include a silicon substrate for semiconductor processing. The N-type substrate (N-substrate) may include a first surface and a second surface opposite to the first surface, with light RL incident on the first surface. In some implementations, the N-type substrate (N-substrate) may include an N-type body substrate. In some implementations, the N-type substrate (N-substrate) can be obtained by growing an N-type epitaxial layer on an N-type body substrate or a P-type body substrate.

[0141] The first output node 1000a and the second output node 1000b can be located on the second surface of the N-type substrate (N substrate) opposite to the first surface on which light is incident.

[0142] The first output node 1000a and the second output node 1000b can be regions doped with P-type impurities. The first output node 1000a and the second output node 1000b can detect holes 1001 generated in a unit pixel.

[0143] Because photons arriving at a unit pixel RL can undergo photoelectric conversion, and can generate electrons and holes 1001. Figure 5 An example is shown where three holes 1001 are generated at a specific location by reaching the light RL. However, other implementations are possible. At least one hole 1001 can be generated at any location within a unit pixel, and an avalanche process can be performed.

[0144] The first output node 1000a and the second output node 1000b can detect holes 1001 in the form of voltage pulses.

[0145] According to the implementation method, the first output node 1000a and the second output node 1000b may further include multiple P-type impurity regions with different concentrations.

[0146] The first bias node 1200a may have a shape surrounding the first output node 1000a. In the example, the first bias node 1200a may surround the first output node 1000a while being spaced apart from it. The first bias node 1200a may have a shape extending from a second surface of the N-type substrate (N substrate) toward a first surface of the N-type substrate (N substrate).

[0147] The first bias node 1200a may include a first high-concentration region 1210a, a first intermediate region 1220a, and a first well region 1230a. The first high-concentration region 1210a, the first intermediate region 1220a, and the first well region 1230a may be N-type doped regions.

[0148] The first high-concentration region 1210a may be the region with the highest concentration among the regions included in the first bias node 1200a. The first intermediate region 1220a may be located between the first high-concentration region 1210a and the first well region 1230a, and may have a concentration higher than that of the N-type substrate (N-substrate). The concentration of the first well region 1230a may be higher than that of the N-type substrate (N-substrate).

[0149] According to the implementation method, the doping concentration can be decreased in the order of the first high concentration region 1210a, the first intermediate region 1220a, the first well region 1230a, and the N-type substrate.

[0150] Since the concentration of the region included in the first bias node 1200a decreases from the second surface of the N-type substrate toward the first surface, the electric field (or reverse bias) caused by the bias voltage provided to the first bias node 1200a can affect deeper locations of the N-type substrate.

[0151] Therefore, even if photons reach deep into the N-type substrate, an avalanche process can be performed, thus improving the sensitivity of SPADs.

[0152] The second bias node 1200b may include a second high-concentration region 1210b, a second intermediate region 1220b, and a second well region 1230b. According to an embodiment, the doping concentration of the N-type impurity may decrease in the order of the second high-concentration region 1210b, the second intermediate region 1220b, the second well region 1230b, and the N-type substrate.

[0153] The first bias node 1200a and the second bias node 1200b can be electrically connected through a first connection region 1100. The first connection region 1100 can be a region doped with N-type impurities and can have the same impurity concentration as the first well region 1230a or the second well region 1230b.

[0154] The thickness of the connection region (e.g., 1100) may be the length of the connection region (e.g., 1100) in a direction perpendicular to the first surface of the N-type substrate, and the width of the connection region (e.g., 1100) may be the length of the connection region (e.g., 1100) in a direction parallel to the first surface of the N-type substrate.

[0155] Similarly, the thickness of the output node (e.g., 1000a) can be the length of the output node (e.g., 1000a) in a direction perpendicular to one surface of the N-type substrate, and the width of the output node (e.g., 1000a) can be the length of the output node (e.g., 1000a) in a direction parallel to one surface of the N-type substrate.

[0156] Furthermore, the thickness of the bias node (e.g., 1200a) can be the length of the bias node (e.g., 1200a) in a direction perpendicular to one surface of the N-type substrate, and the width of the bias node (e.g., 1200a) can be the length of the bias node (e.g., 1200a) in a direction parallel to one surface of the N-type substrate.

[0157] Reference Figure 5 The width of the bias node (e.g., 1200a) can be greater than the width of the connection region (e.g., 1100), and the thickness of the bias node (e.g., 1200a) can be greater than the thickness of the connection region (e.g., 1100).

[0158] The above reference Figure 2 The preset voltage described for determining whether to operate in the first or second mode can vary depending on the thickness and width of the first connection area 1100.

[0159] For example, as the thickness of the first connection region 1100 increases, the potential caused by the voltage supplied to the first bias node 1200a can be easily transferred to the second bias node 1200b. Therefore, as the thickness of the first connection region 1100 increases, the preset voltage can be reduced, and the unit pixel can operate with a low bias voltage in the first mode.

[0160] Reference Figure 5 The first cross-sectional structure 200a, the first separation structure 1300 included in the unit pixel may include a first outer separation layer 1310 and a first inner separation layer 1320.

[0161] The first separation structure 1300 can separate the first bias node 1200a and the second bias node 1200b from each other and can prevent holes from moving between the first bias node 1200a and the second bias node 1200b.

[0162] The first outer separator layer 1310 included in the first separator structure 1300 may include a silicon oxide film, a silicon nitride film, or a polycrystalline silicon film.

[0163] The first inner separator layer 1320 may include a silicon oxide film, a silicon nitride film, a polycrystalline silicon film, a metal layer, or an air layer.

[0164] The first separation structure 1300 can be formed by patterning one surface of an N-type substrate to form a deep trench and filling the trench with a first outer separation layer 1310 and a first inner separation layer 1320.

[0165] The first partition structure 1300 can be formed to have a smaller depth relative to one surface of the N-type substrate than the second partition structure 1400, so that the first connection region 1100 can be formed.

[0166] Reference Figure 5 The first cross-sectional structure 200a, the second separation structure 1400 included in the unit pixel may include a second outer separation layer 1410, a second inner separation layer 1420 and a trench layer 1430.

[0167] The second partition structure 1400 can extend from one side of the N-type substrate to the opposite side to prevent holes from moving between adjacent unit pixels. The second partition structure 1400 can be configured to surround a plurality of SPADs included in a unit pixel. In the example, the second partition structure 1400 can be disposed outside the plurality of SPADs while being spaced apart from the plurality of SPADs.

[0168] The second outer separator layer 1410 included in the second separator structure 1400 may include at least one of a silicon oxide film, a silicon nitride film, or a polycrystalline silicon film.

[0169] The second inner separator layer 1420 may include at least one of a silicon oxide film, a silicon nitride film, a polycrystalline silicon film, a metal layer, or an air layer.

[0170] The trench layer 1430 may have a shape extending from the second surface of the N-type substrate toward the first surface of the N-type substrate. The trench layer 1430 may include at least one of a silicon oxide film, a silicon nitride film, a polycrystalline silicon film, a metal layer, or an air layer.

[0171] The second separation structure 1400 can be formed by patterning one surface of the N-type substrate to form a deep trench and filling the trench with a second outer separation layer 1410 and a second inner separation layer 1420. Alternatively, a trench layer 1430 can be formed by patterning the opposite surfaces of the N-type substrate.

[0172] Figure 6 This is an example along Figure 2 A diagram illustrating an embodiment of the cross-sectional structure cut by the first cutting line A-A'.

[0173] Reference Figure 6 Examples along Figure 2 The second cross-section structure 200b is obtained by the first cutting line A-A'.

[0174] The description will proceed under the assumption that the second cross-sectional structure 200b is formed on a P-type substrate (P-substrate) doped with P-type impurities (e.g., group III elements). Figure 6 The second cross-sectional structure 200b. However, other implementations are also possible, and the second cross-sectional structure 200b can be a structure formed in a well region doped with P-type impurities inside an N-type substrate doped with N-type impurities (e.g., group V elements).

[0175] Referring to the second cross-sectional structure 200b, the unit pixel may include a microlens ML located on a P-type substrate (P substrate) and a grid structure GS located between adjacent microlenses ML.

[0176] In addition, the unit pixel may include a first output node 2000a, a second output node 2000b, a first connection region 2100, a first bias node 2200a, a second bias node 2200b, a first separation structure 2300, and a second separation structure 2400 located inside the P-type substrate (P substrate).

[0177] Besides the type of impurity doping Figure 6 The second cross-section structure 200b and Figure 5 The first cross-sectional structure 200a is basically the same, so repeated descriptions will be omitted, and the discussion will mainly focus on the similarity to the first cross-section structure 200a. Figure 5 The differences shown in the examples.

[0178] A P-type substrate (P-substrate) can be a silicon substrate used for semiconductor processing. A P-type substrate (P-substrate) can include a surface and an opposing surface opposite to the surface, on which light RL is incident. A P-type substrate (P-substrate) can be a P-type body substrate, a substrate in which a P-type epitaxial layer is grown on an N-type body substrate, or a substrate in which a P-type epitaxial layer is grown on a P-type body substrate.

[0179] The first output node 2000a and the second output node 2000b can be located on the second surface of the P-type substrate (P-substrate) opposite to the first surface on which light is incident.

[0180] The first output node 2000a and the second output node 2000b can be regions doped with N-type impurities. The first output node 2000a and the second output node 2000b can detect electrons 2001 generated in a unit pixel.

[0181] Because photons arriving at a unit pixel (RL) can undergo photoelectric conversion, electrons (2001) and holes can be generated. Figure 6An example is given of generating three electrons 2001 at a specific location by reaching the light RL. However, other implementations are also possible. At least one electron 2001 can be generated at any location within a unit pixel, and an avalanche process can be performed.

[0182] The first output node 2000a and the second output node 2000b can detect electrons 2001 in the form of voltage pulses.

[0183] The first bias node 2200a may have a shape that surrounds the first output node 2000a and extends from the second opposing surface of the P-type substrate (P substrate) toward the first surface of the P-type substrate (P substrate).

[0184] The first bias node 2200a may include a first high-concentration region 2210a, a first intermediate region 2220a, and a first well region 2230a. The first high-concentration region 2210a, the first intermediate region 2220a, and the first well region 2230a may be P-type doped regions.

[0185] According to the implementation method, the doping concentration can be decreased in the order of the first high concentration region 2210a, the first intermediate region 2220a, the first well region 2230a, and the P-type substrate.

[0186] The second bias node 2200b may have a shape surrounding the second output node 2000b. In the example, the second bias node 2200b may surround the second output node 2000b while being spaced apart from it. The second bias node 2200b may have a shape extending from a second surface of the P-type substrate (P-substrate) toward a first surface of the P-type substrate (P-substrate).

[0187] The second bias node 2200b may include a second high-concentration region 2210b, a second intermediate region 2220b, and a second well region 2230b. The second high-concentration region 2210b, the second intermediate region 2220b, and the second well region 2230b may be P-type doped regions.

[0188] According to the implementation method, the doping concentration can be decreased in the order of the second high concentration region 2210b, the second intermediate region 2220b, the second well region 2230b, and the P-type substrate.

[0189] The first bias node 2200a and the second bias node 2200b can be electrically connected through a first connection region 2100. The first connection region 2100 can be a region doped with P-type impurities and can have the same impurity concentration as the first well region 2230a or the second well region 2230b.

[0190] Reference Figure 6Each unit pixel may include a first separation structure 2300 and a second separation structure 2400. The first separation structure 2300 can prevent charge from moving between adjacent bias nodes.

[0191] The first outer separator layer 2310 included in the first separator structure 2300 may include at least one of a silicon oxide film, a silicon nitride film, or a polycrystalline silicon film.

[0192] The first inner separator layer 2320 may include at least one of a silicon oxide film, a silicon nitride film, a polycrystalline silicon film, a metal layer, or an air layer.

[0193] The second partition structure 2400 may include a second outer partition layer 2410, a second inner partition layer 2420, and a trench layer 2430.

[0194] The second partition structure 2400 can extend from one side of the P-type substrate to the opposite side to prevent electrons from moving between adjacent unit pixels. The second partition structure 2400 can be configured to surround a plurality of SPADs included in the unit pixels. In the example, the second partition structure 2400 can be disposed outside the plurality of SPADs while being spaced apart from the plurality of SPADs.

[0195] The second outer separator layer 2410 included in the second separator structure 2400 may include at least one of a silicon oxide film, a silicon nitride film, or a polycrystalline silicon film.

[0196] The second inner separator layer 2420 may include at least one of a silicon oxide film, a silicon nitride film, a polycrystalline silicon film, a metal layer, or an air layer.

[0197] The trench layer 2430 may have a shape extending from the second surface of the P-type substrate toward the first surface of the P-type substrate. The trench layer 2430 may include at least one of a silicon oxide film, a silicon nitride film, a polycrystalline silicon film, a metal layer, or an air layer.

[0198] Figure 7 Examples include Figure 1 A diagram illustrating an implementation of a unit pixel in a pixel array.

[0199] Figure 7 An example is shown: a planar view of a unit pixel 500 taken from the direction of incident light on the pixel array.

[0200] Reference Figure 7 The unit pixel 500 included in the pixel array may include a first SPAD (SPAD1d), a second SPAD (SPAD2d), a third SPAD (SPAD3d), and a fourth SPAD (SPAD4d) arranged in a 2x2 matrix.

[0201] The first SPAD (SPAD1d) may include a first bias node BN1d and a first output node ON1d. The second SPAD (SPAD2d) may include a second bias node BN2d and a second output node ON2d. The third SPAD (SPAD3d) may include a third bias node BN3d and a third output node ON3d. The fourth SPAD (SPAD4d) may include a fourth bias node BN4d and a fourth output node ON4d.

[0202] Figure 7 The unit pixel 500 shown may include a connection area disposed between two adjacent bias nodes and electrically connecting the two adjacent bias nodes.

[0203] The unit pixel 500 may include a first connection region IC12d connecting the first bias node BN1d and the second bias node BN2d, a second connection region IC13d connecting the first bias node BN1d and the third bias node BN3d, a third connection region IC24d connecting the second bias node BN2d and the fourth bias node BN4d, and a fourth connection region IC34d connecting the third bias node BN3d and the fourth bias node BN4d.

[0204] according to Figure 7 In one implementation, the unit pixel 500 may include a first separating structure IS1d located between four SPADs (SPAD1d, SPAD2d, SPAD3d, and SPAD4d) and a second separating structure IS2d surrounding the four SPADs (SPAD1d, SPAD2d, SPAD3d, and SPAD4d). The second separating structure IS2d may be disposed outside the four SPADs (SPAD1d, SPAD2d, SPAD3d, and SPAD4d).

[0205] The first to fourth connection regions IC12d, IC13d, IC24d, and IC34d can be disposed between the first partition structure IS1d and the second partition structure IS2d. The first to fourth connection regions IC12d, IC13d, IC24d, and IC34d can contact the first partition structure IS1d and the second partition structure IS2d.

[0206] and Figures 2 to 4 The implementation methods differ, and the first to fourth connection regions IC12d, IC13d, IC24d, and IC34d may not overlap with the first separating structure IS1d. Therefore, the first separating structure IS1d may not be formed in the region where the first to fourth connection regions IC12d, IC13d, IC24d, and IC34d are formed.

[0207] The first separation structure IS1d can extend from one surface of the substrate toward the opposing surface on which four SPADs SPAD1d, SPAD2d, SPAD3d and SPAD4d are formed, and can prevent electrons or holes from moving in the areas where the first connection region IC12d, the second connection region IC13d, the third connection region IC24d and the fourth connection region IC34d are not formed.

[0208] The second separation structure IS2d may include protruding structures PS12d, PS13d, PS24d, and PS34d extending from the edge of the second separation structure IS2d toward the first connection region to the fourth connection region IC12d, IC13d, IC24d, and IC34d. The protruding structures PS12d, PS13d, PS24d, and PS34d may extend from one surface of the substrate toward the opposing surface on which the four SPAD1d, SPAD2d, SPAD3d, and SPAD4d are formed, and may prevent electrons or holes from moving in the regions where the first to fourth connection regions IC12d, IC13d, IC24d, and IC34d are not formed.

[0209] Figure 8 This is an example along Figure 7 A diagram illustrating an embodiment of the cross-sectional structure cut by the second cutting line B1-B1'.

[0210] Figure 9 This is an example along Figure 7 A diagram illustrating an embodiment of the cross-sectional structure cut by the third cutting line B2-B2'.

[0211] Reference Figure 8 Examples along Figure 7 The second section structure 500a is cut by the second cutting line B1-B1'.

[0212] Reference Figure 9 Examples along Figure 7 The third section structure 500b is cut by the third cutting line B2-B2'.

[0213] Reference Figure 8 and Figure 9 The cross-sectional structure of a unit pixel according to an embodiment of the present disclosure is described.

[0214] The second cross-sectional structure 500a and the third cross-sectional structure 500b are described under the assumption that they are formed on an N-type substrate (N substrate) doped with N-type impurities (e.g., group V elements). Figure 8 The second cross-section structure 500a and Figure 9The third cross-sectional structure 500b. However, other implementations are also possible. For example, the second cross-sectional structure 500a and the third cross-sectional structure 500b can be formed in a well region doped with N-type impurities inside a P-type substrate doped with P-type impurities (e.g., group III elements).

[0215] A unit pixel may include a microlens ML located on an N-type substrate (N substrate) and a grid structure GS located between adjacent microlenses ML.

[0216] In the example, a unit pixel may include a first output node 3000a, a second output node 3000b, a first connection region 3100, a first bias node 3200a, a second bias node 3200b, a first separation structure 3300, and a second separation structure 3400 disposed inside an N-type substrate (N substrate).

[0217] Microlenses ML and grating structures GS are the same as those mentioned above. Figure 5 and Figure 6 The components described are basically the same, so repeated descriptions will be omitted.

[0218] An N-type substrate (N-substrate) can be a silicon substrate used for semiconductor processing. An N-type substrate (N-substrate) can include a first surface on which light RL is incident and a second opposing surface opposite the first surface. An N-type substrate (N-substrate) can be an N-type body substrate, a substrate in which an N-type epitaxial layer is grown on a P-type body substrate, or a substrate in which an N-type epitaxial layer is grown on an N-type body substrate.

[0219] The first output node 3000a and the second output node 3000b can be located on the second surface of the N-type substrate (N substrate).

[0220] The first output node 3000a and the second output node 3000b can be regions doped with P-type impurities. The first output node 3000a and the second output node 3000b can detect holes 3000 generated in a unit pixel in the form of voltage pulses.

[0221] According to the implementation, the first output node 3000a and the second output node 3000b may further include multiple P-type impurity regions having different concentrations of each other.

[0222] The first bias node 3200a may have a shape surrounding the first output node 3000a. In the example, the first bias node 3200a may surround the first output node 3000a while being spaced apart from it. The first bias node 3200a may have a shape extending from the second surface of the N-type substrate (N substrate) toward the first surface of the N-type substrate (N substrate).

[0223] The first bias node 3200a may include a first high-concentration region 3210a, a first intermediate region 3220a, and a first well region 3230a. The first high-concentration region 3210a, the first intermediate region 3220a, and the first well region 3230a may be N-type doped regions.

[0224] The first high-concentration region 3210a may be the region with the highest concentration among the regions included in the first bias node 3200a. The first intermediate region 3220a may be located between the first high-concentration region 3210a and the first well region 3230a, and may have a concentration higher than that of the N-type substrate (N-substrate). The concentration of the first well region 3230a may be higher than that of the N-type substrate (N-substrate).

[0225] According to the implementation method, the doping concentration can be decreased in the order of the first high concentration region 3210a, the first intermediate region 3220a, the first well region 3230a, and the N-type substrate.

[0226] The second bias node 3200b may include a second high-concentration region 3210b, a second intermediate region 3220b, and a second well region 3230b. According to an embodiment, the doping concentration of the N-type impurity may decrease in the order of the second high-concentration region 3210b, the second intermediate region 3220b, the second well region 3230b, and the N-type substrate.

[0227] The first bias node 3200a and the second bias node 3200b can be electrically connected through a first connection region 3100. The first connection region 3100 can be a region doped with N-type impurities and can have the same impurity concentration as the first well region 3230a or the second well region 3230b.

[0228] Referring to the second cross-sectional structure 500a and the third cross-sectional structure 500b, the first separation structure 3300 included in the unit pixel may include a first outer separation layer 3310 and a first inner separation layer 3320.

[0229] The first separation structure 3300 can separate the first bias node 3200a and the second bias node 3200b from each other and can prevent holes from moving between the first bias node 3200a and the second bias node 3200b.

[0230] The first outer separator layer 3310 included in the first separator structure 3300 may include a silicon oxide film, a silicon nitride film, or a polycrystalline silicon film.

[0231] The first inner separator layer 3320 may include a silicon oxide film, a silicon nitride film, a polycrystalline silicon film, a metal layer, or an air layer.

[0232] The first separation structure 3300 can be formed by patterning one surface of the N-type substrate to form a deep trench to the opposite surface of the N-type substrate and filling the trench with a first outer separation layer 3310 and a first inner separation layer 3320.

[0233] Referring to the second cross-sectional structure 500a, the first partition structure 3300 may not be formed in the region forming the first connecting region 3100.

[0234] The thickness of the first connection region 3100 in the direction perpendicular to one surface of the N-type substrate can be less than the thickness of the first well region 3230a or the second well region 3230b in the direction perpendicular to one surface of the N-type substrate. (Refer to the above) Figure 2 The preset voltage described for determining whether to operate in the first or second mode can vary depending on the thickness of the first connection region 3100.

[0235] The second separation structure 3400 included in the unit pixel may include a second outer separation layer 3410, a second inner separation layer 3420, and a trench layer 3430.

[0236] The second partition structure 3400 can extend from one side of the N-type substrate to the opposite side to prevent holes from moving between adjacent unit pixels. The second partition structure 3400 can be configured to surround a plurality of SPADs included in a unit pixel. The second partition structure 3400 can be disposed outside the plurality of SPADs included in a unit pixel.

[0237] The second outer separator layer 3410 included in the second separator structure 3400 may include a silicon oxide film, a silicon nitride film, or a polycrystalline silicon film.

[0238] The second inner separator layer 3420 may include a silicon oxide film, a silicon nitride film, a polycrystalline silicon film, a metal layer, or an air layer.

[0239] The trench layer 3430 may have a shape extending from the second surface of the N-type substrate toward the first surface of the N-type substrate. The trench layer 3430 may include at least one of a silicon oxide film, a silicon nitride film, a polycrystalline silicon film, a metal layer, or an air layer.

[0240] The second separation structure 3400 can be formed by patterning one surface of the N-type substrate to form a deep trench and filling the trench with a second outer separation layer 3410 and a second inner separation layer 3420. Alternatively, a trench layer 3430 can be formed by patterning the opposite surfaces of the N-type substrate.

[0241] Figure 10 Examples include Figure 1 A diagram illustrating an implementation of a unit pixel in a pixel array.

[0242] Figure 10 An example is shown: a planar view of a unit pixel 600 taken from the direction of incident light on the pixel array.

[0243] Reference Figure 10 The unit pixel 600 included in the pixel array may include a first SPAD SPAD1e, a second SPAD SPAD2e, a third SPAD SPAD3e, and a fourth SPAD SPAD4e arranged in a 2x2 matrix.

[0244] The first SPAD SPAD1e may include a first bias node BN1e and a first output node ON1e. The second SPAD SPAD2e may include a second bias node BN2e and a second output node ON2e. The third SPAD SPAD3e may include a third bias node BN3e and a third output node ON3e. The fourth SPAD SPAD4e may include a fourth bias node BN4e and a fourth output node ON4e.

[0245] The first bias nodes to the fourth bias nodes BN1e, BN2e, BN3e, and BN4e can have a rectangular shape with rounded corners. Furthermore, the first output nodes to the fourth output nodes ON1e, ON2e, ON3e, and ON4e can have a circular shape.

[0246] Because the first to fourth bias nodes BN1e, BN2e, BN3e, and BN4e have a rectangular shape with rounded corners, the area where the bias voltage is applied can be larger than the unit pixel in other embodiments (e.g., Figure 7 The region of 500.

[0247] Figure 10 The unit pixel 600 shown may include a connection region disposed between two adjacent bias nodes and electrically connecting the two adjacent bias nodes.

[0248] The unit pixel 600 may include a first connection region IC12e connecting the first bias node BN1e and the second bias node BN2e, a second connection region IC13e connecting the first bias node BN1e and the third bias node BN3e, a third connection region IC24e connecting the second bias node BN2e and the fourth bias node BN4e, and a fourth connection region IC34e connecting the third bias node BN3e and the fourth bias node BN4e.

[0249] according to Figure 10In one implementation, the unit pixel 600 may include a first separating structure IS1e located between the four SPADs (SPAD1e, SPAD2e, SPAD3e, and SPAD4e) and a second separating structure IS2e surrounding the four SPADs (SPAD1e, SPAD2e, SPAD3e, and SPAD4e). In this example, the second separating structure IS2e may be disposed outside the four SPADs (SPAD1e, SPAD2e, SPAD3e, and SPAD4e).

[0250] The first to fourth connection regions IC12e, IC13e, IC24e, and IC34e can be disposed between the first partition structure IS1e and the second partition structure IS2e. The first to fourth connection regions IC12e, IC13e, IC24e, and IC34e can contact the first partition structure IS1e and the second partition structure IS2e.

[0251] and Figures 2 to 4 The implementation methods differ, and the first to fourth connection regions IC12e, IC13e, IC24e, and IC34e may not overlap with the first separating structure IS1e. In other words, the first separating structure IS1e may not be formed in the region forming the first to fourth connection regions IC12e, IC13e, IC24e, and IC34e.

[0252] Furthermore, the width of one side of the first to fourth connection regions IC12e, IC13e, IC24e and IC34e can be equal to the width of the first partition structure IS1e or the second partition structure IS2e.

[0253] The first separation structure IS1e can extend from one surface of the substrate toward the opposing surface on which the four SPADs SPAD1e, SPAD2e, SPAD3e and SPAD4e are formed, and can prevent electrons or holes from moving in the regions where the first to fourth connection regions IC12e, IC13e, IC24e and IC34e are not formed.

[0254] The second separation structure IS2e may include protruding structures PS12e, PS13e, PS24e, and PS34e extending from the edge of the second separation structure IS2e toward the first connection region to the fourth connection region IC12e, IC13e, IC24e, and IC34e. The protruding structures PS12e, PS13e, PS24e, and PS34e may extend from one surface of the substrate toward the opposite surface where the four SPADs SPAD1e, SPAD2e, SPAD3e, and SPAD4e are formed, and can prevent electrons or holes from moving in the regions where the first to fourth connection regions IC12e, IC13e, IC24e, and IC34e are not formed.

[0255] Figure 11 This is an example along Figure 10 A diagram illustrating an embodiment of the cross-sectional structure cut by the fourth cutting line C1-C1'.

[0256] Figure 12 This is an example along Figure 10 A diagram illustrating an embodiment of the cross-sectional structure cut by the fifth cutting line C2-C2'.

[0257] Reference Figure 11 Examples along Figure 10 The fourth section structure 600a is cut by the fourth cutting line C1-C1'.

[0258] Reference Figure 12 Examples along Figure 10 The fifth section structure 600b is obtained by cutting the fifth cutting line C2-C2'.

[0259] Reference Figure 11 and Figure 12 The cross-sectional structure of a unit pixel according to an embodiment of the present disclosure is described.

[0260] The fourth cross-section structure 600a and the fifth cross-section structure 600b will be described under the assumption that they are formed on an N-type substrate (N substrate) doped with N-type impurities (e.g., group V elements). Figure 11 The fourth section structure 600a and Figure 12 The fifth cross-section structure 600b. However, other implementations are also possible. For example, the fourth cross-section structure 600a and the fifth cross-section structure 600b can be structures formed in a well region doped with N-type impurities inside a P-type substrate doped with P-type impurities (e.g., group III elements).

[0261] A unit pixel may include a microlens ML located on an N-type substrate (N substrate) and a grid structure GS located between adjacent microlenses ML.

[0262] In addition, the unit pixel may include a first output node 4000a, a second output node 4000b, a first connection region 4100, a first bias node 4200a, a second bias node 4200b, a first separation structure 4300, and a second separation structure 4400 inside an N-type substrate (N substrate).

[0263] Microlenses ML and grating structures GS are the same as those mentioned above. Figure 5 and Figure 6 The components described are basically the same, so repeated descriptions will be omitted.

[0264] An N-type substrate (N-substrate) can be a silicon substrate used for semiconductor processing. An N-type substrate (N-substrate) can include a surface and an opposing surface opposite to the surface, on which light RL is incident. An N-type substrate (N-substrate) can be an N-type body substrate, a substrate in which an N-type epitaxial layer is grown on a P-type body substrate, or a substrate in which an N-type epitaxial layer is grown on an N-type body substrate.

[0265] The first output node 4000a and the second output node 4000b can be located on opposite surfaces of the N-type substrate (N substrate).

[0266] The first output node 4000a and the second output node 4000b can be regions doped with P-type impurities. The first output node 4000a and the second output node 4000b can detect holes generated in a unit pixel in the form of voltage pulses.

[0267] According to the implementation method, the first output node 4000a and the second output node 4000b may further include multiple P-type impurity regions with different concentrations.

[0268] The first bias node 4200a may have a shape surrounding the first output node 4000a. In the example, the first bias node 4200a may surround the first output node 1000a while being spaced apart from the first output node 4000a. The first bias node 4200a may have a shape extending from a second opposing surface of the N-type substrate (N substrate) toward a first surface of the N-type substrate (N substrate).

[0269] The first bias node 4200a may include a first high-concentration region 4210a, a first intermediate region 4220a, and a first well region 4230a. The first high-concentration region 4210a, the first intermediate region 4220a, and the first well region 4230a may be N-type doped regions.

[0270] The first high-concentration region 4210a may be the region with the highest concentration among the regions included in the first bias node 4200a. The first intermediate region 4220a may be located between the first high-concentration region 4210a and the first well region 4230a, and may have a concentration higher than that of the N-type substrate (N-substrate). The concentration of the first well region 4230a may be higher than that of the N-type substrate (N-substrate).

[0271] According to the implementation method, the doping concentration can be decreased in the order of the first high concentration region 4210a, the first intermediate region 4220a, the first well region 4230a, and the N-type substrate.

[0272] The second bias node 4200b may include a second high-concentration region 4210b, a second intermediate region 4220b, and a second well region 4230b. According to an embodiment, the doping concentration of the N-type impurity may decrease in the order of the second high-concentration region 4210b, the second intermediate region 4220b, the second well region 4230b, and the N-type substrate.

[0273] The first bias node 4200a and the second bias node 4200b can be electrically connected through a first connection region 4100. The first connection region 4100 can be a region doped with N-type impurities and can have the same impurity concentration as the first well region 4230a or the second well region 4230b.

[0274] The thickness of the first connection region 4100 in the direction perpendicular to one surface of the N-type substrate can be equal to the thickness of the first well region 4230a or the second well region 4230b in the direction perpendicular to one surface of the N-type substrate.

[0275] When the thickness of the first connection region 4100 is equal to the thickness of either the first well region 4230a or the second well region 4230b, the bias voltage supplied to one of the first well region 4230a and the second well region 4230b can easily affect the other. Therefore, compared to embodiments where the thickness of the first connection region 4100 is less than the thickness of either the first well region 4230a or the second well region 4230b, the preset voltage used to determine whether to operate in the first mode or the second mode can be reduced.

[0276] Referring to the fourth cross-sectional structure 600a and the fifth cross-sectional structure 600b, the first separation structure 4300 included in the unit pixel may include a first outer separation layer 4310 and a first inner separation layer 4320.

[0277] The first separation structure 4300 can separate the first bias node 4200a and the second bias node 4200b from each other and can prevent holes from moving between the first bias node 4200a and the second bias node 4200b.

[0278] The first outer separator layer 4310 included in the first separator structure 4300 may include a silicon oxide film, a silicon nitride film, or a polycrystalline silicon film.

[0279] The first inner separator layer 4320 may include a silicon oxide film, a silicon nitride film, a polycrystalline silicon film, a metal layer, or an air layer.

[0280] The first separation structure 4300 can be formed by patterning one surface of the N-type substrate to form a deep trench to the opposite surface of the N-type substrate and filling the trench with a first outer separation layer 4310 and a first inner separation layer 4320.

[0281] Referring to the fourth section structure 600a, the first partition structure 4300 may not be formed in the area where the first connecting region 4100 is formed.

[0282] The second separation structure 4400 included in the unit pixel may include a second outer separation layer 4410, a second inner separation layer 4420, and a trench layer 4430.

[0283] The second partition structure 4400 can extend from one side of the N-type substrate to the opposite side to prevent holes from moving between adjacent unit pixels. The second partition structure 4400 can be configured to surround a plurality of SPADs included in a unit pixel. The second partition structure 4400 can be located outside the plurality of SPADs included in a unit pixel.

[0284] The second outer separator layer 4410 included in the second separator structure 4400 may include a silicon oxide film, a silicon nitride film, or a polycrystalline silicon film.

[0285] The second inner separator layer 4420 may include a silicon oxide film, a silicon nitride film, a polycrystalline silicon film, a metal layer, or an air layer.

[0286] The trench layer 4430 may have a shape extending from the second surface of the N-type substrate toward the first surface of the N-type substrate. The trench layer 4430 may include at least one of a silicon oxide film, a silicon nitride film, a polycrystalline silicon film, a metal layer, or an air layer.

[0287] The second separation structure 4400 can be formed by patterning one surface of the N-type substrate to form a deep trench and filling the trench with a second outer separation layer 4410 and a second inner separation layer 4420. Alternatively, a trench layer 4430 can be formed by patterning the opposite surfaces of the N-type substrate.

[0288] The image sensing device according to embodiments of the present disclosure can adjust the bias voltage supplied to the single-photon avalanche diode, thereby increasing the photon detection efficiency of the single-photon avalanche diode or increasing the resolution of the image sensing device.

[0289] Furthermore, this disclosure can provide various effects that can be recognized directly or indirectly.

[0290] In the foregoing, although the present disclosure has been described with reference to exemplary embodiments and accompanying drawings, the present disclosure is not limited thereto, and variations and improvements can be made to the disclosed embodiments and other embodiments based on the content described or illustrated in this document.

[0291] Cross-reference to related applications

[0292] This application claims priority to Korean Patent Application No. 10-2024-0114382, filed on August 26, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. An image sensing device, the image sensing device comprising: A single-photon avalanche diode (SPAD), wherein the single-photon avalanche diodes are arranged adjacent to each other; as well as A connection region, which is located between two adjacent SPADs within the SPAD. Each of the SPADs includes: Output node, the output node outputs voltage pulses; and A bias node, configured to overlap with the output node and receive a bias voltage, and The connection region connects the bias node included in the SPAD.

2. The image sensing device according to claim 1, wherein, The output node is the cathode, and the bias node is the anode.

3. The image sensing device according to claim 1, wherein, The output node is the anode, and the bias node is the cathode.

4. The image sensing device according to claim 1, further comprising: A first separation structure is located between the two adjacent SPADs; as well as A second partition structure is disposed outside the SPAD.

5. The image sensing device according to claim 4, wherein, The first separating structure overlaps with the connecting area.

6. The image sensing device according to claim 4, wherein, The second partition structure includes a protruding structure extending toward the first partition structure, and The connecting region is located between the first separating structure and the protruding structure.

7. The image sensing device according to claim 1, wherein, The bias node has a circular shape.

8. The image sensing device according to claim 1, wherein, The offset node has a rounded rectangular shape.

9. The image sensing device according to claim 1, wherein, The impurity doping type of the output node is different from that of the bias node.

10. The image sensing device according to claim 4, wherein, The first partition structure and the second partition structure are included in the substrate, and Wherein, the depth of the first separating structure extending from the first surface of the substrate toward the second surface of the substrate opposite to the first surface of the substrate is less than the depth of the second separating structure.

11. The image sensing device according to claim 4, wherein, The first partition structure and the second partition structure are included in the substrate, and Wherein, the depth of the first separating structure extending from the first surface of the substrate toward the second surface of the substrate opposite to the first surface of the substrate is equal to the depth of the second separating structure.

12. The image sensing device according to claim 1, wherein, The bias voltage is a first bias voltage from each of the SPAD output voltage pulses or a second bias voltage from the SPAD output voltage pulses provided only from the bias voltage.

13. An image sensing device, the image sensing device comprising: A substrate having a first surface onto which light is incident; A single-photon avalanche diode (SPAD), wherein the single-photon avalanche diodes are located inside the substrate and adjacent to each other; A connection region that connects two adjacent SPADs in the SPAD; A first separation structure is located between two adjacent SPADs in the SPAD; as well as A second partition structure is located outside the SPAD. The first separation structure extends from the first surface of the substrate toward the connection region.

14. The image sensing device according to claim 13, wherein, Each of the SPADs includes: An output node, the output node being in contact with a second surface of the substrate, the second surface being opposite to a first surface of the substrate; and A bias node, which overlaps with the output node and is located inside the substrate.

15. The image sensing device according to claim 14, wherein, The doping type of the output node is different from that of the bias node.

16. The image sensing device according to claim 13, wherein, The second separation structure extends from the first surface of the substrate to the second surface of the substrate opposite to the first surface of the substrate.

17. The image sensing device according to claim 13, wherein, The connection area has a smaller width than the SPAD.

18. The image sensing device according to claim 13, wherein, The connection area has a smaller thickness than the SPAD.

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