Display panel and display device

Abstract

The invention provides a display panel and a display device.The display panel comprises a first substrate, a plurality of first thin film transistors located on one side of the first substrate, and first signal lines located on one sides of the first thin film transistors and insulated from the first thin film transistors; the plurality of first spacers are positioned on one side, facing the first substrate, of the second substrate; the orthographic projection of the first spacer on the first substrate and the orthographic projection of the first thin film transistor on the first substrate have an overlapping area, and the orthographic projection of the first spacer and the orthographic projection of the first signal line on the first substrate have an overlapping area.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Liquid crystal panels still dominate the low-end market due to their low cost. By improving the transmittance of liquid crystal panels, the cost of optical films used in backlight films can be reduced, reducing overall module costs and enhancing product competitiveness.

[0003] Spacers are designed in the display panel to support the liquid crystal box and ensure that it has a certain degree of pressure resistance when subjected to external forces.

[0004] Summary of the Invention

[0005] The present disclosure provides a display panel and a display device, wherein the display panel includes:

[0006] a first substrate, a plurality of first thin film transistors located on one side of the first substrate, and a first signal line located on one side of the first thin film transistor and insulated from the first thin film transistor;

[0007] a second substrate, and a plurality of first spacers located on a side of the second substrate facing the first substrate; an orthographic projection of the first spacers on the first substrate having an overlapping area with an orthographic projection of the first thin film transistor on the first substrate, and an overlapping area with an orthographic projection of the first signal line on the first substrate.

[0008] In a possible implementation, the display panel further includes: data lines and touch leads located on the first substrate and extending along a first direction and insulated from each other, and gate lines extending along a second direction, wherein the first direction intersects the second direction;

[0009] The first signal line is the touch lead.

[0010] In a possible implementation, the first thin film transistor includes a first gate electrode, a first active layer, and a first source and drain electrode that are stacked; the first source and drain electrode includes a first source electrode integrally connected to the data line, and a first drain electrode separated from the first source electrode;

[0011] An orthographic projection of a portion of the outer boundary of the first signal line away from the first drain electrode on the first substrate is located within an orthographic projection of the first spacer on the first substrate.

[0012] In a possible implementation, the display panel further includes at least one first raised portion located on the first substrate;

[0013] An orthographic projection of the first raised portion on the first substrate overlaps with an orthographic projection of the first signal line on the first substrate, and overlaps with an orthographic projection of the first spacer on the first substrate.

[0014] In a possible implementation manner, the first raised portion is a single film layer, or a composite structure including multiple film layers.

[0015] In a possible implementation manner, the first padding portion is located in a region where the gate line overlaps with the first signal line.

[0016] In a possible implementation manner, the first raised portion and the first active layer are in the same layer and made of the same material.

[0017] In a possible implementation manner, the first gate protrudes from the gate line toward a side close to the first drain;

[0018] The first padding portion and the first gate are located on the same side of the gate line, and an orthographic projection of the first padding portion on the first substrate has a gap with the gate line.

[0019] In a possible implementation manner, the first gate protrudes from both sides of the gate line along the first direction X;

[0020] The first raised portions are distributed on both sides of the gate line, and the orthographic projections of the first raised portions on different sides on the first substrate have gaps with the gate line.

[0021] In a possible implementation manner, the first raised portion includes a first floating metal and a first floating pattern located on a side of the first floating metal facing away from the first substrate;

[0022] The first floating metal and the first gate are formed in the same layer and material, and the first floating pattern and the first active layer are formed in the same layer and material.

[0023] In a possible implementation, an orthographic projection area of ​​the first floating metal on the first substrate is larger than an orthographic projection area of ​​the first floating pattern on the first substrate, and the orthographic projection of the first floating metal on the first substrate covers the orthographic projection of the first floating pattern on the first substrate.

[0024] In a possible implementation, the display panel further includes a plurality of second thin film transistors located on the first substrate, and a second raised portion on one side of the second thin film transistors;

[0025] The display panel also includes a plurality of second spacers located on the side of the second substrate facing the first substrate, and the orthographic projection of the second spacers on the first substrate has an overlapping area with the orthographic projection of the second thin film transistor on the first substrate, and has an overlapping area with the orthographic projection of the second raised portion on the first substrate.

[0026] In a possible implementation, the second thin film transistor includes a second gate electrode, a second active layer, and a second source and drain electrode that are stacked; the second source and drain electrode includes a second source electrode integrally connected to the data line, and a second drain electrode separated from the first source electrode;

[0027] The second padding portion and the second drain electrode are located on different sides of the data line.

[0028] In a possible implementation manner, an orthographic projection of the second raised portion on the first substrate is located within an orthographic projection of the second gate on the first substrate.

[0029] In a possible implementation manner, the second padding portion includes a second floating metal, and the second floating metal and the second source and drain are made of the same layer and material.

[0030] In a possible implementation manner, the second raised portion further includes a second floating pattern, and the second floating pattern and the second active layer are in the same layer and made of the same material.

[0031] In a possible implementation manner, the second source electrode has a straight side at a side away from the second drain electrode; and the second raised portion has a straight side at an outer boundary facing the second source electrode.

[0032] In a possible implementation manner, the second source electrode has a recess on a side facing away from the second drain electrode; and the second raised portion has a protrusion on an outer boundary facing the second source electrode.

[0033] In a possible implementation manner, an orthographic projection of the second gate on the first substrate and an orthographic projection of the second raised portion on the first substrate have an overlapping region.

[0034] In a possible implementation, the orthographic projection of the second raised portion on the first substrate is located within the orthographic projection of the second gate on the first substrate; and the orthographic projection of at least part of the second source on the first substrate is located within the orthographic projection of the second gate on the first substrate.

[0035] In one possible embodiment, the maximum length of the orthographic projection of the first spacer on the first substrate in the second direction is greater than the maximum length of the orthographic projection of the second spacer on the first substrate in the second direction; the maximum length of the orthographic projection of the first spacer on the first substrate in the first direction is approximately equal to the maximum length of the orthographic projection of the second spacer on the first substrate in the second direction.

[0036] In a possible implementation manner, the second spacer includes a first sub-spacer and a second sub-spacer;

[0037] The height of the first sub-spacer in a direction perpendicular to the first substrate is greater than the height of the second sub-spacer in the direction perpendicular to the first substrate, and the height of the first sub-spacer in a direction perpendicular to the first substrate is greater than the height of the first spacer in the direction perpendicular to the first substrate.

[0038] In a possible implementation, the display panel includes a surface film layer located on the first substrate, and a distance between the surface film layer and the first substrate is greater than a distance between the remaining film layers located on the first substrate and the first substrate;

[0039] There is a first gap between the first spacer and the surface film layer, and there is a second gap between the second sub-spacer and the surface film layer; the first sub-spacer is in contact with the surface film layer.

[0040] In a possible implementation manner, a length of an orthographic projection of the first sub-spacer on the first substrate in the second direction is smaller than a length of an orthographic projection of the second sub-spacer on the first substrate in the second direction.

[0041] In a possible implementation manner, an orthographic projection of the first sub-spacer on the first substrate does not overlap with an orthographic projection of the second drain on the first substrate.

[0042] In a possible implementation, the second gate is in the same layer and material as the first gate, the second active layer is in the same layer and material as the first active layer, and the second source and drain are in the same layer and material as the first source and drain.

[0043] In a possible implementation, the display panel further includes a pixel electrode located on the first substrate, and the pixel electrode is located between the first gate and the first active layer;

[0044] The first drain electrode is in contact with and electrically connected to the pixel electrode, and the second drain electrode is in contact with and electrically connected to the pixel electrode.

[0045] In a possible implementation, the display panel further includes a pixel electrode located on the first substrate, wherein the pixel electrode is located on a side of the first source and drain away from the first active layer;

[0046] The first drain electrode is electrically connected to the pixel electrode through a first via hole, and the second drain electrode is electrically connected to the pixel electrode through a second via hole.

[0047] In a possible implementation, the display panel further includes a common electrode layer located on the first substrate, the common electrode layer being reused as a touch electrode layer and having a plurality of mutually insulated touch electrode blocks;

[0048] The touch leads are electrically connected to the touch electrode blocks one by one through via holes.

[0049] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIG1 is a schematic cross-sectional view of FIG2A taken along the dotted line AB;

[0051] FIG2A is a schematic top view of a display panel according to an embodiment of the present disclosure;

[0052] FIG2B is a schematic diagram of a single film layer including a gate line in FIG2A;

[0053] FIG2C is a schematic diagram of a single film layer including a first active layer in FIG2A ;

[0054] FIG2D is a schematic diagram of a single film layer including the first source and drain electrodes in FIG2A ;

[0055] FIG2E is a schematic diagram of a single film layer including a first spacer in FIG2A ;

[0056] FIG2F is a schematic diagram of a single film layer of the black matrix in FIG2A ;

[0057] FIG3 is a schematic cross-sectional view of FIG4A taken along the dotted line AB;

[0058] FIG4A is a second schematic top view of a display panel provided by an embodiment of the present disclosure;

[0059] FIG4B is a schematic diagram of a single film layer including a gate line in FIG4A;

[0060] FIG4C is a schematic diagram of a single film layer including the first active layer in FIG4A ;

[0061] FIG4D is a schematic diagram of a single film layer including the first source and drain electrodes in FIG4A ;

[0062] FIG4E is a schematic diagram of a single film layer including a first spacer in FIG4A ;

[0063] FIG4F is a schematic diagram of a single film layer of the black matrix in FIG4A ;

[0064] FIG5 is a third schematic top view of a display panel provided in an embodiment of the present disclosure;

[0065] FIG6A is a fourth schematic top view of a display panel provided by an embodiment of the present disclosure;

[0066] FIG6B is a schematic cross-sectional view of FIG6A taken along the dotted line AB;

[0067] FIG6C is a schematic diagram of a single film layer including a gate line in FIG6A;

[0068] FIG6D is a schematic diagram of a single film layer including the first active layer in FIG6A;

[0069] FIG6E is a schematic diagram of a single film layer including the first source and drain electrodes in FIG6A ;

[0070] FIG6F is a schematic diagram of a single film layer including a first spacer in FIG6A ;

[0071] FIG6G is a schematic diagram of a single film layer of the black matrix in FIG6A ;

[0072] FIG6H is a schematic diagram showing the concave and convex portions being rectangular;

[0073] FIG6I is a schematic diagram showing a case where the concave and convex portions are triangular;

[0074] FIG6J is a schematic diagram showing a case where the concave and convex portions are semicircular;

[0075] FIG6K is a schematic diagram showing that the concave and convex portions are arc-shaped;

[0076] FIG6L is a schematic diagram showing that the concave and convex portions are wavy;

[0077] FIG7A is a fifth schematic top view of a display panel provided by an embodiment of the present disclosure;

[0078] FIG7B is a sixth schematic top view of a display panel provided by an embodiment of the present disclosure;

[0079] FIG8A is a seventh schematic top view of a display panel provided by an embodiment of the present disclosure;

[0080] FIG8B is a schematic cross-sectional view of FIG8A taken along the dotted line AB;

[0081] FIG8C is a schematic diagram of a single film layer including gate lines in FIG8A;

[0082] FIG8D is a schematic diagram of a single film layer including the first active layer in FIG8A;

[0083] FIG8E is a schematic diagram of a single film layer including the first source and drain electrodes in FIG8A ;

[0084] FIG8F is a schematic diagram of a single film layer including a first spacer in FIG8A;

[0085] FIG8G is a schematic diagram of a single film layer of the black matrix in FIG8A ;

[0086] FIG9A is an eighth schematic top view of a display panel provided by an embodiment of the present disclosure;

[0087] FIG9B is a schematic diagram of a single film layer including the first source and drain electrodes in FIG9A ;

[0088] FIG10 is a schematic top view of a touch electrode layer provided by an embodiment of the present disclosure;

[0089] 11 is a schematic diagram showing an arrangement of a plurality of first spacers, first sub-spacers, and second sub-spacers when the first thin film transistor T1 is an oxide thin film transistor;

[0090] FIG12A is an enlarged schematic diagram of the dotted line frame S1 in FIG11 ;

[0091] FIG12B is an enlarged schematic diagram of the dotted line frame S2 in FIG11 ;

[0092] 13 is a schematic diagram showing an arrangement of the first spacer, the first sub-spacer and the second sub-spacer when the first thin film transistor T1 is a polysilicon thin film transistor;

[0093] FIG14A is an enlarged schematic diagram of the dotted line frame S3 in FIG13 ;

[0094] FIG14B is an enlarged schematic diagram of the dotted line frame S4 ​​in FIG13 . DETAILED DESCRIPTION

[0095] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0096] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0097] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0098] When describing some embodiments, the terms "electrically connected" and "connected" and their derivatives may be used. For example, the term "point connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

[0099] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0100] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0101] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0102] As used herein, "approximately" or "substantially" includes the stated value and an average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0103] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0104] In LCD panels, spacers are typically placed beneath the black matrix of the color filter substrate, between two color resists, corresponding to the thin-film transistor (TFT) area of ​​the array substrate. In mobile phones, spacers are placed between each pixel to ensure maximum contact density. The contact density of the spacers above the TFT area is often used as a reference value for compressive strength.

[0105] In view of this, referring to Figures 1 to 4F, wherein Figure 1 is a schematic cross-sectional view of Figure 2A taken along the dotted line AB, Figures 2B to 2F are schematic diagrams of single film layers of each film layer in Figure 2A, Figure 3 is a schematic cross-sectional view of Figure 4A taken along the dotted line CD, and Figures 4B to 4F are schematic diagrams of single film layers of each film layer in Figure 4A, an embodiment of the present disclosure provides a display panel, comprising:

[0106] A first substrate 11, a plurality of first thin film transistors T1 located on one side of the first substrate 11, and a first signal line L located on one side of the first thin film transistor T1 and insulated from the first thin film transistor T1; specifically, the first substrate 11 may be provided with a plurality of thin film transistors, and among the plurality of thin film transistors, thin film transistors with the first signal line L disposed around them may serve as the first thin film transistor T1, and thin film transistors without the first signal line L disposed around them may serve as the second thin film transistor T2;

[0107] The second substrate 21 includes a plurality of first spacers 241 located on the side of the second substrate 21 facing the first substrate 11; the orthographic projection of the first spacers 241 on the first substrate 11 overlaps with the orthographic projection of the first thin film transistor T1 on the first substrate 11, and also overlaps with the orthographic projection of the first signal line L on the first substrate 11.

[0108] In the embodiment of the present disclosure, the orthographic projection of the first spacer 241 on the first substrate 11 has an overlapping area with the orthographic projection of the first thin film transistor T1 on the first substrate 11, and has an overlapping area with the orthographic projection of the first signal line L on the first substrate 11. When the display panel is pressed, the area where the first signal line L is located can also support the first spacer 241, thereby improving the pressure resistance of the display panel without sacrificing the aperture ratio.

[0109] In one possible embodiment, the display panel further includes: data lines 154 and touch leads 153 located on the first substrate 11 and extending along a first direction X and insulated from each other, and gate lines 123 extending along a second direction Y, wherein the first direction X intersects the second direction Y; and first signal lines L are touch leads 153. In the disclosed embodiment, the first signal lines L are touch leads 153. Existing touch leads 153 on the display panel can be utilized as the first signal lines L, and the first spacers 241 are also disposed in the region where the first signal lines L are located. This eliminates the need for separately fabricating the first signal lines L, thereby improving the pressure resistance of the display panel while simplifying the display panel manufacturing process.

[0110] In a specific implementation, optionally, the first signal line L may also be other signal lines of the display panel. As long as the signal line is arranged around the thin film transistor in the display panel and is insulated from the thin film transistor, it can serve as the first signal line L. For example, in one possible embodiment, the first signal line L may also be the lead of the common electrode in the display panel.

[0111] In a possible embodiment, with reference to Figures 1 to 4F , the first thin film transistor T1 includes a first gate electrode 121, a first active layer 141, and a first source and drain electrode that are stacked; the first source and drain electrode includes a first source electrode 151 integrally connected to the data line 154, and a first drain electrode 152 separated from the first source electrode 151; the orthographic projection of a portion of the outer boundary S1 of the first signal line L away from the first drain electrode 152 on the first substrate 11 is located within the orthographic projection of the first spacer 241 on the first substrate 11. Specifically, for example, with reference to Figure 2A , the orthographic projection of a portion of the outer boundary S1 of the first signal line L away from the first drain electrode 152 on the first substrate 11 does not exceed the orthographic projection of an outer boundary S2 of the first spacer 241 away from the first drain electrode 152 on the first substrate 11. In the embodiment of the present disclosure, the orthographic projection of the portion of the outer boundary S1 of the first signal line L away from the first drain 152 on the first substrate 11 is located within the orthographic projection of the first spacer 241 on the first substrate 11, that is, in the second direction Y, the orthographic projection of the first spacer 241 on the first substrate 11 can cross the orthographic projection of the first signal line L on the first substrate 11, thereby maximizing the utilization of the area where the first signal line L is located, so as to achieve maximum effective support for the first spacer 241 when it is pressed.

[0112] Specifically, as shown in Figure 2A or Figure 4A, the second thin film transistor T2 may include a second gate electrode 124, a second active layer 144, and a second source and drain electrode that are stacked; the second source and drain electrode includes a second source electrode 156 integrally connected to the data line 154, and a second drain electrode 157 separated from the second source electrode 156.

[0113] 1 to 4F , preferably, the first thin film transistor T1 provided in the embodiment of the present disclosure may be a bottom-gate thin film transistor. In a specific implementation, optionally, the first thin film transistor provided in the embodiment of the present disclosure may also be a top-gate thin film transistor.

[0114] Specifically, as shown in FIG. 1 to FIG. 2F , the thin film transistor (including the first thin film transistor T1) provided in the embodiment of the present disclosure may be an oxide transistor. When the thin film transistor is an oxide thin film transistor, it may have a smaller size, which is conducive to realizing a narrow-frame design of a display panel. Specifically, the active layer in the oxide transistor may be an oxide semiconductor. For example, the material of the active layer may be indium gallium zinc oxide (In-Ga-Zn-Ox, IGZO).

[0115] When the thin film transistor provided in the embodiment of the present disclosure is an oxide thin film transistor, the structure shown in FIG1 to FIG2F is further described in detail as follows:

[0116] The first active layer 141 may be located on a side of the first gate 121 away from the first substrate 11 , the first source and drain may be located on a side of the first active layer 141 away from the first gate 121 , and a gate insulating layer 13 may be further disposed between the first gate 121 and the first active layer 141 ;

[0117] The display panel may further include a first passivation layer 161 located on a side of the first source and drain electrodes away from the first active layer 141, a first electrode 17 located on a side of the first passivation layer 161 away from the first source and drain electrodes, a second passivation layer 162 located on a side of the first electrode 17 away from the first passivation layer 161, and a second electrode 19 located on a side of the second passivation layer 162 away from the first electrode 17; specifically, the first electrode 17 may be a common electrode, the second electrode 19 may be a pixel electrode, and the materials of the first electrode 17 and the second electrode 19 may be indium tin oxide; the second electrode 19 may be electrically connected to the first drain electrode 152 through a via K1; at the position of the first thin film transistor T1, the first drain electrode 152 and the pixel electrode (second electrode 19) may be electrically connected through the first via K1; at the position of the second thin film transistor T2, the second drain electrode 157 and the pixel electrode (second electrode 19) may be electrically connected through the second via K2;

[0118] Specifically, the first gate 121 can protrude from one side of the gate line 123, for example, the first gate 121 protrudes from the gate line 123 toward the side close to the first drain 152; the first drain 152 includes: a first main body 1521, and an extension portion 1522 extending from the first main body 1521 toward the side of the first gate 121, the orthographic projection of the first active layer 141 on the first substrate 11 has an overlapping area with the orthographic projection of the first gate 121 on the first substrate 11; the orthographic projection of the first active layer 141 on the first substrate 11 has an overlapping area with the orthographic projection of the extension portion 1522 on the first substrate 11.

[0119] Specifically, the display panel may further include: a color filter layer located between the second substrate 21 and the first spacer 241; specifically, the color filter layer may include a blue color resist 231, a red color resist 232 and a green color resist (not shown in the figure); specifically, in combination with FIG1 , the orthographic projection of the first spacer 241 on the second substrate 21 has an overlapping area with the orthographic projection of the blue color resist 231 on the second substrate 21, and has an overlapping area with the orthographic projection of the red color resist 232 on the second substrate 21; of course, in some possible embodiments, the orthographic projection of the first spacer 241 on the second substrate 21 has an overlapping area with the orthographic projection of the blue color resist 231 on the second substrate 21, and has an overlapping area with the orthographic projection of the green color resist on the second substrate 21 has an overlapping area with the orthographic projection of the first spacer 241 on the second substrate 21; in other possible embodiments, the orthographic projection of the first spacer 241 on the second substrate 21 has an overlapping area with the orthographic projection of the red color resist 232 on the second substrate 21, and has an overlapping area with the orthographic projection of the green color resist on the second substrate 21; a black matrix 22 can be further provided between the color filter layer and the second substrate 21, and an optical adhesive layer 25 can be further provided on the side of the color filter layer away from the first substrate 21; the first substrate 11 and the various film layers on the first substrate 11 can form a first substrate 1, and the second substrate 21 and the various film layers on the second substrate 21 can form a second substrate 2. Specifically, the first substrate 1 can be an array substrate, and the second substrate 2 can be a color filter substrate.

[0120] Specifically, with reference to FIG. 3 to FIG. 4F , the thin film transistor (including the first thin film transistor T1 ) provided in the embodiment of the present disclosure may be a polysilicon transistor;

[0121] When the thin film transistor provided in the embodiment of the present disclosure is a polysilicon thin film transistor, the structures shown in FIG3 and FIG4F are further described in detail as follows:

[0122] The first active layer 141 may be located on a side of the first gate 121 away from the first substrate 11 , the first source and drain may be located on a side of the first active layer 141 away from the first gate 121 , and a gate insulating layer 13 may be further disposed between the first gate 121 and the first active layer 141 ;

[0123] The display panel may further include a first electrode 17 located between the gate insulating layer 13 and the first active layer 141, a third passivation layer 163 located on a side of the first source and drain electrode away from the first active layer 141, and a second electrode 19 located on a side of the third passivation layer 163 away from the first source and drain electrode. Specifically, the first electrode 17 may be a pixel electrode, and the second electrode 19 may be a common electrode. The materials of the first electrode 17 and the second electrode 19 may be indium tin oxide. The first electrode 17 may be a pixel electrode and may be directly in contact with and electrically connected to the first drain electrode 152.

[0124] Specifically, the first gate 121 may protrude from both sides of the gate line 123, for example, the first gate 121 protrudes from both sides of the gate line 123 along the first direction X; the first drain 152 includes: a third main portion 1523 extending along the first direction X, and a fourth main portion 1524 connected to one end of the third main portion 1523 and extending along the second direction Y; the orthographic projection of the first active layer 141 on the first substrate 11 has an overlapping area with the orthographic projection of the first gate 121 on the first substrate 11, and the orthographic projection of the first active layer 141 on the first substrate 11 has an overlapping area with the orthographic projection of the fourth main portion 1524 on the first substrate 11; in the first direction X, the orthographic projection of the first spacer 241 on the first substrate 11 has an overlapping area with the orthographic projection of the fourth main portion 1524 on the first substrate 11, and the orthographic projection of the first spacer 241 on the first substrate 11 does not overlap with the orthographic projection of the third main portion 1523 on the first substrate 11.

[0125] Specifically, the display panel may further include: a color filter layer located between the second substrate 21 and the first spacer 241; specifically, the color filter layer may include a blue color resist 231, a red color resist 232 and a green color resist (not shown in the figure); specifically, in combination with FIG3 , the orthographic projection of the first spacer 241 on the second substrate 21 has an overlapping area with the orthographic projection of the blue color resist 231 on the second substrate 21, and has an overlapping area with the orthographic projection of the red color resist 232 on the second substrate 21; of course, in some possible embodiments, the orthographic projection of the first spacer 241 on the second substrate 21 has an overlapping area with the orthographic projection of the blue color resist 231 on the second substrate 21, and has an overlapping area with the orthographic projection of the green color resist on the second substrate 21 has an overlapping area; in other possible embodiments, the orthographic projection of the first spacer 241 on the second substrate 21 has an overlapping area with the orthographic projection of the red color resist 232 on the second substrate 21, and has an overlapping area with the orthographic projection of the green color resist on the second substrate 21; a black matrix 22 can be further provided between the color filter layer and the second substrate 21, and an optical adhesive layer 25 can be further provided on the side of the color filter layer away from the first substrate 11; the first substrate 11 and the various film layers on the first substrate 11 can form a first substrate 1, and the second substrate 21 and the various film layers on the second substrate 21 can form a second substrate 2. Specifically, the first substrate 1 can be an array substrate, and the second substrate 2 can be a color filter substrate.

[0126] In one possible embodiment, referring to Figures 5-8F, Figure 6B is a schematic cross-sectional view of Figure 6A taken along dotted line AB, Figures 6C-6G are schematic single-layer views of each film layer in Figure 6A, Figure 8B is a schematic cross-sectional view of Figure 8A taken along dotted line CD, and Figures 8C-8G are schematic single-layer views of each film layer in Figure 8A. The display panel further includes at least one first raised portion F1 located on the first substrate 11; the orthographic projection of the first raised portion F1 on the first substrate 11 overlaps with the orthographic projection of the first signal line L on the first substrate 11, and also overlaps with the orthographic projection of the first spacer 241 on the first substrate. Thus, when the display panel is pressed, the area where the first raised portion F1 is located can also support the first spacer 241, thereby further improving the pressure resistance of the display panel without sacrificing the aperture ratio.

[0127] In a specific implementation, the first raised portion F1 can be a single film layer, or a composite structure including multiple film layers. The display panel can be provided with one first raised portion F1, two first raised portions F1, three first raised portions F1, or more first raised portions F1; the position of the first raised portion F1 can be flexibly set as needed, as described in detail below:

[0128] In a possible embodiment, referring to FIG7A , the first padding portion 143 (F1) is located in the region where the gate line 123 overlaps with the first signal line L. Specifically, the first padding portion 143 (F1) is in the same layer and made of the same material as the first active layer 141. In the embodiment of the present disclosure, since the region where the first thin-film transistor T1 is located has the first active layer 141, the first padding portion 143 (F1) is provided in the region where the gate line 123 overlaps with the first signal line L, and the first padding portion 143 (F1) is in the same layer and made of the same material as the first active layer 141, the height of the region where the first thin-film transistor T1 is located can be roughly the same as the height of the region where the gate line 123 overlaps with the first signal line L, thereby making the gap between the first spacer 241 and the topmost film layer of the first substrate 1 consistent, thereby playing a role in supporting the first spacer 241 in terms of height. In addition, the first raised portion 143 (F1) is made of the same layer and material as the first active layer 141. The first raised portion 143 (F1) can be formed at the same time as the first active layer 141. This simplifies the manufacturing process of the display panel while satisfying the requirement that the height of the area where the first thin film transistor T1 is located is roughly the same as the height of the area where the gate line 123 and the first signal line L overlap.

[0129] Specifically, as shown in Figure 7A, the orthographic projection of the first padding portion 143 (F1) on the first substrate 11 can be similar to the orthographic projection shape of the area formed by the overlap of the gate line 123 and the first signal line L on the first substrate 11. For example, the orthographic projection shape of the area formed by the overlap of the gate line 123 and the first signal line L on the first substrate 11 is a rectangle, and the orthographic projection of the first padding portion 143 (F1) on the first substrate 11 is also a rectangle; specifically, in combination with Figures 8B, 8C and 8D, in the first direction X, the length L1 of the first padding portion 143 (F1) is greater than the length L2 of the gate line 123; in the second direction Y, the length L3 of the first padding portion 143 (F1) is greater than the length L4 of the first signal line L.

[0130] It should be noted that the embodiment of the present disclosure is merely a schematic illustration of setting the first padding portion F1 in the region where the gate line 123 overlaps the first signal line L, taking the first thin film transistor T1 shown in FIG7A as an example being a polysilicon thin film transistor. In a specific implementation, if the first thin film transistor T1 is an oxide thin film transistor, the first padding portion F1 may also be set in the region where the gate line 123 overlaps the first signal line L, and the first padding portion 143 (F1) may be made of the same layer and material as the first active layer 141.

[0131] In one possible embodiment, in a structure where the first thin-film transistor T1 is an oxide thin-film transistor, as shown in Figures 5-6G , the first gate 121 protrudes from the gate line 123 toward the side closer to the drain 152. The first raised portion 122 (F1) / 142 (F1) and the first gate 121 are located on the same side of the gate line 123, and the orthographic projection of the first raised portion 122 (F1) / 142 (F1) on the first substrate 11 is spaced apart from the gate line 123. Specifically, as shown in Figures 5-6G , the first raised portion F1 includes a first floating metal 122 and a first floating pattern 142 located on a side of the first floating metal 122 facing away from the first substrate 11. The first floating metal 122 and the first gate 121 are formed from the same layer and material, and the first floating pattern 142 and the first active layer 141 are formed from the same layer and material. In the embodiment of the present disclosure, in the first direction X, when the first spacer 241 is extended over the first signal line L, at the region where the first thin film transistor T1 is located, the first spacer 241 has both the first gate 121 and the first active layer 141 in the region where the orthographic projection of the first substrate 11 is located. By providing the first raised portion 122 (F1) / 142 (F1) located on the same side of the gate line 123 as the first gate 121 in the region where the first signal line L is located, the first spacer 241 can be supported on both the left and right sides in the first direction X, thereby achieving balanced support. This avoids the situation where the height is higher only in the region where the first thin film transistor T1 is located and lower in the region where the first signal line L is located, which would prevent the first spacer 241 from being effectively supported due to inconsistent heights when the display panel is pressed. In addition, the first floating metal 122 and the first gate 121 are made of the same layer and material, and the first floating pattern 142 and the first active layer 141 are made of the same layer and material. This can simplify the manufacturing process of the display panel while satisfying the requirement of making the height of the area where the first thin film transistor T1 is located and the height of the area where the first signal line L is located roughly the same.

[0132] In addition, the first raised portion 122 (F1) / 142 (F1) has a gap between its orthographic projection on the first substrate 11 and the gate line 123. The first raised portion 122 (F1) / 142 (F1) includes a first floating metal 122 and a first floating pattern 142 located on the side of the first floating metal 122 facing away from the first substrate 11. The first floating metal 122 and the first gate 121 are formed in the same layer and material, and the first floating pattern 142 and the first active layer 141 are formed in the same layer and material. Since the first floating metal 122 and the gate line 123 have a gap and are not connected, no signal is loaded during actual use. This can improve the pressure resistance of the display panel while not increasing the load on the gate line 123 and the first signal line L.

[0133] In one possible embodiment, for a structure in which the first thin-film transistor T1 is a polysilicon thin-film transistor, as shown in Figures 7B-8G , the first gate 121 protrudes from both sides of the gate line 123 along the first direction X; first raised portions 122(F1) / 142(F1) are distributed on both sides of the gate line 123, and the orthographic projections of the first raised portions 122(F1) / 142(F1) on different sides on the first substrate 11 are spaced apart from the gate line 123. Specifically, as shown in Figures 7B-8G , the first raised portions 122(F1) / 142(F1) include a first floating metal 122 and a first floating pattern 142 located on a side of the first floating metal 122 facing away from the first substrate 11; the first floating metal 122 and the first gate 121 are formed from the same layer and material, and the first floating pattern 142 and the first active layer 141 are formed from the same layer and material. In the disclosed embodiment, the first gate 121 protrudes from both sides of the gate line 123 along the first direction X. The first raised portions 122(F1) / 142(F1) are distributed on both sides of the gate line 123. When the display panel is pressed, the first raised portions 122(F1) / 142(F1) on both sides can provide effective support after the first spacer 241 fluctuates in position due to the pressure. Furthermore, the first floating metal 122 and the first gate 121 are constructed from the same layer and material, and the first floating pattern 142 and the first active layer 141 are constructed from the same layer and material, simplifying the display panel manufacturing process.

[0134] In addition, the first gate 121 protrudes from both sides of the gate line 123 along the first direction X. The first raised portions F1 on different sides have gaps between their orthographic projections on the first substrate 11 and the gate line 123. The first raised portions 122 (F1) / 142 (F1) include a first floating metal 122 and a first floating pattern 142 located on the side of the first floating metal 122 facing away from the first substrate 11. The first floating metal 122 and the first gate 121 are formed from the same layer and material, and the first floating pattern 142 and the first active layer 141 are formed from the same layer and material. Since the first floating metals 122 on different sides have gaps between their orthographic projections on the first substrate 11 and the gate line 123 and are not connected, in actual use, the first floating metal 122 does not carry any signal, thereby improving the pressure resistance of the display panel while not increasing the load on the gate line 123 and the first signal line L.

[0135] In one possible embodiment, as shown in conjunction with FIG6A and FIG8A , the orthographic projection area of ​​the first floating metal 122 on the first substrate 11 is larger than the orthographic projection area of ​​the first floating pattern 142 on the first substrate 11, and the orthographic projection of the first floating metal 122 on the first substrate 11 overlaps the orthographic projection of the first floating pattern 142 on the first substrate 11. Specifically, the orthographic projection of the first floating metal 122 on the first substrate 11 is located within the region where the orthographic projection of the black matrix 22 on the first substrate 11 is located; and the orthographic projection of the first floating pattern 142 on the first substrate 11 is located within the region where the orthographic projection of the black matrix 22 on the first substrate 11 is located. In this way, the pressure resistance of the display panel can be improved without affecting the aperture ratio of the display panel.

[0136] In one possible embodiment, as shown in conjunction with Figures 6A, 8A, and 9A, the display panel further includes a second raised portion F2 located on one side of the second thin-film transistor T2. The display panel further includes a plurality of second spacers 242 located on the side of the second substrate 21 facing the first substrate 11. The orthographic projections of the second spacers 242 on the first substrate 11 overlap with the orthographic projections of the second thin-film transistor T2 on the first substrate 11, and also overlap with the orthographic projections of the second raised portion F2 on the first substrate 11. In the disclosed embodiment, the display panel further includes a second raised portion F2 located on one side of the second thin-film transistor T2. The orthographic projections of the second spacers 242 on the first substrate 11 overlap with the orthographic projections of the second thin-film transistor T2 on the first substrate 11, and also overlap with the orthographic projections of the second raised portion F2 on the first substrate 11. When the display panel is pressed, the area where the second raised portion F2 is located can also support the second spacers 242, thereby improving the pressure resistance of the display panel without compromising the aperture ratio.

[0137] In one possible embodiment, as shown in Figures 6A, 8A, and 9A, the second raised portion F2 and the second drain electrode 157 of the second thin film transistor T2 are located on different sides of the data line 154. In this way, the left and right sides of the second spacer 242 can be balanced and supported in the second direction Y.

[0138] In one possible embodiment, in conjunction with Figures 6A, 8A, and 9A, the orthographic projection of the second raised portion F2 on the first substrate 11 is located within the orthographic projection of the second gate 124 on the first substrate 11. Specifically, the orthographic projection of the second raised portion F2 on the first substrate 11 is located within the orthographic projection of the second gate 124 on the first substrate 11. It can be understood that the orthographic projection of the second raised portion F2 on the first substrate 11 is located within the orthographic projection of the second gate 124 and the portion of the gate line 123 connected to the second gate 124 on the first substrate 11. Specifically, in conjunction with Figures 6C-6G and 8C-8G, the length L5 of the second raised portion F2 in the first direction X can be substantially the same as the length L6 of the second gate 124 in the first direction X. It is understandable that in the actual manufacturing process, due to process limitations, it is difficult to achieve the requirement that the length L5 of the second pad portion F2 in the first direction X is exactly the same as the length L6 of the second gate 124 in the first direction X. Therefore, in the embodiment of the present disclosure, the length L5 of the second pad portion F2 in the first direction X is approximately the same as the length L6 of the second gate 124 in the first direction X. It can be understood that the difference between the two and the ratio range of either one of them is less than 10%.

[0139] In one possible embodiment, as shown in conjunction with Figures 6A, 8A, and 9A, the second raised portion F2 includes a second floating metal 155, which is formed from the same layer and material as the second source and drain electrodes. In the disclosed embodiment, the second raised portion F2 includes the second floating metal 155, which is formed from the same layer and material as the second source and drain electrodes. This simplifies the display panel manufacturing process while ensuring that the height of the region where the second thin-film transistor T2 is located is approximately the same as that of the region where the second raised portion F2 is located.

[0140] In a possible implementation, similar to the first elevated portion F1 , the second elevated portion F2 further includes a second floating pattern (not shown in the figure). The second floating pattern may be in the same layer and material as the second active layer 144 .

[0141] In one possible embodiment, as shown in conjunction with Figures 6A-6L , the second source electrode 156 has a recess P1 on a side away from the second drain electrode 157, and the second raised portion F2 has a raised portion P2 on an outer boundary facing the second source electrode 156. In the disclosed embodiment, the recess P1 on the side away from the second drain electrode 157 of the second source electrode 156 can reduce the overlapping area between the data line 154 and the gate line 123 and / or the gate electrode 124, thereby reducing the parasitic capacitance between the data line 154 and the gate line 123 and / or the gate electrode 124. Since the second source electrode 156 has the recess P1 on the side away from the second drain electrode 157, the second raised portion F2 can have a raised portion P2 on an outer boundary facing the second source electrode 156. This can increase the orthographic projection area of ​​the second raised portion F2 on the first substrate 11 while ensuring mutual insulation between the second raised portion F2 and the data line 154, thereby effectively supporting the second spacer 242.

[0142] In a specific implementation, the orthographic projection shape of the recess P1 on the first substrate 11 may be similar to the orthographic projection shape of the protrusion P2 on the first substrate 11. Specifically, the orthographic projection shape of the recess P1 on the first substrate 11 may be a trapezoid, as shown in FIG6E; in other embodiments, the orthographic projection shape of the recess P1 on the first substrate 11 may also be a rectangle, as shown in FIG6H; in other embodiments, the orthographic projection shape of the recess P1 on the first substrate 11 may also be a triangle, as shown in FIG6I; in other embodiments, the orthographic projection shape of the recess P1 on the first substrate 11 may also be a semicircle, as shown in FIG6J; in other embodiments, the orthographic projection shape of the recess P1 on the first substrate 11 may also be an arc, as shown in FIG6K; in other embodiments, the orthographic projection shape of the recess P1 on the first substrate 11 may also be a wave shape, as shown in FIG6L; specifically , the orthographic projection shape of the protrusion P2 on the first substrate 11 may be a trapezoid, as shown in FIG6E ; in other embodiments, the orthographic projection shape of the protrusion P2 on the first substrate 11 may also be a rectangle, as shown in FIG6H ; in other embodiments, the orthographic projection shape of the protrusion P2 on the first substrate 11 may also be a triangle, as shown in FIG6I ; in other embodiments, the orthographic projection shape of the protrusion P2 on the first substrate 11 may also be a semicircle, as shown in FIG6J ; in other embodiments, the orthographic projection shape of the protrusion P2 on the first substrate 11 may also be an arc, as shown in FIG6K ; in other embodiments, the orthographic projection shape of the protrusion P2 on the first substrate 11 may also be a wave, as shown in FIG6L .

[0143] In a possible implementation, as shown in FIG. 9A-FIG . 9B and FIG. 8A-FIG . 8G , the second source 156 may be formed as a straight edge at a side away from the second drain 157 ; and the second raised portion F2 may be formed as a straight edge at an outer boundary facing the second source 156 .

[0144] In a possible implementation, as shown in FIG. 5 to FIG. 8G , an orthographic projection of the second gate 124 on the first substrate 11 and an orthographic projection of the second raised portion F2 on the first substrate 11 have an overlapping region.

[0145] In a possible embodiment, in combination with Figures 5-8G, the orthographic projection of the second raised portion F2 on the first substrate 11 is located within the orthographic projection of the second gate 124 on the first substrate 11, and the orthographic projection of at least part of the second source 156 on the first substrate 11 is located within the orthographic projection of the second gate 124 on the first substrate 11.

[0146] In one possible embodiment, the shape of the first spacer 241 may be similar to the shape of the second spacer 242. Specifically, the shape of the first spacer 241 may be truncated cone-shaped, and the shape of the second spacer 242 may be truncated cone-shaped. Specifically, the truncated cone-shaped first spacer 241 and the second spacer 242 may both have a top surface facing the first substrate 11 and a bottom surface facing the second substrate 21, and the area of ​​the top surface is smaller than the area of ​​the bottom surface. In the embodiment of the present disclosure, the orthographic projections of the first spacer 241 and the second spacer 242 on the first substrate 11 can be understood as the orthographic projections of the top surface of the first spacer 241 and the top surface of the second spacer 242 on the first substrate 11.

[0147] In one possible embodiment, with reference to Figures 2A-2F, 4A-4F, 6A-6F, and 8A-8F, the orthographic projection shape of the first spacer 241 on the first substrate 11 may be similar to the orthographic projection shape of the second spacer 242 on the first substrate 11. Specifically, the orthographic projection shape of the first spacer 241 on the first substrate 11 may be an ellipse or a circle, and the orthographic projection shape of the second spacer 242 on the first substrate 11 may be an ellipse or a circle, as shown in Figure 2D, 4E, 6E, or 8E; in other embodiments, the orthographic projection shape of the first spacer 241 on the first substrate 11 may also be a quadrilateral, pentagon, hexagon, or octagon.

[0148] In one possible embodiment, as shown in conjunction with Figures 2A-2F, 4A-4F, 6A-6G, and 8A-8G, a maximum length d1 of the orthogonal projection of the first spacer 241 on the first substrate 11 in the second direction Y is greater than a maximum length d2 of the orthogonal projection of the second spacer 242 on the first substrate 11 in the second direction Y. A maximum length d3 of the orthogonal projection of the first spacer 241 on the first substrate 11 in the first direction X is substantially equal to a maximum length d4 of the orthogonal projection of the second spacer 242 on the first substrate 11 in the first direction X. Specifically, when the orthographic projection of the first spacer 241 on the first substrate 11 is an ellipse, the maximum length d1 of the orthographic projection of the first spacer 241 on the first substrate 11 in the second direction Y can be understood as the length of the major axis of the ellipse; when the orthographic projection of the second spacer 242 on the first substrate 11 is an ellipse, the maximum length d2 of the orthographic projection of the second spacer 242 on the first substrate 11 in the second direction Y can be understood as the length of the major axis of the ellipse; specifically, when the orthographic projection of the first spacer 241 on the first substrate 11 is an ellipse, the maximum length d3 of the orthographic projection of the first spacer 241 on the first substrate 11 in the first direction X can be understood as the length of the minor axis of the ellipse; the maximum length d4 of the orthographic projection of the second spacer 242 on the first substrate 11 in the first direction X can be understood as the length of the minor axis of the ellipse.

[0149] In a possible embodiment, in combination with Figures 2A-2F, 4A-4F, 6A-6G, 8A-8G, 11, 12A-12B, 13, and 14A-14B, Figure 11 is a schematic diagram of an arrangement of multiple first spacers, first sub-spacers, and second sub-spacers when the first thin film transistor T1 is an oxide thin film transistor, Figure 12A is an enlarged schematic diagram of the dotted line frame S1 in Figure 11, Figure 12B is an enlarged schematic diagram of the dotted line frame S2 in Figure 11, and Figure 13 is a schematic diagram of the first spacer, first sub-spacer, and second sub-spacer when the first thin film transistor T1 is a polysilicon thin film transistor. A schematic diagram of the arrangement of spacers, Figure 14A is an enlarged schematic diagram of the dotted frame S3 in Figure 13, and Figure 14B is an enlarged schematic diagram of the dotted frame S4 ​​in Figure 13, the second spacer 242 includes a first sub-spacer 2421 and a second sub-spacer 2422; the height of the first sub-spacer 2421 in the direction perpendicular to the first substrate 11 (not shown in the figure) is greater than the height of the second sub-spacer 2422 in the direction perpendicular to the first substrate 11 (not shown in the figure), and the height of the first sub-spacer 2421 in the direction perpendicular to the first substrate 11 (not shown in the figure) is greater than the height of the first spacer 241 in the direction perpendicular to the first substrate 11 (not shown in the figure).

[0150] Specifically, the orthographic projection shape of the first sub-spacer 2421 on the first substrate 11 can be elliptical, circular, quadrilateral, pentagonal, hexagonal or octagonal; the orthographic projection shape of the second sub-spacer 2422 on the first substrate 11 can be elliptical, circular, quadrilateral, pentagonal, hexagonal or octagonal.

[0151] Specifically, the first sub-spacer 2421 can be a main spacer (Main PS), and the second sub-spacer 2422 and the first spacer 241 can both be sub-spacers (Sub PS). Specifically, the display panel includes a surface film layer located on the first substrate 11, and the distance between the surface film layer and the first substrate 11 is greater than the distance between the remaining film layers located on the first substrate 11 and the first substrate 11, that is, the surface film layer can be a film layer disposed on the outermost surface of the first substrate 11. Specifically, for example, the surface film layer can be an alignment film (not shown in the figure) for aligning liquid crystals; the first spacer 241 has a first gap with the surface film layer, and the second sub-spacer 2422 has a second gap with the surface film layer; the first sub-spacer 2421 is in contact with the surface film layer, that is, the first sub-spacer 2421 can be in contact with the surface film layer disposed on the first substrate 11, and the first sub-spacer 241 and the second sub-spacer 2422 can have gaps with the surface film layer disposed on the first substrate 11.

[0152] Specifically, in combination with Figures 11 and 12A-12B, the first sub-spacer 2421 can be located in an area where the touch lead 153 is not located, so as to avoid the first spacer 241 contacting the surface film layer of the first substrate 11. The second drain electrode 157 of the second thin film transistor T2 needs to be connected to the pixel electrode (second electrode 19) through the second via hole K2. The first sub-spacer 2421 may damage the second via hole K2, thereby affecting the conduction between the second drain electrode 157 and the pixel electrode.

[0153] Specifically, as shown in Figures 11, 12A-12B, 13, and 14A-14B, the distribution density of the main spacer (first sub-spacer 2421) can be smaller than the distribution density of the auxiliary spacers (first spacer 241 and second sub-spacer 2422). Specifically, for every consecutive arrangement of multiple auxiliary spacers (first spacer 241 and second sub-spacer 2422), one main spacer (first sub-spacer 2421) can be provided. Specifically, for example, the ratio of the distribution density of the main spacer (first sub-spacer 2421) to the distribution density of the auxiliary spacers (first spacer 241 and second sub-spacer 2422) can be in the range of 1 / 84 to 10 / 84. Specifically, for example, the sum of the main spacers (first sub-spacers 2421) and the sub-spacers (first spacers 241 and second sub-spacers 2422) is 84 as a setting cycle, wherein the number of main spacers (first sub-spacers 2421) can be set to 3, and the number of sub-spacers (first spacers 241 and second sub-spacers 2422) can be set to 80. Among the 80 sub-spacers (first spacers 241 and second sub-spacers 2422), the number of first spacers 241 can be set to 28, and the number of second sub-spacers 2422 can be set to 52.

[0154] In one possible embodiment, as shown in conjunction with Figures 2A-2F, 4A-4F, 6A-6F, and 8A-8F, a maximum length d21 of the first sub-spacer 2421 in the second direction Y of the orthographic projection of the first substrate 11 is less than a maximum length d22 of the second sub-spacer 2422 in the second direction Y of the orthographic projection of the first substrate. Specifically, the maximum length d21 of the first sub-spacer 2421 in the second direction Y of the orthographic projection of the first substrate 11 can be understood as the length of the major axis of an ellipse; when the orthographic projection of the second spacer 242 on the first substrate 11 is an ellipse, the maximum length d22 of the second sub-spacer 2422 in the second direction Y of the orthographic projection of the first substrate 11 can be understood as the length of the major axis of the ellipse.

[0155] Specifically, the difference between the maximum length d1 of the orthogonal projection of the first spacer 241 on the first substrate 11 in the second direction Y and the maximum length d22 of the orthogonal projection of the second sub-spacer 2422 on the first substrate 11 in the second direction Y is in the range of 3 μm to 10 μm. Specifically, the difference between the maximum length d1 of the orthogonal projection of the first spacer 241 on the first substrate 11 in the second direction Y and the maximum length d22 of the orthogonal projection of the second sub-spacer 2422 on the first substrate 11 in the second direction Y can be 3 μm, 4.5 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm. The difference between the maximum length d22 of the orthogonal projection of the second sub-spacer 2422 on the first substrate 11 in the second direction Y and the maximum length d21 of the orthogonal projection of the first sub-spacer 2421 on the first substrate 11 in the second direction Y is in the range of 2 μm to 5 μm. The difference between the maximum length d22 of the second sub-spacer 2422 in the second direction Y of the orthographic projection of the first substrate 11 and the maximum length d21 of the first sub-spacer 2421 in the second direction Y is 2 μm, 3 μm, 4 μm or 5 μm.

[0156] Specifically, the maximum length d1 of the first spacer 241 in the second direction Y of the orthographic projection of the first substrate 11 is 18μm to 24μm, specifically, the maximum length d1 of the first spacer 241 in the second direction Y of the orthographic projection of the first substrate 11 is 18μm, 19μm, 20μm, 21μm, 22μm, 23μm or 24μm; specifically, the maximum length d22 of the second sub-spacer 2422 in the second direction Y of the orthographic projection of the first substrate 11 is 11μm to 17μm, specifically, the maximum length d22 of the second sub-spacer 2422 in the second direction Y of the orthographic projection of the first substrate 11 is 11μm, 12μm, 13μm, 14μm, 15μm, 16μm or 17μm. The maximum length d21 of the orthographic projection of the first sub-spacer 2421 in the second direction Y of the first substrate 11 is 7 μm to 14 μm, specifically 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm or 14 μm.

[0157] In one possible embodiment, the maximum length d3 of the orthographic projection of the first spacer 241 on the first substrate 11 in the first direction X is 8 μm to 14 μm, the maximum length d4 of the orthographic projection of the second sub-spacer 2422 on the first substrate 11 in the first direction X is 8 μm to 14 μm, and the maximum length d4 of the orthographic projection of the first sub-spacer 2421 on the first substrate 11 in the first direction X is 8 μm to 14 μm. Specifically, the maximum length d3 of the orthographic projection of the first spacer 241 on the first substrate 11 in the first direction X is 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, or 14 μm. Specifically, the maximum length d4 of the orthographic projection of the second sub-spacer 2422 on the first substrate 11 in the first direction X is 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, or 14 μm. Specifically, the maximum length d4 of the orthographic projection of the first sub-spacer 2421 in the first direction X of the first substrate 11 is 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm or 14 μm.

[0158] In one possible embodiment, the orthographic projection shape of the first sub-spacer 2421 on the first substrate 11 may be circular. Specifically, the maximum length d21 of the orthographic projection of the first sub-spacer 2421 on the first substrate 11 in the second direction Y may be 11 μm, and the maximum length d4 of the orthographic projection of the first sub-spacer 2421 on the first substrate 11 in the first direction X may be 11 μm. In another possible embodiment, the orthographic projection shape of the first sub-spacer 2421 on the first substrate 11 may be elliptical. As shown in Figures 6F, 7A and 8F, the maximum length d21 of the orthographic projection of the first sub-spacer 2421 on the first substrate 11 in the second direction Y may be 11 μm, and the maximum length d4 of the orthographic projection of the first sub-spacer 2421 on the first substrate 11 in the first direction X may be 10 μm.

[0159] Specifically, in a possible embodiment, in combination with Figures 6A and 6F, for a structure in which the first thin film transistor T1 is an oxide thin film transistor, the maximum length d3 of the first spacer 241 in the first direction X of the orthographic projection of the first substrate 11 may be 12 μm, and the maximum length d1 of the first spacer 241 in the second direction Y of the orthographic projection of the first substrate 11 may be 18.5 μm; the maximum length d4 of the second sub-spacer 2422 in the first direction X of the orthographic projection of the first substrate 11 may be 11 μm, and the maximum length d22 of the second sub-spacer 2422 in the second direction Y of the orthographic projection of the first substrate 11 may be 14 μm.

[0160] Specifically, in a possible embodiment, in combination with what is shown in FIG7A , for a structure in which the first thin film transistor T1 is a polycrystalline silicon thin film transistor, a maximum length d3 of the orthographic projection of the first spacer 241 on the first substrate 11 in the first direction X may be 11 μm, and a maximum length d1 of the orthographic projection of the first spacer 241 on the first substrate 11 in the second direction Y may be 21 μm; a maximum length d4 of the orthographic projection of the second sub-spacer 2422 on the first substrate 11 in the first direction X may be 11 μm, and a maximum length d22 of the orthographic projection of the second sub-spacer 2422 on the first substrate 11 in the second direction Y may be 14 μm.

[0161] In a possible embodiment, in combination with Figures 8A and 8F, for a structure in which the first thin film transistor T1 is a polycrystalline silicon thin film transistor and a second raised portion F2 is provided, the maximum length d3 of the orthographic projection of the first spacer 241 on the first substrate 11 in the first direction X may be 11 μm, and the maximum length d1 of the orthographic projection of the first spacer 241 on the first substrate 11 in the second direction Y may be 21 μm; the maximum length d4 of the orthographic projection of the second sub-spacer 2422 on the first substrate 11 in the first direction X may be 11 μm, and the maximum length d22 of the orthographic projection of the second sub-spacer 2422 on the first substrate 11 in the second direction Y may be 18 μm.

[0162] In a possible embodiment, as shown in Figures 2A-2F, 4A-4F, 6A-6G, and 8A-8G, the orthographic projection of the first sub-spacer 2421 on the first substrate 11 does not overlap with the orthographic projection of the second drain 157 on the first substrate 11.

[0163] In a possible embodiment, as shown in Figures 2A-2F, 4A-4F, 6A-6G, and 8A-8G, the second gate 124 is made of the same layer and material as the first gate 121, the second active layer 144 is made of the same layer and material as the first active layer 141, and the second source and drain are made of the same layer and material as the first source and drain.

[0164] In one possible embodiment, as shown in Figure 10 , the common electrode layer is reused as a touch electrode layer, comprising multiple, insulated touch electrode blocks 170. The touch leads 153 are electrically connected to the touch electrode blocks 170 one by one through vias. It should be noted that Figure 10 is merely a schematic illustration of a touch electrode layer comprising five rows and six columns of touch electrode blocks 170. In a specific implementation, the touch electrode layer may also comprise multiple rows and columns of touch electrode blocks 170, and the disclosed embodiments are not limited thereto.

[0165] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0166] In the embodiment of the present disclosure, the orthographic projection of the first spacer 241 on the first substrate 11 has an overlapping area with the orthographic projection of the first thin film transistor T1 on the first substrate 11, and has an overlapping area with the orthographic projection of the first signal line L on the first substrate 11. When the display panel is pressed, the area where the first signal line L is located can also support the first spacer 241, thereby improving the pressure resistance of the display panel without sacrificing the aperture ratio.

[0167] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0168] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A display panel, wherein: include: a first substrate, a plurality of first thin film transistors located on one side of the first substrate, and a first signal line located on one side of the first thin film transistor and insulated from the first thin film transistor; a second substrate, and a plurality of first spacers located on a side of the second substrate facing the first substrate; The orthographic projection of the first spacer on the first substrate has an overlapping area with the orthographic projection of the first thin film transistor on the first substrate, and has an overlapping area with the orthographic projection of the first signal line on the first substrate.

2. The display panel according to claim 1, wherein: The display panel further includes: data lines and touch leads located on the first substrate and extending along a first direction and insulated from each other, and gate lines extending along a second direction, wherein the first direction intersects the second direction; The first signal line is the touch lead.

3. The display panel according to claim 2, wherein: The first thin film transistor includes a first gate electrode, a first active layer, and a first source and drain electrode that are stacked; the first source and drain electrode includes a first source electrode integrally connected to the data line, and a first drain electrode separated from the first source electrode; An orthographic projection of a portion of the outer boundary of the first signal line away from the first drain electrode on the first substrate is located within an orthographic projection of the first spacer on the first substrate.

4. The display panel according to claim 2 or 3, wherein: The display panel further includes at least one first raised portion located on the first substrate; An orthographic projection of the first raised portion on the first substrate overlaps with an orthographic projection of the first signal line on the first substrate, and overlaps with an orthographic projection of the first spacer on the first substrate.

5. The display panel according to claim 4, wherein: The first raised portion is a single film layer, or a composite structure including multiple film layers.

6. The display panel according to claim 5, wherein: The first padding portion is located in a region where the gate line overlaps with the first signal line.

7. The display panel according to claim 6, wherein: The first raised portion and the first active layer are formed in the same layer and made of the same material.

8. The display panel according to claim 5, wherein: The first gate protrudes from the gate line toward a side close to the first drain; The first padding portion and the first gate are located on the same side of the gate line, and an orthographic projection of the first padding portion on the first substrate has a gap with the gate line.

9. The display panel according to claim 5, wherein: The first gate protrudes from both sides of the gate line along the first direction X; The first raised portions are distributed on both sides of the gate line, and the orthographic projections of the first raised portions on different sides on the first substrate have gaps with the gate line.

10. The display panel according to claim 8 or 9, wherein: The first padding portion includes a first floating metal and a first floating pattern located on a side of the first floating metal facing away from the first substrate; The first floating metal and the first gate are formed in the same layer and material, and the first floating pattern and the first active layer are formed in the same layer and material.

11. The display panel according to claim 10, wherein: An orthographic projection area of ​​the first floating metal on the first substrate is larger than an orthographic projection area of ​​the first floating pattern on the first substrate, and the orthographic projection of the first floating metal on the first substrate covers the orthographic projection of the first floating pattern on the first substrate.

12. The display panel according to any one of claims 3 to 11, wherein: The display panel further includes a plurality of second thin film transistors located on the first substrate, and a second padding portion on one side of the second thin film transistors; The display panel also includes a plurality of second spacers located on the side of the second substrate facing the first substrate, and the orthographic projection of the second spacers on the first substrate has an overlapping area with the orthographic projection of the second thin film transistor on the first substrate, and has an overlapping area with the orthographic projection of the second raised portion on the first substrate.

13. The display panel according to claim 12, wherein: The second thin film transistor includes a second gate electrode, a second active layer, and a second source and drain electrode that are stacked; the second source and drain electrode includes a second source electrode integrally connected to the data line, and a second drain electrode separated from the first source electrode; The second padding portion and the second drain electrode are located on different sides of the data line.

14. The display panel according to claim 13, wherein: The orthographic projection of the second raised portion on the first substrate is located within the orthographic projection of the second gate on the first substrate.

15. The display panel according to claim 13 or 14, wherein: The second padding portion includes a second floating metal, and the second floating metal and the second source and drain are made of the same layer and material.

16. The display panel according to claim 15, wherein: The second raised portion further includes a second floating pattern, and the second floating pattern and the second active layer are in the same layer and made of the same material.

17. The display panel according to any one of claims 12 to 16, wherein: The second source electrode has a straight side at a side away from the second drain electrode; and the second raised portion has a straight side at an outer boundary facing the second source electrode.

18. The display panel according to any one of claims 12 to 16, wherein: The second source electrode has a recess on a side away from the second drain electrode; and the second raised portion has a protrusion on an outer boundary facing the second source electrode.

19. The display panel according to any one of claims 12 to 18, wherein: An orthographic projection of the second gate on the first substrate and an orthographic projection of the second raised portion on the first substrate have an overlapping area.

20. The display panel according to any one of claims 12 to 19, wherein: The orthographic projection of the second raised portion on the first substrate is located within the orthographic projection of the second gate on the first substrate; At least a portion of the orthographic projection of the second source on the first substrate is located within the orthographic projection of the second gate on the first substrate.

21. The display panel according to any one of claims 12 to 20, wherein: The maximum length of the orthographic projection of the first spacer on the first substrate in the second direction is greater than the maximum length of the orthographic projection of the second spacer on the first substrate in the second direction; The maximum length of the orthographic projection of the first spacer on the first substrate in the first direction is substantially equal to the maximum length of the orthographic projection of the second spacer on the first substrate in the second direction.

22. The display panel according to any one of claims 13 to 21, wherein: The second spacer includes a first sub-spacer and a second sub-spacer; The height of the first sub-spacer in a direction perpendicular to the first substrate is greater than the height of the second sub-spacer in the direction perpendicular to the first substrate, and the height of the first sub-spacer in a direction perpendicular to the first substrate is greater than the height of the first spacer in the direction perpendicular to the first substrate.

23. The display panel according to claim 22, wherein: The display panel includes a surface film layer located on the first substrate, wherein the distance between the surface film layer and the first substrate is greater than the distance between the remaining film layers located on the first substrate and the first substrate; There is a first gap between the first spacer and the surface film layer, and there is a second gap between the second sub-spacer and the surface film layer; the first sub-spacer is in contact with the surface film layer.

24. The display panel according to claim 22 or 23, wherein: A length of an orthographic projection of the first sub-spacer on the first substrate in the second direction is smaller than a length of an orthographic projection of the second sub-spacer on the first substrate in the second direction.

25. The display panel according to any one of claims 22 to 24, wherein: An orthographic projection of the first sub-spacer on the first substrate does not overlap with an orthographic projection of the second drain on the first substrate.

26. The display panel according to any one of claims 13 to 25, wherein: The second gate is formed of the same layer and material as the first gate, the second active layer is formed of the same layer and material as the first active layer, and the second source and drain are formed of the same layer and material as the first source and drain.

27. The display panel according to claim 26, wherein: The display panel further includes a pixel electrode located on the first substrate, wherein the pixel electrode is located between the first gate and the first active layer; The first drain electrode is in contact with and electrically connected to the pixel electrode, and the second drain electrode is in contact with and electrically connected to the pixel electrode.

28. The display panel according to claim 26, wherein: The display panel further includes a pixel electrode located on the first substrate, wherein the pixel electrode is located on a side of the first source and drain electrodes away from the first active layer; The first drain electrode is electrically connected to the pixel electrode through a first via hole, and the second drain electrode is electrically connected to the pixel electrode through a second via hole.

29. The display panel according to claim 27 or 28, wherein: The display panel further includes a common electrode layer located on the first substrate, wherein the common electrode layer is reused as a touch electrode layer and has a plurality of touch electrode blocks insulated from each other; The touch leads are electrically connected to the touch electrode blocks one by one through via holes.

30. A display device, wherein: Comprising the display panel according to any one of claims 1-29.

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