Display panel, display device and manufacturing method of display panel

Abstract

The invention discloses a display panel, a display device and a manufacturing method of the display panel. The display panel comprises an array substrate (1) and an opposite substrate (2) which are oppositely arranged, the frame sealing glue (3) is located between the array substrate (1) and the opposite substrate (2) and located in the non-display area (BB); the conductive part (4) comprises a first conductive part (41) and a second conductive part (42); the first conductive part (41) is located between the array substrate (1) and the opposite substrate (2) and located in the binding area (DP), a part of the first conductive part (41) is overlapped with the frame sealing glue (3), and a part of the first conductive part (41) extends out of the frame sealing glue (3) and faces the area of one side of the display area (AA); the second conductive part (42) is located between the array substrate (1) and the opposite substrate (2) and located in the binding opposite side area (DPO), a part of the second conductive part (42) is overlapped with the frame sealing glue (3), and a part of the second conductive part (42) extends to the area outside the frame sealing glue (3) and away from one side of the display area (AA); the conductive part (4) is configured to conduct electric signals of the array substrate (1) and the opposite substrate (2).

Description

Display panel, display device and manufacturing method of display panel TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a display panel, a display device and a manufacturing method of the display panel. BACKGROUND

[0002] The principle of vertical alignment (VA) display technology is that the electrodes of an array substrate and the electrodes of a counter substrate are powered to form an up-down voltage field to drive the rotation of liquid crystals in a liquid crystal cell. Different rotation angles of the liquid crystals result in different light passing intensities, so as to control the display of the panel. The frame sealant plays a role of encapsulation in the liquid crystal cell and seals the array substrate and the counter substrate. Meanwhile, the frame sealant also plays a role of conducting the upper and lower electrodes through conductive particles (for example, gold balls) in the frame sealant.

[0003] SUMMARY

[0004] The present disclosure provides a display panel, a display device and a manufacturing method of the display panel. The display panel has a display area and a non-display area located at the periphery of the display area. The non-display area includes a binding area located at one side of the display area and a binding opposite area located at the other side of the display area and opposite to the binding area. The display panel includes:

[0005] an array substrate and a counter substrate arranged oppositely;

[0006] a frame sealant located between the array substrate and the counter substrate and in the non-display area;

[0007] a conductive part including a first conductive part and a second conductive part. The first conductive part is located between the array substrate and the counter substrate and in the binding area. The first conductive part partially overlaps the frame sealant and partially extends out of the frame sealant and towards an area at one side of the display area. The second conductive part is located between the array substrate and the counter substrate and in the binding opposite area. The second conductive part partially overlaps the frame sealant and partially extends out of the frame sealant and away from an area at one side of the display area. The conductive part is configured to conduct electrical signals of the array substrate and the counter substrate.

[0008] In a possible implementation, the frame sealant includes a first frame sealant edge and a second frame sealant edge. The minimum distance between the first frame sealant edge and the display area is smaller than the minimum distance between the second frame sealant edge and the display area.

[0009] The first conductive part overlaps the first frame sealant edge, and the second conductive part overlaps the second frame sealant edge.

[0010] In a possible implementation, the display panel comprises: a first panel outer edge and a second panel outer edge; the first panel outer edge is located on the same side of the display area as the binding area, and the second panel outer edge is located on the same side of the display area as the binding opposite area.

[0011] The minimum distance between the sealing frame and the first outer edge is smaller than the minimum distance between the sealing frame and the second outer edge.

[0012] In a possible implementation, the display panel further comprises: a first barrier portion and a second barrier portion.

[0013] The first barrier portion is located between the first conductive portion and the display area, and the second barrier portion is located between the second conductive portion and the second panel outer edge.

[0014] In a possible implementation, the first barrier portion comprises: a first sub-barrier portion and a second sub-barrier portion; the first sub-barrier portion has the same extension direction as the outer edge of the first conductive portion on the side facing the display area; and the second sub-barrier portion is connected to the end of the first sub-barrier portion and is bent towards the side of the first conductive portion.

[0015] The second barrier portion comprises: a third sub-barrier portion and a fourth sub-barrier portion; the third sub-barrier portion has the same extension direction as the outer edge of the second conductive portion on the side facing the display area; and the fourth sub-barrier portion is connected to the end of the third sub-barrier portion and is bent towards the side of the second conductive portion.

[0016] In a possible implementation, the display panel comprises a plurality of first conductive portions and / or a plurality of second conductive portions.

[0017] The plurality of first conductive portions are located in the binding area and arranged in sequence along the extension direction of the binding area; and the plurality of second conductive portions are located in the binding opposite area and arranged in sequence along the extension direction of the binding opposite area.

[0018] In a possible implementation, the first conductive portion is in a strip shape and extends along the extension direction of the binding area; and the second conductive portion is in a strip shape and extends along the extension direction of the binding opposite area.

[0019] In a possible implementation, the array substrate comprises: a first substrate and a plurality of first common patterns.

[0020] The orthogonal projection of the first common electrode pattern on the first substrate at least partially overlaps the orthogonal projection of the conductive portion on the first substrate.

[0021] In a possible implementation, the outer contour of the first common pattern is a pentagon, a hexagon or an octagon.

[0022] In a possible implementation, the first common pattern comprises a peripheral trace portion, a plurality of first trace portions inside the peripheral trace portion and a plurality of second trace portions; the first trace portions and the second trace portions intersect to form a plurality of first opening regions.

[0023] At least two of the first opening regions have different areas.

[0024] In a possible implementation, at least one of the peripheral trace portion, the first trace portions and the second trace portions has a plurality of second opening regions; the second opening regions have areas smaller than those of the first opening regions.

[0025] In a possible implementation, the array substrate comprises a via electrode on the side of the first common pattern facing the counter substrate, and a first insulating layer between the via electrode and the first common pattern; the via electrode is electrically connected to the conductive portion.

[0026] The first insulating layer has a first via hole, and the first common pattern is electrically connected to the via electrode through the first via hole.

[0027] In a possible implementation, the first common pattern corresponds to the first via hole, and the area of the first via hole is 50% to 90% of the area of the first common pattern.

[0028] In a possible implementation, the first via hole comprises a plurality of first sub-via holes; the plurality of first sub-via holes of the same first via hole are all located within the projection of the first common pattern on the first substrate.

[0029] In a possible implementation, the first via hole comprises a second sub-via hole and a plurality of third sub-via holes; the third sub-via holes have sizes smaller than that of the second sub-via hole; part of the first common pattern overlaps the sealant, and part of the first common pattern does not overlap the sealant.

[0030] The second sub-via hole is located in the region where the first common pattern overlaps the sealant in the projection of the first substrate; the third sub-via hole is located in the region of the first common pattern other than the region where the first common pattern overlaps the sealant in the projection of the first substrate.

[0031] In a possible implementation, the array substrate includes a first common electrode trace; the opposite substrate includes a second common electrode trace; the first common electrode trace and the second common electrode trace are electrically connected through the conductive part.

[0032] The first common electrode trace includes the first common pattern.

[0033] In a possible implementation, the first common pattern does not overlap with the first common electrode trace in the orthographic projection of the first substrate; and the first via overlaps with the first common electrode trace in the orthographic projection of the first substrate.

[0034] The first common pattern is electrically connected with the first common electrode trace through the first via and the transfer electrode.

[0035] In a possible implementation, the display panel further includes a first non-display area located at the periphery of the display area and connecting the binding area and the opposite binding area.

[0036] Of the binding area, the opposite binding area and the first non-display area, only the binding area and the opposite binding area are provided with the conductive part.

[0037] In a possible implementation, the first non-display area includes a gate drive unit and a gate drive signal trace located on a side of the gate drive unit away from the display area.

[0038] In the first non-display area, the sealant overlaps with at least part of the gate drive signal trace.

[0039] The display device provided by the embodiments of the present disclosure includes the display panel provided by the embodiments of the present disclosure.

[0040] The display panel provided by the embodiments of the present disclosure includes the manufacturing method of the display panel provided by the embodiments of the present disclosure.

[0041] The sealant is coated on the periphery of the display area of the opposite substrate and / or the array substrate.

[0042] The first conductive part is formed in the binding area, and part of the first conductive part overlaps with the sealant, and part of the first conductive part extends out of the sealant and towards the area on the side of the display area.

[0043] The second conductive part is formed in the opposite binding area, and part of the second conductive part overlaps with the sealant, and part of the second conductive part extends out of the sealant and away from the area on the side of the display area.

[0044] The array substrate and the counter substrate are pressed together to adhere the array substrate and the counter substrate. BRIEF DESCRIPTION OF DRAWINGS

[0045] FIG. 1A is a top view of a display panel according to an embodiment of the present disclosure;

[0046] FIG. 1B is a partial enlarged view of the binding area DP in FIG. 1A;

[0047] FIG. 1C is a partial enlarged view of the binding opposite area DPO in FIG. 1A;

[0048] FIG. 1D is another partial enlarged view of the binding area DP in FIG. 1A;

[0049] FIG. 1E is another partial enlarged view of the binding opposite area DPO in FIG. 1A;

[0050] FIG. 2 is a top view of a display panel according to another embodiment of the present disclosure;

[0051] FIG. 3 is a top view of a display panel according to another embodiment of the present disclosure;

[0052] FIG. 4 is a schematic view of a first common pattern according to an embodiment of the present disclosure;

[0053] FIG. 5 is a schematic view of a first common pattern according to another embodiment of the present disclosure;

[0054] FIG. 6 is a schematic view of a first common pattern according to another embodiment of the present disclosure;

[0055] FIG. 7A is a cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0056] FIG. 7B is a top view corresponding to FIG. 7A;

[0057] FIG. 8A is a cross-sectional view of a display panel according to another embodiment of the present disclosure;

[0058] FIG. 8B is a top view corresponding to FIG. 8A;

[0059] FIG. 9A is a cross-sectional view of a display panel according to another embodiment of the present disclosure;

[0060] FIG. 9B is a top view corresponding to FIG. 9A;

[0061] FIG. 10 is a schematic view of a first common electrode wire according to an embodiment of the present disclosure;

[0062] FIG. 11 is a schematic view of another first via and first common pattern according to an embodiment of the present disclosure;

[0063] FIG. 12 is a partial schematic view of the first non-display area BB1;

[0064] FIG. 13 is a schematic view of a manufacturing process of a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort are within the scope of the present disclosure. The embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand that the manners and contents can be converted into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents of the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0066] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second”, and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms “include” or “contain” and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms “connect” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0067] As used herein, “about” or “approximately” includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art to be considered equivalent in light of the margin of error in measuring the particular quantity (i.e., limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ± 30%, 20%, 10%, 5% of the stated value. In the present specification, “about” can mean within 10% of the numerical value.

[0068] In the drawings, the thicknesses of layers, films, panels, regions, etc., can be exaggerated for clarity. Descriptive terminology such as "above," "below," "left," "right," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, relating to the illustrations as shown in the figures is intended to be used herein for descriptive purposes only, and is not intended to convey or be construed as indicating or implying that the present disclosure is necessarily limited to the particular orientation or spatial arrangement shown in the figures. The orientation of constituent elements in the figures described herein are merely provided for the purposes of illustration and not limitation as described herein. Constituent elements can be positioned in any orientation or manner consistent with that described herein, without constituting a departure from the scope of the present disclosure.

[0069] In this specification, terms of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or locational relationship are used to describe the positional relationship of constituent elements with reference to the drawings only for the convenience of describing this specification and simplifying the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting on the present disclosure. The positional relationship of constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, the terms described in the specification are not limited, and can be appropriately replaced according to the situation.

[0070] In this specification, unless explicitly stated and limited otherwise, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or communication inside two elements. The above terms in the present disclosure can be understood according to the situation by those skilled in the art.

[0071] In this specification, "electrically connected" includes the case where constituent elements are connected together through an element having some kind of electrical effect. The "element having some kind of electrical effect" is not particularly limited as long as it can perform transmission of electrical signals between the connected constituent elements. Examples of the "element having some kind of electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.

[0072] In this specification, "parallel" means a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus can include a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" means a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus can include a state in which the angle is 85° or more and 95° or less.

[0073] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly speaking, and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon, etc. There can be some small deformation due to tolerance, there can be a lead angle, an arc edge, and deformation, etc.

[0074] In the present specification, "film" and "layer" can be exchanged with each other. For example, "conductive layer" can be changed to "conductive film" sometimes. Similarly, "insulating film" can be changed to "insulating layer" sometimes.

[0075] In order to keep the following description of the embodiments of the present disclosure clear and brief, the present disclosure omits the detailed description of known functions and known components.

[0076] At present, the VA display product usually sets the conductive particles (for example, gold balls) of the array substrate and the opposite substrate on one side of the display area or the display panel edge, for example, in the non-display area outside the entire display panel display area, the conductive particles are all set on one side of the display panel edge, this kind of setting mode will cause the side where the binding area is located in the non-display area, due to the small distance between the sealing frame glue and the outer edge of the display panel, when the array substrate and the opposite substrate are pressed together, the sealing frame glue overflows to the area outside the edge of the display panel, which is not conducive to the smooth cutting in the display panel cutting process, and is not conducive to the subsequent assembly of the display panel with other structures. In addition, in order to prevent the risk of electrical connection between the conductive particles and the signal lines in the non-display area of the display panel, the sealing frame glue is set away from the signal lines in the non-display area, resulting in a large frame of the display panel.

[0077] Referring to FIGS. 1A-1C and 7A, the display panel provided by the embodiments of the present disclosure has a display area AA and a non-display area BB located outside the display area AA; the non-display area BB includes a binding area DP located on one side of the display area AA, and a binding opposite area DPO located on the other side of the display area AA and opposite to the binding area DP, the binding area DP includes a plurality of binding pads which can be used for binding electrical connection with a circuit board, wherein the display panel includes:

[0078] The array substrate 1 and the opposite substrate 2 are oppositely arranged;

[0079] The sealing frame glue 3 is located between the array substrate 1 and the opposite substrate 2, and is located in the non-display area BB;

[0080] The conductive part 4 comprises: a first conductive part 41 and a second conductive part 42; the first conductive part 41 is located between the array substrate 1 and the opposite substrate 2, and is located in the binding area DP, the first conductive part 41 partially overlaps the sealant 3, and partially extends to the area outside the sealant 3 and towards the side of the display area AA; the second conductive part 42 is located between the array substrate 1 and the opposite substrate 2, and is located in the opposite binding area DPO, the second conductive part 42 partially overlaps the sealant 3, and partially extends to the area outside the sealant 3 and away from the side of the display area AA; the conductive part 4 is configured to conduct electrical signals of the array substrate 1 and the opposite substrate 2.

[0081] In the non-display area BB outside the display area AA of the display panel, on one hand, the width of the binding area DP in the direction perpendicular to the extension direction of the binding area DP is greater than the width of the remaining non-display area BB (for example, the width c1 of the binding area DP in the direction perpendicular to the extension direction of the binding area DP is greater than the width c2 of the opposite area DPO of the binding area DP, and the first non-display area BB1 where the gate drive circuit GOA is arranged); on the other hand, the sealing frame glue 3 on the side of the binding area DP is generally required to be closer to the outer edge of the display panel. Optionally, the edge of the display panel refers to the edge of the color film substrate in the display panel. For example, as shown in FIGS. 1B and 1C, the distance b1 between the sealing frame glue 3 of the binding area DP and the outer edge of the display panel is less than the distance b2 between the sealing frame glue 3 of the opposite area DPO of the binding area DP and the outer edge of the display panel, so that the sealing frame glue 3 and the outer edge of the display panel have a smaller spacing. When the spacing between the sealing frame glue 3 and the outer edge of the display panel is large, a large gap exists, water vapor is easily accumulated, and the subsequent binding of the terminal of the binding area DP and the control chip IC is not conducive. Therefore, in the embodiment of the present disclosure, for the binding area DP, as shown in FIG. 1B, part of the first conductive part 41 overlaps the sealing frame glue 3, and part of the first conductive part 41 extends outside the sealing frame glue 3 and towards the side of the display area AA. That is, the first conductive part 41 can be arranged on the side close to the display area AA. On one hand, since the width of the binding area DP is large, even if the first conductive part 41 is arranged on the side close to the display area AA, the normal display of the display area AA will not be affected. On the other hand, since the spacing between the sealing frame glue 3 and the outer edge of the display panel is small, if part of the first conductive part 41 is arranged in the sealing frame glue 3 and part of the first conductive part 41 extends outside the sealing frame glue 3 and towards the side of the outer edge of the display panel, the first conductive part 41 is easily overflowed to the outer edge of the display panel or the area outside the display panel when the array substrate and the opposite substrate are pressed together, which is not conducive to the segmentation of the display panel (that is, if the first conductive part 41 overflows, the display panel is not easy to separate from the mother board when the mother board including a plurality of display panels is cut to form a plurality of display panels), and the overflow of the first conductive part 41 is also not conducive to the subsequent assembly of the display panel and other structures. As shown in FIG. 1C, part of the second conductive part 42 overlaps the sealing frame glue 3, and part of the second conductive part 42 extends outside the sealing frame glue 3 and away from the side of the display area AA. That is, the second conductive part 42 can be arranged on the side away from the display area AA (that is, close to the outer edge of the display panel). On one hand, since the spacing b2 between the sealing frame glue 3 of the opposite area DPO of the binding area DP and the outer edge of the display panel is large (for example, the spacing b2 between the sealing frame glue 3 of the opposite area DPO of the binding area DP and the outer edge of the display panel is 0.4mm-0.8mm, and optionally 0.55mm, while the spacing b1 between the sealing frame glue 3 of the binding area DP and the outer edge of the display panel is 0.08-0.3mm, and optionally 0.15mm, for example, b2 is greater than b1 by 0.4mm), thus, if the second conductive part 41 is arranged on the side away from the display area AA (i.e. on the side close to the outer edge of the display panel), the second conductive part 42 will not overflow to the area outside the outer edge of the display panel, and there will be no problem of difficulty in dividing the display panel and difficulty in assembling with other structures; on the other hand, since the width of the binding opposite side area DPO along the extension direction thereof is narrow, if the second conductive part 42 is arranged on the side close to the display area AA, the second conductive part 42 is easy to overflow to the display area when the array substrate and the opposite substrate are pressed together, which affects the normal display of the display panel.

[0082] In the embodiments of the present disclosure, the first conductive part 41 and / or the second conductive part 42 are partially located in the sealant 3 and partially extend to the area outside the sealant 3, which can reduce the overlapping area of the first conductive part 41 and / or the second conductive part 42 and the sealant 3, and improve the problem that the film layer at the area where the first conductive part 41 and / or the second conductive part 42 are located is thicker than other positions, which causes the cell spacing to be different, resulting in whitening at the area where the first conductive part 41 and / or the second conductive part 42 are located, and affecting the normal display of the display panel.

[0083] In specific implementation, the first conductive part 41 and the second conductive part 42 can be formed by the following steps: first, forming the first adhesive (which can form the sealant after being pressed and cured) on the opposite substrate, then forming the second adhesive (which can form the first conductive part 41 and the second conductive part 42 after being pressed and cured) containing conductive particles (for example, gold balls), and then pressing the array substrate and the opposite substrate, and curing the first adhesive and the second adhesive, thereby forming the sealant 3, the first conductive part 41 and the second conductive part 42. The flowability of the second adhesive can be better than that of the first adhesive, so that the second adhesive is easy to flow and flatten during pressing, which is beneficial to the uniformity of the thickness of the adhesive at the positions of the conductive part 4 and the non-conductive part 4. Optionally, the first adhesive can be an adhesive without conductive particles. Optionally, the material of the first adhesive can be the same as or different from that of the second adhesive, which is not limited herein.

[0084] In a possible implementation, referring to FIG. 7A, the first conductive part 41 can include: the frame glue 401 and the conductive particles 402 mixed in the frame glue 401; and the second conductive part 42 can include: the frame glue 401 and the conductive particles 402 mixed in the frame glue 401; wherein the conductive particles 402 can include gold balls; the frame glue materials of the first conductive part 41 and the second conductive part 42 can be the same. Referring to FIG. 1B, after the first conductive part 41 is arranged in the frame glue 3, the frame glue 3 located on the side of the first conductive part 41 away from the display area AA can be free of the conductive particles, the width d1 of the area free of the conductive particles can account for 20% to 60% of the width d2 of the frame glue 3, for example, the width d1 of the area free of the conductive particles can account for 40% of the width d2 of the frame glue 3; referring to FIG. 1C, after the second conductive part 42 is arranged in the frame glue 3, the frame glue 3 located on the side of the first conductive part 41 close to the display area AA can be free of the conductive particles, the width d3 of the area free of the conductive particles can account for 20% to 60% of the width d4 of the frame glue 3, for example, the width d3 of the area free of the conductive particles can account for 40% of the width d4 of the frame glue 3.

[0085] In a possible implementation, referring to FIG. 1B and FIG. 1C, the frame glue 3 includes: a first frame glue edge 31 and a second frame glue edge 32; the minimum distance a1 between the first frame glue edge 31 and the display area AA is smaller than the minimum distance a2 between the second frame glue edge 32 and the display area AA; that is, the first frame glue edge 31 can be an inner edge of the frame glue 3, and the second frame glue edge 32 can be an outer edge of the frame glue 3; the first conductive part 41 overlaps the first frame glue edge 31, and the second conductive part 42 overlaps the second frame glue edge 32.

[0086] In a possible implementation, the minimum distance a1 between the first frame glue edge 31 and the display area AA can be the distance between the first frame glue edge 31 and the edge of the display sub-pixel opening area closest to the first frame glue edge 31; and the minimum distance a2 between the second frame glue edge 32 and the display area AA can be the distance between the second frame glue edge 32 and the edge of the display sub-pixel opening area closest to the second frame glue edge 32.

[0087] In a possible implementation, referring to FIG. 1B and FIG. 1C, the central region of the first conductive part 41 is located in the frame glue 3; and the central region of the second conductive part 42 is located in the frame glue 3; that is, most of the first conductive part 41 and / or the second conductive part 42 are located in the region where the frame glue 3 is located; optionally, 60% to 90% of the first conductive part 41 and / or the second conductive part 42 are located in the region where the frame glue 3 is located.

[0088] In a possible implementation, referring to FIGS. 1B and 1C, the display panel includes a first panel outer edge w1 and a second panel outer edge w2. The first panel outer edge w1 is located on the same side of the display area AA as the binding area DP, and the second panel outer edge w2 is located on the same side of the display area AA as the opposite binding area DPO. In other words, referring to FIG. 1A, the first panel outer edge w1 can be a lower edge of the display panel, and the second panel outer edge w2 can be an upper edge of the display panel. The minimum distance b1 between the first outer edge w1 and the sealant 3 is less than the minimum distance b2 between the second outer edge w2 and the sealant 3. In this way, the sealant 3 of the binding area DP has a smaller distance from the first panel outer edge w1, so as to avoid a larger gap between the two, which is easy to accumulate water vapor and is not conducive to subsequent binding of the terminal of the binding area DP and the control chip IC.

[0089] In a possible implementation, referring to FIGS. 1B and 1C, the display panel further includes a first blocking part 51 and / or a second blocking part 52. The first blocking part 51 is located between the first conductive part 41 and the display area AA. The second blocking part 52 is located between the second conductive part 42 and the second panel outer edge w2.

[0090] In the embodiments of the present disclosure, the positional relationship design factors of the first conductive part 41 and / or the second conductive part 42 and the sealant 3 include: when the first conductive part 41 and / or the second conductive part 42 overlap with the sealant 3, the sealant height at the position is higher than the sealant position without the first conductive part 41 and / or the second conductive part 42, for example, if the first conductive part 41 and / or the second conductive part 42 is too close to the display area AA, the in-plane box gap (Gap) is high, which causes Mura; for example, if the first conductive part 41 and / or the second conductive part 42 is too close to the outer edge of the display panel, the sealant 3 is coated on the cutting line of the display panel, which causes abnormal segmentation; in the embodiments of the present disclosure, the first conductive part 41 is arranged at a position close to the display area AA of the sealant 3 on the side of the binding area DP, and the distance between the sealant 3 and the outer edge of the display panel is about 0.15 mm, the size of the first conductive part 41 is about 1 mm, and the dotting accuracy of the first conductive part 41 and / or the second conductive part 42 and the coating accuracy of the sealant 3 are considered; if the first conductive part 41 is arranged close to the outer edge of the display panel, the first conductive part 41 must completely overlap with the sealant 3, which will inevitably cause the sealant at the dotting position to be thick, which will cause the Gap to be abnormally high, causing Mura or the sealant height to be uneven, which will cause the sealant to peel off; at the same time, in order to place the alignment liquid to cover the first conductive part 41, a first blocking part 51 is arranged at the edge of the first conductive part 41, which not only effectively prevents the alignment liquid from covering the first conductive part 41 from causing the array substrate and the opposite substrate to be conductive, but also prevents the first conductive part 41 from flowing to the display area AA to form display abnormalities. On the opposite side of the binding area DP, the second conductive part 42 is arranged at a position close to the outer edge of the display panel, and the distance between the sealant 3 and the outer edge of the display panel is about 0.55 mm, which is greater than the distance between the sealant 3 and the outer edge of the display panel in the binding area DP, that is, 0.4 mm. On the opposite side of the binding area DP, the second conductive part 42 is arranged outside the sealant 3, away from the AA area, which effectively reduces the risk of Mura caused by high Gap, and a second blocking part 52 is arranged outside the dotting position of the second conductive part 42, which is used to prevent the sealant outside the dotting position of the second conductive part 42 from overflowing onto the cutting line.

[0091] In a possible implementation, as shown in FIGS. 1B and 1C, the first blocking part 51 includes a first sub-blocking part 511 and a second sub-blocking part 512. The extension direction of the first sub-blocking part 511 is the same as the extension direction of the outer edge of the side of the first conductive part 41 facing the display area AA. The second sub-blocking part 512 is connected to the end of the first sub-blocking part 511 and is bent toward the side of the first conductive part 41. In this way, the alignment liquid is effectively blocked.

[0092] The second barrier portion 52 comprises a third sub-barrier portion 521 and a fourth sub-barrier portion 522. The extending direction of the third sub-barrier portion 521 is the same as the extending direction of the second conductive portion 42 towards the outer edge of the display area AA. The fourth sub-barrier portion 522 is connected to the end of the third sub-barrier portion 521 and is bent towards the side of the second conductive portion 42, so as to effectively block the alignment liquid.

[0093] In a possible implementation, as shown in FIG. 1D and FIG. 1E, the first barrier portion 51 further comprises a fifth barrier portion 515. The fifth barrier portion 515 is connected to the other end of the second sub-barrier portion 512. The extension line of the fifth barrier portion 515 in the orthographic projection of the substrate 11 overlaps the orthographic projection of the first conductive portion 41 and / or the first common pattern 6 on the substrate 11. The fifth barrier portion 515 can extend the blocking area of the alignment liquid. The second barrier portion 52 further comprises a sixth barrier portion 516. The sixth barrier portion 516 is connected to the other end of the fourth sub-barrier portion 522. The extension line of the sixth barrier portion 516 in the orthographic projection of the substrate 11 overlaps the orthographic projection of the second conductive portion 42 and / or the first common pattern 6 on the substrate 11. The sixth barrier portion 516 can extend the blocking area of the alignment liquid.

[0094] In a possible implementation, as shown in FIG. 1B and FIG. 1C, the extending direction of the second sub-barrier portion 512 can be perpendicular to the extending direction of the first sub-barrier portion 511. The extending direction of the fourth sub-barrier portion 522 can be perpendicular to the extending direction of the third sub-barrier portion 521. In another possible implementation, as shown in FIG. 1D and FIG. 1E, the second sub-barrier portion 512 and the first sub-barrier portion 511 form an acute angle. The fourth sub-barrier portion 522 and the third sub-barrier portion 521 form an acute angle.

[0095] In another possible implementation, as shown in FIG. 1D and FIG. 1E, the extending direction of the fifth barrier portion 515 can be parallel to the extending direction of the first sub-barrier portion 511. The extending direction of the sixth barrier portion 516 can be parallel to the extending direction of the third sub-barrier portion 521.

[0096] In a possible implementation, the first barrier portion 51 and the second barrier portion 52 can be arranged on the opposite substrate. In a possible implementation, the first barrier portion 51 and the second barrier portion 52 can be arranged on the array substrate. In a possible implementation, the first barrier portion 51 and the second barrier portion 52 can be arranged on the same side substrate as the sealant 3. For example, the sealant 3 is arranged on the opposite substrate 2, and the first barrier portion 51 and the second barrier portion 52 are also arranged on the opposite substrate 2.

[0097] In a possible implementation, referring to FIG. 1A, the display panel includes a plurality of first conductive parts 41 and a plurality of second conductive parts 42. The plurality of first conductive parts 41 are located in the binding area DP and arranged in sequence along the extension direction of the binding area DP. The plurality of second conductive parts 42 are located in the binding opposite area DPO and arranged in sequence along the extension direction of the binding opposite area DPO. That is, the first conductive part 41 is a plurality of separate independent structures, and the second conductive part 42 is a plurality of separate independent structures.

[0098] In a possible implementation, the number of the second conductive parts 42 provided in the binding opposite area DPO is different from the number of the first conductive parts 41 provided in the binding area DP. The number of the second conductive parts 42 provided in the binding opposite area DPO can be greater than the number of the first conductive parts 41 provided in the binding area DP. For example, the number of the first conductive parts 41 provided in the binding area DP can be 4-8, for example, 6. The number of the second conductive parts 42 provided in the binding opposite area DPO can be 8-12, for example, 10.

[0099] In a possible implementation, in the binding area DP, at least part of the first conductive parts 41 can be provided in the area between adjacent flexible circuit boards.

[0100] In a possible implementation, referring to FIG. 2, the first conductive part 41 is in a strip shape and extends along the extension direction of the binding area DPO. The second conductive part 42 is in a strip shape and extends along the extension direction of the binding opposite area DPO. In the embodiment of the present disclosure, the linear coating method can be used to form the first conductive part 41 and the second conductive part 42 in a strip shape. Reducing the first conductive part 41 and / or the second conductive part 42 in a dot shape can cause a larger gap formed by the inward movement of the frame glue, resulting in water vapor residue and corrosion problems.

[0101] In a possible implementation, referring to FIG. 3, the display panel includes a plurality of first conductive parts 41, and the plurality of first conductive parts 41 are located in the binding area DP and arranged in sequence along the extension direction of the binding area DP. The second conductive part 42 is in a strip shape and extends along the extension direction of the binding opposite area DPO. In a possible implementation, the first conductive part 41 is in a strip shape and extends along the extension direction of the binding area DP. The display panel includes a plurality of second conductive parts 42, and the plurality of second conductive parts 42 are located in the binding opposite area DPO and arranged in sequence along the extension direction of the binding opposite area DPO.

[0102] In a possible implementation, referring to FIGS. 4, 5 and 6, the array substrate includes a first substrate 11, and a plurality of first common patterns 6 on one side of the first substrate 11. A projection of the first common electrode pattern 6 on the first substrate 11 at least partially overlaps a projection of the conductive part 4 on the first substrate 11. In a possible implementation, a projection of the conductive part 4 (the first conductive part 41 and / or the second conductive part 42) on the first substrate 11 covers a projection of the first common pattern 6 on the first substrate 11. In the embodiment of the present disclosure, the array substrate further includes a plurality of first common patterns 6, which can serve as marks for the positions where the first conductive part 41 and / or the second conductive part 42 are to be formed. That is, the plurality of first common patterns 6 can be formed first, and then the first conductive part 41 and / or the second conductive part 42 can be formed at the positions marked by the first common patterns 6.

[0103] In a possible implementation, the first common pattern 6 and the conductive part 4 can be arranged one by one.

[0104] In a possible implementation, the first common pattern 6 has a pentagonal, hexagonal or octagonal outer contour. In a possible implementation, referring to FIGS. 4-6, the first common pattern 6 has an octagonal outer contour. The octagonal first common pattern 6 is easy to identify, and facilitates the formation of the first conductive part 41 and / or the second conductive part 42.

[0105] In a possible implementation, the size of the first common pattern 6 can range from (0.5 mm to 1.5 mm) * (0.5 mm to 1.5 mm).

[0106] In a possible implementation, referring to FIGS. 4, 5 and 6, the first common pattern 6 includes a peripheral wiring part 61, a plurality of first wiring parts 62 inside the peripheral wiring part 61, and a plurality of second wiring parts 63. The first wiring part 62 and the second wiring part 63 cross to form a plurality of first opening regions 60. The areas of at least two of the plurality of first opening regions 60 are different. In the embodiment of the present disclosure, the first common pattern 6 includes a plurality of first opening regions 60, which can avoid the problem that the first common pattern 6 is solid and opaque, and thus affects the light transmission at the position and causes the sealant to be difficult to cure. Optionally, the opening rate of the first common pattern 6 can be greater than or equal to 50% and less than 100%.

[0107] In a possible implementation, as shown in FIG. 4, the first common pattern 6 includes two first wiring portions 62 and two second wiring portions 63, each first wiring portion 62 connects two opposite end points of the octagon, and each second wiring portion 63 connects two opposite end points of the octagon, the first wiring portions 62 and the second wiring portions 63 are perpendicular to each other, forming nine first opening areas 60, each first opening area 60 has a large opening area and is easier to be identified as a Mark pattern, but the number of the first wiring portions 62 and the second wiring portions 63 is not too large to affect the thickness of the frame glue.

[0108] In a possible implementation, as shown in FIG. 5, the first common pattern 6 includes a larger number of first wiring portions 62 and second wiring portions 63, for example, nine first wiring portions 62 and nine second wiring portions 63, each first wiring portion 62 connects two opposite end points of the octagon, and the first wiring portions 62 and the second wiring portions 63 are perpendicular to each other, forming more first opening areas 60, and the first wiring portions 62 and the second wiring portions 63 are uniformly distributed, which can reduce the wiring resistance, but there is a problem that the Mark is not easy to be identified.

[0109] In a possible implementation, as shown in FIG. 6, the first common pattern 6 includes three first wiring portions 62 and three second wiring portions 63, part of the first wiring portions 62 is perpendicular to the peripheral wiring portion 61, and part of the second wiring portions 63 is perpendicular to part of the peripheral wiring portion 61, the first wiring portions 62 and the second wiring portions 63 are perpendicular to each other, forming a plurality of first opening areas 60, and the first wiring portions 62 and the second wiring portions 63 shown in FIG. 6 are uniformly distributed and are easy to be identified as a Mark pattern.

[0110] In a possible implementation, as shown in FIG. 4, at least one of the peripheral wiring portion 61, the first wiring portion 62 and the second wiring portion 63 has a plurality of second opening areas 600, and the area of the second opening area 600 is smaller than the area of the first opening area 60. In a possible implementation, at least one of the peripheral wiring portion 61, the first wiring portion 62 and the second wiring portion 63 has a plurality of half opening areas (for example, the position 600 shown in FIG. 4 is a half opening area, that is, the thickness of the metal film layer at this position is smaller than that of the metal film layer without the half opening area), and optionally, the metal film at this position can be hollowed out to be a through hole state to improve the curing of the frame glue. Referring to FIG. 4, the second opening area and the peripheral wiring portion 61, the first wiring portion 62 and the second wiring portion 63 are all overlapped in the direction perpendicular to the display panel.

[0111] In a possible implementation, referring to FIGS. 7A-7B, 8A-8B, 9A-9B, and 10, the array substrate includes a first common electrode trace 12, and the counter substrate includes a second common electrode trace 23. The first common electrode trace 12 and the second common electrode trace 23 are electrically connected through the conductive part 4. That is, the second common electrode trace 23 of the counter substrate is electrically connected to the first common electrode trace 12 of the array substrate through the conductive part 4. The first common electrode trace 12 includes the first common pattern 6. That is, the first common pattern 6 is arranged on the first common electrode trace 12 as a dotting mark of the conductive part 4.

[0112] In a possible implementation, referring to FIGS. 7A-7B, 8A-8B, 9A-9B, and 10, the array substrate includes a first common electrode trace 12, and the counter substrate includes a second common electrode trace 23. The first common electrode trace 12 and the second common electrode trace 23 are electrically connected through the conductive part 4. That is, the second common electrode trace 23 of the counter substrate is electrically connected to the first common electrode trace 12 of the array substrate through the conductive part 4. The first common electrode trace 12 includes the first common pattern 6. That is, the first common pattern 6 is arranged on the first common electrode trace 12 as a dotting mark of the conductive part 4.

[0113] In a possible implementation, the first common pattern 6 can be of the same layer and material as the gate line.

[0114] Optionally, the switch-over electrode 13 can be of the same layer and material as the common electrode layer or the pixel electrode layer. Optionally, the material of the switch-over electrode 13 can include indium tin oxide.

[0115] In a possible implementation, referring to FIGS. 7A-7B, the first common pattern 6 corresponds to the first via hole K1 one by one. That is, a larger first via hole K1 is arranged at the position of each first common pattern 6, and the area of the first via hole K1 is 50% to 90% of the area of the first common pattern 6. In the embodiment of the present disclosure, the first via hole K1 is larger, the conduction area is larger, the conduction resistance is smaller, and the conduction effect is better. However, the large-area opening at the position of the conductive part 4 causes the film layer at this position to be thinner than other positions, which causes the frame glue at this position to be thinner, resulting in abnormal Gap. In addition, the large distance between the upper and lower conductive particles 402 increases the probability of not being conductive.

[0116] In a possible implementation, referring to FIG. 7B, the first insulating layer 14 is further provided with a plurality of second through holes K2 at the periphery of the first through hole K1; the plurality of second through holes K2 can improve the problem that the first through hole K1 has a large difference in film layer thickness with the periphery, leading to abnormal Gap.

[0117] In a possible implementation, the area of the first through hole K1 is greater than 70% of the area of the first common pattern 6, so as to have a better conduction effect.

[0118] In a possible implementation, referring to FIGS. 8A-8B, the first through hole K1 includes a plurality of first sub-through holes K11; the plurality of first sub-through holes K11 of the same first through hole K1 are all located in the projection of the first common pattern 6 on the first substrate 11. In the embodiment of the present disclosure, the first through hole K1 includes a plurality of first sub-through holes K11, which are designed as small holes, and the conductive particles 402 have a good conduction effect, but the first sub-through hole K11 has a small conduction area, which may have a large conduction resistance problem.

[0119] In a possible implementation, referring to FIGS. 9A-9B, the first through hole K1 includes a second sub-through hole K12 and a plurality of third sub-through holes K13; the size of the third sub-through hole K13 is smaller than the size of the second sub-through hole K12; the first common pattern 6 partially overlaps the sealant 3 and partially does not overlap the sealant 3; the projection of the second sub-through hole K12 on the first substrate 11 is located in the overlapping area of the first common pattern 6 and the sealant 3; the projection of the third sub-through hole K13 on the first substrate 11 is located in the area outside the overlapping area of the first common pattern 6 and the sealant 3. In the embodiment of the present disclosure, a large hole is punched at the overlapping area of the first common pattern 6 and the sealant 3, and a small hole is punched at other positions, which not only solves the problem that the sealant is too high at the overlapping area of the conductive part 4 and the sealant 3, but also increases the conduction area of the through hole.

[0120] The structures shown in FIGS. 7A-7B, 8A-8B, and 9A-9B are all holes punched at the position of the conductive part 4. In another possible implementation, referring to FIG. 11, the projection of the first common pattern 6 on the first substrate 11 does not overlap the projection of the first common electrode trace 12 on the substrate; and the projection of the first through hole K1 on the substrate 11 overlaps the projection of the first common electrode trace 12 on the first substrate 11; the first common pattern 6 is electrically connected to the first common electrode trace 12 through the first through hole K1 and the transfer electrode 13. That is, in the embodiment of the present disclosure, the first through hole K1 is designed outside the sealant 3, is connected to the position of the conductive part 4 (that is, the first common pattern 6) through the transfer electrode 13, and the first common pattern 6 only serves as a Mark mark inspection function.

[0121] In a conventional technology, a VA display product is designed to incorporate gold balls into the frame sealant, and the frame sealant containing the gold balls is coated around the display panel. Due to the gold balls in the frame sealant, the lower wire of the frame sealant can only be configured with a common signal (COM) electrode, and other signal electrodes cannot be configured. The advantage of this frame sealant form is that the upper and lower electrode conduction effects are good, and the entire frame sealant can play a conduction role. However, there are problems: 1. prone to electrostatic discharge (ESD) failure. The frame sealant contains gold balls. If other signal wires are covered, due to the conduction effect of the gold balls, the distance between the upper and lower signals is shortened, and reliability or electrostatic testing is prone to upper and lower burnout or electrostatic failure; 2. not suitable for narrow frame. The display panel is configured with a gate drive circuit on both sides of the non-display area. Due to the need for metal wire replacement, a transparent electrode (such as a switching electrode) needs to be configured. The transparent electrode is in a bare state. If the frame sealant with gold balls is coated thereon, a short circuit problem between two signals will occur. Therefore, the frame sealant cannot be configured at the same position as the gate drive circuit. In this way, the frame of the non-display area where the gate drive circuit is set needs to be increased, which is contrary to the current narrow frame design direction. If you want to adapt to the narrow frame, you need to compress the width of the frame sealant. This will result in poor sealing of the frame sealant, which is prone to moisture entering and causing failure or bubbles, affecting product yield and reliability.

[0122] In a possible implementation, as shown in FIG. 1A, the display panel further includes: a first non-display area BB1 located at the periphery of the display area AA and connected to the binding area DP and the binding opposite area DPO; of the binding area DP, the binding opposite area DPO and the first non-display area BB1, only the binding area DP and the binding opposite area DPO are provided with the conductive part 4. In this way, the first non-display area BB1 where the gate drive circuit GOA is arranged can not be provided with the conductive part 4 containing the conductive particles 402, and thus the first non-display area BB1 can not be provided with the conductive part 4 and the gate drive circuit GOA and / or the gate drive signal wire GZ at the same time, thereby avoiding the problem of electrostatic failure, and because the conductive part 4 and the gate drive circuit GOA and / or the gate drive signal wire GZ cannot be overlapped, if the first non-display area BB1 is provided with the conductive part 4 and the gate drive circuit GOA and / or the gate drive signal wire GZ at the same time, and the projection does not overlap, the first non-display area BB1 will be wider, which is not conducive to narrow frame design.

[0123] In a possible implementation, referring to FIG. 12, the first non-display area BB1 includes a third display panel outer edge w3, a gate drive unit GOA, and a gate drive signal wire GZ located on a side of the gate drive unit GOA away from the display area 11. In the first non-display area BB1, the sealant 3 overlaps at least part of the gate drive signal wire GZ. In the embodiment of the present disclosure, the binding area DP and the binding opposite area DPO are provided with the conductive part 4, and the first non-display area BB1 is not provided with the conductive part 4. The sealant 3 and the gate drive signal wire GZ can be combined together, which is beneficial to save space and realize a narrow frame design.

[0124] Based on the same inventive concept, the present disclosure also provides a display device, which includes the display panel provided by the present disclosure.

[0125] Based on the same inventive concept, the present disclosure also provides a manufacturing method of the display panel provided by the present disclosure, which includes the following steps, referring to FIG. 13.

[0126] Step S100, applying a sealant on a display area of a counter substrate and / or an array substrate;

[0127] Step S200, forming a first conductive part in a binding area, and making part of the first conductive part overlap the sealant, and part of the first conductive part extend out of the sealant and to a region on a side of the display area;

[0128] Step S300, forming a second conductive part in a binding opposite area, and making part of the second conductive part overlap the sealant, and part of the second conductive part extend out of the sealant and to a region on a side away from the display area;

[0129] Step S400, pressing the counter substrate and the array substrate to adhere the array substrate and the counter substrate.

[0130] Although the preferred embodiments of the present application have been described, those skilled in the art who understand the basic inventive concept can make additional changes and modifications to the embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0131] Obviously, persons of skill in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and equivalents thereof, the present application is also intended to include these modifications and variations.

Claims

1. A display panel having a display area and a non-display area located around the periphery of the display area; the non-display area comprising: A bonding area located on one side of the display area, and a bonding opposite area located on the other side of the display area and opposite to the bonding area, wherein the display panel includes: An array substrate and a facing substrate arranged opposite to each other; The sealing adhesive is located between the array substrate and the opposing substrate, and is located in the non-display area; The conductive portion includes: a first conductive portion and a second conductive portion; the first conductive portion is located between the array substrate and the opposing substrate, and is located in the bonding region, wherein the first conductive portion partially overlaps with the sealant, and partially extends beyond the sealant and faces the display area; the second conductive portion is located between the array substrate and the opposing substrate, and is located in the bonding opposite region, wherein the second conductive portion partially overlaps with the sealant, and partially extends beyond the sealant and is away from the display area; the conductive portion is configured to conduct electrical signals between the array substrate and the opposing substrate.

2. The display panel as claimed in claim 1, wherein, The sealing adhesive includes: a first sealing adhesive edge and a second sealing adhesive edge; the minimum distance between the first sealing adhesive edge and the display area is less than the minimum distance between the second sealing adhesive edge and the display area; The first conductive part overlaps with the edge of the first sealing adhesive, and the second conductive part overlaps with the edge of the second sealing adhesive.

3. The display panel as described in claim 1 or 2, wherein, The display panel includes: a first panel outer edge and a second panel outer edge; the first panel outer edge and the bonding area are located on the same side of the display area, and the second panel outer edge and the bonding opposite side area are located on the same side of the display area; The minimum distance between the sealing adhesive and the first outer edge is less than the minimum distance between the sealing adhesive and the second outer edge.

4. The display panel as claimed in claim 3, wherein, The display panel further includes: a first blocking part, and / or, a second blocking part; The first barrier portion is located between the first conductive portion and the display area; the second barrier portion is located between the second conductive portion and the outer edge of the second panel.

5. The display panel as claimed in claim 4, wherein, The first blocking portion includes: a first sub-blocking portion and a second sub-blocking portion; the extending direction of the first sub-blocking portion is the same as the extending direction of the outer edge of the first conductive portion toward the display area; the second sub-blocking portion is connected to the end of the first sub-blocking portion and is bent toward the first conductive portion. The second blocking portion includes: a third sub-blocking portion and a fourth sub-blocking portion; the extending direction of the third sub-blocking portion is the same as the extending direction of the outer edge of the second conductive portion toward the display area; the fourth sub-blocking portion is connected to the end of the third sub-blocking portion and is bent toward the side of the second conductive portion.

6. The display panel according to any one of claims 1-5, wherein, The display panel includes a plurality of first conductive portions and a plurality of second conductive portions; The plurality of first conductive parts are all located in the bonding area and are arranged sequentially along the extension direction of the bonding area; the plurality of second conductive parts are all located in the bonding opposite side area and are arranged sequentially along the extension direction of the bonding opposite side area.

7. The display panel as described in any one of claims 1-5, wherein, The first conductive portion is strip-shaped and extends along the extension direction of the bonding region; the second conductive portion is strip-shaped and extends along the extension direction of the bonding opposite side region.

8. The display panel according to any one of claims 1-7, wherein, The array substrate includes: a first substrate and a plurality of first common patterns; The orthographic projection of the first common electrode pattern onto the first substrate at least partially overlaps with the orthographic projection of the conductive portion onto the first substrate.

9. The display panel as claimed in claim 8, wherein, The outer contour of the first common pattern is a pentagon, hexagon, or octagon.

10. The display panel as claimed in claim 8 or 9, wherein, The first common pattern includes: an outer wiring portion, multiple first wiring portions located inside the outer wiring portion, and multiple second wiring portions; the first wiring portions and the second wiring portions intersect to form multiple first opening areas; At least two of the plurality of first opening regions have different areas.

11. The display panel as claimed in claim 10, wherein, At least one of the peripheral wiring section, the first wiring section, and the second wiring section has a plurality of second opening areas; the area of ​​the second opening area is smaller than the area of ​​the first opening area.

12. The display panel as claimed in any one of claims 8-11, wherein, The array substrate includes: a transfer electrode located on the side of the first common pattern facing the opposing substrate, and a first insulating layer located between the transfer electrode and the first common pattern; the transfer electrode is electrically connected to the conductive portion; The first insulating layer has a first via, and the first common pattern is electrically connected to the adapter electrode through the first via.

13. The display panel as claimed in claim 12, wherein, The first common pattern corresponds to the first via, and the area of ​​the first via is 50% to 90% of the area of ​​the first common pattern.

14. The display panel as claimed in claim 12, wherein, The first via includes: a plurality of first sub-vias; the orthographic projections of the plurality of first sub-vias of the same first via onto the first substrate are all located within the orthographic projection of the first common pattern onto the first substrate.

15. The display panel as claimed in claim 12, wherein, The first via includes: a second sub-via and a plurality of third sub-vias; the size of the third sub-via is smaller than the size of the second sub-via; the first common pattern part overlaps with the sealing adhesive, and part does not overlap with the sealing adhesive; The second sub-via's orthographic projection onto the first substrate is located in the area where the first common pattern overlaps with the sealant; the third sub-via's orthographic projection onto the first substrate is located in the area outside the area where the first common pattern overlaps with the sealant.

16. The display panel according to any one of claims 9-15, wherein, in, The array substrate includes a first common electrode trace; the opposing substrate includes a second common electrode trace; the first common electrode trace and the second common electrode trace are electrically connected through the conductive portion; The first common electrode trace includes the first common pattern.

17. The display panel as claimed in claim 12, wherein, The orthographic projection of the first common pattern onto the first substrate does not overlap with the orthographic projection of the first common electrode trace onto the substrate; and the orthographic projection of the first via onto the substrate overlaps with the orthographic projection of the first common electrode trace onto the first substrate. The first common pattern is electrically connected to the first common electrode trace via the first via through the adapter electrode.

18. The display panel according to any one of claims 1-17, wherein, The display panel further includes: a first non-display area located outside the display area and connecting the binding area and the binding opposite side area; Of the binding area, the binding opposite area, and the first non-display area, only the binding area and the binding opposite area are provided with the conductive part.

19. The display panel as claimed in claim 18, wherein, The first non-display area includes: a gate driving unit, and a gate driving signal trace located on the side of the gate driving unit away from the display area; In the first non-display area, the sealing adhesive overlaps with at least a portion of the gate drive signal traces.

20. A display device, wherein, include: The display panel as described in any one of claims 1-19.

21. A method for manufacturing a display panel as described in any one of claims 1-19, wherein, The manufacturing method includes: A sealing adhesive is applied around the display area of ​​the opposing substrate and / or the array substrate; A first conductive portion is formed in the bonding area, and the first conductive portion partially overlaps with the sealant, and partially extends beyond the sealant and faces the display area. A second conductive portion is formed in the bonding opposite area, and the second conductive portion partially overlaps with the sealant, and partially extends beyond the sealant and away from the display area. The opposing substrate and the array substrate are pressed together to bond the array substrate and the opposing substrate.

Images