Array substrate, display panel and display device

Abstract

An array substrate, a display panel (41) and a display device. The array substrate comprises: a substrate (1) comprising a first region (AA) and a peripheral region; a plurality of sub-pixel units (5), each sub-pixel unit (5) in the plurality of sub-pixel units (5) comprising a thin film transistor (501) and a first electrode (502) electrically connected to the thin film transistor (501), the first electrode (502) being located on one side of the thin film transistor (501) facing away from the substrate (1); and the electrode structure (2) is positioned between the thin film transistor (501) and the first electrode (502). The electrode structure (2) comprises a second electrode (201) and a first electrode wire (202) which is in contact and electric connection with the second electrode (201) on one side, deviating from the substrate (1), of the second electrode (201). The second electrode (201) comprises a first opening (2011); the first electrode wire (202) comprises a first portion (202-1) and a first protruding portion (202-2) adjacent to the first portion (202-1). The orthographic projection of the first protruding part (202-2) on the substrate (1) is located between the orthographic projection of the first opening (2011) on the substrate (1) and the orthographic projection of the first part (202-1) on the substrate (1).

Description

Array substrate, display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and particularly relates to an array substrate, a display panel and a display device. BACKGROUND

[0002] With the development of information technology, electronic devices are widely used in people's daily life, and liquid crystal displays, as the most widely used flat panel display, play an important role in display panels. With the continuous progress of technology, users have higher and higher requirements for the display effect of display screens.

[0003] In order to improve the stability of the display common electrode voltage of high refresh rate products, a common electrode trace is added in the panel, so as to improve the stability of the voltage of the common electrode. However, the common electrode trace is arranged in the same layer as the scan line, which reduces the pixel aperture ratio and affects the transmittance of the display product, resulting in high overall power consumption of the product.

[0004] SUMMARY

[0005] An array substrate provided by an embodiment of the present disclosure includes:

[0006] A substrate includes a first region and a peripheral region surrounding the first region;

[0007] A plurality of sub-pixel units are arranged in a first direction and a second direction in the first region; the first direction intersects the second direction; each of the plurality of sub-pixel units includes a thin film transistor and a first electrode electrically connected to the thin film transistor; the first electrode is located on a side of the thin film transistor away from the substrate;

[0008] An electrode structure is located between the thin film transistor and the first electrode; the electrode structure includes a second electrode and a first electrode line in contact and electrically connected to the second electrode on a side of the second electrode away from the substrate; the second electrode includes a first opening; the first electrode line includes a first portion and a first protruding portion adjacent to the first portion; a projection of the first protruding portion on the substrate is located between a projection of the first opening on the substrate and a projection of the first portion on the substrate.

[0009] In some embodiments, a projection of the electrode structure on the substrate and a projection of the plurality of sub-pixel units on the substrate both overlap; the first opening corresponds to the sub-pixel unit one by one, and the first electrode line includes a plurality of first protruding portions;

[0010] The first protruding portion is located on one side of the first portion in the second direction; in the first direction, a width of at least part of the first protruding portion is greater than or equal to a width of the first opening.

[0011] In some embodiments, in the first direction, the width of the first protruding portion is greater than the width of the first opening.

[0012] In the first direction, the portions of the first protruding portion that extend beyond the first opening are located on both sides of the first opening, respectively.

[0013] In some embodiments, the first protruding portion has a flush area with the edge of the first opening in the orthographic projection of the substrate in the first direction.

[0014] In some embodiments, the first electrode line comprises a plurality of first sub-electrode lines extending in the first direction.

[0015] The first sub-electrode line comprises a first portion extending in the first direction, and a plurality of first protruding portions located on one side of the first portion in the second direction, and the orthographic projection of the first opening in the substrate in the second direction is located on one side of the orthographic projection of the first protruding portion in the substrate.

[0016] In some embodiments, the array substrate further comprises:

[0017] A plurality of scan lines located between the substrate and the electrode structure; the plurality of scan lines extend in the first direction.

[0018] The orthographic projection of the first sub-electrode line in the substrate and the orthographic projection of the scan line in the substrate have an overlapping area, and in part of the overlapping area, the orthographic projection of the first portion in the substrate falls within the orthographic projection of the scan line in the substrate.

[0019] The orthographic projection of the scan line in the substrate towards the edge of the first opening on one side has a first distance with the orthographic projection of the first opening in the substrate, and the orthographic projection of the first protruding portion in the substrate towards the edge of the first opening on one side has a second distance with the orthographic projection of the first opening in the substrate, and the second distance is smaller than the first distance.

[0020] In some embodiments, the array substrate further comprises:

[0021] A plurality of spacers located on the side of the first electrode structure away from the substrate; the plurality of spacers comprises a plurality of first spacers; the orthographic projection of the first spacer in the substrate and the orthographic projection of the first electrode line in the substrate do not overlap with each other, and the first sub-electrode line is disconnected in the area where the first spacer is arranged; the orthographic projection of the connection line of the first sub-electrode line in the disconnected area and the orthographic projection of the first spacer in the substrate overlap in the substrate; and the disconnected area is located between two first protruding portions.

[0022] In some embodiments, the width of the disconnected area in the first direction is greater than the width of the two first openings in the first direction.

[0023] The first protruding portion located at one side of the disconnected region has a width in the first direction smaller than that of the first protruding portion in the remaining region.

[0024] In some embodiments, the electrode structure further comprises: a plurality of first strip portions arranged in the same layer as the first electrode lines; in the second direction, the first strip portions are located on one side of the first opening in the orthographic projection of the substrate.

[0025] In some embodiments, the first strip portions have a flush area with the edge of the first opening in the orthographic projection of the substrate.

[0026] In some embodiments, the first strip portions comprise a plurality of sub-portions disconnected from each other and arranged in the first direction.

[0027] In some embodiments, the first electrode comprises a plurality of slits;

[0028] The slits overlap the sub-portions in the orthographic projection of the substrate.

[0029] In some embodiments, the first opening in the orthographic projection of the substrate overlaps the area between the sub-portions in the orthographic projection of the substrate.

[0030] In some embodiments, the width of at least part of the first strip portions in the first direction is greater than or equal to the width of the first opening in the first direction.

[0031] In some embodiments, the electrode structure further comprises: a plurality of second strip portions arranged in the same layer as the first electrode lines in the wiring area; the second strip portions are electrically connected to the first strip portions and the first electrode lines.

[0032] In some embodiments, the second strip portions extend in the second direction;

[0033] In the first direction, the orthographic projection of the second strip portions is located on at least one side of the orthographic projection of the first opening in the substrate;

[0034] The second strip portions are electrically connected to the first protruding portions.

[0035] In some embodiments, the second strip portions extend in the first direction, and the second strip portions are located on at least one side of the first strip portions in the first direction;

[0036] The first electrode lines further comprise: a plurality of second sub-electrode lines extending in the second direction;

[0037] At least part of the second strip portions are further electrically connected to the second sub-electrode lines.

[0038] In some embodiments, the array substrate further comprises:

[0039] a plurality of data lines between the substrate and the electrode structure; the number of the second sub-electrode lines is less than the number of the data lines;

[0040] The first sub-electrode line further includes a plurality of second protruding portions on the first portion side in the second direction.

[0041] Part of the data lines in the plurality of data lines overlap the second sub-electrode lines in the orthographic projection of the substrate, and the rest of the data lines in the plurality of data lines overlap the second protruding portions in the orthographic projection of the substrate.

[0042] The part of the second strip portion is electrically connected with the second protruding portion.

[0043] In some embodiments, the electrode structure further includes a plurality of second strip portions in the wiring area and arranged in the same layer as the first electrode lines.

[0044] The second strip portion extends in the second direction.

[0045] In the first direction, the orthographic projection of the second strip portion is at least on one side of the orthographic projection of the first opening in the substrate.

[0046] One end of the second strip portion is electrically connected with the first strip portion, and the second strip portion is not directly connected with the first protruding portion.

[0047] In some embodiments, the array substrate further includes:

[0048] a plurality of first vias; the first electrode and the thin film transistor are electrically connected through the first vias; the orthographic projection of the first vias in the substrate falls within the orthographic projection of the first opening in the substrate.

[0049] In some embodiments, the second electrode extends to the peripheral area.

[0050] The first electrode line further includes:

[0051] a first peripheral electrode line in the peripheral area.

[0052] The array substrate further includes:

[0053] a second peripheral electrode line arranged in the same layer as the gate of the thin film transistor; the second peripheral electrode line is electrically connected with the first peripheral electrode line.

[0054] a third peripheral electrode line arranged in the same layer as the first electrode; the first peripheral electrode line and the second peripheral electrode line are electrically connected through the third peripheral electrode line.

[0055] The peripheral region includes a first peripheral region located on one side of the first region in the second direction; in the first peripheral region, the first peripheral electrode line is covered by the third peripheral electrode line on the projection of the substrate substrate.

[0056] In some embodiments, the electrode structure further includes:

[0057] A plurality of second openings located in the first peripheral region; the second openings pass through the second electrode; the edge of the projection of the substrate substrate is located between the second opening in the projection of the substrate substrate and the first region;

[0058] The array substrate further includes:

[0059] A plurality of connection electrodes arranged in the same layer as the source electrode of the thin film transistor in the first peripheral region;

[0060] A plurality of second vias located in the first peripheral region; the connection electrode and the second peripheral electrode line are electrically connected through the second via;

[0061] A plurality of third vias located in the first peripheral region; the third via falls into the projection of the first peripheral electrode line on the projection of the substrate substrate, and the first peripheral electrode line and the third peripheral electrode line are electrically connected through the third via;

[0062] A plurality of fourth vias located in the first peripheral region; the fourth via falls into the projection of the second opening on the projection of the substrate substrate, and the third peripheral electrode line and the connection electrode are electrically connected through the fourth via.

[0063] The display panel provided by the embodiment of the present disclosure includes:

[0064] The array substrate provided by the embodiment of the present disclosure includes:

[0065] The counter substrate is arranged opposite to the array substrate;

[0066] The liquid crystal layer is located between the array substrate and the counter substrate;

[0067] The array substrate includes a first strip-shaped portion;

[0068] The counter substrate includes a black matrix; the black matrix includes a plurality of opening regions;

[0069] The first strip-shaped portion falls into the projection of the black matrix on the projection of the substrate substrate.

[0070] The display device provided by the embodiment of the present disclosure includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0071] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0072] FIG. 1 is a structural schematic diagram of an array substrate provided by the related art;

[0073] FIG. 2 is a structural schematic diagram of an array substrate provided by an embodiment of the present disclosure;

[0074] FIG. 3 is a sectional view along CC' in FIG. 2 provided by an embodiment of the present disclosure;

[0075] FIG. 4 is a sectional view along EE' in FIG. 2 provided by an embodiment of the present disclosure;

[0076] FIG. 5 is an enlarged structural schematic diagram of the F region in FIG. 2 provided by an embodiment of the present disclosure;

[0077] FIG. 6 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0078] FIG. 7 is a structural schematic diagram of still another array substrate provided by an embodiment of the present disclosure;

[0079] FIG. 8 is a structural schematic diagram of still another array substrate provided by an embodiment of the present disclosure;

[0080] FIG. 9 is a structural schematic diagram of still another array substrate provided by an embodiment of the present disclosure;

[0081] FIG. 10 is a structural schematic diagram of still another array substrate provided by an embodiment of the present disclosure;

[0082] FIG. 11 is a structural schematic diagram of still another array substrate provided by an embodiment of the present disclosure;

[0083] FIG. 12 is a structural schematic diagram of still another array substrate provided by an embodiment of the present disclosure;

[0084] FIG. 13 is a sectional view along KK' in FIG. 12 provided by an embodiment of the present disclosure;

[0085] FIG. 14 is a structural schematic diagram of still another array substrate provided by an embodiment of the present disclosure;

[0086] FIG. 15 is a structural schematic diagram of still another array substrate provided by an embodiment of the present disclosure;

[0087] FIG. 16 is a structural schematic diagram of still another array substrate provided by an embodiment of the present disclosure;

[0088] FIG. 17 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0089] FIG. 18 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0090] FIG. 19 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0091] FIG. 20 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0092] FIG. 21 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0093] FIG. 22 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0094] FIG. 23 is a sectional view along MM' in FIG. 22 according to an embodiment of the present disclosure;

[0095] FIG. 24 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0096] FIG. 25 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0097] FIG. 26 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0098] FIG. 27 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure;

[0099] FIG. 28 is a structural schematic diagram of a display panel according to an embodiment of the present disclosure;

[0100] FIG. 29 is a structural schematic diagram of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0101] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of, but not all of the embodiments of the present disclosure. And in the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0102] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the meanings as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", and similar terms are used to distinguish one element from another, and are not necessarily used to describe a sequential or chronological order. The terms "comprises", "comprising", or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "connected", "coupled", or any other variation thereof are intended to cover a physical or mechanical connection, an electrical connection, or both, between two or more elements.

[0103] It should be noted that the size and shape of the various figures in the drawings are not to scale, and are intended merely to illustrate the present disclosure. Identical or similar reference signs are used throughout the drawings to indicate identical or similar elements or elements having identical or similar functions.

[0104] In the related art, the common electrode wire is arranged in the same layer as the scan line, which causes the pixel aperture ratio to decrease, thereby affecting the transmittance of the display product, and causing the overall power consumption of the product to be high. The problem of aperture ratio reduction caused by the common electrode wire being arranged in the same layer as the scan line can be avoided by making the common electrode wire contact the common electrode. When the common electrode wire and the common electrode are manufactured, a mask can be used to form the pattern of the common electrode wire and the pattern of the common electrode through a half-tone mask process. However, when the common electrode is located below the pixel electrode, as shown in FIG. 1, a common electrode opening 4301 needs to be formed on the common electrode 43, and the distance between the common electrode opening 4301 and the common electrode wire 19 is greater than 0. When the common electrode 43 and the common electrode wire 19 are manufactured using the half-tone mask process, the common electrode layer and the common electrode wire layer are formed in sequence, then positive photoresist is coated on the common electrode wire layer, the photoresist is completely exposed in the area where the common electrode opening 4301 needs to be manufactured, the photoresist is incompletely exposed in the area outside the common electrode opening 4301 and the common electrode wire 19, and the area corresponding to the pattern of the common electrode wire 19 is not exposed. When the distance between the common electrode opening 4301 and the common electrode wire 19 is less than the process fluctuation of the incompletely exposed area, that is, the area of the incompletely exposed area is small, the incompletely exposed area may expand downward, that is, the actual width of the area where the photoresist is not exposed is smaller than the designed width, thereby causing the width of the common electrode wire 19 to be smaller than the designed width, and the common electrode wire 19 is prone to breakage.

[0105] The array substrate provided by the embodiments of the present disclosure is shown in FIGS. 2-5, and the array substrate comprises:

[0106] The substrate 1 comprises a first area AA and a peripheral area (not shown) surrounding the first area AA;

[0107] The plurality of sub-pixel units 5 are arranged in the first direction X and the second direction Y in the first area AA. The first direction X and the second direction Y are perpendicular to each other. Each of the plurality of sub-pixel units 5 comprises a thin film transistor 501 and a first electrode 502 electrically connected to the thin film transistor 501. The first electrode 502 is located on a side of the thin film transistor 501 away from the substrate 1.

[0108] The electrode structure 2 is located between the thin film transistor 501 and the first electrode 502. The electrode structure 2 comprises a second electrode 201 and a first electrode line 202 in contact with the second electrode 201 on a side of the second electrode 201 away from the substrate 1. The second electrode 201 comprises a first opening 2011. The first electrode line 202 comprises a first portion 202-1 and a first protruding portion 202-2 adjacent to the first portion 202-1. A projection of the first protruding portion 202-2 on the substrate 1 is located between a projection of the first opening 2011 on the substrate 1 and a projection of the first portion 202-1 on the substrate 1.

[0109] The array substrate provided by the embodiments of the present disclosure can reduce the resistance of the second electrode and improve the working stability of the electrode structure by electrically connecting the first electrode line and the second electrode. In addition, the first electrode line comprises the first protruding portion between the first portion and the first opening. Even if the actual exposure area in the area corresponding to the first opening is larger than the designed exposure area in the direction of the first electrode line during the manufacturing of the electrode structure, which causes the actual line width of the first protruding portion to be smaller than the designed line width, the line width of the first portion corresponding to the first protruding portion will not be affected, thereby avoiding the risk of disconnection of the first portion and improving the manufacturing yield of the first electrode line, and further improving the yield of the array substrate and saving costs.

[0110] It should be noted that FIG. 3 is a sectional view along CC' in FIG. 2, FIG. 4 is a sectional view along EE' in FIG. 2, and FIG. 5 is an enlarged view of the F region in FIG. 2.

[0111] In some embodiments, as shown in FIGS. 2 and 5, the area between the projection of the first opening 2011 on the substrate 1 and the projection of the first portion 202-1 on the substrate 1 is covered by the projection of the first protruding portion 202-2 on the substrate 1.

[0112] In a direction perpendicular to the arrangement direction of the first protruding portion 202-2 and the first opening 2011, the width of at least part of the first protruding portion 202-2 is greater than or equal to the width of the first opening 2011.

[0113] The array substrate provided by the embodiments of the present disclosure is characterized in that the width of at least part of the first protruding part 202-2 is greater than or equal to the width of the first opening, so that the first protruding part covers the area between the first opening and the first part in the orthographic projection of the substrate substrate, that is, the area between the first opening and the first part is provided with the first protruding part, which can ensure that the first electrode line corresponding to the area of the first opening will not be at risk of disconnection.

[0114] It should be noted that the direction in which the first protruding part 202-2 and the first opening 2011 are arranged refers to the direction in which the orthographic projection of the closest two first protruding parts 202-2 and the first opening 2011 is arranged. For example, as shown in FIG. 2, the first protruding part 202-2 is located on one side of the first part 202-1 in the second direction, and the first opening 2011 is located on one side of the first protruding part 202-2 in the second direction. The direction perpendicular to the direction in which the first protruding part 202-2 and the first opening 2011 are arranged is the first direction X, that is, in the first direction X, the width of at least part of the first protruding part 202-2 is greater than or equal to the width of the first opening 2011.

[0115] In some embodiments, as shown in FIGS. 5, 7, and 8, in the direction perpendicular to the direction in which the first protruding part 202-2 and the first opening 2011 are arranged, the width of the first protruding part 202-2 is greater than the width of the first opening 2011.

[0116] In some embodiments, as shown in FIGS. 5, 7, and 8, in the first direction X, the width of the first protruding part 202-2 is greater than the width of the first opening 2011.

[0117] In the first direction X, the part of the first protruding part 202-2 that exceeds the first opening 2011 is located on both sides of the first opening 2011. Thus, it can be ensured that the area between the first opening and the first part is provided with the first protruding part, and it can be ensured that the first electrode line corresponding to the area of the first opening will not be at risk of disconnection.

[0118] Alternatively, as shown in FIG. 6, in the direction perpendicular to the direction in which the first protruding part 202-2 and the first opening 2011 are arranged, the width of the first protruding part 202-2 is equal to the width of the first opening 2011.

[0119] In some embodiments, as shown in FIGS. 5 and 7, the pattern of the first protruding part 202-2 is a combination of a rectangular Q3 and a trapezoidal Q4. Alternatively, in some embodiments, as shown in FIGS. 6 and 8, the pattern of the first protruding part 202-2 is a trapezoid.

[0120] In some embodiments, as shown in FIGS. 2 and 3, the orthographic projection of the first protruding part 202-2 on the substrate substrate 1 away from the edge of the side of the first part 202-1 has a flush area with the edge of the orthographic projection of the first opening 2011.

[0121] The array substrate provided by the embodiments of the present disclosure is provided with a first protruding portion between the first opening and the first portion, and the edge of the first protruding portion and the edge of the first opening have a flush area, that is, there is no area with only the second electrode and no first electrode line between the first opening and the first protruding portion in the orthographic projection of the substrate. Thus, during the manufacturing of the electrode structure, there is no incomplete exposure area between the first opening and the first protruding portion, which avoids the risk of the actual line width of the first electrode line being smaller than the designed line width due to the expansion of the incomplete exposure area, further improves the manufacturing yield of the first electrode line, and further improves the yield of the array substrate and saves costs.

[0122] In some embodiments, the thickness of the second electrode is much smaller than the thickness of the first electrode line. Generally, the thickness of the second electrode is about 700 angstroms, and the thickness of the first electrode line is about 3000 angstroms. As shown in FIG. 3, the pattern of the second electrode and the pattern of the first electrode line are formed by a patterning process on the electrode structure, the thickness of the second electrode 201 is relatively thin, and the side of the second electrode 201 at the first opening 2011 is generally a first plane P1 perpendicular to the direction of the substrate 1. The thickness of the first electrode line 202 is relatively thick, and the side of the first electrode line 202 at the area corresponding to the first opening 2011 includes an inclined side P2 with an acute angle with the plane of the substrate 1. The side of the first electrode line 202 can also include a second plane P3 perpendicular to the direction of the substrate 1, and the second plane P3 is connected to the inclined side P2 on the side of the inclined side P2 facing the substrate 1. As shown in FIG. 3, the side of the first electrode line 202 includes the second plane P3, and the second plane P3 and the first plane P1 have a flush area. Alternatively, if the side of the first electrode line 202 only includes the inclined side P2, the edge of the inclined side P2 closest to the side of the first opening 2011 has a flush area with the first plane P1.

[0123] In some embodiments, as shown in FIG. 2, the first area AA includes a plurality of sub-pixel areas 101 arranged in the first direction X and the second direction Y, and at least a wiring area 102 located between adjacent sub-pixel areas 101.

[0124] The array substrate further includes:

[0125] A plurality of scan lines 4 located between the substrate 1 and the electrode structure 2, the plurality of scan lines 4 extending in the first direction X and arranged in the second direction Y;

[0126] A plurality of data lines 9 located between the substrate 1 and the electrode structure 2, the plurality of data lines 9 extending in the second direction Y and arranged in the first direction X; the plurality of scan lines 4 and the plurality of data lines 9 are arranged in a cross manner;

[0127] The first electrode line 202, the first opening 2011, the thin film transistor 501, the scan line 4, and the data line 9 are in orthographic projection on the wiring area 102 of the substrate 1; the first electrode 502 is in orthographic projection on the wiring area 102 and the sub-pixel area 101 of the substrate 1, and one sub-pixel area 101 corresponds to one first electrode 502.

[0128] It should be noted that the data line extends along the second direction Y, which can be as shown in FIG. 2, that is, the data line 9 extends along a straight line in the second direction Y. Alternatively, the data line can extend along a straight line in the second direction Y.

[0129] It should be noted that the array substrate provided by the embodiments of the present disclosure can be applied to a liquid crystal display panel, and the liquid crystal display panel further includes an opposite substrate arranged opposite to the array substrate. The first area corresponds to a display area of the display panel, that is, the first area coincides with the display area. The opposite substrate includes a black matrix, and the black matrix has an opening area, the opening area is in orthographic projection on the substrate and coincides with the sub-pixel area, and the black matrix is in orthographic projection on the substrate and has an overlapping area with the wiring area located in the first area. The sub-pixel area of the array substrate and the opening area of the opposite substrate correspond to a sub-pixel opening area of the display panel. The first area includes: a region where parts of the scan lines and the data lines are located, and a region surrounded by a plurality of scan lines and a plurality of data lines, that is, the scan lines and the data lines extend from the first area to the peripheral area; in the first area, the region where the scan lines and the data lines are located corresponds to the wiring area, the plurality of scan lines and the plurality of data lines divide the first area into a plurality of sub-areas, and the sub-pixel area is located in the sub-area.

[0130] In some embodiments, as shown in FIG. 2, the electrode structure 2 is in orthographic projection on the substrate 1 and overlaps with the plurality of sub-pixel units 5 in orthographic projection on the substrate 1; the first opening 2011 corresponds to the sub-pixel unit 5 one by one, and the first electrode line 202 includes a plurality of first protruding portions 202-2.

[0131] In some embodiments, the first electrode is a pixel electrode, and the second electrode is a common electrode, and the second electrode can be a planar electrode arranged in an entire area; that is, the second electrode is in orthographic projection on the substrate and overlaps with the plurality of sub-pixel areas and the wiring area.

[0132] In some embodiments, the first electrode and the second electrode are both transparent electrodes, so as to avoid affecting the light transmittance of the sub-pixel area; the first electrode and the second electrode, for example, include a transparent conductive material. The transparent conductive material, for example, is indium tin oxide;

[0133] The material of the first electrode line is a metal material, for example, molybdenum-niobium alloy (MoNb), copper (Cu), or molybdenum / niobium / titanium (Mo / Ni / Ti) alloy.

[0134] For example, the sheet resistance of the second electrode is about 40 ohms / square (Ω / □), and the sheet resistance of the first electrode line is about 0.065 Ω / □. The first electrode line is in electrical connection with the second electrode in contact, which is equivalent to the second electrode being in parallel connection with the first electrode line, can greatly reduce the resistance of the second electrode, improve the working stability of the second electrode, and when the array substrate is applied to a display panel, the display effect can be improved.

[0135] In some embodiments, as shown in FIG. 2, the first electrode 502 further includes a plurality of slits 28. The slits 28 extend along the second direction Y, and the projection of the slits 28 on the substrate 1 overlaps with the projection of the first opening 2011 on the substrate 1. Thus, when the array substrate provided by the embodiments of the present disclosure is applied to a liquid crystal display panel, the liquid crystal alignment liquid can better infiltrate the area corresponding to the first opening.

[0136] In some embodiments, as shown in FIG. 2, the pattern of the projection of the slits 28 on the substrate 1 is a polyline, i.e., the slits 28 extend along the second direction Y in a zigzag manner.

[0137] In some embodiments, as shown in FIG. 2, the first electrode line 202 includes a plurality of first sub-electrode lines 2022 extending along the first direction X; the projection of the first sub-electrode lines 202 on the substrate 1 overlaps with the projection of the scan lines 4 on the substrate 1.

[0138] The first sub-electrode line 2022 includes a first portion 202-1 extending along the first direction X, and a plurality of first protruding portions 202-2 located on one side of the first portion 202-1 in the second direction Y, and the projection of the first opening 2011 on the substrate 1 is located on one side of the projection of the first protruding portion 202-2 on the substrate 1 in the second direction Y.

[0139] In some embodiments, the first direction X is the row direction, and the second direction Y is the column direction. The wiring area on one side of a row of sub-pixel areas is referred to as a wiring area row, and the wiring area on one side of a column of sub-pixel areas is referred to as a wiring area column. As shown in FIG. 2, the plurality of first openings 101 corresponding to a row of sub-pixel units 5 and the scan lines 4 electrically connected with the row of sub-pixel units 5 are located on the same side of the wiring area 102 of the same row of sub-pixel areas 101, i.e., in the same wiring area row, and correspondingly, the plurality of first openings 2011 and the first sub-electrode lines 2022 are located in the same wiring area row. Due to the limited space of the wiring area row, the distance between the first opening 2011 and the first sub-electrode line 2022 in the second direction Y is small, and the first protruding portion 202-2 arranged between the first portion 202-1 of the first sub-electrode line 2022 and the first opening 2011 can reduce the risk of disconnection of the first sub-electrode line 2022.

[0140] In specific implementation, as shown in FIG. 2, the first portion 202-1 is a strip-shaped trace extending along the first direction X.

[0141] In some embodiments, as shown in FIG. 2, the first protruding part 202-2 included in the first sub-electrode line 2022 has a flush area with the edge of the first opening 2011 in the projection of the substrate 1. That is, the first sub-electrode line 2022 has a flush area with the edge of the first opening 2011 in the projection of the substrate 1, which can avoid the risk of disconnection of the first sub-electrode line caused by the expansion of the incomplete exposure area.

[0142] In some embodiments, for other patterns of the first sub-electrode line, as shown in FIG. 9 and FIG. 10, the first sub-electrode line 2022 has a flush area with the edge of the first opening 2011 in the projection of the substrate 1.

[0143] In this way, compared with the case where the distance between the edge of the first sub-electrode line in the projection of the substrate and the edge of the first opening in the projection of the substrate is greater than 0, there is no incomplete exposure area between the first opening and the first sub-electrode line, and the risk of disconnection of the first sub-electrode line can also be avoided.

[0144] In some embodiments, as shown in FIG. 9, the first sub-electrode line 2022 on one side of the first opening 2011 includes a strip-shaped part Q1 extending in the first direction X, and the strip-shaped part Q1 has a flush area with the edge of the first opening 2011 in the projection of the substrate 1.

[0145] Alternatively, as shown in FIG. 10, the first sub-electrode line 2022 has a recessed area Q2 recessed away from the side of the first opening 2011 at the edge of the projection of the substrate 1, and the recessed area Q2 has a flush area with the edge of the first opening 2011 in the projection of the substrate 1.

[0146] In some embodiments, as shown in FIG. 9 and FIG. 10, in the flush area, the width of the first sub-electrode line 2022 is greater than or equal to the width of the edge of the first opening 2011 closest to the first sub-electrode line 2022, so that the edge of the first opening 2011 closest to the first sub-electrode line 2022 has a flush area with the edge of the first sub-electrode line 2022 in the projection of the substrate 1. It can be ensured that the first sub-electrode line in the area corresponding to the first opening will not have the risk of disconnection.

[0147] In some embodiments, as shown in FIG. 2 and FIG. 5, in the partial area, the first portion 2021-1 falls within the projection of the scan line 4 on the substrate 1. Specifically, for example, in the partial wiring area 102, the line width of the scan line 4 is greater than the line width of the first portion 202-1; and in the area where the line width of the scan line 4 is greater than the line width of the first portion 202-1, the first portion 2021-1 falls within the projection of the scan line 4 on the substrate 1.

[0148] The array substrate provided by the embodiments of the present disclosure can save wiring space, thereby increasing the size of the sub-pixel area and improving the aperture ratio.

[0149] In some embodiments, as shown in FIG. 5, the projection of the scan line 4 on the substrate 1 towards the edge of the first opening 2011 has a first interval h1 from the projection of the first opening 2011 on the substrate 1, and the projection of the first protruding portion 202-2 on the substrate 1 towards the edge of the first opening 2011 has a second interval from the projection of the first opening 2011 on the substrate 1, and the second interval is smaller than the first interval h1. In FIG. 5, the edge of the first protruding portion 202-2 and the edge of the first opening 2011 have a flush area, i.e., the second interval is 0.

[0150] The array substrate provided by the embodiments of the present disclosure has a second interval smaller than the first interval, i.e., the projection of the first protruding portion on the substrate covers part of the edge of the projection of the scan line on the substrate, thereby ensuring the width of the first protruding portion in the second direction Y and avoiding the risk of incomplete exposure area expansion leading to disconnection of the first sub-electrode line.

[0151] In some embodiments, as shown in FIG. 11, the array substrate further comprises:

[0152] A plurality of spacers 3 are located on the side of the first electrode 502 structure 2 away from the substrate 1; the projection of the spacer 3 on the substrate 1 overlaps with the projection of the scan line 4 on the substrate 1, and the projection of the spacer 3 on the substrate 1 overlaps with the projection of the data line 9 on the substrate 1; the plurality of spacers 3 comprises:

[0153] A plurality of first spacers 301; the projection of the first spacer 301 on the substrate 1 does not overlap with the projection of the first electrode line 202 on the substrate 1, and the first sub-electrode line 2021 is disconnected in the area where the first spacer 301 is arranged; the projection of the first spacer 301 on the substrate 1 overlaps with the projection of the line connecting the disconnected area 45 of the first sub-electrode line 2021 on the substrate 1, and the disconnected area 45 is located between two first protruding portions 202-2.

[0154] It should be noted that when the array substrate includes the spacers and the spacers include the first spacers, the size of the first spacers needs to be monitored and measured. Since the first electrode lines are metal traces and have the light reflection characteristic, the monitoring and measurement of the manufacturing of the spacers is affected, the manufacturing yield of the spacers is affected, and then the manufacturing yield of the display product is affected.

[0155] The array substrate provided by the embodiments of the present disclosure can avoid the light reflection of the first electrode lines affecting the data detection in the manufacturing process of the first spacers, can improve the manufacturing yield of the first spacers, and then improve the manufacturing yield of the array substrate.

[0156] It should be noted that the connection of the first sub-electrode line in the disconnected region refers to the connection in the disconnected region and in the extension direction of the first sub-electrode line.

[0157] In some embodiments, as shown in FIG. 11, in the first direction X, the distance h6 between the orthographic projection of the first spacer 301 on the substrate 1 and the orthographic projection of the disconnected first sub-electrode line 2021 on the substrate 1 is greater than 0.

[0158] The array substrate provided by the embodiments of the present disclosure can avoid the light reflection of the first electrode lines affecting the data detection in the manufacturing process of the first spacers, can improve the manufacturing yield of the first spacers, and then improve the manufacturing yield of the array substrate.

[0159] In some embodiments, as shown in FIG. 11, in the first direction X, the distance between the orthographic projection of the first sub-electrode line 2021 on the substrate 1 and the orthographic projection of the first spacer 301 on the substrate 1 on both sides of the first spacer 301 is substantially equal.

[0160] It should be noted that the distance between the orthographic projection of the first sub-electrode line on the substrate and the orthographic projection of the first spacer on the substrate on both sides of the first spacer substantially equal refers to that, considering the process error, the difference between the distance between the orthographic projection of the first sub-electrode line on the substrate and the orthographic projection of the first spacer on the substrate on both sides of the first spacer is less than the error, and then it can be considered that the distance between the orthographic projection of the first sub-electrode line on the substrate and the orthographic projection of the first spacer on the substrate on both sides of the first spacer is equal.

[0161] In some embodiments, as shown in FIG. 11, the width h2 of the disconnected region 45 in the first direction X is greater than the width h3 of the two first openings 2011 in the first direction X.

[0162] The width h4 of the first protruding portion 202-2 located on one side of the disconnected area 45 in the first direction X is less than the width h8 of the first protruding portion 202-2 in the remaining area in the first direction X.

[0163] The width h4 of the first protruding portion 202-2 located on one side of the disconnected area 45 in the first direction X is less than the width h5 of the first opening 2011 in the first direction X.

[0164] It should be noted that the first protruding portion in the remaining area refers to the first protruding portion without the disconnected area on both sides.

[0165] In a specific implementation, the distance between the orthographic projection of the first spacer on the substrate and the orthographic projection of the disconnected first sub-electrode line on the substrate 1 is related to the position accuracy a1 of the first spacer when the first spacer is made and the spacer line width fluctuation a2, and needs to satisfy: h6≥a1+a2 / 2. The width of the first spacer in the first direction X is h7, the width of the two first openings 2011 in the first direction X is h3, and the width h2 of the disconnected area 45 in the first direction X is h6×2+h7.

[0166] In some embodiments, h2>h3, and the first protruding portion 202-2 located on both sides of the first spacer needs to be disconnected, that is, the width h4 of the first protruding portion 202-2 located on one side of the disconnected area 45 in the first direction X is less than the width h8 of the first protruding portion 202-2 in the remaining area in the first direction X.

[0167] In some embodiments, h2<h3, and the first protruding portion 202-2 located on one side of the disconnected area 45 in the first direction X can only be disconnected, that is, the width h4 of the first protruding portion 202-2 located on one side of the disconnected area 45 in the first direction X is equal to the width h8 of the first protruding portion 202-2 in the remaining area in the first direction X.

[0168] In some embodiments, h2=h3, and the width h8 of the first protruding portion 202-2 in the remaining area in the first direction X is equal to the width h5 of the first opening 2011 in the first direction X, and the width h4 of the first protruding portion 202-2 located on one side of the disconnected area 45 in the first direction X is equal to the width h8 of the first protruding portion 202-2 in the remaining area in the first direction X. Alternatively, h2=h3, and the width h8 of the first protruding portion 202-2 in the remaining area in the first direction X is greater than the width h5 of the first opening 2011 in the first direction X, and the width h4 of the first protruding portion 202-2 located on one side of the disconnected area 45 in the first direction X is less than the width h8 of the first protruding portion 202-2 in the remaining area in the first direction X.

[0169] In a specific implementation, on both sides of the disconnection region, the area between the first opening 2011 and the orthographic projection of the first portion 202-1 on the substrate 1 is covered by the orthographic projection of the first protruding portion 202-2 on the substrate 1. The area between the first opening 2011 and the orthographic projection of the disconnection region 45 on the substrate 1 in the second direction Y does not belong to the area between the first opening 2011 and the orthographic projection of the first portion 202-1 on the substrate 1.

[0170] In some embodiments, as shown in FIG. 2, the first electrode line 202 further includes: a plurality of second sub-electrode lines 2022 extending in the second direction Y; the second sub-electrode line 2022 is consistent with the extension direction of the data line 9;

[0171] The orthographic projection of the second sub-electrode line 2022 on the substrate 1 overlaps the orthographic projection of the data line 9 on the substrate 1.

[0172] The array substrate provided by the embodiments of the present disclosure has the same extension direction of the second sub-electrode line and the data line, the second sub-electrode line and the data line are located in the wiring area, and the orthographic projection of the second sub-electrode line on the substrate overlaps the orthographic projection of the data line on the substrate, which can reduce the total width of the orthographic projection of the second sub-electrode line and the data line on the substrate in the first direction, and further reduce the width of the wiring area in the first direction, thereby improving the sub-pixel aperture ratio.

[0173] It should be noted that if the data line extends in the second direction Y in a bent manner, the second sub-electrode line extends in the second direction Y in a bent manner. If the data line extends in the second direction Y in a straight line, the second sub-electrode line extends in the second direction Y in a straight line.

[0174] In some embodiments, as shown in FIG. 2, in the first direction X, the line width of the data line 9 is greater than or equal to the line width of the second sub-electrode line 2022 in at least part of the area;

[0175] The orthographic projection of the second sub-electrode line 2022 on the substrate 1 falls within the orthographic projection of the data line 9 on the substrate 1.

[0176] The array substrate provided by the embodiments of the present disclosure has the same extension direction of the second sub-electrode line and the data line, and the orthographic projection of the second sub-electrode line on the substrate falls within the orthographic projection of the data line on the substrate, which can further reduce the total width of the orthographic projection of the second sub-electrode line and the data line on the substrate in the first direction, and further reduce the width of the wiring area in the first direction, thereby improving the sub-pixel aperture ratio.

[0177] In some embodiments, as shown in FIG. 2, the number of second sub-electrode lines 2022 is less than the number of data lines 9.

[0178] It should be noted that in the related art, the common electrode wire also includes a longitudinally extending wire, the number of the longitudinally extending wire is the same as the number of the data line, and the orthographic projection of the longitudinally extending wire and the data line substantially coincides. If there is a registration deviation between the longitudinally extending wire and the data line, the size of the sub-pixel region in the first direction will be affected, and then the sub-pixel aperture ratio will be affected.

[0179] The array substrate provided by the embodiments of the present disclosure has a number of second sub-electrode wires less than the number of data lines. Even if there is a registration deviation between the second sub-electrode wire and the data line, the influence on the sub-pixel aperture ratio can be reduced, the display effect can be improved, and the user experience can be improved.

[0180] In some embodiments, as shown in FIG. 2, the number of data lines 9 spaced between the orthographic projections of any two adjacent second sub-electrode wires 2022 on the substrate 1 is the same. For example, the ratio of the number of data lines 9 to the number of second sub-electrode wires 2022 is 3n; wherein n is a positive integer. The data line is a data line located in the first region and electrically connected to the thin film transistor, i.e., the data line is a data line that needs to transmit a data signal. Correspondingly, the orthographic projection of any two adjacent second sub-electrode wires on the substrate is spaced by 3n columns of sub-pixel regions.

[0181] The array substrate provided by the embodiments of the present disclosure has a number of second sub-electrode wires less than the number of data lines. Even if there is a registration deviation between the second sub-electrode wire and the data line, the influence on the sub-pixel aperture ratio can be reduced, the display effect can be improved, and the user experience can be improved.

[0182] In some embodiments, as shown in FIG. 2, n = 1.

[0183] It should be noted that the array substrate includes a plurality of sub-pixels, and each pixel includes 3 sub-pixels. When n = 1, i.e., one pixel corresponds to one second sub-electrode wire, the display uniformity can be ensured while reducing the influence on the sub-pixel aperture ratio.

[0184] In some embodiments, in order to ensure display uniformity, each pixel corresponds to at least one second sub-electrode wire. That is, the ratio of the number of data lines to the number of second sub-electrode wires is m:k, m is the number of sub-pixels included in a pixel, m is a positive integer greater than 1, and k is a positive integer not greater than m; the data line is a data line located in the first region and electrically connected to the thin film transistor, i.e., the data line is a data line that needs to transmit a data signal. In specific implementation, when m = 3, i.e., each pixel includes 3 sub-pixels, then k = 1 or k = 2 or k = 3. When it is necessary to make the number of data lines greater than the number of second sub-electrode wires to reduce the influence on the sub-pixel aperture ratio, then k = 1 or k = 2.

[0185] In some embodiments, as shown in FIG. 11, the plurality of spacers 3 further comprises a plurality of second spacers 302; the thickness of the second spacers 302 is less than the thickness of the first spacers 301.

[0186] The orthographic projection of the second spacers 302 on the substrate 1 overlaps the orthographic projection of the first electrode lines 202 on the substrate 1.

[0187] The orthographic projection of the first sub-electrode lines 2021 on the substrate 1 and the orthographic projection of the second sub-electrode lines 2022 on the substrate 1 both overlap the orthographic projection of the second spacers 302 on the substrate 1.

[0188] It should be noted that the data monitoring of the first spacers is more important in the manufacturing process of the spacers. The array substrate provided by the embodiments of the present disclosure is characterized in that the orthographic projection of the second spacers on the substrate overlaps the orthographic projection of the first electrode lines on the substrate, which ensures the electrical connection performance of the first electrode lines without affecting the data monitoring of the first spacers, thereby avoiding the disconnection of the first electrode lines.

[0189] In some embodiments, as shown in FIG. 11, the width of the second spacers 302 in the first direction X is less than the width of the first spacers 301 in the first direction X, and / or the width of the second spacers 302 in the second direction Y is less than the width of the first spacers 301 in the second direction Y.

[0190] In some embodiments, as shown in FIG. 11, the first electrode lines 202 further comprise: a plurality of second protruding parts 202-3; the second protruding parts 202-3 are electrically connected to the first parts 202-1, and the second protruding parts 202-3 and the first protruding parts 202-2 are located on the same side of the first parts 202-1 in the second direction Y.

[0191] Part of the plurality of data lines 9 overlaps the orthographic projection of the second sub-electrode lines 2022 on the substrate 1, and the rest of the plurality of data lines 9 overlaps the orthographic projection of the second protruding parts 202-3 on the substrate 1.

[0192] In some embodiments, as shown in FIG. 11, the orthographic projection of the second protruding parts 202-3 on the substrate 1 overlaps the orthographic projection of the second spacers 302 on the substrate 1.

[0193] The array substrate provided by the embodiments of the present disclosure is characterized in that the second protruding parts and the second sub-electrode lines are located in different wiring areas of columns, the orthographic projection of the second protruding parts on the substrate overlaps the orthographic projection of the second spacers on the substrate, so that the first electrode lines are arranged below the second spacers, which can improve the height uniformity of the second spacers, and when the array substrate is applied to a display panel, the height difference of the second spacers at different positions can be avoided to affect the performance of the display panel.

[0194] In some embodiments, as shown in FIG. 11, the width of the second protruding part 202-3 in the first direction X is equal to the width of the second sub-electrode line 2022 in the first direction X.

[0195] In some embodiments, as shown in FIG. 11, in the first direction X, the line width of the data line 9 is greater than or equal to the line width of the second protruding part 202-3 in the first direction X at least in part of the region.

[0196] The orthogonal projection of the second protruding part 202-3 on the substrate substrate 1 falls within the orthogonal projection of the data line 9 on the substrate substrate 1.

[0197] The array substrate provided by the embodiments of the present disclosure can further reduce the total width of the second protruding part and the data line in the first direction in the orthogonal projection of the substrate substrate, and further reduce the width of the wiring area in the first direction, and improve the sub-pixel aperture ratio.

[0198] In some embodiments, as shown in FIG. 11, the orthogonal projection of the second protruding part 202-3 on the substrate substrate 1 overlaps with the orthogonal projection of the gate G of the thin film transistor on the substrate substrate 1.

[0199] In some embodiments, as shown in FIG. 11, in the first direction X, the width of the second protruding part 202-3 and the width of the second sub-electrode line 2022 are both less than the width of the second spacer 302.

[0200] In some embodiments, as shown in FIG. 11, the orthogonal projection of the second protruding part 202-3 on the substrate substrate 1 falls within the orthogonal projection of the second spacer 302 on the substrate substrate 1.

[0201] In some embodiments, as shown in FIG. 12, the electrode structure 2 further comprises: a plurality of first strip-shaped parts 203 located in the wiring area 102 and arranged in the same layer as the first electrode line 202;

[0202] In the second direction Y, the orthogonal projection of the first strip-shaped part 203 on the substrate substrate 1 is located on the side of the orthogonal projection of the first opening 2011 on the substrate substrate 1 away from the first sub-electrode line 2021, that is, the orthogonal projection of the first strip-shaped part 203 on the substrate substrate 1 is located between the orthogonal projection of the first opening 2011 on the substrate substrate 1 and the sub-pixel area 101.

[0203] It should be noted that in the related art, the first opening is toward the side of the sub-pixel area, the electrode structure only includes the second electrode without the pattern of the metal line, that is, the first opening is a completely exposed area, the side of the first opening toward the sub-pixel area is an incompletely exposed area, and when the process fluctuates, the first opening may expand toward the side of the sub-pixel area, and even extend to the sub-pixel area, which affects the light efficiency of the display product when the array substrate is applied to the display product.

[0204] The array substrate provided in the embodiments of the present disclosure is provided with the first strip-shaped part corresponding to the first electrode line and the non-exposed area between the first opening and the sub-pixel area. Even if the process fluctuates during the manufacturing of the electrode structure and the exposed area and the incompletely exposed area expand toward the side of the sub-pixel area, the existence of the non-exposed area corresponding to the first strip-shaped part can prevent the first opening from extending to the sub-pixel area and prevent the light efficiency of the display product from being affected.

[0205] In some embodiments, as shown in FIG. 12, in the second direction Y, the orthographic projection of the first strip-shaped part 203 and the orthographic projection of the first protruding part 202-2 on the substrate 1 are located on two sides of the orthographic projection of the first opening 2011 on the substrate 1.

[0206] In some embodiments, as shown in FIG. 12, the minimum distance from the edge of the side of the first strip-shaped part 203 away from the first opening 2011 to the sub-pixel area 101 is greater than or equal to 0.

[0207] FIG. 12 takes the minimum distance from the edge of the side of the first strip-shaped part 203 away from the first opening 2011 to the sub-pixel area 101 as an example.

[0208] In some embodiments, as shown in FIG. 12 and FIG. 13, the edge of the side of the first strip-shaped part 203 toward the first opening 2011 has a flush area with the edge of the orthographic projection of the first opening 2011 on the substrate 1.

[0209] It should be noted that FIG. 13 is a cross-sectional view along KK' in FIG. 12.

[0210] The array substrate provided in the embodiments of the present disclosure has the flush area between the edge of the first strip-shaped part and the edge of the first opening, which is more conducive to preventing the first opening from extending to the sub-pixel area.

[0211] In some embodiments, as shown in FIG. 15, the first strip-shaped part 203 includes a plurality of sub-parts 2031 that are disconnected from each other and arranged along the first direction X.

[0212] The array substrate provided in the embodiments of the present disclosure includes the sub-parts that are disconnected from each other, so that the array substrate provided in the embodiments of the present disclosure can be applied to a liquid crystal display panel, and the liquid crystal alignment liquid can better infiltrate the area corresponding to the first strip-shaped part.

[0213] In some embodiments, as shown in FIG. 16, the slit 28 overlaps the projection of the sub-portion 2031 on the substrate 1 with the projection of the substrate 1. The wettability of the liquid crystal alignment liquid can be further improved.

[0214] In some embodiments, as shown in FIG. 17, the first opening 2011 overlaps the area between the projection of the sub-portion 2031 on the substrate 1 and the projection of the substrate 1.

[0215] It should be noted that the first opening 2011 extends to the area between the projections of the two sub-portions 2031 on the substrate 1, but the second electrode 201 remains under the sub-portion 2031, that is, the projection of the sub-portion 2031 on the substrate 1 does not overlap the projection of the first opening 2011 on the substrate 1.

[0216] In some embodiments, as shown in FIG. 14, the width of at least part of the first strip portion 203 in the first direction X is greater than or equal to the width of the first opening 2011 in the first direction X. At least part of the area, the first opening is provided with a first strip portion on the side facing the sub-pixel area, so as to ensure that the first opening does not extend to the sub-pixel area.

[0217] In some embodiments, as shown in FIG. 14, at least part of the first strip portion 203 is located on one side of the first spacer 301 in the first direction X; the distance h9 between the first strip portion 203 and the first spacer 301 is greater than or equal to a1+a2 / 2, so as to avoid the influence of the first strip portion on the monitoring of the first spacer while avoiding the extension of the first opening to the sub-pixel area.

[0218] In some embodiments, as shown in FIG. 14, the distance h9 between the first strip portion 203 and the first spacer 301 is equal to the distance h6 between the first sub-signal line 2021 and the first spacer 301.

[0219] In specific implementation, it is necessary to satisfy: h9=h6≥a1+a2 / 2. The width of the first spacer in the first direction X is h7, the width of the two first openings 2011 in the first direction X is h3, and the width of the break area 45 in the first direction X is h2=h6×2+h7.

[0220] In some embodiments, h2>h3, the width of the first strip portion located on one side of the first spacer in the first direction X is less than the width of the first strip portion in the remaining area in the first direction X.

[0221] In some embodiments, h2<h3, the width of the first strip portion located on one side of the first spacer in the first direction X can be set to be equal to the width of the first strip portion in the remaining area in the first direction X.

[0222] In some embodiments, h2=h3, the width of the first strip located on one side of the first spacer in the first direction X can be equal to the width of the first strip in the first direction X in the remaining area, or the width of the first strip located on one side of the first spacer in the first direction X can be less than the width of the first strip in the first direction X in the remaining area.

[0223] It should be noted that the remaining area refers to the area where the first strip is located which is not adjacent to the first spacer.

[0224] In some embodiments, as shown in FIGS. 18-20, the electrode structure 2 further comprises: a plurality of second strips 204 located in the wiring area 102 and arranged in the same layer as the first electrode line 202; the second strip 204 is electrically connected with the first strip 203 and the first electrode line 202.

[0225] In some embodiments, as shown in FIGS. 18 and 19, the second strip 204 extends along the second direction Y;

[0226] In the first direction X, the orthographic projection of the second strip 204 on the substrate 1 is located on one side of the orthographic projection of the first opening 2011 on the substrate 1;

[0227] The second strip 204 is electrically connected with the first protruding part 202-2.

[0228] It should be noted that FIG. 18 takes the orthographic projection of the second strip 204 on the substrate 1 located on one side of the orthographic projection of the first opening 2011 on the substrate 1 as an example for illustration, and in FIG. 18, the orthographic projection of the second strip 204 on the substrate 1 is located on the right side of the orthographic projection of the first opening 2011 on the substrate 1, and in specific implementation, the orthographic projection of the second strip 204 on the substrate 1 can also be located on the left side of the orthographic projection of the first opening 2011 on the substrate 1. FIG. 19 takes the orthographic projection of two second strips 204 on the substrate 1 located on both sides of the orthographic projection of the first opening 2011 on the substrate 1 as an example for illustration.

[0229] It should be noted that in FIGS. 18 and 19, the first sub-electrode line break area and the spacer are not shown. In specific implementation, in the first direction, if the second strip extending along the second direction is arranged on both sides of the first spacer, the distance between the second strip and the first spacer needs to be ≥a1+a2 / 2, so as to avoid the influence of the second strip on the monitoring of the first spacer. If the distance between the first opening and the first spacer cannot meet the above requirement for arranging the second strip, no second strip is arranged between the orthographic projection of the first opening and the first spacer on the substrate.

[0230] In a specific implementation, the edge of the second strip-shaped portion can be flush with the edge of the first opening, or the distance between the edge of the second strip-shaped portion and the edge of the first opening in the orthographic projection of the substrate can be greater than 0.

[0231] Alternatively, in some embodiments, as shown in FIG. 20, the second strip-shaped portion 204 extends in the first direction X, and the second strip-shaped portion 204 is located at least on one side of the first strip-shaped portion 203 in the first direction X.

[0232] The at least part of the second strip-shaped portion 204 is also electrically connected with the second sub-electrode line 2022.

[0233] The part of the second strip-shaped portion 204 is electrically connected with the second protruding portion 202-3.

[0234] It should be noted that in FIG. 20, the first sub-electrode line break region and the spacers are not shown. In a specific implementation, in the first direction, if the second strip-shaped portion is arranged on both sides of the first spacer, the distance between the second strip-shaped portion and the first spacer needs to be greater than or equal to a1+a2 / 2, so as to avoid the influence of the second strip-shaped portion on the monitoring of the first spacer. If the distance between the first strip-shaped portion and the first spacer cannot meet the above requirement for arranging the second strip-shaped portion, the second strip-shaped portion is not arranged between the orthographic projection of the first strip-shaped portion and the orthographic projection of the first spacer on the substrate.

[0235] Alternatively, in some embodiments, as shown in FIG. 21, the electrode structure 2 further includes a plurality of second strip-shaped portions 204 arranged in the wiring region 102 and in the same layer as the first electrode line 202.

[0236] The second strip-shaped portion 204 extends in the second direction Y.

[0237] In the first direction X, the orthographic projection of the second strip-shaped portion 204 is located at least on one side of the orthographic projection of the first opening 2011 on the substrate 1.

[0238] One end of the second strip-shaped portion 204 is electrically connected with the first strip-shaped portion, and the second strip-shaped portion 204 is not directly connected with the first protruding portion 202-2.

[0239] It should be noted that the second strip-shaped portion 204 is not directly connected with the first protruding portion 202-2, which means that the second strip-shaped portion 204 and the first protruding portion 202-2 are not integrally connected but are disconnected from each other. However, the two can be electrically connected through the second electrode.

[0240] It should be noted that FIG. 21 takes two second strip-shaped portions 204 as an example, which are located on both sides of the orthographic projection of the first opening 2011 on the substrate 1.

[0241] It should be noted that in FIG. 21, the first sub-electrode line break region and the spacers are not shown. In a specific implementation, in the first direction, if the two sides of the first spacer are provided with the second strip-shaped portion extending in the second direction, the distance between the second strip-shaped portion and the first spacer needs to be ≥a1+a2 / 2, so as to avoid the influence of the second strip-shaped portion on the monitoring of the first spacer. If the distance between the first opening and the first spacer cannot meet the above requirement for the arrangement of the second strip-shaped portion, the second strip-shaped portion is not arranged between the orthographic projection of the first opening and the orthographic projection of the first spacer on the substrate.

[0242] In a specific implementation, the edge of the second strip-shaped portion and the edge of the first opening can have a flush area, or the distance between the edge of the second strip-shaped portion and the edge of the first opening in the orthographic projection on the substrate can be greater than 0.

[0243] In some embodiments, as shown in FIGS. 2-5, the array substrate further comprises:

[0244] a plurality of first vias 8; the first electrode 502 and the thin film transistor 501 are electrically connected through the first via 8; the orthographic projection of the first via 8 on the substrate falls within the orthographic projection of the first opening 2011 on the substrate.

[0245] In some embodiments, as shown in FIGS. 3-4, the first electrode 502 and the drain D comprise a plurality of insulating layers 7;

[0246] The plurality of insulating layers 7 between the first electrode 502 and the drain D comprise a first insulating layer 701 between the electrode structure 2 and the drain D, and a second insulating layer 702 between the electrode structure 2 and the first electrode 502;

[0247] The second insulating layer 702 comprises a plurality of first vias 8;

[0248] The first insulating layer 701 comprises a fifth via 32; the orthographic projection of the fifth via 32 on the substrate falls within the orthographic projection of the first opening 2011 on the substrate, the orthographic projection of the first via 8 on the substrate falls within the orthographic projection of the fifth via 32 on the substrate, and the orthographic projection of the first via 8 on the substrate and the orthographic projection of the fifth via 32 on the substrate both fall within the orthographic projection of the drain D on the substrate;

[0249] Part of the second insulating layer 702 extends to the first opening 2011 and the fifth via 32, so that the first electrode 502 is electrically connected with the drain D through the first via 8 penetrating the second insulating layer 702.

[0250] In some embodiments, as shown in FIG. 2, the thin film transistor 5 comprises an active layer 5011, a gate G, a source S and a drain D; the gate G is electrically connected with the scan line 4, the source S is electrically connected with the data line 9, and the drain D is electrically connected with the first electrode 502.

[0251] In some embodiments, as shown in FIG. 5, the thin film transistor is a bottom gate structure, i.e. the active layer 501 is located on the side of the gate G away from the substrate 1; the source S and the drain D are located on the side of the active layer 501 away from the substrate 1.

[0252] The array substrate further comprises a third insulating layer 30 between the active layer 501 and the gate G, and a buffer layer 31 between the gate G and the substrate 1.

[0253] In some embodiments, the scan line is provided in the same layer as the gate, and the data line is provided in the same layer as the source and the drain; specifically, the scan line is integrally connected with the gate, and the data line is integrally connected with the source.

[0254] It should be noted that, in the present disclosure, "in the same layer" means that the film layers used for manufacturing specific patterns are formed by using the same film forming process, and then the layer structure is formed by using the same mask plate through one patterning process. That is, one patterning process corresponds to one mask. According to different specific patterns, one patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns can be at the same height or have the same thickness, or can be at different heights or have different thicknesses.

[0255] In some embodiments, as shown in FIG. 22, the second electrode (not shown) extends to the peripheral area NA;

[0256] The first electrode line 202 further comprises:

[0257] The first peripheral electrode line 2023 is located in the peripheral area NA.

[0258] The array substrate further comprises:

[0259] The second peripheral electrode line 12 is provided in the same layer as the gate of the thin film transistor 501 in the peripheral area NA; the second peripheral electrode line 12 is electrically connected with the first peripheral electrode line 2023.

[0260] The array substrate provided by the embodiments of the present disclosure further comprises the first peripheral electrode line and the second peripheral electrode line which are electrically connected with the second electrode in the peripheral area, so that the resistance of the second electrode can be further reduced.

[0261] In some embodiments, the first sub-electrode line and the second sub-electrode line both extend to the peripheral area and are connected with the first peripheral electrode line.

[0262] In some embodiments, the first peripheral electrode line, the second peripheral electrode line enclose the first area in the orthographic projection of the substrate.

[0263] In some embodiments, as shown in FIG. 22, in the second direction Y, the width of the orthographic projection of the first peripheral electrode line 2023 on the substrate 1 is less than the width of the orthographic projection of the second peripheral electrode line 12 on the substrate 1.

[0264] In some embodiments, as shown in FIG. 22, FIG. 24, the array substrate further comprises:

[0265] The third peripheral electrode line 33 is disposed in the same layer as the first electrode 502; the first peripheral electrode line 2023 and the second peripheral electrode line 12 are electrically connected through the third peripheral electrode line 33.

[0266] The peripheral area NA includes a first peripheral area NA-1 located on one side of the first area AA in the second direction Y; in the first peripheral area NA-1, the edge of the orthographic projection of the first peripheral electrode line 2023 on the substrate 1 is covered by the orthographic projection of the third peripheral electrode line 33 on the substrate 1.

[0267] In some embodiments, as shown in FIG. 22, FIG. 23, the first electrode structure 2 comprises:

[0268] A plurality of second openings 13 are located in the peripheral area 102; the second openings 13 pass through the second electrode 201 and the first peripheral electrode line 2023;

[0269] A plurality of connection electrodes 14 are disposed in the same layer as the source electrode (not shown) of the thin film transistor in the first peripheral area NA-1;

[0270] A plurality of second vias 15 are located in the first peripheral area NA-1; the connection electrode 14 and the second peripheral electrode line 12 are electrically connected through the second via 15;

[0271] A plurality of third vias 16 are located in the first peripheral area NA-1; the third via 16 falls within the orthographic projection of the first peripheral electrode line 2023 on the substrate 1 in the orthographic projection of the substrate 1, and the first peripheral electrode line 2023 and the third peripheral electrode line 33 are electrically connected through the third via 16;

[0272] A plurality of fourth vias 17 are located in the first peripheral area NA-1; the fourth via 17 falls within the orthographic projection of the second opening 13 on the substrate 1 in the orthographic projection of the substrate 1, and the third peripheral electrode line 33 and the connection electrode 14 are electrically connected through the fourth via 17.

[0273] The array substrate provided by the embodiments of the present disclosure is provided with a connection electrode, the connection electrode is electrically connected with the second peripheral electrode line, the third peripheral electrode line is electrically connected with the connection electrode and the second peripheral electrode line, the electrical connection between the third peripheral electrode line, the first peripheral electrode line, the connection electrode and the second peripheral electrode line is realized, the number of the insulating layers penetrated by the second via hole, the third via hole and the fourth via hole is small, the lap joint disconnection caused by the too deep via hole depth is avoided, the yield of the array substrate can be improved, and the preparation difficulty of the array substrate is reduced. The first peripheral electrode line is electrically connected with the second peripheral electrode line through the third peripheral electrode line and the connection electrode, and the resistance of the electrode line can be reduced.

[0274] It should be noted that FIG. 23 is a sectional view of MM' in FIG. 22.

[0275] In some embodiments, as shown in FIG. 23, the third insulating layer 30 includes the second via hole 15, that is, the second via hole 15 penetrates the third insulating layer 30; the second insulating layer 702 includes the third via hole 16, that is, the third via hole 16 penetrates the second insulating layer 702; the first insulating layer 701 further includes the sixth via hole 34, the orthographic projection of the sixth via hole 34 on the substrate substrate 1 falls within the orthographic projection of the second opening 13 on the substrate substrate 1, and the orthographic projection of the fourth via hole 17 on the substrate substrate 1 falls within the orthographic projection of the sixth via hole 34 on the substrate substrate 1; the fourth via hole 17 penetrates the second insulating layer 702.

[0276] In some embodiments, as shown in FIG. 23, the orthographic projection of the second via hole 15 on the substrate substrate 1 does not overlap with the orthographic projection of the third via hole 16 on the substrate substrate 1 and the orthographic projection of the fourth via hole 17 on the substrate substrate 1.

[0277] In some embodiments, as shown in FIG. 23, the distance between the edge of the orthographic projection of the third peripheral electrode line 2023 on the substrate substrate 1 toward the side of the second opening 13 and the edge of the orthographic projection of the second opening 13 on the substrate substrate 1 is greater than 0.

[0278] In some embodiments, the first peripheral area includes a fan-out area.

[0279] The orthographic projection of the connection electrode, the second opening, the second via hole, the third via hole and the fourth via hole on the substrate substrate 1 falls within the area between the first area and the fan-out area.

[0280] In some embodiments, the orthographic projection of the first peripheral electrode line, the second peripheral electrode line and the third peripheral electrode line on the substrate substrate surrounds the first area.

[0281] In some embodiments, the pattern of the second peripheral electrode line 12 and the conductive layer where the second peripheral electrode line 12 is located is as shown in FIG. 25, and the second peripheral electrode line 12 extends to the fan-out area NA-101.

[0282] Specifically, the fan-out area includes a first binding electrode electrically connected with the second peripheral electrode line, and the first binding electrode can be used for binding with the driving element, so that the driving element provides a common voltage signal to the second peripheral electrode line and the first electrode structure through the first binding electrode.

[0283] It should be noted that FIG. 2 takes the first electrode line 202 including the first sub-electrode line 2021 and the second sub-electrode line 2022 as an example for illustration, and the first sub-electrode line 2021 includes the first protruding part 202-2. Alternatively, in some embodiments, the first electrode line can only include the second sub-electrode line extending along the second direction Y.

[0284] In some embodiments, as shown in FIG. 26, the first electrode line 202 includes a plurality of second sub-electrode lines 2022 extending along the second direction Y.

[0285] The second sub-electrode line 2022 includes the first part 202-1 and a plurality of first protruding parts 202-2, and the first via 2011 is located on one side of the first protruding part 202-2 in the orthographic projection of the substrate substrate 1 in the first direction X.

[0286] In some embodiments, as shown in FIG. 26, in the first direction X, both sides of the first part 202-1 are adjacent to the first protruding part 202-2.

[0287] Based on the same inventive concept, the embodiments of the present disclosure also provide a preparation method of an array substrate, as shown in FIG. 27, comprising:

[0288] S101, providing a substrate substrate; the substrate substrate includes a first area and a peripheral area surrounding the first area;

[0289] S102, forming a plurality of thin film transistors on one side of the substrate substrate;

[0290] S103, sequentially forming a second electrode layer and a first electrode line layer on the side of the thin film transistor away from the substrate substrate;

[0291] S104, performing a patterning process on the second electrode layer and the first electrode line layer to form a pattern of an electrode structure; the electrode structure includes a pattern of a second electrode formed by performing a patterning process on the second electrode layer, and a pattern of a first electrode line formed by performing a patterning process on the first electrode line layer; the pattern of the second electrode includes a first opening; the pattern of the first electrode line includes a first part and a first protruding part adjacent to the first part; the first protruding part is located between the first opening in the orthographic projection of the substrate substrate and the first part in the orthographic projection of the substrate substrate.

[0292] S105, forming a plurality of first electrode lines on a side of the first electrode lines away from the substrate substrate; the thin film transistor is electrically connected with the first electrode line at the first opening.

[0293] The preparation method of the array substrate provided by the embodiments of the present disclosure forms a first electrode line layer on a side of the second electrode layer away from the substrate substrate, and then performs a patterning process on the second electrode layer and the first electrode line layer to form an electrode structure. One mask can be used to form the pattern of the first electrode line and the pattern of the second electrode by a half-tone mask process, which can save one mask, save the process flow, and save the cost. The first electrode line is in contact with the second electrode for electrical connection, which can reduce the resistance of the second electrode and improve the working stability of the electrode structure. Moreover, the first electrode line includes a first protruding portion between the first portion and the first opening. Even if the actual exposure area is larger than the designed exposure area in the direction of the first electrode line in the region corresponding to the first opening during the manufacturing process of the electrode structure, the actual line width of the first protruding portion is smaller than the designed line width, which will not affect the line width of the first portion corresponding to the first protruding portion, avoid the risk of disconnection of the first portion, improve the manufacturing yield of the first electrode line, and further improve the yield of the array substrate and save the cost.

[0294] In some embodiments, the thin film transistor is formed, specifically including:

[0295] forming a pattern of a gate of the thin film transistor;

[0296] forming a pattern of a source and a drain of the thin film transistor;

[0297] forming a first insulating layer on a side of the source and the drain away from the substrate substrate, and performing a patterning process on the first insulating layer to form a plurality of fifth vias; the fifth via falls within the orthographic projection of the first opening on the substrate substrate;

[0298] After forming the electrode structure, the method further includes

[0299] forming a second insulating layer; the second insulating layer covers the first opening and the fifth via;

[0300] performing a patterning process on the second insulating layer to form a pattern of a plurality of first vias; the first via falls within the orthographic projection of the first opening on the substrate substrate, and the first via falls within the orthographic projection of the fifth via on the substrate substrate; the second electrode is electrically connected with the drain through the first via.

[0301] In some embodiments, before forming the gate, the method further includes:

[0302] forming a buffer layer;

[0303] forming the gate simultaneously includes:

[0304] forming a pattern of scan lines;

[0305] after forming the gate electrode, and before forming the source electrode and the drain electrode, further comprising:

[0306] forming a pattern of a third insulating layer and a pattern of an active layer in sequence;

[0307] simultaneously with forming the source electrode and the drain electrode, further comprising:

[0308] forming a pattern of data lines.

[0309] In some embodiments, the first electrode line further comprises: a first peripheral electrode line located in the peripheral region;

[0310] simultaneously with forming the pattern of the gate electrode of the thin film transistor, further comprising:

[0311] forming a pattern of a second peripheral electrode line;

[0312] after forming the pattern of the gate electrode of the thin film transistor, and before forming the pattern of the source electrode and the drain electrode of the thin film transistor, further comprising:

[0313] forming a third insulating layer, and performing a patterning process on the third insulating layer to form a plurality of second vias penetrating through the third insulating layer;

[0314] simultaneously with forming the pattern of the source electrode and the drain electrode of the thin film transistor, further comprising:

[0315] forming a pattern of a plurality of connection electrodes; the connection electrodes are electrically connected to the second peripheral electrode line through the second vias;

[0316] after forming the first insulating layer, further comprising:

[0317] performing a patterning process on the first insulating layer to form a plurality of sixth vias penetrating through the first insulating layer;

[0318] simultaneously with forming the first electrode structure, further comprising:

[0319] forming a second opening penetrating through the first peripheral electrode line and extending to the second electrode in the peripheral region; wherein the sixth via falls within the projection of the second opening on the substrate in the projection of the substrate, and the second insulating layer covers the second opening and the sixth via;

[0320] after forming the second insulating layer, further comprising:

[0321] performing a patterning process on the second insulating layer to form a plurality of third vias and a plurality of fourth vias; the third vias fall within the projection of the first peripheral electrode line on the substrate in the projection of the substrate, and the fourth vias fall within the projection of the second opening and the sixth via on the substrate in the projection of the substrate;

[0322] forming the pattern of the first electrode simultaneously further comprises:

[0323] forming a pattern of a third peripheral electrode line; the third peripheral electrode line is electrically connected to the first peripheral electrode line through a third via, and the third peripheral electrode line is electrically connected to the connecting electrode through a fourth via.

[0324] In some embodiments, the patterning process on the second electrode layer and the first electrode line layer forms a pattern of an electrode structure, specifically comprising:

[0325] S1031, coating a photoresist layer on a side of the first electrode line layer away from the substrate;

[0326] S1032, exposing the photoresist layer by a half-tone mask process, removing the photoresist layer in the first removal area, and thinning the photoresist layer in the second removal area;

[0327] S1033, removing the first electrode line layer in the first removal area by an etching process;

[0328] S1034, removing the photoresist layer in the second removal area;

[0329] S1035, removing the second electrode layer in the first removal area by an etching process to form a pattern of the second electrode;

[0330] S1036, removing the first electrode line layer in the second removal area by an etching process to form a pattern of the first electrode line;

[0331] S1037, removing the photoresist layer on the side of the pattern of the first electrode line away from the substrate.

[0332] In specific implementation, the photoresist layer in the second removal area is removed by an Ashing process. The first removal area corresponds to the area where both the second electrode layer and the first electrode line layer need to be removed, and the second removal area corresponds to the area outside the first removal area where only the first electrode line layer needs to be removed. The first removal area includes, for example, the areas corresponding to the first opening and the second opening. If the second electrode layer in the first removal area is removed by an etching process first, and then the photoresist in the second removal area is removed by an Ashing process, the sidewall of the second insulating layer exposed in the first removal area will be etched, and the second electrode will be in a suspended state. The preparation method of the array substrate provided in the embodiments of the present disclosure removes the photoresist layer in the second removal area first, and then removes the second electrode layer in the first removal area after removing the first electrode line in the first removal area, so that the second insulating layer under the second electrode will not be etched.

[0333] In some embodiments, the patterning process on the first electrode line layer to form the pattern of the first electrode line further comprises: forming a pattern of the first strip part.

[0334] In some embodiments, the patterning process on the first electrode line layer forms a pattern of the first electrode line, and simultaneously includes forming a pattern of the second strip part.

[0335] In some embodiments, after forming the pattern of the first electrode, further includes:

[0336] forming a pattern of the spacer.

[0337] Based on the same inventive concept, the embodiments of the present disclosure further provide a display panel, as shown in FIG. 28, which includes:

[0338] The array substrate 38 provided by the embodiments of the present disclosure includes:

[0339] The counter substrate 39 is arranged opposite to the array substrate 38.

[0340] The liquid crystal layer 40 is located between the array substrate 38 and the counter substrate 39.

[0341] The display panel provided by the embodiments of the present disclosure includes the above-mentioned array substrate provided by the present disclosure, and the first electrode line and the second electrode are in contact and electrically connected, which can reduce the resistance of the second electrode and improve the working stability of the electrode structure. Moreover, the first electrode line includes the first protruding part located between the first part and the first opening. Even if in the process of manufacturing the electrode structure, the actual exposure area in the region corresponding to the first opening is larger than the designed exposure area in the direction of the first electrode line, which causes the actual line width of the first protruding part to be smaller than the designed line width, it will not affect the line width of the first part corresponding to the first protruding part, avoiding the risk of disconnection of the first part only, improving the manufacturing yield of the first electrode line, and further improving the yield of the array substrate and saving costs.

[0342] In some embodiments, the array substrate includes the first strip part.

[0343] The counter substrate includes a black matrix, and the black matrix includes a plurality of opening regions.

[0344] The first strip part falls within the orthographic projection of the black matrix on the substrate.

[0345] In some embodiments, the counter substrate also includes a substrate. For the convenience of distinction, the substrate included in the array substrate is referred to as the first substrate, and the substrate included in the counter substrate is referred to as the second substrate. The black matrix is located on the side of the second substrate facing the liquid crystal layer, and the counter substrate further includes a color resist on the side of the second substrate facing the liquid crystal layer. The color resist is located in the opening region, and the spacer is located on the side of the black matrix facing the liquid crystal layer. In the display region, the orthographic projection of the black matrix on the substrate coincides with the wiring region, and the orthographic projection of the opening region on the substrate coincides with the sub-pixel region.

[0346] In a specific implementation, the color resist is projected onto the sub-pixel region. The color resist includes a red color resist corresponding to the red sub-pixel region, a blue color resist corresponding to the blue sub-pixel region, and a green color resist corresponding to the green sub-pixel region.

[0347] In some embodiments, the minimum distance from the edge of the first opening side of the first strip to the opening region is greater than or equal to 0.

[0348] Based on the same inventive concept, the display device provided by the embodiments of the present disclosure also includes a display panel 41 provided by the embodiments of the present disclosure, as shown in FIG. 29.

[0349] In some embodiments, in the display device provided by the embodiments of the present disclosure, as shown in FIG. 29, a backlight module 42 can also be arranged on the light entering side of the array substrate 38. The backlight module can be a direct type backlight module or a side type backlight module.

[0350] In a specific implementation, the side type backlight module can include a lamp strip, a reflection sheet, a light guide plate, a diffusion sheet, a prism group, etc., and the lamp strip is located on one side of the light guide plate in the thickness direction. The direct type backlight module can include a matrix light source, a reflection sheet, a diffusion plate, and a brightness enhancement film, etc., which are arranged on the light emitting side of the matrix light source, and the reflection sheet includes an opening corresponding to the position of each lamp bead in the matrix light source. The lamp bead in the lamp strip and the lamp bead in the matrix light source can be a light emitting diode (LED), such as a micro light emitting diode (Mini LED, Micro LED, etc.). The micro light emitting diode with a sub-millimeter level or even a micron level is the same as the organic light emitting diode (OLED) and belongs to a self-luminous device. Like the organic light emitting diode, it has a series of advantages such as high brightness, ultra-low delay, and ultra-large viewing angle. Moreover, since the inorganic light emitting diode emits light based on a metal semiconductor with more stable properties and lower resistance, it has the advantages of lower power consumption, longer service life, and better resistance to high and low temperatures compared with the organic light emitting diode which emits light based on organic matter. When the micro light emitting diode is used as a backlight source, it can achieve more precise dynamic backlight effect, effectively improve the screen brightness and contrast, and solve the glare phenomenon caused by the traditional dynamic backlight between the light and dark areas of the screen, thereby optimizing the visual experience.

[0351] The display device provided by the embodiments of the present disclosure is any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by those skilled in the art, and are not described here to avoid repetition. The implementation of the display device can refer to the embodiments of the display panel and the array substrate described above, and the repeated parts are not described here again.

[0352] In summary, the array substrate, the display panel and the display device provided by the embodiments of the present disclosure have the following advantages. The first electrode line is in contact with the second electrode and is electrically connected to the second electrode, so that the resistance of the second electrode can be reduced and the working stability of the electrode structure can be improved. In addition, the first electrode line includes the first protruding portion between the first portion and the first opening. Even if, during the manufacturing process of the electrode structure, the actual exposure area in the region corresponding to the first opening is larger than the designed exposure area in the direction of the first electrode line, which causes the actual line width of the first protruding portion to be smaller than the designed line width, the line width of the first portion corresponding to the first protruding portion will not be affected, the risk of disconnection caused by the first portion alone can be avoided, the manufacturing yield of the first electrode line can be improved, and the yield of the array substrate can be improved, thereby saving costs.

[0353] Although preferred embodiments of the present application have been described, those skilled in the art who understand the basic inventive concept can make additional changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0354] Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, The array substrate includes: The substrate includes a first region and a peripheral region surrounding the first region; Multiple sub-pixel units are arranged in an array in the first region along a first direction and a second direction; the first direction and the second direction intersect; each of the multiple sub-pixel units includes: a thin-film transistor, and a first electrode electrically connected to the thin-film transistor; the first electrode is located on the side of the thin-film transistor away from the substrate. An electrode structure is located between the thin-film transistor and the first electrode; the electrode structure includes: a second electrode, and a first electrode line electrically connected to the second electrode on the side of the second electrode facing away from the substrate; the second electrode includes: a first opening; the first electrode line includes: a first portion, and a first protrusion adjacent to the first portion; the orthographic projection of the first protrusion on the substrate is located between the orthographic projection of the first opening on the substrate and the orthographic projection of the first portion on the substrate.

2. The array substrate according to claim 1, wherein, The orthographic projection of the electrode structure onto the substrate overlaps with the orthographic projection of the plurality of sub-pixel units onto the substrate; the first opening corresponds one-to-one with the sub-pixel unit, and the first electrode line includes a plurality of first protrusions; The first protrusion is located on one side of the first portion in the second direction; in the first direction, at least a portion of the width of the first protrusion is greater than or equal to the width of the first opening.

3. The array substrate according to claim 2, wherein, In the first direction, the width of the first protrusion is greater than the width of the first opening; In the first direction, the portion of the first protrusion that extends beyond the first opening is located on both sides of the first opening.

4. The array substrate according to any one of claims 1 to 3, wherein, The first protrusion has a flush region with the edge of the first opening on the side of the substrate from which the orthographic projection of the first protrusion is directed.

5. The array substrate according to any one of claims 1 to 4, wherein, The first electrode line includes: a plurality of first sub-electrode lines extending along the first direction; The first sub-electrode line includes a first portion extending along the first direction and a plurality of first protrusions located on one side of the first portion in the second direction, wherein the first opening is located on the side of the first protrusions in the second direction where the orthographic projection of the substrate is on the same side as the orthographic projection of the substrate.

6. The array substrate according to claim 5, wherein, The array substrate further includes: Multiple scan lines are located between the substrate and the electrode structure; the multiple scan lines extend along the first direction; The first sub-electrode line has an overlapping region in the orthographic projection on the substrate and the scan line has an overlapping region in the orthographic projection on the substrate. In part of the overlapping region, the orthographic projection of the first part on the substrate falls within the orthographic projection of the scan line on the substrate. The scanning line has a first gap between the edge of the orthographic projection of the substrate toward the first opening and the first opening in the orthographic projection of the substrate, and the first protrusion has a second gap between the edge of the orthographic projection of the substrate toward the first opening and the first opening in the orthographic projection of the substrate, the second gap being smaller than the first gap.

7. The array substrate according to claim 5 or 6, wherein, The array substrate further includes: Multiple spacers are located on the side of the first electrode structure facing away from the substrate; the multiple spacers include multiple first spacers; the orthographic projection of the first spacer on the substrate does not overlap with the orthographic projection of the first electrode line on the substrate, and the first sub-electrode line is disconnected in the area where the first spacer is located; the orthographic projection of the first spacer on the substrate overlaps with the orthographic projection of the line connecting the first sub-electrode line in the disconnected area on the substrate, and the disconnected area is located between the two first protrusions.

8. The array substrate according to claim 7, wherein, The width of the disconnected area in the first direction is greater than the width of the two first openings in the first direction; The width of the first protrusion located on one side of the disconnected area in the first direction is smaller than the width of the first protrusion in the first direction in the remaining areas.

9. The array substrate according to any one of claims 5 to 8, wherein, The electrode structure further includes: a plurality of first strip portions disposed in the same layer as the first electrode line; in the second direction, the orthographic projection of the first strip portion on the substrate is located on the side of the orthographic projection of the first opening on the substrate that is away from the first sub-electrode line.

10. The array substrate according to claim 9, wherein, The edge of the first strip portion facing the first opening has a flush area with the edge of the first opening projected onto the substrate.

11. The array substrate according to any one of claims 9 to 10, wherein, The first strip portion includes a plurality of mutually disconnected sub-parts arranged along the first direction.

12. The array substrate according to claim 11, wherein, The first electrode includes multiple slits; The orthographic projection of the slit onto the substrate overlaps with the orthographic projection of the sub-part onto the substrate.

13. The array substrate according to claim 11 or 12, wherein, The area between the first opening and the orthographic projection of the sub-part on the substrate overlaps.

14. The array substrate according to any one of claims 9 to 13, wherein, At least a portion of the first strip has a width in the first direction that is greater than or equal to the width of the first opening in the first direction.

15. The array substrate according to any one of claims 9 to 14, wherein, The electrode structure further includes: a plurality of second strip portions located in the wiring area and disposed on the same layer as the first electrode line; the second strip portions are electrically connected to the first strip portions and the first electrode line.

16. The array substrate according to claim 15, wherein, The second strip extends along the second direction; In the first direction, the orthographic projection of the second strip portion onto the substrate is at least located on one side of the orthographic projection of the first opening onto the substrate. The second strip portion is electrically connected to the first protrusion portion.

17. The array substrate according to claim 15, wherein, The second strip extends along the first direction, and the second strip is located at least on one side of the first strip in the first direction; The first electrode line further includes: a plurality of second sub-electrode lines extending along the second direction; At least a portion of the second strip is also electrically connected to the second sub-electrode line.

18. The array substrate according to claim 17, wherein, The array substrate further includes: Multiple data lines are located between the substrate and the electrode structure; the number of the second sub-electrode lines is less than the number of data lines. The first sub-electrode line further includes: a plurality of second protrusions located on one side of the first portion in the second direction; A portion of the data lines have their orthographic projections on the substrate overlapping with the orthographic projections of the second sub-electrode line on the substrate; the remaining data lines have their orthographic projections on the substrate overlapping with the orthographic projections of the second protrusion on the substrate. Part of the second strip portion is electrically connected to the second protrusion portion.

19. The array substrate according to any one of claims 9 to 14, wherein, The electrode structure further includes: a plurality of second strip-shaped portions located in the wiring area and disposed in the same layer as the first electrode line; The second strip extends along the second direction; In the first direction, the orthographic projection of the second strip portion onto the substrate is at least located on one side of the orthographic projection of the first opening onto the substrate. One end of the second strip is electrically connected to the first strip, and the second strip is not directly connected to the first protrusion.

20. The array substrate according to any one of claims 1 to 19, wherein, The array substrate further includes: Multiple first vias; the first electrode is electrically connected to the thin-film transistor through the first vias; the orthographic projection of the first via on the substrate falls within the orthographic projection of the first opening on the substrate.

21. The array substrate according to any one of claims 1 to 20, wherein, The second electrode extends into the peripheral region; The first electrode wire further includes: The first peripheral electrode line is located in the peripheral region; The array substrate further includes: The second peripheral electrode line is disposed on the same layer as the gate of the thin-film transistor in the peripheral region; the second peripheral electrode line is electrically connected to the first peripheral electrode line. The third peripheral electrode line is disposed in the same layer as the first electrode; the first peripheral electrode line and the second peripheral electrode line are electrically connected through the third peripheral electrode line. The peripheral region includes a first peripheral region located on one side of the first region in the second direction; in the first peripheral region, the edge of the orthographic projection of the first peripheral electrode line onto the substrate is covered by the orthographic projection of the third peripheral electrode line onto the substrate.

22. The array substrate according to claim 21, wherein, The electrode structure further includes: Multiple second openings are located in the fan-out region; the second openings penetrate the second electrode; the edge of the orthographic projection of the substrate is located between the orthographic projection of the second opening and the first region. The array substrate further includes: Multiple connection electrodes are disposed in the same layer as the source electrode of the thin-film transistor in the first peripheral region; Multiple second vias are located in the first peripheral area; the connecting electrode is electrically connected to the second peripheral electrode line through the second vias. Multiple third vias are located in the first peripheral region; the orthographic projection of the third vias onto the substrate falls within the orthographic projection of the first peripheral electrode lines onto the substrate, and the first peripheral electrode lines and the third peripheral electrode lines are electrically connected through the third vias. Multiple fourth vias are located in the first peripheral region; the orthographic projection of the fourth via on the substrate falls within the orthographic projection of the second opening on the substrate, and the third peripheral electrode line is electrically connected to the connecting electrode through the fourth vias.

23. A display panel, wherein, The display panel includes: The array substrate according to any one of claims 1 to 22; An opposing substrate is disposed opposite to the array substrate; A liquid crystal layer is located between the array substrate and the opposing substrate; The array substrate includes a first strip-shaped portion; The opposing substrate includes a black matrix; the black matrix includes multiple opening regions; The orthographic projection of the first stripe onto the substrate falls within the orthographic projection of the black matrix onto the substrate.

24. A display device, wherein, The display device includes: the display panel according to claim 23.

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