Array substrate, preparation method thereof and display device

Abstract

The invention provides an array substrate, a preparation method thereof and a display device. The array substrate comprises a substrate (12), at least one first transistor arranged on the substrate (12), at least one data line (DL) and at least one pixel electrode (10), the at least one first transistor comprises a first active layer (15) and a first gate (17); the first grid electrode (17) is located on the side, away from the substrate (12), of the first active layer (15), and the orthographic projection of the first grid electrode (17) and the orthographic projection of the first active layer (15) on the substrate (12) are at least partially overlapped; the first active layer (15) is electrically connected with the data line (DL) and the pixel electrode (10) respectively; the data line (DL) is positioned on one side, close to the substrate (12), of the first active layer (15); the pixel electrode (10) is located on the side, away from the substrate (12), of the first grid electrode (17).

Description

Array substrate, manufacturing method thereof, and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display device. Background Art

[0002] Liquid Crystal Display (LCD) is a common type of display. LCDs use two sheets of polarized material with a liquid crystal solution between them. Passing an electric current through the liquid causes the crystals to rearrange, preventing light from passing through them. Thus, each crystal acts like a Venetian blind, allowing light to pass through but also blocking it. Currently, LCDs are being developed to be lightweight, thin, short, and compact.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display device.

[0006] In one aspect, an embodiment of the present disclosure provides an array substrate, comprising:

[0007] a substrate, at least one first transistor, at least one data line, and at least one pixel electrode disposed on the substrate;

[0008] The at least one first transistor includes a first active layer and a first gate; the first gate is located on a side of the first active layer away from the substrate, and the first gate and the first active layer at least partially overlap on the orthographic projection of the substrate; the first active layer is electrically connected to a data line and a pixel electrode, respectively; the data line is located on a side of the first active layer close to the substrate; and the pixel electrode is located on a side of the first gate away from the substrate.

[0009] In an exemplary embodiment, the array substrate includes a first conductive layer, a semiconductor layer, and a second conductive layer sequentially arranged in a direction away from the substrate;

[0010] The first conductive layer includes the data line and the light-shielding block, the orthographic projection of the light-shielding block on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate, the semiconductor layer includes the first active layer, the second conductive layer includes the first gate and the first connecting electrode, and the first active layer is electrically connected to the data line through the first connecting electrode.

[0011] In an exemplary embodiment, the array substrate further includes at least one storage capacitor; the at least one storage capacitor includes: a first electrode and a second electrode; the second electrode is electrically connected to the pixel electrode, the first electrode is located on a side of the second electrode close to the substrate, and the first electrode and the second electrode at least partially overlap in their orthographic projections on the substrate.

[0012] In an exemplary embodiment, the second electrode plate and the pixel electrode are an integrated structure.

[0013] In an exemplary embodiment, the array substrate further comprises: a plurality of insulating layers located on a side of the first gate away from the substrate; the plurality of insulating layers are provided with at least a first through hole and a second through hole;

[0014] The pixel electrode is electrically connected to the first active layer through the first through hole, and at least a portion of the second electrode plate is located in the second through hole;

[0015] The plurality of insulating layers include a first passivation layer, an organic insulating layer, and a second passivation layer that are sequentially arranged in a direction away from the substrate.

[0016] In an exemplary embodiment, the array substrate further includes a first passivation layer and a second passivation layer located on a side of the first gate away from the substrate, and the first passivation layer is closer to the substrate than the second passivation layer;

[0017] The second electrode is located on a surface of the second passivation layer that is away from the first passivation layer.

[0018] In an exemplary embodiment, the first electrode plate and the first gate are in the same layer structure.

[0019] In an exemplary embodiment, the second electrode plate and the first gate are in the same layer structure.

[0020] In an exemplary embodiment, the array substrate further comprises: a plurality of insulating layers located on a side of the first gate away from the substrate; the plurality of insulating layers are provided with at least a first through hole and a second through hole;

[0021] The pixel electrode is electrically connected to the first active layer through the first through hole, and the pixel electrode is electrically connected to the second electrode plate through the second through hole;

[0022] The plurality of insulating layers include: a first passivation layer, an organic insulating layer, and a second passivation layer sequentially disposed in a direction away from the substrate; or, a first passivation layer and a second passivation layer sequentially disposed in a direction away from the substrate.

[0023] In an exemplary embodiment, the first electrode plate and the data line are in the same layer structure.

[0024] In an exemplary embodiment, the array substrate further includes: at least one light shielding block, the orthographic projection of the light shielding block on the substrate partially overlaps with the orthographic projection of the first active layer on the substrate; the at least one light shielding block and the data line are in the same layer structure.

[0025] In an exemplary embodiment, the first electrode plate and the light shielding block are an integrated structure.

[0026] In an exemplary embodiment, the array substrate further includes: a common electrode; the common electrode is located on a side of the pixel electrode close to the substrate; the common electrode is a planar electrode, and the pixel electrode has a plurality of slits.

[0027] In an exemplary embodiment, the array substrate further comprises: a common electrode; the common electrode is located on a side of the pixel electrode away from the substrate, the pixel electrode is electrically connected to the first active layer via a third connecting electrode, and the third connecting electrode and the common electrode are in the same layer structure;

[0028] The pixel electrode is a planar electrode, and the common electrode has a plurality of slits.

[0029] In an exemplary embodiment, the first active layer includes a channel region, a first region and a second region located on opposite sides of the channel region; the data line is electrically connected to the first region, and the pixel electrode is electrically connected to the second region.

[0030] In another aspect, an embodiment of the present disclosure provides a display device comprising the array substrate, an opposing substrate, and a liquid crystal layer according to any of the above embodiments; the array substrate and the opposing substrate are disposed opposite each other, and the liquid crystal layer is located between the array substrate and the opposing substrate.

[0031] In an exemplary embodiment, the display device further includes a common electrode; the common electrode is located on a side of the opposing substrate close to the liquid crystal layer; the pixel electrode is provided with at least one first slit, and the common electrode is provided with at least one second slit, and the orthographic projections of the first slit and the second slit on the substrate do not overlap.

[0032] In another aspect, an embodiment of the present disclosure provides a method for preparing an array substrate. The method comprises:

[0033] forming a data line on one side of the substrate;

[0034] forming a first transistor on a side of the data line away from the substrate, the first transistor comprising a first active layer and a first gate, wherein the first gate and the first active layer at least partially overlap with each other in an orthographic projection on the substrate, and the data line is electrically connected to the first active layer; the first gate is located on a side of the first active layer away from the substrate;

[0035] A pixel electrode is formed on a side of the first active layer away from the substrate, and the pixel electrode is electrically connected to the first active layer.

[0036] In an exemplary embodiment, the manufacturing method further includes forming a storage capacitor after forming the data line; the storage capacitor includes:

[0037] A first electrode plate is located on one side of the substrate; and

[0038] The second electrode plate is located on a side of the first electrode plate away from the substrate, and is disposed opposite the first electrode plate; the second electrode plate is electrically connected to the pixel electrode. In the disclosed embodiment, by arranging the data line on a side of the first transistor closer to the substrate, the capacitance between the data line and the pixel electrode can be reduced, thereby reducing power consumption of the data line and improving the performance of the array substrate.

[0039] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0040] Summary of the Figures

[0041] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0042] FIG1 is a schematic front view of an array substrate according to an embodiment of the present disclosure;

[0043] FIG2 is a first cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0044] FIG3 is a second cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0045] FIG4 is a third cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0046] FIG5 is a fourth cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0047] FIG6 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure;

[0048] FIG7 is a schematic front view of an array substrate according to another embodiment of the present disclosure;

[0049] FIG8 is a first cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0050] FIG9 is a second cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0051] FIG10 is a third cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0052] FIG11 is a fourth cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0053] FIG12 is a fifth cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0054] FIG13 is a sixth cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0055] FIG14 is a seventh cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0056] FIG15 is a schematic cross-sectional view eight of an array substrate according to another embodiment of the present disclosure;

[0057] FIG16 is a ninth cross-sectional view of an array substrate according to another embodiment of the present disclosure;

[0058] FIG17 is a cross-sectional schematic diagram ten of an array substrate according to another embodiment of the present disclosure;

[0059] FIG18 is a schematic cross-sectional view eleven of an array substrate according to another embodiment of the present disclosure;

[0060] FIG19 is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure;

[0061] FIG20 is a first cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0062] FIG21 is a second cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0063] FIG22 is a third cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0064] FIG23 is a fourth cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0065] FIG24 is a fifth cross-sectional view of an array substrate according to another embodiment of the present disclosure;

[0066] FIG25 is a sixth cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0067] FIG26 is a seventh cross-sectional view of an array substrate according to another embodiment of the present disclosure;

[0068] FIG27 is a schematic cross-sectional view eight of an array substrate according to another embodiment of the present disclosure;

[0069] FIG28 is a ninth cross-sectional view of an array substrate according to another embodiment of the present disclosure;

[0070] FIG29 is a cross-sectional schematic diagram ten of an array substrate according to yet another embodiment of the present disclosure;

[0071] FIG30 is a schematic cross-sectional view eleven of an array substrate according to another embodiment of the present disclosure;

[0072] FIG31 is a first cross-sectional schematic diagram of a display device according to another embodiment of the present disclosure;

[0073] FIG32 is a second schematic cross-sectional view of a display device according to another embodiment of the present disclosure.

[0074] Details

[0075] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0076] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0077] The ordinal numbers such as "first," "second," and "third" in this disclosure are provided to avoid confusion among constituent elements, and are not intended to limit the number. The "plurality" in this disclosure includes two or more.

[0078] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements are appropriately changed according to the direction in which the constituent elements are described. Therefore, the words and phrases are not limited to those described in the specification and can be appropriately replaced according to the circumstances.

[0079] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0080] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0081] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0082] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged.

[0083] In this disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0084] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0085] In the present disclosure, “about” and “approximately” refer to values ​​that are not strictly defined but allow for process and measurement errors.

[0086] The triangles, rectangles, trapezoids, pentagons or hexagons in the present disclosure are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0087] Top-gate thin-film transistors (TFTs) are ideal for display products requiring high refresh rates and low power consumption due to their high on-state current, excellent stability, and low parasitic capacitance. However, existing top-gate displays require a large number of light-shielding layers, resulting in high costs and a limited range of applications.

[0088] An embodiment of the present disclosure provides an array substrate. The array substrate includes: a substrate, at least one first transistor disposed on the substrate, at least one data line, and at least one pixel electrode; the at least one first transistor includes a first active layer and a first gate; the first gate is located on a side of the first active layer away from the substrate, and the first gate and the first active layer have an orthographic projection on the substrate that at least partially overlap; the first active layer is electrically connected to the data line and the pixel electrode, respectively; the data line is located on a side of the first active layer closer to the substrate; and the pixel electrode is located on a side of the first gate away from the substrate.

[0089] In the embodiment of the present disclosure, by arranging the data line on the side of the first transistor close to the substrate, the capacitance between the data line and the pixel electrode can be reduced, thereby reducing the power consumption of the data line and improving the performance of the array substrate.

[0090] Figure 1 is a schematic front view of an array substrate according to one embodiment of the present disclosure. As shown in Figure 1 , the array substrate may include a display area AA and a border area BB located around the display area AA. The border area BB may include a first border area B1 located on one side of the display area AA and a second border area B2 located on the remaining sides of the display area AA. For example, the first border area B1 may include the bottom border of the array substrate, and the second border area B2 may include the top, left, and right borders of the array substrate.

[0091] In one exemplary embodiment, as shown in FIG1 , the display area AA may include: a plurality of data lines DL and a plurality of gate lines GL disposed on a substrate. The plurality of gate lines GL may extend along a first direction X and be sequentially arranged along a second direction Y different from the first direction X. The plurality of data lines DL may extend along the second direction Y and be sequentially arranged along the first direction X. The first direction X and the second direction Y may intersect; for example, the first direction X may be perpendicular to the second direction Y. The plurality of data lines DL and the plurality of gate lines GL may be located in different film layers; for example, the plurality of data lines DL may be located on a side of the plurality of gate lines GL closer to the substrate.

[0092] In an exemplary embodiment, as shown in FIG1 , a plurality of data lines DL and a plurality of gate lines GL may intersect to form a plurality of sub-pixel areas. The area defined by the intersection of adjacent data lines DL and adjacent gate lines GL may be a sub-pixel area. A sub-pixel may be provided in a corresponding sub-pixel area. The sub-pixel area may include an opening area and a non-opening area surrounding the opening area. The non-opening area may be an area blocked by the black matrix of the opposing substrate of the array substrate, and the opening area may be an area not blocked by the black matrix of the opposing substrate. Adjacent gate lines GL and data lines DL may both be located within the non-opening area. The array substrate of the disclosed embodiment may be used to implement a display function, and the opening area of ​​each sub-pixel area may be configured for display. The non-opening area surrounds the opening area and does not display. However, the disclosed embodiment is not limited to this. In some examples, the array substrate may be used to implement other functions.

[0093] In one exemplary embodiment, the display area AA may include: a plurality of pixel units disposed on a substrate. At least one pixel unit may include: three sub-pixels (e.g., a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along a first direction X). The three sub-pixels of the pixel unit may be, for example, a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged sequentially in the order of blue sub-pixel, green sub-pixel, and red sub-pixel. As shown in FIG1 , at least one sub-pixel may include: a pixel electrode 10 and a common electrode (not shown in FIG1 ), and the orthographic projections of the pixel electrode 10 and the common electrode of the sub-pixel on the substrate may overlap. The common electrode of the plurality of sub-pixels in the display area AA may be a single-piece structure. For example, the common electrode may be located on a side of the pixel electrode 10 away from the substrate. The sub-pixel may also include a first transistor 11. The first transistor 11 may be located adjacent to the intersection of a data line DL and a gate line GL. The first transistor 11 may include a first gate, a first electrode, and a second electrode. The first gate may be electrically connected to the gate line GL, the first electrode of the first transistor 11 may be electrically connected to the data line DL, and the second electrode may be electrically connected to the pixel electrode 10 of the sub-pixel. The first transistor 11 may be configured to provide a data signal transmitted by the data line DL to the pixel electrode 10 of the sub-pixel under the control of the gate line GL.

[0094] Liquid crystal display devices have various display modes, such as ADS (Advanced Super Dimension Switch) mode, TN (twisted nematic) mode, and VA (Vertical Alignment) mode. In the ADS mode, the pixel electrode and common electrode are both located on one side of the array substrate. In the TN and VA modes, the pixel electrode and common electrode are respectively arranged on both sides of the liquid crystal layer, with the pixel electrode located on the array substrate side and the common electrode located on the opposing substrate side.

[0095] The ADS mode operates on the principle that liquid crystal molecules lie in a plane parallel to the glass substrate. When no voltage is applied, light passing through the lower polarizer becomes linearly polarized, parallel to the short axis of the liquid crystal molecules. This polarization cannot be rotated, and is therefore absorbed by the upper polarizer and prevented from exiting. When voltage is applied, a transverse electric field forms on the liquid crystal, aligning the liquid crystal molecules along the direction of the electric field. After passing through the lower polarizer and the liquid crystal layer, the light becomes elliptically polarized, allowing it to pass through the upper polarizer and exit.

[0096] The TN mode operates under the principle that in the absence of voltage, the liquid crystal molecules are twisted into a 90° alignment by the alignment films. Light passes through the lower polarizer and the liquid crystal molecules before exiting through the upper polarizer. When voltage is applied, most of the liquid crystal molecules, except for those near the upper and lower polarizers, align vertically. Light passing through the lower polarizer passes through the liquid crystal layer without deflection. However, since its polarization axis is parallel to the upper polarizer, the light is absorbed and cannot be emitted.

[0097] The VA mode operates on the principle that liquid crystal molecules are aligned perpendicular to the glass substrate. When no voltage is applied, light passing through the lower polarizer forms linear polarization parallel to the short axis of the liquid crystal molecules. This polarization cannot be rotated, and is therefore absorbed by the upper polarizer and prevented from being emitted. When voltage is applied, the liquid crystal molecules are deflected in the direction of the electric field. Light passing through the lower polarizer and liquid crystal layer becomes elliptically polarized, allowing it to pass through the upper polarizer and be emitted.

[0098] The following describes the structure of the array substrate in conjunction with several different display modes of a liquid crystal display device. Figures 2 to 6 illustrate the structure of the array substrate in ADS mode. Figures 8 to 19 illustrate the structure of the array substrate in TN mode. Figures 20 to 32 illustrate the structure of the array substrate in VA display mode.

[0099] Figure 2 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure. As shown in Figure 2, the array substrate may include a substrate 12 and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on the substrate 12. A first insulating layer 14 is disposed between the first conductive layer and the semiconductor layer. A second insulating layer 16 is disposed between the semiconductor layer and the second conductive layer. In the embodiment of the present disclosure, the second insulating layer 16 may also be referred to as a gate insulating (GI) layer. The first conductive layer may include a data line DL and a light shielding block 13. The semiconductor layer may include a first active layer 15 of a first transistor 11. The second conductive layer may include a first gate electrode 17 of the first transistor 11 and a first connecting electrode 18. The first active layer 15 may be electrically connected to the data line DL via the first connecting electrode 18. The third conductive layer includes a common electrode, and the fourth conductive layer includes a pixel electrode. In other examples, the data line DL may be located on a different layer from the light shielding block 13. For example, the light shielding block may be located on the side of the data line closer to the substrate.

[0100] In an exemplary embodiment, the data lines DL and the light shielding blocks 13 may be provided as a same-layer structure, which can simplify the manufacturing process of the array substrate and reduce the number of masks used.

[0101] In an exemplary embodiment, substrate 12 may provide support for film layers other than substrate 12 in the array substrate. For example, substrate 12 may be a transparent substrate. For example, substrate 12 may be a rigid substrate or a flexible substrate. For example, the material of the rigid substrate may include, but is not limited to, one or more of glass and quartz. The material of the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. However, the embodiments of the present disclosure are not limited to this.

[0102] In an exemplary embodiment, the first conductive layer may be made of a metal material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the first conductive layer may be made of an alloy of metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The first conductive layer may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti.

[0103] In one exemplary embodiment, the second conductive layer can be made of a metal material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the first conductive layer can be made of an alloy of metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), such as aluminum-neodymium (AlNd) or molybdenum-niobium (MoNb). The second conductive layer can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti.

[0104] 2 , the orthographic edge of the first insulating layer 14 on the substrate 12 may cover the orthographic edge of the data line DL on the substrate 12, and the orthographic edge of the first insulating layer 14 on the substrate 12 may cover the orthographic edge of the light shielding block 13 on the substrate 12. The first insulating layer 14 may also be referred to as an interlayer dielectric (ILD) layer.

[0105] In an exemplary embodiment, the first insulating layer 14 may be made of an inorganic material, such as silicon oxynitride (SiO x N y ) or one or more of silicon nitride (SiN) or silicon oxide (SiO) or silicon dioxide (SiO2), etc. The first insulating layer 14 can be a single layer or a multi-layer or composite layer.

[0106] In an exemplary embodiment, as shown in FIG2 , the first insulating layer 14 may be provided with a first via K1. The first via K1 extends through the first insulating layer 14 along the thickness direction of the array substrate. The orthographic projection of the first via K1 on the substrate 12 may overlap with the orthographic projection of the data line DL on the substrate 12. The first via K1 may expose a portion of the surface of the data line DL. For example, the orthographic projection of the first via K1 on the substrate 12 may be located in the middle of the orthographic projection of the data line DL on the substrate 12.

[0107] In an exemplary embodiment, the material of the semiconductor layer may include an oxide semiconductor material. For example, the semiconductor layer may be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), and indium zinc tin oxide (IZTO). As shown in FIG2 , the orthographic projection of the first active layer 15 on the substrate 12 may overlap with the orthographic projection of the data line DL and the light shielding block 13 on the substrate 12. For example, the orthographic projection of the first active layer 15 on the substrate 12 partially overlaps with the orthographic projection of the data line DL on the substrate 12.

[0108] In an exemplary embodiment, as shown in FIG2 , the first active layer 15 may include a channel region 150, a first region 151 located on opposite sides of the channel region 150, and a second region 152. For example, during the fabrication process, a portion of the first active layer 15 may be subjected to a conductorization process to form the first region 151 and the second region 152, respectively. The first region 151 of the first active layer 15 may serve as the first electrode of the first transistor, and the second region 152 of the first active layer 15 may serve as the second electrode of the first transistor. The presently disclosed embodiments do not limit the conductorization process for the semiconductor layer.

[0109] In an exemplary embodiment, as shown in FIG2 , the channel region 150 of the first active layer 15 and the orthographic projection of the light shielding block 13 on the substrate 12 at least partially overlap. For example, the orthographic projection of the light shielding block 13 on the substrate 12 may cover the orthographic projection of the channel region 150 on the substrate 12. By shielding the channel region 150 of the first active layer 15 of the first transistor by the light shielding block 13, the characteristics of the first transistor can be prevented from being affected by external light.

[0110] 2 , the second region 152 may at least partially overlap with the orthographic projection of the light shielding block 13 on the substrate 12 . For example, the orthographic projection of the second region 152 on the substrate 12 may be within the orthographic projection of the light shielding block 13 on the substrate 12 .

[0111] In an exemplary embodiment, as shown in FIG. 2 , the second insulating layer 16 may cover the first active layer 15 .

[0112] In an exemplary embodiment, the material and structure of the second insulating layer 16 may be the same as those of the first insulating layer 14 .

[0113] In an exemplary embodiment, as shown in FIG2 , the second insulating layer 16 may be provided with a second via K2. The second via K2 penetrates the second insulating layer 16 along the thickness direction of the array substrate. The second via K2 and the first via K1 have at least a partial overlap in their orthographic projection on the substrate 12, and the second via K2 is connected to the first via K1. For example, the orthographic projection of the second via K2 on the substrate 12 may cover the orthographic projection of the first via K1 on the substrate 12. The orthographic projection of the second via K2 on the substrate 12 may overlap with the orthographic projection of the data line DL on the substrate 12. The second via K2 may expose a portion of the surface of the data line DL. As shown in FIG2 , the second via K2 also exposes a portion of the surface of the first region 151 of the first active layer 15.

[0114] In one exemplary embodiment, as shown in FIG2 , the second insulating layer 16 may be provided with a third via K3. The third via K3 penetrates the second insulating layer 16 along the thickness direction of the array substrate. The third via K3 may at least partially overlap with the orthographic projection of the second region 152 of the first active layer 15 on the substrate 12. For example, the orthographic projection of the third via K3 on the substrate 12 covers the orthographic projection of the second region 152 on the substrate 12. As shown in FIG2 , the third via K3 exposes a portion of the surface of the second region 152 of the first active layer 15.

[0115] In an exemplary embodiment, as shown in FIG. 2 , the second insulating layer 16 does not cover the second region 152 of the first active layer 15 .

[0116] In an exemplary embodiment, as shown in FIG2 , the orthographic projection of the first gate 17 on the substrate 12 may overlap with the orthographic projections of the first active layer 15 of the semiconductor layer and the light shielding block 13 on the substrate 12. For example, the orthographic projection of the first gate 17 on the substrate 12 may be located within the orthographic projection of the channel region 150 of the first active layer 15 on the substrate 12. Alternatively, the orthographic projection of the first gate 17 on the substrate 12 may overlap with the orthographic projection of the channel region 150 of the first active layer 15 on the substrate 12.

[0117] In an exemplary embodiment, the gate line GL may be provided in the same layer as the first gate electrode 17. For example, the orthographic projection of the gate line GL on the substrate 12 may not overlap with the orthographic projections of the first active layer 15 and the light shielding block 13 on the substrate 12.

[0118] In an exemplary embodiment, the gate line GL may be integrally formed with the first gate electrode 17. For example, the gate line GL may extend along the first direction X, and the first gate electrode 17 may protrude from the gate line GL in the second direction Y toward a side closer to the pixel electrode 10.

[0119] In one exemplary embodiment, as shown in FIG2 , the first connection electrode 18 may be located on a side of the second insulating layer 16 away from the substrate 12 . The orthographic projection of the first connection electrode 18 on the substrate 12 may overlap a portion of the orthographic projection of the second via K2 on the substrate 12 . The orthographic projection of the first connection electrode 18 on the substrate 12 may overlap the orthographic projection of the first via K1 on the substrate 12 . The first connection electrode 18 may be electrically connected to the first region 151 of the first active layer 15 of the first transistor through the second via K2 . The first connection electrode 18 may be electrically connected to the data line DL through the first via K1 and the second via K2 . The data line DL is electrically connected to the first region 151 of the first active layer 15 of the first transistor via the first connection electrode 18 .

[0120] In an exemplary embodiment, as shown in FIG2 , the orthographic projection of the first connection electrode 18 on the substrate 12 may only cover a portion of the orthographic projection of the second via K2 on the substrate 12. That is, the first connection electrode 18 does not completely fill the second via K2. This design prevents the first connection electrode 18 and the first gate 17 from being too close to each other, thereby preventing a short circuit between the two and reducing gate-source parasitic capacitance.

[0121] In one exemplary embodiment, as shown in FIG2 , the array substrate may further include a third insulating layer 19 located on one side of the substrate 12. The third insulating layer 19 is located on a side of the first gate electrode 17 away from the substrate 12. The third insulating layer 19 may cover the first gate electrode 17 and the first connecting electrode 18. In the embodiment of the present disclosure, the third insulating layer 19 may also be referred to as a first passivation (PVX) layer.

[0122] In an exemplary embodiment, the third insulating layer 19 may be made of an inorganic material, such as silicon oxynitride (SiO x N y ) or one or more of silicon nitride (SiN) or silicon oxide (SiO) or silicon dioxide (SiO2) etc.

[0123] In an exemplary embodiment, as shown in FIG2 , the third insulating layer 19 may be provided with a fourth via K4. The fourth via K4 penetrates the third insulating layer 19 along the thickness direction of the array substrate. The orthographic projection of the fourth via K4 on the substrate 12 may at least partially overlap with the orthographic projection of the third via K3 on the substrate 12. For example, the orthographic projection of the fourth via K4 on the substrate 12 is located inside the orthographic projection of the third via K3 on the substrate 12. The fourth via K4 may at least partially overlap with the orthographic projection of the second region 152 of the first active layer 15 on the substrate 12. For example, the orthographic projection of the fourth via K4 on the substrate 12 is located within the orthographic projection of the second region 152 on the substrate 12. As shown in FIG2 , the fourth via K4 exposes a portion of the surface of the second region 152 of the first active layer 15.

[0124] In an exemplary embodiment, as shown in FIG2 , the array substrate may further include a common electrode 20 located on one side of the substrate 12. The common electrode 20 is located on a side of the third insulating layer 19 away from the substrate 12. The orthographic projection of the common electrode 20 on the substrate 12 may overlap with the orthographic projections of the first gate electrode 17 and the first connecting electrode 18 on the substrate 12. For example, the orthographic projection of the common electrode 20 on the substrate 12 may overlap with the orthographic projection of the first connecting electrode 18 on the substrate 12 and partially cover the orthographic projection of the first gate electrode 17 on the substrate 12.

[0125] In an exemplary embodiment, the common electrode 20 may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0126] In an exemplary embodiment, the common electrode 20 may be a planar electrode or a linear electrode.

[0127] In one exemplary embodiment, as shown in FIG2 , the array substrate may further include a fourth insulating layer 21 located on one side of the substrate 12. The fourth insulating layer 21 is located on the side of the common electrode 20 away from the substrate 12. The orthographic projection of the fourth insulating layer 21 on the substrate 12 may cover the orthographic projection of the common electrode 20 on the substrate 12. In the disclosed embodiment, the fourth insulating layer 21 may also be referred to as a second passivation (PVX) layer.

[0128] In an exemplary embodiment, the fourth insulating layer 21 may be made of an inorganic material, such as silicon oxynitride (SiO x N y ) or one or more of silicon nitride (SiN) or silicon oxide (SiO) or silicon dioxide (SiO2) etc.

[0129] In an exemplary embodiment, the fourth insulating layer 21 may be provided with a fifth via K5. The fifth via K5 penetrates the fourth insulating layer 21 along the thickness direction of the array substrate. The orthographic projection of the fifth via K5 on the substrate 12 may at least partially overlap with the orthographic projection of the fourth via K4 on the substrate 12, and the fifth via K5 and the fourth via K4 are connected. For example, the orthographic projection of the fifth via K5 on the substrate 12 may cover the orthographic projection of the fourth via K4 on the substrate 12. The fifth via K5 and the orthographic projection of the second region 152 of the first active layer 15 on the substrate 12 at least partially overlap. As shown in FIG. 2 , the fifth via K5 exposes a portion of the surface of the second region 152 of the first active layer 15.

[0130] In one exemplary embodiment, as shown in FIG2 , the pixel electrode 10 may be located on a side of the fourth insulating layer 21 away from the substrate 12. The orthographic projection of the pixel electrode 10 on the substrate 12 may at least partially overlap with the orthographic projection of the common electrode 20 on the substrate 12. The pixel electrode 10 and the common electrode 20 are separated by the fourth insulating layer 21. As shown in FIG2 , a portion of the pixel electrode 10 may be electrically connected to the second region 152 of the first active layer 15 via the fifth via K5, the fourth via K4, and the third via K3.

[0131] In an exemplary embodiment, the pixel electrode 10 may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0132] In an exemplary embodiment, the pixel electrode 10 may be a planar electrode or a linear electrode.

[0133] In the embodiment of the present disclosure, by setting the data line DL on the side of the first transistor close to the substrate 12 (for example, the data line DL and the light shielding block 13 are set on the same layer), the capacitance between the data line DL and the pixel electrode can be reduced, thereby reducing the power consumption of the data line and improving the performance of the array substrate.

[0134] Figure 3 is a second schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure. As shown in Figure 3, the array substrate of this example includes a substrate 12, and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on the substrate 12. The third conductive layer includes a pixel electrode, and the fourth conductive layer includes a common electrode and a third connecting electrode. The pixel electrode 10 is located on the side of the fourth insulating layer 21 closest to the substrate 12, while the common electrode 20 is located on the side of the fourth insulating layer 21 away from the substrate 12.

[0135] In one exemplary embodiment, as shown in FIG3 , the third connection electrode 26 can be co-layered with the common electrode 20. The fifth via K5 can expose a portion of the surface of the pixel electrode 10, and the third connection electrode 26 is electrically connected to the portion of the pixel electrode 10 exposed by the fifth via K5. Using the third connection electrode to electrically connect the pixel electrode and the first active layer can simplify the manufacturing steps of the array substrate. For other structures of the array substrate of this example, refer to the description of the array substrate shown in FIG2 , and will not be further elaborated here.

[0136] Figure 4 is a third schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure. As shown in Figure 4, the array substrate of this example includes: a substrate 12, and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on the substrate 12. A third insulating layer 19 is disposed between the second conductive layer and the third conductive layer, and a fourth insulating layer 21 is disposed between the third conductive layer and the fourth conductive layer. An organic insulating layer 22 is also disposed between the fourth insulating layer 21 and the third insulating layer 19. The pixel electrode 10 is located on a side of the fourth insulating layer 21 away from the substrate 12, and the common electrode 20 is located on a side of the fourth insulating layer 21 closer to the substrate 12. Providing an organic insulating layer can reduce crosstalk from the first gate to the common electrode.

[0137] As shown in Figure 4, the organic insulating layer 22 is provided with a sixth via K6. The orthographic projections of the fifth via K5 and the sixth via K6 on the substrate 12 at least partially overlap, and the fifth via K5 and the sixth via K6 are interconnected. For example, the orthographic projections of the fifth via K5 and the sixth via K6 on the substrate 12 overlap. The pixel electrode 10 is electrically connected to the second region 152 of the first active layer 15 via the fifth via K5, the sixth via K6, the fourth via K4, and the third via K3. For other structures of the array substrate, refer to the description of the array substrate shown in Figure 2 above and will not be elaborated here.

[0138] In the embodiment of the present disclosure, the fifth via hole K5 , the sixth via hole K6 , and the fourth via hole K4 may collectively constitute a first through hole.

[0139] In an exemplary embodiment, the material of the organic insulating layer 22 can be one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, or polyether resin.

[0140] Figure 5 is a fourth schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure. The array substrate in this example includes a substrate 12, and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on the substrate 12. A third insulating layer 19 is disposed between the second and third conductive layers, and a fourth insulating layer 21 is disposed between the third and fourth conductive layers. The pixel electrode 10 is located on the side of the fourth insulating layer 21 closest to the substrate 12, and the common electrode 20 is located on the side of the fourth insulating layer 21 away from the substrate 12.

[0141] In one exemplary embodiment, as shown in FIG5 , the array substrate may further include a third connection electrode 26. The third connection electrode 26 may be co-layered with the common electrode 20. The fifth via K5 exposes a portion of the surface of the pixel electrode 10, and the third connection electrode 26 is electrically connected to the portion of the pixel electrode 10 exposed by the fifth via K5. For other structures of the array substrate, refer to the description of the array substrate shown in FIG2 , and will not be further elaborated here.

[0142] The structure of the array substrate is described below using an example of its fabrication process. The "patterning process" referred to in the embodiments of the present disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal, inorganic, or transparent conductive materials. For organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed by any one or more of spray coating, spin coating, and inkjet printing; and etching can be performed by any one or more of dry etching and wet etching, although this disclosure does not limit this. A "thin film" refers to a thin layer of a material produced on a substrate using deposition, coating, or other processes. If a "thin film" does not require a patterning process during the entire fabrication process, it can also be referred to as a "layer." If a "thin film" requires a patterning process during the entire fabrication process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. A "layer" after the patterning process contains at least one "pattern." In the embodiments of the present disclosure, a "same-layer structure" refers to a layer within the array substrate.

[0143] Taking the array substrate structure shown in FIG. 2 as an example, the preparation process of the array substrate may include the following steps:

[0144] (1) Provide a substrate.

[0145] (2) Forming a first conductive layer.

[0146] A first conductive film is deposited on the substrate and patterned by a patterning process to form a first conductive layer disposed on the substrate. The first conductive layer in the display area may include data lines and light shielding blocks.

[0147] (3) Forming a semiconductor layer.

[0148] A first insulating film and a semiconductor film are sequentially deposited on the substrate having the aforementioned structure, and the semiconductor film is patterned by a patterning process to form a semiconductor layer disposed on the first insulating film. The semiconductor layer may include a first active layer of a first transistor.

[0149] (4) Forming a second insulating layer.

[0150] A second insulating film is deposited on the substrate forming the aforementioned structure, and the second insulating film is etched to form a second insulating layer. The first insulating layer is also etched to form a first insulating layer. The first insulating layer is provided with a first via hole. The second insulating layer is provided with a second via hole and a third via hole.

[0151] (5) Forming a second conductive layer.

[0152] A second conductive film is deposited on the substrate having the aforementioned structure and patterned using a patterning process to form a second conductive layer disposed on the second insulating layer. The second conductive layer in the display area may include a gate line, a first gate electrode of the first transistor, and a first connecting electrode. The first connecting electrode is electrically connected to the data line via the second via hole and the first via hole.

[0153] (6) Form a fourth insulating layer.

[0154] A third insulating film, a third conductive layer, and a fourth insulating film are sequentially deposited on the substrate forming the aforementioned structure. The fourth insulating film is patterned using a patterning process to form a fourth insulating layer, and the third insulating film is etched to form a third insulating layer. A fourth via hole is provided in the third insulating layer, and a fifth via hole is provided in the fourth insulating layer. The third conductive layer in the display area may include a common electrode.

[0155] (7) Forming a fourth conductive layer.

[0156] A fourth conductive film is deposited on the substrate having the aforementioned structure and patterned using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer. The fourth conductive layer in the display area may include a pixel electrode. The pixel electrode may be electrically connected to the second region of the first active layer via the fifth via and the fourth via.

[0157] FIG6 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure. As shown in FIG6 , an embodiment of the present disclosure further provides a display device. The display device can implement an Advanced Super Dimension Switch (ADS) mode. The display device can include the array substrate described in any of the aforementioned embodiments.

[0158] The display device may also include a counter substrate 1 and a liquid crystal layer 2 disposed between the array substrate and the counter substrate 1. The pixel electrodes and common electrodes included in the array substrate can be configured to generate an electric field that controls the deflection of liquid crystal molecules in the liquid crystal layer 2. As shown in Figure 6, the pixel electrodes 10 and the common electrodes 20 are both located on the array substrate, while no electrodes are provided on the counter substrate 1. As shown in Figure 6, the liquid crystal molecules in the liquid crystal layer 2 can be horizontally aligned on the array substrate, with the horizontal direction parallel to the XY plane.

[0159] In an exemplary embodiment, as shown in Figure 6 , the counter substrate 1 may include a base substrate, and a black matrix 3 and a color filter layer 4 disposed on the base substrate. However, the present disclosure is not limited thereto.

[0160] Figure 7 is a schematic front view of an array substrate according to another embodiment of the present disclosure. As shown in Figure 7, a sub-pixel may include a first transistor 11 and a storage capacitor 27. The first transistor 11 may be located near the intersection of a data line DL and a gate line GL. The structure of the array substrate will be described below using a display device implementing a TN mode and a VA mode as an example. For example, the second plate of the storage capacitor may be electrically connected to the pixel electrode.

[0161] Figure 8 is a cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure. As shown in Figure 8 , the array substrate may include a substrate 12, and a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer located on one side of the substrate 12. The first conductive layer may include a data line DL and a light shielding block 13. The semiconductor layer may include a first active layer 15 of a first transistor 11. The second conductive layer may include a first gate electrode 17 of the first transistor 11. The third conductive layer may include a pixel electrode 10.

[0162] As shown in FIG8 , the array substrate may further include a first insulating layer 14 between the first conductive layer and the semiconductor layer, a second insulating layer 16 between the second conductive layer and the semiconductor layer, and a third insulating layer 19 and a fourth insulating layer 21 between the third conductive layer and the second conductive layer.

[0163] FIG9 is a second cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure. As shown in FIG9 , the storage capacitor may include a first electrode plate 23 disposed on one side of the substrate 12. The first electrode plate 23 may be located on the same side of the substrate 12 as the data line DL and the light shielding block 13. As shown in FIG9 , the storage capacitor may further include a second electrode plate 24 disposed on a side of the fourth insulating layer 21 away from the substrate 12. The orthographic projections of the first electrode plate 23 and the second electrode plate 24 on the substrate 12 may at least partially overlap. For example, the orthographic projections of the first electrode plate 23 and the second electrode plate 24 on the substrate 12 may overlap.

[0164] In an exemplary embodiment, the first electrode plate 23 can be made of a metal material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the first electrode plate 23 can be an alloy material of a metal material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb). The first electrode plate 23 can have a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti.

[0165] In an exemplary embodiment, the first electrode 23 may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0166] In an exemplary embodiment, the first electrode plate 23 and the light shielding block 13 may be in the same layer structure.

[0167] In an exemplary embodiment, the second electrode 24 and the pixel electrode 10 may be in the same layer structure.

[0168] In an exemplary embodiment, as shown in FIG. 9 , the second electrode 24 and the pixel electrode 10 may be an integrated structure, which can simplify the process of preparing the storage capacitor and reduce the overall manufacturing cost of the array substrate.

[0169] Figure 10 is a third cross-sectional view of an array substrate according to another embodiment of the present disclosure. As shown in Figure 10 , the first electrode 23 and the light shielding block 13 can be an integrated structure, which can simplify the process of preparing the storage capacitor and reduce the overall manufacturing cost of the array substrate.

[0170] FIG11 is a fourth cross-sectional view of an array substrate according to another embodiment of the present disclosure. As shown in FIG11 , the first electrode plate 23 may be located on a side of the second insulating layer 16 away from the substrate 12. For example, the first electrode plate 23 may be provided on the same layer as the first gate 17.

[0171] FIG12 is a fifth cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure. As shown in FIG12 , the first electrode 23 and the light shielding block 13 are located on the same side of the substrate 12. The second electrode 24 may be located on a side of the second insulating layer 16 away from the substrate 12. The array substrate may further include a second connecting electrode 25. A portion of the second connecting electrode 25 may be located on a side of the fourth insulating layer 21 away from the substrate 12. For example, the second connecting electrode 25 may be provided in the same layer as the pixel electrode 10. The second connecting electrode 25 may be electrically connected to the second electrode 24 via a seventh via K7 provided in the fourth insulating layer 21 and an eighth via K8 provided in the third insulating layer 19.

[0172] In an exemplary embodiment, as shown in FIG. 12 , the orthographic projection of the second connecting electrode 25 on the substrate 12 may cover the orthographic projection of the second electrode plate 24 on the substrate 12 and cover the orthographic projection of the first electrode plate 23 on the substrate 12 .

[0173] In an exemplary embodiment, as shown in FIG. 12 , the second connection electrode 25 and the pixel electrode 10 may be an integrated structure, which can simplify the manufacturing process of the storage capacitor and reduce the manufacturing cost.

[0174] In an exemplary embodiment, as shown in FIG. 12 , the first electrode plate 23 and the light shielding block 13 may be in the same layer structure.

[0175] Figure 13 is a sixth cross-sectional view of an array substrate according to another embodiment of the present disclosure. As shown in Figure 13 , the first electrode plate 23 and the light shielding block 13 may be an integrated structure, which can simplify the manufacturing process of the storage capacitor.

[0176] FIG14 is a seventh cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure. The array substrate further includes an organic insulating layer 22. The organic insulating layer 22 is located between the third insulating layer 19 and the fourth insulating layer 21. As shown in FIG14 , the organic insulating layer 22 is provided with a sixth via K6. The fourth insulating layer 21 is provided with a fifth via K5, and the orthographic projections of the fifth via K5 and the sixth via K6 on the substrate 12 at least partially overlap, and the fifth via K5 and the sixth via K6 are connected. For example, the orthographic projections of the fifth via K5 and the sixth via K6 on the substrate 12 overlap. The pixel electrode 10 is electrically connected to the second region 152 of the first active layer 15 via the fifth via K5, the sixth via K6, the fourth via K4, and the third via K3.

[0177] Figure 15 is a cross-sectional schematic diagram eight of an array substrate according to another embodiment of the present disclosure. As shown in Figure 15, the storage capacitor may further include a first electrode 23 disposed on one side of the substrate 12. The first electrode 23 may be located on the same side of the substrate 12 as the data line DL and the light shielding block 13. As shown in Figure 15, the array substrate may further include a second electrode 24 disposed on the side of the fourth insulating layer 21 away from the substrate 12. The orthographic projections of the first electrode 23 and the second electrode 24 on the substrate 12 may at least partially overlap. For example, the orthographic projection of the second electrode 24 on the substrate 12 may cover the orthographic projection of the first electrode 23 on the substrate 12. As shown in Figure 15, the second electrode 24 and the pixel electrode 10 may be a same-layer structure. For example, the second electrode 24 and the pixel electrode 10 may be an integral structure.

[0178] As shown in Figure 15 , the fourth insulating layer 21 is provided with a seventh via hole K7, the third insulating layer 19 is provided with an eighth via hole K8, and the organic insulating layer 22 is provided with a ninth via hole K9. The seventh via hole K7, the eighth via hole K8, and the ninth via hole K9 are interconnected. The second electrode plate 24 can be provided at the bottom of the eighth via hole K8, which is located on the side closest to the substrate 12.

[0179] In the embodiment of the present disclosure, the seventh via hole K7 , the eighth via hole K8 , and the ninth via hole K9 together constitute a second through hole.

[0180] Fig. 16 is a ninth cross-sectional view of an array substrate according to another embodiment of the present disclosure. As shown in Fig. 16 , the first electrode plate 23 and the light shielding block 13 may be an integrated structure.

[0181] FIG17 is a cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure. As shown in FIG17 , the first electrode 23 and the light shielding block 13 are located on the same side of the substrate 12. The second electrode 24 is located on the side of the second insulating layer 16 away from the substrate 12. For example, the second electrode 24 can be provided on the same layer as the first gate 17. As shown in FIG17 , the storage capacitor may further include a second connecting electrode 25. A portion of the second connecting electrode 25 is located on the side of the fourth insulating layer 21 away from the substrate 12. The second connecting electrode 25 is electrically connected to the second electrode 24 via the seventh via K7, the ninth via K9, and the eighth via K8.

[0182] In an exemplary embodiment, as shown in FIG. 17 , the orthographic projection of the second connecting electrode 25 on the substrate 12 may cover the orthographic projection of the second electrode plate 24 on the substrate 12 , and the orthographic projection of the second connecting electrode 25 on the substrate 12 may cover the orthographic projection of the first electrode plate 23 on the substrate 12 .

[0183] Fig. 18 is a cross-sectional view of an array substrate according to another embodiment of the present disclosure. As shown in Fig. 18 , the first electrode plate 23 and the light shielding block 13 may be an integrated structure.

[0184] In the embodiment of the present disclosure, the second plate of the storage capacitor is electrically connected to the pixel electrode, and the first plate is arranged on the side of the second plate close to the substrate. This can reduce the surface area of ​​the storage capacitor and the space occupied by the storage capacitor, which is conducive to the miniaturization design of the array substrate.

[0185] The structure of the array substrate is described below by taking the array substrate manufacturing process as an example. Taking the array substrate structure shown in FIG17 as an example, the array substrate manufacturing process may include the following steps:

[0186] (1) Provide a substrate.

[0187] (2) Forming a first conductive layer.

[0188] A first conductive film is deposited on the substrate and patterned by a patterning process to form a first conductive layer disposed on the substrate. The first conductive layer in the display area may include data lines, light shielding blocks, and a first electrode plate.

[0189] (3) Forming a semiconductor layer.

[0190] A first insulating film and a semiconductor film are sequentially deposited on the substrate having the aforementioned structure, and the semiconductor film is patterned by a patterning process to form a semiconductor layer disposed on the first insulating film. The semiconductor layer may include a first active layer of a first transistor.

[0191] (4) Forming a second insulating layer.

[0192] A second insulating film is deposited on the substrate forming the aforementioned structure, the second insulating film is etched to form a second insulating layer, and the first insulating film is etched to form a first insulating layer. The first insulating layer is provided with a first via hole. The second insulating layer is provided with a second via hole and a third via hole.

[0193] (5) Forming a second conductive layer.

[0194] A second conductive film is deposited on the substrate having the aforementioned structure and patterned using a patterning process to form a second conductive layer disposed on the second insulating layer. The second conductive layer in the display area may include a gate line, a first gate electrode of the first transistor, a first connecting electrode, and a second plate. The first connecting electrode is electrically connected to the data line via the second via hole and the first via hole.

[0195] (6) Form a fourth insulating layer.

[0196] A third insulating film, an organic film, and a fourth insulating film are sequentially deposited on the substrate forming the aforementioned structure. The fourth insulating film is patterned using a patterning process to form a fourth insulating layer. The third insulating film is etched to form a third insulating layer, and the organic film is etched to form an organic insulating layer. The third insulating layer is provided with a fourth via hole and an eighth via hole, the fourth insulating layer is provided with a fifth via hole and a seventh via hole, and the organic insulating layer is provided with a sixth via hole and a ninth via hole.

[0197] (7) Forming a third conductive layer.

[0198] A third conductive film is deposited on the substrate having the aforementioned structure and patterned using a patterning process to form a third conductive layer disposed on the fourth insulating layer. The third conductive layer in the display area may include a pixel electrode and a second connecting electrode. The pixel electrode is electrically connected to the second region of the first active layer via a fifth via, a sixth via, and a fourth via. The second connecting electrode is electrically connected to the second electrode plate via a seventh via, a ninth via, and an eighth via.

[0199] Figure 19 is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure. As shown in Figure 19 , another embodiment of the present disclosure provides a display device. The display device may include the array substrate shown in any of the aforementioned embodiments (e.g., Figures 8 to 18 ). The display device may implement a TN (twisted nematic) mode. The display device may also include an opposing substrate 1 and a liquid crystal layer 2 disposed between the array substrate and the opposing substrate 1.

[0200] As shown in FIG19 , the display device may further include a common electrode 20. The common electrode 20 and the pixel electrode 10 may be disposed on opposite sides of the liquid crystal layer 2. As shown in FIG19 , the common electrode 20 is located on the side of the liquid crystal layer 2 closest to the counter substrate 1. The pixel electrode 10 and the common electrode 20 may be configured to generate an electric field that controls the deflection of the liquid crystal molecules in the liquid crystal layer 2. As shown in FIG19 , the liquid crystal molecules in the liquid crystal layer 2 may be vertically aligned with respect to the array substrate.

[0201] In an exemplary embodiment, as shown in FIG. 19 , the common electrode 20 may be a planar electrode.

[0202] In an exemplary embodiment, as shown in Figure 19 , the counter substrate 1 may include a base substrate, and a black matrix 3 and a color filter layer 4 disposed on the base substrate. However, the present disclosure is not limited thereto.

[0203] Figure 20 is a schematic cross-sectional view of an array substrate according to another embodiment of the present disclosure. As shown in Figure 20 , the array substrate may include a substrate 12, and a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer located on one side of the substrate 12. The first conductive layer may include a data line DL and a light shielding block 13. The semiconductor layer may include a first active layer 15 of a first transistor 11. The second conductive layer may include a first gate electrode 17 of the first transistor 11. The third conductive layer may include a pixel electrode 10.

[0204] The array substrate may further include a first insulating layer 14 between the first conductive layer and the semiconductor layer, a second insulating layer 16 between the second conductive layer and the semiconductor layer, and a third insulating layer 19 and a fourth insulating layer 21 between the third conductive layer and the second conductive layer.

[0205] In an exemplary embodiment, as shown in FIG. 20 , the pixel electrode 10 may be a linear electrode.

[0206] FIG21 is a second cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure. As shown in FIG21 , the storage capacitor may further include a first electrode plate 23 disposed on one side of the substrate 12. The first electrode plate 23 may be located on the same side of the substrate 12 as the data line DL and the light shielding block 13. As shown in FIG21 , the array substrate may further include a second electrode plate 24 disposed on a side of the fourth insulating layer 21 away from the substrate 12. The orthographic projections of the first electrode plate 23 and the second electrode plate 24 on the substrate 12 may at least partially overlap. For example, the orthographic projections of the first electrode plate 23 and the second electrode plate 24 on the substrate 12 may overlap.

[0207] In an exemplary embodiment, the first electrode plate 23 and the light shielding block 13 may be in the same layer structure.

[0208] In an exemplary embodiment, the second electrode 24 and the pixel electrode 10 may be in the same layer structure.

[0209] In an exemplary embodiment, as shown in FIG. 21 , the second electrode 24 and the pixel electrode 10 may be an integrated structure, which can simplify the process of preparing the storage capacitor and reduce the overall manufacturing cost of the array substrate.

[0210] Figure 22 is a third cross-sectional view of an array substrate according to another embodiment of the present disclosure. As shown in Figure 22 , the first electrode 23 and the light shielding block 13 can be an integrated structure, which can simplify the process of preparing the storage capacitor and reduce the overall manufacturing cost of the array substrate.

[0211] Figure 23 is a fourth cross-sectional view of an array substrate according to another embodiment of the present disclosure. As shown in Figure 23 , the first electrode 23 may be located on a side of the second insulating layer 16 away from the substrate 12. For example, the first electrode 23 and the first gate 17 may be in the same layer.

[0212] Figure 24 is a fifth cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure. As shown in Figure 24, the first electrode 23 and the light shielding block 13 are located on the same side of the substrate 12. The second electrode 24 may be located on the side of the second insulating layer 16 away from the substrate 12. The storage capacitor may further include a second connecting electrode 25. A portion of the second connecting electrode 25 may be located on the side of the fourth insulating layer 21 away from the substrate 12. For example, the second connecting electrode 25 may be provided in the same layer as the pixel electrode 10. The second connecting electrode 25 is electrically connected to the second electrode 24 via a seventh via K7 provided in the fourth insulating layer 21 and an eighth via K8 provided in the third insulating layer 19.

[0213] In an exemplary embodiment, as shown in FIG. 24 , the orthographic projection of the second connecting electrode 25 on the substrate 12 may cover the orthographic projection of the second electrode plate 24 on the substrate 12 and cover the orthographic projection of the first electrode plate 23 on the substrate 12 .

[0214] In an exemplary embodiment, as shown in FIG. 24 , the second connection electrode 25 and the pixel electrode 10 may be an integrated structure, which can simplify the manufacturing process of the storage capacitor and reduce the manufacturing cost.

[0215] In an exemplary embodiment, as shown in FIG. 24 , the first electrode plate 23 and the light shielding block 13 may be in the same layer structure.

[0216] Figure 25 is a sixth cross-sectional view of an array substrate according to another embodiment of the present disclosure. As shown in Figure 25 , the first electrode plate 23 and the light shielding block 13 can be an integrated structure, which can simplify the manufacturing process of the storage capacitor.

[0217] 26 is a seventh cross-sectional view of an array substrate according to another embodiment of the present disclosure. The array substrate may further include an organic insulating layer 22 . The organic insulating layer 22 is located between the third insulating layer 19 and the fourth insulating layer 21 .

[0218] As shown in Figure 26, the organic insulating layer 22 is provided with a sixth via hole K6. The fourth insulating layer 21 is provided with a fifth via hole K5. The orthographic projections of the fifth via hole K5 and the sixth via hole K6 on the substrate 12 at least partially overlap, and the fifth via hole K5 and the sixth via hole K6 are intersecting. For example, the orthographic projections of the fifth via hole K5 and the sixth via hole K6 on the substrate 12 overlap. The pixel electrode 10 is electrically connected to the second region 152 of the first active layer 15 via the fifth via hole K5, the sixth via hole K6, the fourth via hole K4, and the third via hole K3.

[0219] FIG27 is a cross-sectional schematic diagram eight of an array substrate according to another embodiment of the present disclosure. As shown in FIG27 , the storage capacitor may further include a first electrode 23 disposed on one side of the substrate 12. The first electrode 23 may be located on the same side of the substrate 12 as the data line DL and the light shielding block 13. As shown in FIG27 , the storage capacitor may further include a second electrode 24 disposed on the side of the fourth insulating layer 21 away from the substrate 12. The orthographic projections of the first electrode 23 and the second electrode 24 on the substrate 12 may at least partially overlap. For example, the orthographic projection of the second electrode 24 on the substrate 12 may cover the orthographic projection of the first electrode 23 on the substrate 12. As shown in FIG27 , the second electrode 24 and the pixel electrode 10 may be a same-layer structure. For example, the second electrode 24 and the pixel electrode 10 may be an integral structure.

[0220] As shown in Figure 27, the fourth insulating layer 21 is provided with a seventh via hole K7, the third insulating layer 19 is provided with an eighth via hole K8, and the organic insulating layer 22 is provided with a ninth via hole K9. The seventh via hole K7, the eighth via hole K8, and the ninth via hole K9 are interconnected. The second electrode plate 24 can be provided at the bottom of the eighth via hole K8, which is located on the side closest to the substrate 12.

[0221] Fig. 28 is a ninth cross-sectional view of an array substrate according to another embodiment of the present disclosure. As shown in Fig. 28 , the first electrode plate 23 and the light shielding block 13 may be an integrated structure.

[0222] FIG29 is a cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure. As shown in FIG29 , the first electrode 23 and the light shielding block 13 are located on the same side of the substrate 12. The second electrode 24 is located on the side of the second insulating layer 16 away from the substrate 12. For example, the second electrode 24 can be provided on the same layer as the first gate 17. As shown in FIG29 , the storage capacitor may further include a second connecting electrode 25. A portion of the second connecting electrode 25 is located on the side of the fourth insulating layer 21 away from the substrate 12. The second connecting electrode 25 is electrically connected to the second electrode 24 via the seventh via K7, the ninth via K9, and the eighth via K8.

[0223] In an exemplary embodiment, as shown in FIG. 29 , the orthographic projection of the second connecting electrode 25 on the substrate 12 may cover the orthographic projection of the second electrode plate 24 on the substrate 12 , and the orthographic projection of the second connecting electrode 25 on the substrate 12 may cover the orthographic projection of the first electrode plate 23 on the substrate 12 .

[0224] Fig. 30 is a cross-sectional view of an array substrate according to another embodiment of the present disclosure. As shown in Fig. 30 , the first electrode plate 23 and the light shielding block 13 may be an integrated structure.

[0225] In the embodiment of the present disclosure, the second plate of the storage capacitor is electrically connected to the pixel electrode, and the first plate is arranged on the side of the second plate close to the substrate. This can reduce the surface area of ​​the storage capacitor and the space occupied by the storage capacitor, which is conducive to the miniaturization design of the array substrate.

[0226] The structure of the array substrate is described below by taking the example of the manufacturing process of the array substrate. Taking the array substrate structure shown in FIG27 as an example, the manufacturing process of the array substrate may include the following steps:

[0227] (1) Provide a substrate.

[0228] (2) Forming a first conductive layer.

[0229] A first conductive film is deposited on the substrate and patterned by a patterning process to form a first conductive layer disposed on the substrate. The first conductive layer in the display area may include data lines, light shielding blocks, and a first electrode plate.

[0230] (3) Forming a semiconductor layer.

[0231] A first insulating film and a semiconductor film are sequentially deposited on the substrate having the aforementioned structure, and the semiconductor film is patterned by a patterning process to form a semiconductor layer disposed on the first insulating film. The semiconductor layer may include a first active layer of a first transistor.

[0232] (4) Forming a second insulating layer.

[0233] A second insulating film is deposited on the substrate forming the aforementioned structure, the second insulating film is etched to form a second insulating layer, and the first insulating film is etched to form a first insulating layer. The first insulating layer is provided with a first via hole. The second insulating layer is provided with a second via hole and a third via hole.

[0234] (5) Forming a second conductive layer.

[0235] A second conductive film is deposited on the substrate having the aforementioned structure and patterned using a patterning process to form a second conductive layer disposed on the second insulating layer. The second conductive layer in the display area may include a gate line, a first gate electrode of the first transistor, and a first connecting electrode. The first connecting electrode is electrically connected to the data line via the second via hole and the first via hole.

[0236] (6) Form a fourth insulating layer.

[0237] A third insulating film, an organic film, and a fourth insulating film are sequentially deposited on the substrate having the aforementioned structure. The fourth insulating film is patterned using a patterning process to form a fourth insulating layer. The third insulating film is etched to form a third insulating layer, and the organic film is etched to form an organic insulating layer. The third insulating layer is provided with a fourth via hole and an eighth via hole. The organic insulating layer is provided with a sixth via hole and a ninth via hole. The fourth insulating layer is provided with a fifth via hole and a seventh via hole.

[0238] (7) Forming a third conductive layer.

[0239] A third conductive film is deposited on the substrate having the aforementioned structure and patterned using a patterning process to form a third conductive layer disposed on the fourth insulating layer. The third conductive layer in the display area may include a pixel electrode and a second electrode plate. The pixel electrode is electrically connected to the second region of the first active layer via a fifth via, a sixth via, and a fourth via. The second electrode plate forms a storage capacitor with the first electrode plate via a seventh via, a ninth via, and an eighth via.

[0240] Figure 31 is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure. As shown in Figure 31 , one embodiment of the present disclosure further provides a display device. The display device can implement a VA (Vertical Alignment) mode. The display device may include the array substrate described in any of the aforementioned embodiments (e.g., Figures 20 to 30 ). The display device may also include an opposing substrate 1 and a liquid crystal layer 2 disposed between the array substrate and the opposing substrate 1.

[0241] As shown in Figure 31 , the display device may further include a common electrode 20. The common electrode 20 and the pixel electrode 10 may be disposed on opposite sides of the liquid crystal layer 2. As shown in Figure 31 , the common electrode 20 is located on the side of the liquid crystal layer 2 closest to the opposing substrate 1. The pixel electrode 10 and the common electrode 20 may be configured to generate an electric field that controls the deflection of the liquid crystal molecules in the liquid crystal layer 2. As shown in Figure 31 , the liquid crystal molecules in the liquid crystal layer 2 may be aligned perpendicular to the array substrate. As shown in Figure 31 , the display device is in a dark state.

[0242] In an exemplary embodiment, as shown in FIG. 31 , the common electrode 20 may be a linear electrode and have at least one second slit 201 .

[0243] In an exemplary embodiment, as shown in FIG31 , the pixel electrode 10 may be a linear electrode and have at least one first slit 101. The orthographic projections of the first slit 101 and the second slit 201 on the substrate 12 do not overlap.

[0244] In an exemplary embodiment, as shown in Figure 31 , the counter substrate 1 may include a base substrate, and a black matrix 3 and a color filter layer 4 disposed on the base substrate. However, the present disclosure is not limited thereto.

[0245] FIG32 is a second cross-sectional view of a display device according to another embodiment of the present disclosure. As shown in FIG32 , the display device is in a bright state, and other structures can refer to the structure of the display device shown in FIG31 .

[0246] In the embodiments of the present disclosure, the above-mentioned pixel electrodes, common electrodes, and storage capacitors can be arbitrarily combined. For example, the storage capacitor structure can be combined with the array substrate structure shown in Figures 3 to 7. The present disclosure does not provide examples of any combination of the above-mentioned structures.

[0247] The present disclosure also provides a method for preparing an array substrate, including:

[0248] forming a data line on one side of the substrate;

[0249] forming a first transistor on a side of the data line away from the substrate, the first transistor comprising a first active layer and a first gate, wherein the first gate and the first active layer at least partially overlap with each other in an orthographic projection on the substrate, and the data line is electrically connected to the first active layer; the first gate is located on a side of the first active layer away from the substrate;

[0250] A pixel electrode is formed on a side of the first active layer away from the substrate, and the pixel electrode is electrically connected to the first active layer.

[0251] In an exemplary embodiment, the method for preparing the array substrate further includes forming a storage capacitor after forming the data line; the storage capacitor includes:

[0252] A first electrode plate is located on one side of the substrate; and

[0253] The second electrode plate is located on a side of the first electrode plate away from the substrate, and the second electrode plate is arranged opposite to the first electrode plate; the second electrode plate is electrically connected to the pixel electrode.

[0254] The present disclosure also provides a display device. The display device includes the array substrate described in any of the preceding embodiments. The display device can be any product or component with a display function, such as a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. The present disclosure is not limited thereto.

[0255] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and changes in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. An array substrate, comprising: A substrate, at least one first transistor, at least one data line and at least one pixel electrode arranged on the substrate; The at least one first transistor comprises a first active layer and a first gate; the first gate is located on a side of the first active layer away from the substrate, and the first gate and the first active layer at least partially overlap in their orthographic projections on the substrate; the first active layer is electrically connected to the data line and the pixel electrode, respectively; The data line is located on a side of the first active layer close to the substrate; the pixel electrode is located on a side of the first gate electrode away from the substrate.

2. The array substrate according to claim 1, wherein: The array substrate comprises a first conductive layer, a semiconductor layer and a second conductive layer which are sequentially arranged in a direction away from the substrate; The first conductive layer includes the data line and a light shielding block, the orthographic projection of the light shielding block on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate, the semiconductor layer includes the first active layer, the second conductive layer includes the first gate and a first connecting electrode, and the first active layer is electrically connected to the data line through the first connecting electrode.

3. The array substrate according to claim 1, wherein: The array substrate also includes at least one storage capacitor; the at least one storage capacitor includes: a first electrode plate and a second electrode plate; the second electrode plate is electrically connected to the pixel electrode, the first electrode plate is located on a side of the second electrode plate close to the substrate, and the first electrode plate and the second electrode plate at least partially overlap in their orthographic projections on the substrate.

4. The array substrate according to claim 3, wherein: The second electrode plate and the pixel electrode are an integrated structure.

5. The array substrate according to claim 4, further comprising: A plurality of insulating layers located on a side of the first gate away from the substrate; The plurality of insulating layers are provided with at least a first through hole and a second through hole; The pixel electrode is electrically connected to the first active layer through the first through hole, and at least a portion of the second electrode plate is located in the second through hole; The plurality of insulating layers include: a first passivation layer, an organic insulating layer, and a second passivation layer which are sequentially arranged in a direction away from the substrate.

6. The array substrate according to claim 4, wherein: The array substrate further comprises a first passivation layer and a second passivation layer located on a side of the first gate away from the substrate, and the first passivation layer is closer to the substrate than the second passivation layer; The second electrode plate is located on a surface of the second passivation layer on a side away from the first passivation layer.

7. The array substrate according to claim 4 or 6, wherein: The first electrode plate and the first grid electrode are in the same layer structure.

8. The array substrate according to claim 3, wherein: The second electrode plate and the first grid electrode are in the same layer structure.

9. The array substrate according to claim 8, further comprising: A plurality of insulating layers located on a side of the first gate away from the substrate; The plurality of insulating layers are provided with at least a first through hole and a second through hole; The pixel electrode is electrically connected to the first active layer through the first through hole, and the pixel electrode is electrically connected to the second electrode plate through the second through hole; The plurality of insulating layers include: a first passivation layer, an organic insulating layer, and a second passivation layer sequentially disposed in a direction away from the substrate; or, a first passivation layer and a second passivation layer sequentially disposed in a direction away from the substrate.

10. The array substrate according to any one of claims 3 to 6, wherein: The first electrode plate and the data line are in the same layer structure.

11. The array substrate according to any one of claims 3 to 6, further comprising: at least one light shielding block, wherein an orthographic projection of the light shielding block on the substrate partially overlaps with an orthographic projection of the first active layer on the substrate; The at least one light shielding block and the data line are in the same layer structure.

12. The array substrate according to claim 11, wherein: The first electrode plate and the light shielding block are an integrated structure.

13. The array substrate according to claim 1, further comprising: A common electrode; the common electrode is located on a side of the pixel electrode close to the substrate; The common electrode is a planar electrode, and the pixel electrode has a plurality of slits.

14. The array substrate according to claim 1, further comprising: A common electrode; the common electrode is located at a side of the pixel electrode away from the substrate, the pixel electrode is electrically connected to the first active layer via a third connecting electrode, and the third connecting electrode and the common electrode are in the same layer structure; The pixel electrode is a planar electrode, and the common electrode has a plurality of slits.

15. The array substrate according to claim 1, wherein: The first active layer includes a channel region, a first region and a second region located at opposite sides of the channel region; the data line is electrically connected to the first region, and the pixel electrode is electrically connected to the second region.

16. A display device, comprising the array substrate, an opposing substrate and a liquid crystal layer according to any one of claims 1 to 15; the array substrate and the opposing substrate are arranged opposite to each other, and the liquid crystal layer is located between the array substrate and the opposing substrate.

17. The display device as described in claim 16 further includes a common electrode; the common electrode is located on a side of the opposing substrate close to the liquid crystal layer; the pixel electrode is provided with at least one first slit, and the common electrode is provided with at least one second slit, and the first slit and the second slit do not overlap in their orthographic projections on the substrate.

18. A method for preparing an array substrate, comprising: forming a data line on one side of the substrate; forming a first transistor on a side of the data line away from the substrate, the first transistor comprising a first active layer and a first gate, the first gate and the first active layer at least partially overlap in an orthographic projection of the substrate, and the data line is electrically connected to the first active layer; The first gate is located on a side of the first active layer away from the substrate; A pixel electrode is formed on a side of the first active layer away from the substrate, and the pixel electrode is electrically connected to the first active layer.

19. The manufacturing method according to claim 18, further comprising forming a storage capacitor after forming the data line; the storage capacitor comprises: A first electrode plate, located on one side of the substrate; as well as The second electrode plate is located at a side of the first electrode plate away from the substrate, and the second electrode plate is arranged opposite to the first electrode plate; the second electrode plate is electrically connected to the pixel electrode.

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