A multi-threaded instruction fetch scheduling system

Abstract

This invention provides a multi-threaded instruction fetching and scheduling system, relating to the field of computer architecture technology. It includes a thread dynamic scheduling module that dynamically updates thread priorities based on polling counts and waiting times, ensuring that each thread has a scheduling opportunity during instruction fetching. This avoids the "thread starvation" problem caused by low-priority threads being unable to fetch instructions for extended periods in traditional fixed-priority methods, thus improving scheduling fairness. Furthermore, when a thread experiences a cache miss, the buffer management module in this invention can suspend the corresponding instruction fetch request, while the scheduling logic can immediately switch to another thread to continue fetching instructions. This prevents a single thread from blocking the entire front-end pipeline, significantly improving the overall system's instruction fetching efficiency, throughput, and effective instruction fetching bandwidth.

Description

Technical Field

[0001] This invention relates to the field of computer architecture technology, and more specifically, to a multi-threaded instruction fetching and scheduling system. Background Technology

[0002] With the widespread application of multithreading technology in processors, multiple hardware threads can execute in parallel to improve instruction-level parallelism and system throughput. In multithreaded processors, the front-end fetch unit and instruction storage structures (such as instruction cache (ICache) and instruction tightly coupled memory (ICCM)) are typically shared by multiple threads. Instruction fetch requests from different threads need to be arbitrated and scheduled within limited cache ports and memory bandwidth resources.

[0003] In existing technologies, multi-threaded instruction fetching scheduling mainly employs the following methods: First, fixed-priority scheduling, where threads fetch instructions according to a pre-defined fixed priority. When high-priority threads remain active, low-priority threads may be unable to obtain instruction fetching opportunities for extended periods, easily leading to thread starvation and insufficient overall system fairness. Second, round-robin scheduling, where the scheduler allocates instruction fetching opportunities to each thread in turn. While this can guarantee fairness among threads to some extent, when a thread experiences a cache miss and enters a waiting state, round-robin scheduling may still continue to allocate instruction fetching slots to it, resulting in ineffective scheduling and reducing effective instruction fetching bandwidth.

[0004] Furthermore, in some architectures, if a fetch request from one thread results in a cache miss, the entire front-end fetch unit will be blocked, preventing timely responses to other threads' executable fetch requests. This global blocking mechanism significantly reduces the throughput of multi-threaded systems. While existing technologies incorporate parity checking or partial error detection mechanisms during instruction cache access, errors often necessitate flushing the entire cache or pausing the entire fetch process, lacking independent isolation and fine-grained recovery capabilities for single-threaded fetch requests.

[0005] Therefore, the scheduling mechanism of existing multi-threaded instruction fetching scheduling systems still has shortcomings in terms of fairness and effective bandwidth utilization, and urgently needs improvement. Summary of the Invention

[0006] The purpose of this invention is to provide a multi-threaded instruction fetching and scheduling system to improve the aforementioned problems. To achieve this objective, the technical solution adopted by this invention is as follows:

[0007] This application provides a multi-threaded instruction fetching and scheduling system, including:

[0008] The storage control module is used to receive, store and execute instruction fetch requests, and determine whether the instruction fetch request hits the instruction cache. When the first instruction fetch request hits the instruction cache, the storage control module receives the data corresponding to the first instruction fetch request returned by the instruction cache and transmits it to the instruction fetch unit.

[0009] The buffer management module is used to receive and manage the second instruction fetch request when the second instruction fetch request does not hit the instruction cache.

[0010] When the external bus returns the first data corresponding to the second fetch request, the buffer management module feeds back the return result to the storage control module. The storage control module writes the first data back to its corresponding fetch path according to the return result, and at the same time updates the state of the thread corresponding to the second fetch request to the fetchable state.

[0011] The thread dynamic scheduling module is used to update the priority of the first thread according to the polling count and waiting time of the first thread in each scheduling cycle, and generate a scheduling result based on the priorities of multiple first threads at the end of each scheduling cycle, and transmit the scheduling result to the storage control module, wherein the first thread is the thread in the storage control module that is in the fetchable state corresponding to the fetch request.

[0012] After receiving the scheduling result, the storage control module executes the second thread based on the scheduling result.

[0013] As a preferred embodiment of the present invention, the storage control module includes a thread identifier register module and a multi-source instruction storage arbitration module;

[0014] The thread identifier register module is used to attach a thread identifier to the instruction fetch request when the instruction fetch request enters the instruction fetch unit. The thread identifier is registered in a hardware register and is used to indicate the thread to which the instruction fetch request belongs.

[0015] The multi-source instruction storage arbitration module is used to receive instruction fetch requests, determine the address range based on the instruction fetch address corresponding to the instruction fetch request, and determine whether the instruction fetch request hits the instruction cache if the address range of the instruction fetch request falls into the address range corresponding to the instruction cache.

[0016] When multiple threads initiate instruction fetch requests at the same time, the multi-source instruction storage arbitration module determines the target thread in the current scheduling period based on the scheduling result output by the thread dynamic scheduling module of the previous scheduling period, and executes the instruction fetch request corresponding to the target thread. The scheduling result includes the first thread identifier of the target thread, which is used to instruct the multi-source instruction storage arbitration module to select the instruction fetch path of the instruction fetch request corresponding to the first thread identifier.

[0017] As a preferred embodiment of the present invention, the multi-source instruction storage arbitration module is connected to the instruction cache, the instruction tightly coupled memory, and the bypass path;

[0018] When the multi-source instruction storage arbitration module executes an instruction fetch request, if the fetch address corresponding to the instruction fetch request falls within the address range corresponding to the instruction tightly coupled memory, the instruction fetch request is routed to the instruction tightly coupled memory; if the fetch address corresponding to the instruction fetch request falls within the address range corresponding to the instruction cache, a determination is made as to whether the instruction fetch request has hit the instruction cache; if the fetch address corresponding to the instruction fetch request falls within the address range corresponding to the bypass path, the instruction fetch request initiates a bus access via the bypass path, and after the main memory or peripheral returns data, the multi-source instruction storage arbitration module feeds back the information to the thread corresponding to the instruction fetch request.

[0019] As a preferred embodiment of the present invention, a priority register is allocated to each thread to record the current priority value of the thread;

[0020] During system initialization, the priority register unit for each thread is set to the same initial value;

[0021] At the beginning of each scheduling cycle, the thread dynamic scheduling module receives the status information of each thread. The status information includes the thread identifier, whether it is in a fetchable state, whether it is in a cache miss waiting state, and the waiting time and polling count corresponding to the thread.

[0022] The thread dynamic scheduling module updates the priority of each thread based on the state information of each thread;

[0023] After updating the priorities of all threads, the second thread identifier is transmitted to the multi-source instruction storage arbitration module. The second thread identifier is the thread identifier corresponding to the thread with the highest priority.

[0024] As a preferred embodiment of the present invention, updating the priority of each thread based on the state information of each thread includes:

[0025] If a thread is in a buffer waiting state, its corresponding priority remains unchanged or decays, and it does not participate in the scheduling of the current scheduling cycle.

[0026] If a thread is in a fetchable state and was not selected in the previous scheduling cycle, its waiting time increments, and its corresponding priority value increments by a preset value.

[0027] If a thread is selected to fetch instructions in the current cycle, the value of its corresponding priority is restored to the initial value;

[0028] If the waiting time of a thread exceeds a preset waiting time threshold, the value of its corresponding priority will be increased.

[0029] As a preferred embodiment of the present invention, when the buffer management module receives the second instruction fetch request, the buffer management module generates and stores a record based on the second instruction fetch request. The record includes the thread identifier, the instruction fetch address, the access type, and the current status information corresponding to the second instruction fetch request. One record corresponds to one second instruction fetch request, and the record is used for parallel queuing of the second instruction fetch requests corresponding to different threads.

[0030] When the bus returns the data required for the second fetch request, the buffer management module feeds back the return result corresponding to the second fetch request along with the thread identifier to the multi-source instruction storage arbitration module, so that the multi-source instruction storage arbitration module can resume the fetch execution of the thread corresponding to the second fetch request.

[0031] As a preferred embodiment of the present invention, it also includes an error detection and isolation module;

[0032] During the instruction fetch process, the error detection and isolation module performs parity checks or error detection and correction on the data from the instruction tightly coupled memory and the instruction cache.

[0033] As a preferred embodiment of the present invention, if the error detection and isolation module detects a single-bit error in the second data, it corrects the second data online and rewrites the corrected second data back to storage; if a multi-bit error is detected in the third data, it only blocks the instruction fetch request of the thread corresponding to the third data and notifies the system through an exception mechanism.

[0034] The beneficial effects of this invention are as follows:

[0035] The thread dynamic scheduling module of this invention can dynamically update the thread priority based on the thread polling count and waiting time, so that each thread can get a scheduling opportunity during the instruction fetching process. This avoids the "thread starvation" problem in the traditional fixed priority method, where low-priority threads cannot fetch instructions for a long time, and improves scheduling fairness. At the same time, when a thread experiences a cache miss, the buffer management module of this invention suspends the instruction fetching request of the corresponding thread, and the scheduling logic can immediately switch to other threads to continue fetching instructions. This avoids a single thread blocking the entire front-end pipeline and significantly improves the overall instruction fetching efficiency, throughput and effective instruction fetching bandwidth of the system.

[0036] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing embodiments of the invention. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of a multi-threaded instruction fetching and scheduling system according to an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of another structure of a multi-threaded instruction fetching and scheduling system described in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the dynamic weighted scheduling process of a multi-threaded instruction fetching scheduling system as described in an embodiment of the present invention.

[0041] Figure 4 This is a schematic diagram of the multi-threaded instruction fetching process of a multi-threaded instruction fetching scheduling system according to an embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0043] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0044] Example 1:

[0045] This embodiment provides a multi-threaded instruction fetching and scheduling system.

[0046] It should be noted that, to avoid ambiguity, the English names used in this embodiment will be explained uniformly as follows:

[0047] PC stands for program counter;

[0048] TID is the thread identifier;

[0049] ICache is an instruction cache;

[0050] ICCM stands for instruction tightly coupled memory;

[0051] The Bypass path is a bypass path;

[0052] miss indicates that a cache miss occurred in a certain thread;

[0053] ECC stands for Error Detection and Correction.

[0054] See Figure 1 The diagram shows that the system includes:

[0055] The storage control module is used to receive, store and execute instruction fetch requests, and determine whether the instruction fetch request hits the instruction cache. When the first instruction fetch request hits the instruction cache, the storage control module receives the data corresponding to the first instruction fetch request returned by the instruction cache and transmits it to the instruction fetch unit.

[0056] The buffer management module is used to receive and manage the second instruction fetch request when the second instruction fetch request does not hit the instruction cache.

[0057] When the external bus returns the first data corresponding to the second fetch request, the buffer management module feeds back the return result to the storage control module. The storage control module writes the first data back to its corresponding fetch path according to the return result, and at the same time updates the state of the thread corresponding to the second fetch request to the fetchable state.

[0058] The thread dynamic scheduling module is used to update the priority of the first thread according to the polling count and waiting time of the first thread in each scheduling cycle, and generate a scheduling result based on the priorities of multiple first threads at the end of each scheduling cycle, and transmit the scheduling result to the storage control module, wherein the first thread is the thread in the storage control module that is in the fetchable state corresponding to the fetch request.

[0059] After receiving the scheduling result, the storage control module executes the second thread based on the scheduling result.

[0060] Understandably, this embodiment addresses the issues of insufficient fairness, cache misses blocking other threads, and weak error isolation capabilities in existing multi-threaded processors' instruction fetch scheduling. It proposes a multi-threaded instruction fetch scheduling system based on an improved mechanism. Through buffer management and dynamic priority scheduling strategies, the system achieves high efficiency and reliability in the multi-threaded instruction fetch process, avoids a single thread blocking the entire instruction fetch unit, and improves overall system throughput and operational stability.

[0061] Furthermore, in this embodiment, the storage control module includes a thread identifier register module and a multi-source instruction storage arbitration module;

[0062] like Figure 2 As shown, the PC is the program counter. When an instruction fetch request enters the fetch unit, a unique thread identifier (TID) is attached to it by the thread identifier register module. Each thread identifier is registered in a hardware register and indicates the thread to which the instruction fetch request belongs. The thread identifier, along with the instruction fetch address, is passed to the multi-source instruction storage arbitration module and the miss buffer management module. Through the thread identifier, the source of the request can be distinguished and scheduling independence can be achieved in the multi-threaded instruction fetch process.

[0063] The multi-source instruction store arbitration module connects the instruction cache (ICache), instruction tightly coupled memory (ICCM), and bypass path. The multi-source instruction store arbitration module dynamically selects the instruction fetch path based on the following conditions:

[0064] (1) Address range determination: If the instruction fetch request address falls within the ICCM defined range, the multi-source instruction storage arbitration module will directly route the request to the ICCM and then return the data required by the instruction; if it is a normal cache range, it will enter the ICache; if it is a special bypass access range, the instruction fetch request will initiate bus access through the bypass path, and after the main memory or peripheral device returns the data, the multi-source instruction storage arbitration module will feed back to the corresponding thread.

[0065] (2) Hit status determination: After the instruction fetch request enters the ICache, if the ICache hits, the data is returned directly; if it misses, a miss is initiated. Furthermore, priority control is performed: when multiple threads initiate requests at the same time, the result of the dynamic priority scheduling module determines which thread's request will be executed first.

[0066] (3) When a thread's request misses, the request is sent to the miss buffer management module. The miss buffer records the following: thread identifier (TID), fetch address, access type, and current status information. The miss buffer supports multiple records so that miss requests from different threads can be queued in parallel. During the waiting period for a miss request, the scheduling module will select another thread to continue fetching instructions, ensuring that the pipeline front end is not interrupted. When the external bus returns the required data, the miss buffer management module will send the return result along with the corresponding thread identifier (TID) to the multi-source instruction storage arbitration module. The multi-source instruction storage arbitration module determines the target thread based on the thread identifier, writes the data back to its fetch path, and updates the thread's status to fetchable. At this time, the thread dynamic scheduling module can recalculate the priority and schedule the thread in the next scheduling cycle, thereby achieving automatic recovery after a miss. Therefore, the feedback operation of the miss buffer is equivalent to re-injecting the thread into the multi-source instruction storage arbitration module, enabling it to resume instruction fetching and execution. During this process, the thread dynamic scheduling module only schedules threads that are in the fetchable state within the multi-source instruction storage arbitration module, and does not participate in the arbitration of threads in the miss buffer, thereby avoiding ineffective scheduling of suspended threads.

[0067] Understandably, by setting a miss buffer, when a thread experiences a cache miss, its request can be suspended and queued, while the scheduling logic can immediately switch to other threads to continue fetching instructions. This avoids a single thread blocking the entire front-end pipeline and significantly improves the overall instruction fetching efficiency and throughput of the system.

[0068] The dynamic priority scheduling module, also known as the thread dynamic scheduling module, is based on an improved weighted round-robin mechanism. In this module, the status information of each thread is periodically fed back to the scheduling module. Each thread is allocated a priority register to record its current priority value. During system initialization, the priority registers of all threads are set to the same initial value. At the beginning of each scheduling cycle, the thread dynamic scheduling module dynamically updates the priority of each thread based on its polling count and waiting time: if a thread is in a miss buffer waiting state, its priority remains unchanged or decays according to a set setting, and it does not participate in the current scheduling; if a thread is in an instruction-fetchable state but was not selected in the previous scheduling cycle, its waiting counter increments, and its priority value increases according to a set weight; if a thread is selected to fetch instructions in the current cycle, its priority value is restored to its initial value. Under normal circumstances, each thread takes turns obtaining instruction fetching opportunities in order, ensuring basic fairness in scheduling. If a thread is not scheduled for a long time, its priority counter will automatically increase, allowing it to obtain a higher priority in subsequent arbitrations, thereby preventing thread starvation. If a thread is in a miss waiting state, it is automatically skipped during priority arbitration to avoid invalid instruction fetching. After updating the priorities of all threads, the scheduling module generates a scheduling result based on a weighted round-robin algorithm, selects the thread identifier corresponding to the thread with the highest priority, and transmits it to the multi-source instruction storage arbitration module to control the subsequent instruction fetching path. Through this method, thread scheduling fairness and miss thread isolation are achieved, ensuring that cache misses do not block other threads from fetching instructions, thus improving the effective bandwidth of the instruction fetch frontend and the overall system throughput.

[0069] like Figure 3 As shown, the thread dynamic scheduling module dynamically adjusts the instruction fetching opportunities for all threads within each scheduling cycle. This module updates the weight of each thread in real time based on its polling count and waiting time, thereby improving overall instruction fetching efficiency while ensuring scheduling fairness. During system operation, at the beginning of each scheduling cycle, the thread dynamic scheduling module first reads the status information of all threads, including thread identifier, whether it is in an instruction-fetchable state, whether it is in a cache miss waiting state, and its respective waiting time and polling count. Based on this, the module calculates the current weight value of each thread and uses this weight value as the basis for scheduling priority.

[0070] In a scheduling cycle, the thread dynamic scheduling module selects the thread with the highest weight as a candidate thread based on its weight and determines whether it is in a fetchable state. If the candidate thread is in a cache miss waiting state, the module skips the thread and increases its waiting time to gradually increase its weight in subsequent scheduling cycles. If the candidate thread is in a fetchable state, the multi-source instruction store arbitration module is activated to perform the instruction fetch operation for that thread. After the fetch is completed, the thread's weight is restored to its base value, and its waiting time is reset to zero. Threads that were not selected continue to accumulate their waiting time, gaining a higher weight in the next scheduling cycle and thus increasing their probability of being selected.

[0071] Understandably, in this embodiment, weight is equivalent to priority, used to measure the scheduling order of threads in the current cycle. A thread's weight increases with its waiting time and returns to its base value upon instruction fetching, achieving dynamic and fair scheduling. If a thread is not scheduled for a long time, its weight will gradually increase, eventually being selected first in subsequent cycles, thus effectively avoiding the problem of low-priority threads being unable to fetch instructions for a long time under a fixed-priority approach. On the other hand, when a thread is in a cache miss waiting state, the scheduling module automatically removes it from the current candidates, allowing system resources to be concentrated on threads that can fetch instructions immediately, preventing invalid scheduling.

[0072] The thread dynamic scheduling module selects only the thread with the highest weight to fetch instructions in each scheduling cycle, ensuring the simplicity of the hardware structure and the determinism of the scheduling logic. In systems with multi-port instruction fetching capabilities, several threads with the highest weight can be selected to fetch instructions in parallel within the same cycle to achieve higher fetch bandwidth. In this embodiment, the thread dynamic scheduling module and the multi-source instruction storage arbitration module work together to complete weight updates, candidate thread selection, and status feedback in each clock cycle, forming a closed-loop scheduling control.

[0073] For example, when multiple threads exist in a system, each thread initially has the same weight. As the system runs, the weights of threads that have already fetched instructions are reset, while the weights of unscheduled threads gradually increase as their waiting time grows, thus raising their priority. When a thread's weight exceeds that of other threads, it can get a chance to fetch instructions in the next cycle. In this way, threads with longer waiting times are more likely to be selected, and the entire scheduling process achieves a dynamic balance in time, balancing fairness and efficiency.

[0074] pass Figure 3The dynamic weighted scheduling mechanism shown in this embodiment enables dynamic priority updates based on waiting time and polling count in a multi-threaded instruction fetch system. This mechanism not only ensures that all threads have an opportunity to fetch instructions within a certain period, but also allows for rapid switching to other threads to continue execution in case of exceptions such as cache misses, avoiding front-end blocking during instruction fetching and thus improving the overall instruction fetch bandwidth and execution throughput of the processor.

[0075] Understandably, by introducing a dynamic priority scheduling mechanism based on thread identifiers, combined with a weighted round-robin strategy, each thread can get a scheduling opportunity during the instruction fetching process, thus avoiding the "thread starvation" problem in the traditional fixed priority method where low-priority threads cannot fetch instructions for a long time.

[0076] Furthermore, error detection and isolation mechanisms are included. During the instruction fetching process, parity checks or ECC (Error Detection and Correction) are performed on the data from ICache and ICCM. If a single-bit error is detected, the system corrects the data online and rewrites the corrected data back to storage. If a multi-bit error is detected, only the instruction fetch request of the corresponding thread is blocked, and the system is notified through an exception mechanism. The instruction fetching process of other threads is unaffected and can still be scheduled and executed as usual, thereby ensuring the overall stability and efficiency of the system.

[0077] Understandably, introducing an error detection and isolation mechanism during the instruction fetch process allows for the pause or correction of the instruction fetch process only for the thread where the error occurred when a storage error is detected in the instruction cache or tightly coupled instruction memory. Other threads remain unaffected, thereby achieving thread-level error isolation and recovery and ensuring operational stability in a multi-threaded processing environment.

[0078] The overall workflow of the multi-threaded instruction fetching and scheduling system in this embodiment is as follows: Figure 4 As shown:

[0079] In this process, the thread dynamic scheduling module and the multi-source instruction storage arbitration module work together in a periodic alternation. Within the current clock cycle, the multi-source instruction storage arbitration module executes the instruction fetch operation for the corresponding thread based on the scheduling result output by the thread dynamic scheduling module in the previous cycle, and performs address determination, hit detection, and path selection on the instruction fetch request. After the instruction fetch is completed, the multi-source instruction storage arbitration module feeds back the execution status, hit flag, and thread identifier of the corresponding thread to the thread dynamic scheduling module. Upon receiving the feedback information, the thread dynamic scheduling module dynamically updates the priority based on the hit status, waiting time, and polling count of each thread within the current cycle, and generates the scheduling result for the next cycle. This scheduling result is then executed by the multi-source instruction storage arbitration module in subsequent clock cycles, thus forming a closed-loop control process in time: "arbitration execution—status feedback—priority update—scheduling decision—next cycle arbitration execution." Through this alternating collaborative mechanism, the system can maintain the continuity of instruction fetching while achieving seamless connection between scheduling decisions and execution arbitration, ensuring the fairness and efficiency of the multi-threaded instruction fetching process.

[0080] Specifically, the overall workflow of a multi-threaded instruction fetching and scheduling system is as follows:

[0081] The multi-threaded instruction fetching and scheduling system in this embodiment is equipped with a storage control module, a buffer management module, a thread scheduling module, and an error detection and isolation module. The storage control module includes a multi-source instruction storage arbitration module and a thread identifier register module.

[0082] When an instruction fetch request enters the multi-threaded instruction fetch scheduling system, the thread identifier register module adds a thread identifier to the instruction fetch request.

[0083] At the beginning of each scheduling cycle, the thread dynamic scheduling module updates the priority of the first thread according to the polling count and waiting time of the first thread, and at the end of each scheduling cycle, generates a scheduling result based on the priorities of multiple first threads, and transmits the scheduling result to the multi-source instruction storage arbitration module. The multi-source instruction storage arbitration module executes the second thread based on the scheduling result. The first thread is the thread corresponding to the instruction fetch request in the storage control module. The scheduling result includes the thread identifier corresponding to the second thread.

[0084] If multiple threads initiate instruction fetch requests at the same time, the multi-source instruction storage arbitration module determines the execution order of the threads based on the scheduling result generated by the thread dynamic scheduling module.

[0085] The multi-source instruction storage arbitration module selects the fetch path based on the address of the fetch request. The fetch path includes fetching from the instruction cache, fetching from the instruction tightly coupled memory, and fetching via a bypass path.

[0086] If the fetch address corresponding to the third fetch request falls within the address range corresponding to the instruction cache, the multi-source instruction storage arbitration module determines whether the fetch request hits the instruction cache.

[0087] If the third instruction fetch request hits the instruction cache, the data corresponding to the third instruction fetch request is returned to the storage control module and then returned to the instruction fetch unit.

[0088] If the third instruction fetch request hits the instruction cache but misses, the third instruction fetch request is sent to the buffer management module.

[0089] During the instruction fetching process, the error detection and isolation module performs real-time data verification and thread-level isolation processing for errors.

[0090] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0091] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-threaded instruction fetching and scheduling system, characterized in that, include: The storage control module is used to receive, store and execute instruction fetch requests, and determine whether the instruction fetch request hits the instruction cache. When the first instruction fetch request hits the instruction cache, the storage control module receives the data corresponding to the first instruction fetch request returned by the instruction cache and transmits it to the instruction fetch unit. The buffer management module is used to receive and manage the second instruction fetch request when the second instruction fetch request does not hit the instruction cache. When the external bus returns the first data corresponding to the second fetch request, the buffer management module feeds back the return result to the storage control module. The storage control module writes the first data back to its corresponding fetch path according to the return result, and at the same time updates the state of the thread corresponding to the second fetch request to the fetchable state. The thread dynamic scheduling module is used to update the priority of the first thread according to the polling count and waiting time of the first thread in each scheduling cycle, and generate a scheduling result based on the priorities of multiple first threads at the end of each scheduling cycle, and transmit the scheduling result to the storage control module, wherein the first thread is the thread in the storage control module that is in the fetchable state corresponding to the fetch request. After receiving the scheduling result, the storage control module executes the second thread based on the scheduling result; Each thread is allocated a priority register to record the current priority value of that thread; During system initialization, the priority register unit of each thread is set to the same initial value; at the beginning of each scheduling cycle, the thread dynamic scheduling module receives the status information of each thread, which includes the thread identifier, whether it is in the fetchable state, whether it is in the cache miss waiting state, and the waiting time and polling number corresponding to the thread; the thread dynamic scheduling module updates the priority of each thread based on the status information of each thread. The update of the priority of each thread based on the state information of each thread includes: If a thread is in a buffer waiting state, its corresponding priority remains unchanged or decays, and it does not participate in the scheduling of the current scheduling cycle. If a thread is in an instruction-fetchable state and was not selected in the previous scheduling cycle, its waiting time increments, and its corresponding priority value increases by a preset value; if a thread is selected to fetch instructions in the current cycle, its corresponding priority value is restored to the initial value.

2. The multi-threaded instruction fetching and scheduling system according to claim 1, characterized in that, The storage control module includes a thread identifier register module and a multi-source instruction storage arbitration module; The thread identifier register module is used to attach a thread identifier to the instruction fetch request when the instruction fetch request enters the instruction fetch unit. The thread identifier is registered in a hardware register and is used to indicate the thread to which the instruction fetch request belongs. The multi-source instruction storage arbitration module is used to receive instruction fetch requests, determine the address range based on the instruction fetch address corresponding to the instruction fetch request, and determine whether the instruction fetch request hits the instruction cache if the address range of the instruction fetch request falls into the address range corresponding to the instruction cache. When multiple threads initiate instruction fetch requests at the same time, the multi-source instruction storage arbitration module determines the target thread in the current scheduling period based on the scheduling result output by the thread dynamic scheduling module in the previous scheduling period, and executes the instruction fetch request corresponding to the target thread. The scheduling result includes the first thread identifier of the target thread, which is used to instruct the multi-source instruction storage arbitration module to select the instruction fetch path of the instruction fetch request corresponding to the first thread identifier.

3. The multi-threaded instruction fetching and scheduling system according to claim 2, characterized in that, The multi-source instruction storage arbitration module is connected to the instruction cache, the instruction tightly coupled memory, and the bypass path; When the multi-source instruction storage arbitration module executes an instruction fetch request, if the fetch address corresponding to the instruction fetch request falls within the address range corresponding to the instruction tightly coupled memory, the instruction fetch request is routed to the instruction tightly coupled memory; if the fetch address corresponding to the instruction fetch request falls within the address range corresponding to the instruction cache, a determination is made as to whether the instruction fetch request has hit the instruction cache; if the fetch address corresponding to the instruction fetch request falls within the address range corresponding to the bypass path, the instruction fetch request initiates a bus access via the bypass path, and after the main memory or peripheral returns data, the multi-source instruction storage arbitration module feeds back the information to the thread corresponding to the instruction fetch request.

4. The multi-threaded instruction fetching and scheduling system according to claim 2, characterized in that, After updating the priorities of all threads, the second thread identifier is transmitted to the multi-source instruction storage arbitration module. The second thread identifier is the thread identifier corresponding to the thread with the highest priority.

5. The multi-threaded instruction fetching and scheduling system according to claim 1, characterized in that, The update of the priority of each thread based on the state information of each thread also includes: If the waiting time of a thread exceeds a preset waiting time threshold, the value of its corresponding priority will be increased.

6. The multi-threaded instruction fetching and scheduling system according to claim 2, characterized in that, When the buffer management module receives the second instruction fetch request, the buffer management module generates and stores a record based on the second instruction fetch request. The record includes the thread identifier, instruction fetch address, access type and current status information corresponding to the second instruction fetch request. One record corresponds to one second instruction fetch request. The record is used for parallel queuing of second instruction fetch requests corresponding to different threads. When the bus returns the data required for the second fetch request, the buffer management module feeds back the return result corresponding to the second fetch request along with the thread identifier to the multi-source instruction storage arbitration module, so that the multi-source instruction storage arbitration module can resume the fetch execution of the thread corresponding to the second fetch request.

7. The multi-threaded instruction fetching and scheduling system according to claim 3, characterized in that, It also includes an error detection and isolation module; During the instruction fetch process, the error detection and isolation module performs parity checks or error detection and correction on the data from the instruction tightly coupled memory and the instruction cache.

8. The multi-threaded instruction fetching and scheduling system according to claim 7, characterized in that, If the error detection and isolation module detects a single-bit error in the second data, it corrects the second data online and rewrites the corrected second data back to storage; if it detects a multi-bit error in the third data, it only blocks the instruction fetch request of the thread corresponding to the third data and notifies the system through an exception mechanism.

Images