Cutting channel layout tool verification method, electronic equipment and readable storage medium

Abstract

The invention provides a scribe line layout tool verification method, electronic equipment and a readable storage medium. The method comprises the following steps: acquiring standard scribe line layout data; generating to-be-tested scribe line layout data by using a to-be-verified tool; intercepting a first group of verification data containing standard target graph unit data and standard blank cutting channel data based on standard cutting channel layout data; positioning and intercepting a second group of verification data corresponding to the first group of verification data through the unit name based on to-be-tested scribe line layout data; and performing exclusive-OR logic operation comparison on corresponding data in the two groups of verification data, and verifying the tool according to a comparison result. According to the method, data interception and comparison are performed based on the unit names instead of physical coordinates, so that massive false differences caused by different positions of the target graph units are effectively avoided, and efficient, accurate and automatic verification of the layout generation tool is realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for verifying dicing layout tools, an electronic device, and a readable storage medium. Background Technology

[0002] The photomask data used in integrated circuit manufacturing includes scribe / frame data, which represents the area between chips where target graphic units (items) such as photolithographic marks, measurement patterns, and process monitoring structures are placed. Scribe / frame layout data is typically generated using electronic design automation (EDA) tools. Due to various factors such as price or policy, new tools may be used during production. Using new scribe / frame creation tools, especially newly developed ones, may introduce undiscovered problems, potentially leading to errors in the scribe / frame layout data, ultimately resulting in photomask errors or wafer scrap. Therefore, tool verification is necessary beforehand.

[0003] The main focus is on verifying the following two basic functions of the tool:

[0004] 1. Generate the cutting path layer for each layer according to the cutting path attribute requirements;

[0005] 2. Place the target graphic units that need to be placed on the cutting channel according to certain rules, and at the same time, dig out the cutting channel graphic of each layer at the corresponding position.

[0006] The existing verification method for cut-out layout tools is as follows:

[0007] 1. Prepare standard cutting path layout data;

[0008] 2. Use the cutter layout tool to create the cutter layout data to be tested;

[0009] 3. Perform an XOR logical operation directly between the cut pattern data to be tested and the standard cut pattern data;

[0010] 4. Visually inspect the cut pattern data and XOR results to determine if there is a problem with the cut pattern creation tool.

[0011] Problems with existing methods:

[0012] For target graphic units that need to be placed in large numbers on the dicing track, such as process monitoring structures, photolithography marks, and measurement patterns, the tool has an algorithm to flexibly distribute them in the dicing track. However, the algorithms of different tools may be different, resulting in the same target graphic unit not being able to be completely consistent in the layout data generated by different tools. This leads to many differences in the XOR results, and manual visual judgment of differences is inefficient and cannot guarantee that the same target graphic unit is completely consistent in the layout data generated by different tools. Summary of the Invention

[0013] The technical problem to be solved by the present invention is to provide a method for verifying cut-out layout tools, an electronic device, and a computer-readable storage medium, so as to overcome the problems of difficult and inefficient layout verification caused by the difference in the position of target graphic units in the prior art.

[0014] To achieve the above objectives, the present invention provides a method for verifying cut track layout tools, comprising:

[0015] Step 1: Obtain standard cutting path layout data;

[0016] Step 2: Use the cut pattern creation tool to generate the cut pattern data to be tested;

[0017] Step 3: Based on the standard cut track layout data, extract the first set of verification data, which includes standard target graphic unit data and standard blank cut track data;

[0018] Step 4: Based on the cut pattern data to be tested, extract the second set of verification data. The second set of verification data includes the target graphic unit data to be tested corresponding to the standard target graphic unit data, and the blank cut pattern data to be tested.

[0019] Step 5: Perform an XOR operation on each data point in the first set of verification data and the corresponding data in the second set of verification data to compare them. Based on the comparison results, verify the tool for creating the cut-out layout.

[0020] Preferably, in step three, the first set of verification data is extracted, including:

[0021] Obtain the cell window and cell name of each target graphic unit placed in the standard cutting path layout data;

[0022] Extract standard target graphic unit data from the standard cutting path layout data based on the unit window;

[0023] In the standard cut track layout data, extract the standard blank cut track data in the area where no target graphic unit is placed.

[0024] Preferably, in step three, the standard blank cutting track data consists of multiple sets, which are obtained by capturing areas where no target graphic units are placed in a window of a predetermined size.

[0025] Preferably, in step four, the second set of verification data is extracted, including:

[0026] Using the cell name, search for and locate the corresponding target graphic cell in the cut pattern data to be tested;

[0027] The target graphic unit is located in the unit window of the cutting path layout data to be tested after positioning, and the target graphic unit data to be tested is extracted accordingly.

[0028] Preferably, in step four, the cut position, window size, and number of blank cut track data to be tested correspond to the standard blank cut track data.

[0029] Preferably, step three further includes: generating a standard layout database based on the intercepted standard target graphic unit data and standard blank cutting channel data;

[0030] Step four also includes: generating a test layout database based on the extracted target graphic unit data and blank cutting channel data.

[0031] Preferably, in step five, the XOR logic comparison is performed separately for each layout level;

[0032] The comparison results include: no difference, or a level of difference;

[0033] If all data comparisons show no difference, the tool for creating the cut-out layout is deemed to have passed verification.

[0034] Preferably, in step five, if the comparison result shows that there is a difference level, it is determined whether the difference level belongs to the exemptable difference; if so, it is determined that the cutting path layout creation tool has passed the verification.

[0035] Preferably, in the cut pattern data to be tested generated using the cut pattern creation tool, the placement position of the target graphic unit is not exactly the same as the placement position of the target graphic unit in the standard cut pattern data.

[0036] Preferably, the target graphic unit includes photolithographic marks, measurement patterns, or process monitoring structures; the kerf layout data includes kerf layer patterns that are cut out at the location of the target graphic unit.

[0037] To achieve the above objectives, the present invention also provides an electronic device, comprising:

[0038] processor;

[0039] Memory used to store processor-executable instructions;

[0040] The processor is configured to implement any of the above methods when executing instructions.

[0041] To achieve the above objectives, the present invention also provides a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, implement the method described above.

[0042] As described above, the cutting path layout tool verification method of the present invention has the following beneficial effects:

[0043] This invention eliminates discrepancies caused by inconsistent target graphic unit positions due to different tool layout algorithms by extracting and comparing data based on unit names rather than physical coordinates. This allows verification to accurately focus on the correctness of the unit content itself. Simultaneously, comprehensive verification of the target graphic units and blank cutting areas ensures the generation quality of both functional modules and background layouts. The entire verification process is clear and easily automated, significantly replacing inefficient and error-prone manual visual inspection, drastically reducing the verification cycle from hours to minutes. The final difference report intuitively pinpoints problems to specific units and levels, significantly accelerating tool debugging and import processes. Attached Figure Description

[0044] Figure 1 The diagram shown is a flowchart illustrating a method for verifying a cutting path layout tool according to the present invention.

[0045] Figure 2 The diagram shows the cutting path layout data of the standard of this invention.

[0046] Figure 3 The diagram shows the cutting path layout data to be tested in this invention.

[0047] Figure 4 This diagram illustrates the process by which the present invention extracts the first set of verification data from standard cutting path layout data.

[0048] Figure 5 This diagram illustrates the process by which the present invention extracts the second set of verification data from the cut path layout data to be tested.

[0049] Figure 6 The diagram shows the verification data comparison process and results of this invention. Detailed Implementation

[0050] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] Please see Figure 1 , Figure 1 This is a flowchart illustrating a method for verifying dicing layout tools according to an embodiment of the present invention. In integrated circuit manufacturing, the dicing area is not only used for wafer dicing but also densely distributed with various key auxiliary patterns. Verifying the accuracy of the dicing layout creation tool is of significant economic importance for ensuring photomask quality and avoiding wafer scrap. The method of this embodiment can effectively avoid false alarms caused by non-substantial positional deviations due to differences in different tool algorithms, and intuitively and accurately check whether the data of each target pattern unit is correctly placed in the new tool. Furthermore, this method is easy to automate through programming, and compared to manual visual inspection, it has high accuracy and saves a significant amount of time.

[0052] Step 1: Obtain standard cut track layout data. For example... Figure 2 As shown, standard cut track layout data, to ensure correct layout data, can be generated by a verified layout tool or other methods. It includes the complete cut track and the target graphic units to be placed (Item1 and Item2 in the figure). The data format can be the industry-standard GDSII or OASIS format.

[0053] In some embodiments, the target patterning unit includes lithographic marks, measurement patterns, or process monitoring structures; the kerf layout data includes kerf layer patterns with cutouts at the target patterning unit location. Specifically, lithographic marks may include various marks used for alignment between different lithography machines; measurement patterns may include bar patterns for critical dimension scanning electron microscopy measurements, box-in-box or grating-type targets for overlay error measurements; and process monitoring structures may include active device arrays, resistance and capacitance test structures, etc., for electrical parameter testing. If the tool generates auxiliary layers on the target patterning unit, such as optical proximity correction (OPC) blocking layers or dummy fill blocking layers, this method can also be used for inspection.

[0054] Step 2: Use the cutter layout creation tool to generate the cutter layout data to be tested. For example... Figure 3As shown, the tool to be verified can be a new version of an existing electronic design automation tool, an alternative tool from a different vendor, or an automation script developed in-house. The generation process must call the same technical documents and design rules as the standard data. The original layout of its cutaway hierarchy and the placement of target graphic units must be identical to the standard cutaway layout data.

[0055] In some embodiments, the placement of target graphic units in the cutter layout data generated by the cutter layout creation tool to be verified is not exactly the same as the placement of target graphic units in the standard cutter layout data. This is because different tools have different automatic placement algorithms when handling complex cutter space reuse, resulting in the same target graphic unit (such as...) being placed differently. Figure 3 Compared to Item1 and Item2 in the middle Figure 2 The position of the map data generated by different tools cannot be completely consistent due to changes in the position of the map data. The method in this embodiment is designed to solve this problem and avoid the differences caused by slight coordinate shifts in traditional full-map comparison methods.

[0056] Step 3: Based on the standard cut track layout data, extract the first set of verification data. The first set of verification data includes standard target graphic unit data and standard blank cut track data. For example... Figure 4 As shown, this step can be implemented using layout tools such as KLayout or layout-related application programming interfaces (APIs).

[0057] In some embodiments, step three, capturing the first set of verification data, includes: obtaining the unit window and unit name of each target graphic unit placed in the standard cut track layout data; capturing standard target graphic unit data from the standard cut track layout data according to the unit window; and capturing standard blank cut track data in areas where no target graphic units are placed in the standard cut track layout data. By identifying the unit name, each functional module can be accurately located. Unit window (e.g., ...) Figure 4 The Item capture window defines the boundary range of the cell, ensuring that the captured data includes all the front and back hierarchy information involved in the cell.

[0058] In some embodiments, in step three, the standard blank cutting track data consists of multiple sets, arranged according to a predetermined window size (e.g., ...). Figure 4 The blank cut path capture window (in the image) is a capture of an area where no target graphic unit is placed. The number and size of this capture window can be customized; the more windows, the more accurate the verification results. Selecting multiple sets of blank areas at different locations allows for a more comprehensive verification of the tool's stability in generating cut path layers, such as verifying whether the metal fill density in different areas meets the requirements, or whether the dicing groove openings are continuous.

[0059] In some embodiments, step three further includes: generating a standard layout database based on the captured standard target graphic unit data and standard blank cutting path data. For example... Figure 4 As shown, the extracted standard data are aggregated to form a standard layout database, which includes standard layout data for Item1, standard layout data for Item2, and multiple sets of blank cutting path standard layout data. The standard layout database can be created once and reused multiple times, significantly improving efficiency, especially when regression testing of the same tool is required.

[0060] Step 4: Based on the cut pattern data to be tested, extract the second set of verification data. The second set of verification data includes the target graphic unit data to be tested corresponding to the standard target graphic unit data, and the blank cut pattern data to be tested. For example... Figure 5 As shown, this step can also be achieved using layout tools or layout-related application programming interfaces (APIs).

[0061] In some embodiments, step four, capturing the second set of verification data, includes: using the unit name, searching for and locating the corresponding target graphic unit in the cutter layout data to be tested; obtaining the unit window of the located target graphic unit in the cutter layout data to be tested, and capturing the target graphic unit data to be tested accordingly. Based on the unit name of the target graphic unit placed in the standard cutter layout data, finding units with the same name (such as Item1 and Item2) in the cutter layout data to be tested, and obtaining their unit windows.

[0062] In some embodiments, in step four, the truncated position, window size, and number of blank cut track data to be tested correspond to those of the standard blank cut track data. This ensures the consistency of the background area comparison and enables timely detection of systematic errors that the new tool may introduce when generating the basic cut track structure.

[0063] In some embodiments, step four further includes: generating a layout database based on the extracted target graphic unit data and blank cutting channel data. For example... Figure 5 As shown, the data extracted from the test layout data are collected to form a test layout database.

[0064] Step 5: Perform an XOR operation on each data point in the first set of verification data and the corresponding data in the second set of verification data to compare them. Based on the comparison results, verify the tool for creating the cut-out layout.

[0065] In some embodiments, in step five, the XOR logic comparison is performed separately for each layout level; the comparison results include: no difference, or a difference exists at a certain level; if the comparison results for all data are no difference, then the tool verification for creating the cut-out layout is deemed successful. Figure 6 As shown, each data point in the test layout database is compared one by one with its logically corresponding data in the standard layout database using an XOR operation. Modern integrated circuit layouts contain dozens to hundreds of process layers, including active areas, gates, contact holes, vias, and multilayer metal interconnects. Layer-by-layer comparison can precisely identify which specific layer has a generation error. A test layout can be generated as shown... Figure 6 The report, shown in the table at the bottom, which includes target graphical units and levels of difference, visually displays the verification results.

[0066] In some embodiments, in step five, if the comparison result indicates the existence of a difference level, it is determined whether the difference level belongs to the exemptable difference category; if so, the cut-track layout creation tool verification is deemed successful. Not all XOR differences imply fatal errors. For example, differences in certain text layers used only for annotation, or auxiliary recognition layers that do not participate in actual lithography imaging, can be exempted after engineering evaluation. This method supports generating detailed reports containing a list of difference levels, assisting engineers in making rapid decisions.

[0067] The present invention also provides an electronic device, including a processor and a memory, wherein the memory stores computer program instructions, and the processor executes the computer program instructions to implement the method of any of the above embodiments. The electronic device can be a general-purpose computing device or a special-purpose computing device. For example, the electronic device can be implemented as various computing systems, such as servers, workstations, personal computers, laptops, or computing clusters specifically configured for electronic design automation tasks. In one embodiment, the electronic device may include one or more processors, memory, input / output (I / O) interfaces, and a system bus for coupling various components of the system. The processor can be any type of processing unit, such as, but not limited to: a general-purpose central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, a system-on-a-chip (SoC), discrete gate or transistor logic devices, or a processing core composed of any combination of the above devices. The memory may include volatile memory, such as random access memory (RAM), which may include static random access memory (SRAM) or dynamic random access memory (DRAM); and / or non-volatile memory, such as read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD). The electronic device may also include a communication interface for receiving standard cut-track layout data from a layout database or sending verification reports to user terminals via a network (e.g., a local area network, a wide area network, or the Internet).

[0068] The present invention also provides a non-transitory computer-readable storage medium storing computer program instructions thereon, which, when executed by a processor, implement the methods of any of the above embodiments. The non-transitory computer-readable storage medium can be any tangible medium capable of carrying or storing instructions for use by an instruction execution system, apparatus, or device. For example, a non-transitory computer-readable storage medium can be, but is not limited to: electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), and floppy disks. It should be noted that the non-transitory computer-readable storage medium used herein should not be construed as a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0069] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0070] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for verifying a cutting path layout tool, characterized in that, The method comprises the following steps: Step 1: obtaining standard cutting path layout data; Step 2: generating test cutting path layout data by using a cutting path layout creation tool to be verified; Step 3: based on the standard cutting path layout data, a first group of verification data is intercepted, which comprises standard target pattern cell data and standard blank cutting path data; Step 4: based on the test cutting path layout data, a second group of verification data is intercepted, which comprises test target pattern cell data corresponding to the standard target pattern cell data and test blank cutting path data; Step 5: performing exclusive-OR logical operation comparison between each data in the first group of verification data and corresponding data in the second group of verification data, and verifying the cutting path layout creation tool according to the comparison result.

2. The method of claim 1, wherein: In Step 3, the interception of the first group of verification data comprises: obtaining the cell window and cell name of each target pattern cell placed in the standard cutting path layout data; intercepting the standard target pattern cell data from the standard cutting path layout data according to the cell window; and intercepting the standard blank cutting path data in the region of the standard cutting path layout data where no target pattern cell is placed.

3. The method of claim 2, wherein: In Step 3, the standard blank cutting path data is obtained by intercepting in the region where no target pattern cell is placed according to a predetermined size of window.

4. The method of claim 1, wherein: In Step 4, the interception of the second group of verification data comprises: searching and locating corresponding target pattern cells in the test cutting path layout data by using the cell name; obtaining the cell window of the located target pattern cells in the test cutting path layout data, and intercepting the test target pattern cell data according to the cell window.

5. The method of claim 4, wherein: In Step 4, the interception position, window size and number of the test blank cutting path data correspond to those of the standard blank cutting path data.

6. The method of claim 1, wherein: In Step 3, it further comprises: generating a standard layout database based on the intercepted standard target pattern cell data and standard blank cutting path data; and in Step 4, it further comprises: generating a test layout database based on the intercepted test target pattern cell data and test blank cutting path data.

7. The method of claim 1, wherein: In Step 5, the exclusive-OR logical operation comparison is performed for each layout level respectively; the comparison result comprises: no difference or difference level; if the comparison result of all data is no difference, it is determined that the cutting path layout creation tool passes the verification.

8. The method of claim 7, wherein: In Step 5, if the comparison result is a difference level, it is determined whether the difference level belongs to an excusable difference; if yes, it is determined that the cutting path layout creation tool passes the verification.

9. The method of claim 1, wherein: The placement position of the target pattern cell in the test cutting path layout data generated by using the cutting path layout creation tool to be verified is not completely the same as that of the target pattern cell in the standard cutting path layout data.

10. The method of claim 1, wherein: The target pattern cell comprises a lithography mark, a measurement pattern or a process monitoring structure; and the cutting path layout data comprises a cutting path level pattern hollowed at the position of the target pattern cell.

11. An electronic device, comprising: comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the method of any one of claims 1 to 10 when executing the instructions.

12. A computer-readable storage medium having stored thereon computer program instructions, wherein, the computer program instructions implementing the method of any one of claims 1 to 10 when executed by a processor. the computer program instructions implementing the method of any one of claims 1 to 10 when executed by a processor.

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