A method, apparatus, medium, and equipment for detecting wafer defects.

Abstract

This application relates to the field of semiconductor manufacturing technology, specifically disclosing a wafer defect detection method, apparatus, medium, and device. The method includes: image processing of the original wafer image of the wafer to be tested to obtain a target wafer image; performing annular region division and multi-scale feature extraction processing on the target wafer image to obtain several initial feature maps of different scales corresponding to each annular region; using the target symmetry group equivariant convolutional network submodule in the target detection model to extract features from each initial feature map of each annular region to obtain several target feature maps corresponding to each initial feature map; using the target fusion module in the target detection model to fuse the features of each target feature map to obtain a fused target global feature vector; and performing chip-level defect detection and wafer-level defect detection on the target global feature vector based on the target defect detection module in the target detection model to obtain a target detection result.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a wafer defect detection method, apparatus, medium and equipment. Background Technology

[0002] Wafer chips are the critical carriers in semiconductor manufacturing, and their manufacturing quality directly affects the electrical performance, power consumption, and long-term reliability of integrated circuits. Wafer fabrication typically involves multiple complex processes, including oxidation, photolithography, etching, ion implantation, thin film deposition, and chemical mechanical polishing. Problems such as particle contamination, scratches, pattern breakage, and residue accumulation at any stage can create different types of defects on the wafer surface, potentially leading to chip failure or even complete wafer scrap. Therefore, automated defect detection and classification of each die on the wafer before product shipment is crucial for ensuring yield and process stability. Existing detection approaches can be broadly categorized into two types: traditional image processing methods such as image enhancement, threshold segmentation, and geometric feature analysis; and automatic identification methods based on machine learning and deep learning models.

[0003] Traditional inspection methods typically employ rule-based image processing to identify defects. A typical approach involves first converting the wafer image to grayscale and filtering for noise reduction. Then, a fixed or adaptive threshold is set to segment suspected abnormal regions. Edge detection operators (such as the Sobel and Canny operators) are then used to enhance the contours of linear structures like cracks and breaks. Morphological operations such as dilation, erosion, and opening / closing operations are then used to remove isolated noise and small artifacts. While this method is clear and computationally efficient, it is highly dependent on manually set thresholds and structural elements. It is sensitive to imaging illumination, contrast, and the regularity of the wafer surface pattern. When the texture structure is complex or there are significant variations in process conditions between batches, it is prone to false positives and false negatives, and its generalization ability is limited.

[0004] In recent years, with the widespread application of deep learning technology in the field of vision, wafer defect detection methods based on deep neural networks have gradually become a research focus. These methods construct a multi-layered network structure of convolutional-pooling-nonlinear units to automatically learn multi-level representations from the original wafer image or wafer map, and train a classifier on a large number of labeled samples to achieve end-to-end defect recognition and pattern classification. However, these methods typically treat wafer images as ordinary images in Cartesian coordinates, leading to inaccurate defect recognition / inspection results. Summary of the Invention

[0005] In view of this, this application provides a wafer defect detection method, apparatus, medium and equipment, the main purpose of which is to solve the problem of inaccurate defect detection currently existing.

[0006] To address the above problems, this application provides a wafer defect detection method, comprising:

[0007] Image processing is performed on the original wafer image of the wafer to be tested to obtain the processed target wafer image;

[0008] The target wafer image is divided into annular regions and subjected to multi-scale feature extraction processing to obtain several initial feature maps of different scales corresponding to each annular region.

[0009] Using the target symmetry group equivariant convolutional network submodule in the pre-trained target detection model, feature extraction is performed on each initial feature map corresponding to each annular region to obtain several target feature maps corresponding to each initial feature map.

[0010] By using the target fusion module in the pre-trained target detection model, feature fusion is performed on the feature maps of each target to obtain the fused global feature vector of the target.

[0011] Based on the target defect detection module in the pre-trained target detection model, chip-level defect detection and wafer-level defect detection are performed on the global feature vector of the target to obtain the target detection result.

[0012] Optionally, the image processing of the original wafer image of the wafer to be tested to obtain a processed target wafer image specifically includes:

[0013] The original wafer image is sequentially normalized, denoised, and standardized to obtain a preprocessed wafer image; the preprocessed wafer image is then subjected to attitude correction to obtain a corrected target wafer image.

[0014] Optionally, the step of performing attitude correction on the preprocessed wafer image to obtain a corrected target wafer image specifically includes:

[0015] The preprocessed wafer image is subjected to wafer outer contour detection to determine the position and size of the wafer object to be tested in the wafer image;

[0016] Based on the location and size, the preprocessed wafer image is divided into regions to obtain narrow ring regions;

[0017] Based on the narrow annular region, a reference marker is identified to determine the angle value between the reference marker and a predetermined reference direction.

[0018] The preprocessed wafer image is rotated based on the angle value to obtain the target wafer image.

[0019] Optionally, the target symmetry group equivariant convolutional network submodule includes: a plurality of target equivariant convolutional layers connected in sequence; the number of output channels of each target equivariant convolutional layer increases sequentially.

[0020] Each of the target isovariant convolutional layers contains a target basic convolutional kernel;

[0021] When performing feature extraction, each target isovariant convolutional layer transforms the corresponding target base convolutional kernel based on the transformation matrix corresponding to each pose element in the dihedral symmetry group to obtain a convolutional kernel group corresponding to each output channel, wherein each transformed convolutional kernel in the convolutional kernel group corresponds one-to-one with each pose element.

[0022] Optionally, the step of using the target fusion module in the pre-trained target detection model to perform feature fusion on the feature maps of each target to obtain the fused global feature vector of the target specifically includes:

[0023] For each target feature map corresponding to each initial feature map, feature fusion is performed according to the output channel and the annular region to obtain the target fused feature map corresponding to each annular region;

[0024] For each of the target fusion feature maps, average pooling is performed according to the angular dimension to obtain the radial feature curves corresponding to each annular region;

[0025] For each of the radial feature curves, convergence processing is performed according to the radial dimension to obtain the annular feature vector corresponding to each annular region;

[0026] The target global feature vector is obtained by concatenating the feature vectors of each annular zone in order from the center region to the edge region.

[0027] Optionally, the step of fusing features of each target feature map corresponding to each initial feature map according to the output channel and the annular region to obtain a target fused feature map corresponding to each annular region specifically includes:

[0028] For each target feature map output under the same initial feature map and the same output channel, the first feature fusion is performed to obtain the initial fused feature map corresponding to each output channel, so as to obtain several initial fused feature maps corresponding to each initial feature map.

[0029] Based on the initial fused feature maps corresponding to each initial feature map within the same annular region, a second feature fusion is performed to obtain the target fused feature map corresponding to each annular region.

[0030] Optionally, the target defect detection module in the pre-trained target detection model performs chip-level defect detection and wafer-level defect detection on the global feature vector of the target to obtain the target detection result, specifically including:

[0031] Based on the target global feature vector, the target normalization exponential function in the target defect detection module is used to calculate the first defect probability of the wafer object under test belonging to different defect types, and obtain the wafer-level defect detection result.

[0032] Based on the target fusion feature map corresponding to each annular region, the chip-level feature vector corresponding to each chip unit is determined;

[0033] Based on the feature vectors of each chip, the second defect probability of each chip unit is calculated using the target classification function in the target defect detection module to obtain the chip-level defect detection results.

[0034] The target detection result is obtained based on the wafer-level defect detection result and the chip-level defect detection result.

[0035] To address the above problems, this application provides a wafer defect detection device, comprising:

[0036] The processing module is used to perform image processing on the original wafer image of the wafer to be tested, and obtain the processed target wafer image.

[0037] The region segmentation module is used to perform annular region segmentation and multi-scale feature extraction processing on the target wafer image to obtain several initial feature maps of different scales corresponding to each annular region.

[0038] The feature extraction module is used to extract features from each initial feature map corresponding to each annular region using the target symmetry group equivariant convolutional network submodule in the pre-trained target detection model, thereby obtaining several target feature maps corresponding to each initial feature map.

[0039] The fusion module is used to fuse the feature maps of each target using the target fusion module in the pre-trained target detection model, and obtain the fused global feature vector of the target.

[0040] The detection module is used to perform chip-level defect detection and wafer-level defect detection on the global feature vector of the target based on the target defect detection module in the pre-trained target detection model, and obtain the target detection result.

[0041] To address the aforementioned problems, this application provides a storage medium storing a computer program that, when executed by a processor, implements the steps of any of the aforementioned wafer defect detection methods.

[0042] To address the aforementioned problems, this application provides an electronic device, comprising at least a memory and a processor, wherein the memory stores a computer program, and the processor, when executing the computer program in the memory, implements the steps of any of the aforementioned wafer defect detection methods.

[0043] The wafer defect detection method, apparatus, medium, and device in this application extract features at different scales from the target wafer image according to different annular regions. This obtains multi-scale feature / initial feature maps for each annular region, ensuring comprehensive feature extraction. Subsequently, based on the multi-scale feature / initial feature maps, the target symmetry group equivariant convolutional network submodule in the target detection model can be used to extract target feature maps of the wafer at different orientations. This allows for a stable response to changes in the overall wafer orientation without adding a large number of redundant parameters, enabling subsequent judgments to reflect the defect distribution itself rather than differences in wafer placement angle or mirror direction. Furthermore, the target global feature vector can be accurately fused based on the target feature maps, and chip-level defect detection and wafer-level defect detection can be performed simultaneously based on the target global feature vector, further ensuring the accuracy of the detection results.

[0044] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0045] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0046] Figure 1 This is a flowchart of a wafer defect detection method according to an embodiment of this application;

[0047] Figure 2 This is a structural block diagram of a wafer defect detection device according to another embodiment of this application;

[0048] Figure 3 This is a structural block diagram of an electronic device according to another embodiment of this application. Detailed Implementation

[0049] Various embodiments and features of this application are described herein with reference to the accompanying drawings.

[0050] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this application will be apparent to those skilled in the art.

[0051] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0052] These and other features of this application will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.

[0053] It should also be understood that although this application has been described with reference to some specific examples, those skilled in the art can certainly implement many other equivalent forms of this application.

[0054] The above and other aspects, features and advantages of this application will become more apparent when taken in conjunction with the accompanying drawings and in view of the following detailed description.

[0055] Specific embodiments of this application are described thereafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of this application, which can be implemented in various ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that could obscure the application. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely to serve as a representative basis for teaching those skilled in the art to use this application in a variety of substantially any suitable detailed structures.

[0056] This specification may use the phrases “in one embodiment,” “in another embodiment,” “in yet another embodiment,” or “in other embodiments,” all of which may refer to one or more of the same or different embodiments according to this application.

[0057] This application provides a wafer defect detection method. The method can be implemented on a hardware platform using an industrial camera, a line scan camera, and an industrial computer, or it can be integrated into the software system of existing wafer inspection equipment. Figure 1 As shown, the specific steps include the following:

[0058] Step S101: Perform image processing on the original wafer image of the wafer to be tested to obtain the processed target wafer image;

[0059] In this step, image processing may include normalization, noise reduction, standardization, pose correction, and so on.

[0060] Step S102: Perform ring zone region division and multi-scale feature extraction processing on the target wafer image to obtain several initial feature maps of different scales corresponding to each ring zone region.

[0061] In this step, the target wafer image can be divided into multiple concentric ring regions from the center to the edge, thus obtaining several ring regions. Then, according to different scale information, features are extracted from each ring region to obtain multiple initial feature maps for each ring region, that is, each initial feature map has a different scale.

[0062] Step S103: Using the target symmetry group equal-variable convolutional network submodule in the pre-trained target detection model, feature extraction is performed on each initial feature map corresponding to each annular region to obtain several target feature maps corresponding to each initial feature map.

[0063] In this step, the target symmetry group equivariant convolutional network submodule includes: a number of target equivariant convolutional layers connected in sequence; the number of output channels of each target equivariant convolutional layer increases sequentially; each target equivariant convolutional layer contains a target basic convolutional kernel; when performing feature extraction, each target equivariant convolutional layer transforms the corresponding target basic convolutional kernel based on the transformation matrix corresponding to each pose element in the dihedral symmetry group to obtain a convolutional kernel group corresponding to each output channel of the target equivariant convolutional layer, wherein each transformed convolutional kernel in the convolutional kernel group corresponds one-to-one with each pose element.

[0064] Step S104: Using the target fusion module in the pre-trained target detection model, feature fusion is performed on the feature maps of each target to obtain the fused global feature vector of the target.

[0065] In the specific implementation process, this step can perform feature fusion on each target feature map according to the output channel and the annular region to obtain the target fused feature map. Then, the target fused feature map is converged according to different dimensions to obtain the target global feature vector.

[0066] Step S105: Based on the target defect detection module in the pre-trained target detection model, perform chip-level defect detection and wafer-level defect detection on the global feature vector of the target to obtain the target detection result.

[0067] In the specific implementation process, this step can perform chip-level defect detection and wafer-level defect detection based on the target global feature vector. Subsequently, the results of these two defect detections can be combined to comprehensively determine whether the wafer under test has defects, which helps to improve the accuracy of the detection results.

[0068] The wafer defect detection method in this embodiment extracts features at different scales from different annular regions of the target wafer image, thereby obtaining multi-scale feature / initial feature maps for each annular region. This ensures comprehensive feature extraction. Subsequently, based on the multi-scale feature / initial feature maps, the target symmetry group equivariant convolutional network submodule in the target detection model can be used to extract target feature maps of the wafer at different orientations. This allows for a stable response to changes in the overall wafer orientation without adding a large number of redundant parameters, enabling subsequent judgments to reflect the defect distribution itself rather than differences in wafer placement angle or mirror direction. Furthermore, the target global feature vector can be accurately fused based on the target feature maps. Chip-level defect detection and wafer-level defect detection can then be performed simultaneously based on the target global feature vector, further ensuring the accuracy of the detection results.

[0069] Another embodiment of this application provides a wafer defect detection method, which specifically includes the following steps:

[0070] Step S201: Image acquisition is performed on the wafer to be tested to obtain the original wafer image;

[0071] In the specific implementation of this step, an industrial camera or a line scan camera can be used to perform full-frame imaging of the wafer under test to obtain the original grayscale or color image. Where (x, y) are pixel coordinates. To ensure stable operation of subsequent algorithms, camera exposure time, light source brightness, and light source position can be fixed during the device calibration phase.

[0072] Step S202 involves sequentially performing normalization, denoising, and standardization processing on the original wafer image to obtain a preprocessed wafer image. In practice, this step may include the following steps:

[0073] Step S202-1: Gray-scale normalization and illumination correction processing.

[0074] To reduce the overall brightness and contrast differences caused by different batches and different equipment, linear normalization is performed on the original wafer image:

[0075]

[0076] in and These are the minimum and maximum grayscale values ​​for the entire image and the original wafer image, respectively. To prevent small constants with a denominator of zero.

[0077] Based on this, grid-based adaptive histogram equalization or illumination estimation and correction algorithms can be used to compensate for uneven illumination and obtain an illumination-corrected image. .

[0078] Step S202-2: Edge preservation and noise reduction.

[0079] To suppress random noise without excessively blurring defect edges, this application employs the following bilateral filtering formula to filter and denoise the illumination-corrected image, obtaining a smoothed image / denoised image. The bilateral filtering formula is:

[0080]

[0081] in, and For pixel position, For The neighborhood window centered on σ s Controlling spatial weight decay, σ r Controlling the weight decay of grayscale differences, This is the normalization factor. This process yields a smoothed image. .

[0082] Step S202-3, standardization process.

[0083] To facilitate subsequent network training, smooth images can be applied. Perform zero-mean, unit variance standardization to obtain the preprocessed image. The standardized formula is as follows:

[0084]

[0085] in, and for The global mean and standard deviation. Standardized image / Preprocessed image. As a unified input for subsequent steps.

[0086] In this step, by performing various processing on the original wafer image, differences in illumination and noise can be eliminated, so that subsequent feature extraction is based on a stable and comparable input, thereby highlighting key details of defects and improving overall detection robustness.

[0087] Step S203: Perform attitude correction on the preprocessed wafer image to obtain the corrected target wafer image;

[0088] In this step, the preprocessed wafer image is specifically subjected to wafer outer contour detection to determine the position and size of the wafer object to be tested in the wafer image; based on the position and size, the preprocessed wafer image is divided into regions to obtain narrow ring regions; based on the narrow ring regions, reference markers are identified to determine the angle value between the reference markers and a predetermined reference direction; based on the angle value, the preprocessed wafer image is rotated to obtain the target wafer image.

[0089] Specifically, the posture correction process is as follows:

[0090] Step S203-1, wafer outer contour detection.

[0091] In this step, the specific location and size of the wafer to be tested in the image must first be determined. Based on the preprocessed image I(x, y), edge detection operators such as Canny are used to extract the edge map E(x, y) to highlight the gray-level transition between the outer edge of the wafer and the background. Since the wafer presents an approximately complete circular or slightly notched circular structure in the field of view, a circular Hough transform can be performed on the edge map to scan a series of candidate radii and count the votes at each center position. By smoothing the voting space and performing peak detection, the group with the highest number of votes (x, y) is selected. c y c R) is used as the outer contour parameter of the wafer, where (x) c y c Let R be the coordinates of the wafer center and R be the wafer radius. Even with partial obstruction or minor notches, the Hough transform can still provide a relatively stable estimate based on the remaining effective arc segment, thus ensuring positioning accuracy.

[0092] Step S203-2, Reference marker detection.

[0093] In this step, the reference marks include notch marks or alignment marks. After confirming the wafer outline, it is necessary to further determine the wafer's rotation orientation. In semiconductor manufacturing, notches are typically machined or alignment marks are printed on the outer edge of the wafer as a reference for process flow and wafer mounting orientation. This embodiment uses notch detection as an example for illustration. First, within the radius range [R... A narrow ring is constructed within ΔR, R] to focus attention on the vicinity of the wafer edge. This ring region is then scanned step by step along the angular direction, and the polar angle at a certain point (x, y) is denoted as:

[0094]

[0095] Within each angular window, the continuous length of the edge response, the degree of abrupt change in the mean grayscale, and the local shape features are statistically analyzed and compared with the pre-defined notch template features. The notch location typically manifests as a short arc segment missing from the outer edge or a noticeable depression, with its edge response interrupted and its local grayscale structure significantly different from a normal arc. By finding the edge interruption region with the highest comprehensive score within the range [0, 2π), the angle θ corresponding to the notch center can be determined. notch If the production line uses rectangular alignment marks or etched marks, the center position and orientation of the marks can also be detected within the annular area by combining template matching or shape descriptors, similar to the method for notch detection.

[0096] Step S203-3, posture uniformity and alignment.

[0097] After notch or alignment mark detection, to facilitate comparison of results from different batches of wafers and network training, all wafers need to be aligned to the same reference orientation. A fixed reference angle θ is set. ref (For example, if the notch is designated to point directly downwards or directly to the right), the angle that the current wafer needs to rotate is calculated as follows:

[0098]

[0099] With (x c y c Using y as the rotation center, apply a rotation transformation RΔθ to the entire image I(x,y) to obtain the attitude-corrected wafer image / target wafer image. The announcement is as follows:

[0100]

[0101] This transformation ensures that the notches or alignment marks in the wafer images entering subsequent polar coordinate transformations and isotropic convolutional networks are all at the same reference position. In practice, to avoid information loss due to interpolation, a high-precision interpolation algorithm can be used for the rotation transformation, and the image boundaries can be appropriately expanded before rotation. After this step, the translational and rotational degrees of freedom of the wafer in the image are effectively eliminated, greatly reducing the interference of pose changes on subsequent feature representation and classification results.

[0102] In this step, the wafer's position and size are accurately located within the entire image, and the direction of wafer notches or alignment marks is automatically identified. This enables wafers from different batches and from different machines to be unified into the same coordinate reference system. Through this series of processes, additional differences caused by wafer placement angles, slight eccentricities, or field-of-view shifts can be avoided, allowing subsequent feature extraction to truly focus on the defects themselves, rather than on posture changes.

[0103] Step S204: Perform ring zone region division and multi-scale feature extraction processing on the target wafer image to obtain several initial feature maps of different scales corresponding to each ring zone region.

[0104] This step, in its implementation, specifically includes the following steps:

[0105] Step S204-1, Cartesian-polar coordinate mapping.

[0106] In this step, after obtaining the target wafer image, the wafer center (x) is used as the reference point. c y c Using the origin as the reference point, the target wafer image I... align (x, y) undergoes a coordinate transformation. For any point (x, y) on the image plane, its radius r and angle θ in the polar coordinate system are defined as:

[0107]

[0108] Where r∈[0,R], R is the wafer radius; θ∈[0,2π).

[0109] To represent polar coordinate images on a discrete grid, this application performs uniform sampling along both the radius and angle directions. The number of sampling points along the radius direction is set to N. r The number of sampling points in the angular direction is N θ Then we have:

[0110]

[0111]

[0112] Each sampling point (r) k θ l The corresponding pixel position in the Cartesian coordinate system is:

[0113]

[0114] By performing bilinear interpolation on Ialign(x, y), the polar coordinate wafer image can be obtained:

[0115]

[0116] Thus, in a size of N r ×N θ On the regular grid, a wafer image with "radius × angle" as coordinates is obtained.

[0117] In the specific implementation process, N r and N θThe value of can be selected according to the camera resolution and wafer size, so that the spatial sampling interval of the polar coordinate grid is on the same order of magnitude as the pixel spacing of the original image. This avoids redundant calculations caused by overly dense sampling and prevents the loss of details caused by overly sparse sampling.

[0118] Step S204-2, radial annular zone division.

[0119] In this step, different process-sensitive regions correspond to different radii on the wafer. For example, the central region is often less affected by exposure field uniformity, while the regions near the edges are more susceptible to factors such as lithography edge effects and polishing non-uniformity. Therefore, the polar coordinate map can be partitioned and modeled along the radial direction.

[0120] This application divides the overall radius interval [0, R] into K concentric rings, thus obtaining K ring region areas:

[0121]

[0122] Among them, each subinterval [R k 1, R k For each ring, the set of radius indices for the k-th ring is:

[0123]

[0124] On the polar coordinate graph W(r, θ), belonging to R k The rows are combined to form the k-th ring subgraph:

[0125]

[0126] Annular boundary {R k The settings for [0, R] can be adjusted based on process experience: a simple approach is to divide [0, R] into several segments; alternatively, based on historical data, high-incidence defect radius segments can be statistically analyzed, and the ring bands can be appropriately densified near these locations. In this way, the model can focus on the defect performance of different regions such as the "central area," "intermediate process-sensitive area," and "edge area" during subsequent feature extraction and fusion, instead of treating the entire wafer as a completely homogeneous region.

[0127] Step S204-3: Construction of multi-scale annular feature pyramid.

[0128] After completing the annular zone division, the differences in defect size and the observation scale still need to be considered. Small particle defects and microcracks are only visible in a small neighborhood, while large-area residues and annular defects require observation over a larger area to see the overall structure. To this end, this application constructs a multi-scale feature pyramid within each annular zone, enabling the network to perceive details and global patterns simultaneously at different spatial scales.

[0129] For the k-th annular subgraph W k Set the downsampling step size s along the radial direction and the angular direction respectively. r,k and s θ,k For W k Perform a downsampling operation to obtain the initial feature map of the first scale of the annulus. The specific sampling formula is as follows:

[0130]

[0131] The downsample operation can be implemented using methods such as average pooling, max pooling, or interpolation sampling, making... The size compared to W k It has decreased somewhat.

[0132] Based on this, Then, downsampling is performed step by step at a fixed ratio (e.g., 2 times) to obtain a coarser feature map. , Thus, the zonal subgraph W is obtained. k Several initial feature maps corresponding to the same annular region The formulas for extracting feature maps at various scales are as follows:

[0133]

[0134] Thus, the k-th ring subgraph is obtained. The corresponding multi-scale set containing several initial feature maps :

[0135]

[0136] Typically, for the rings near the wafer center, a smaller downsampling step size can be used to retain more detail; while for the rings near the edges, the step size can be appropriately increased and the number of scales reduced, taking into account the inherent geometric distortions and noise in the edge regions while controlling the overall computational load. In this way, the sampling density of each ring at multiple scales can be flexibly configured according to actual detection requirements.

[0137] Ultimately, the multi-scale feature set of all annular regions can be uniformly represented as:

[0138]

[0139] This set serves as the input to the subsequent symmetry group equivariant convolution feature extraction network, enabling the network to perform convolution operations based on radial partitioning and multi-scale information during the feature extraction stage. This facilitates the differentiation of defect features in the wafer center, transition, and edge regions.

[0140] Step S205: Using the target symmetry group equal-variable convolutional network submodule in the pre-trained target detection model, feature extraction is performed on each initial feature map corresponding to each annular region to obtain several target feature maps corresponding to each initial feature map.

[0141] In this step, the target symmetry group equivariant convolutional network submodule includes: a number of target equivariant convolutional layers connected in sequence; the number of output channels of each target equivariant convolutional layer increases sequentially; each target equivariant convolutional layer contains a target basic convolutional kernel; when performing feature extraction, each target equivariant convolutional layer transforms the corresponding target basic convolutional kernel based on the transformation matrix corresponding to each pose element in the dihedral symmetry group to obtain a convolutional kernel group corresponding to each output channel, wherein each transformed convolutional kernel in the convolutional kernel group corresponds one-to-one with each pose element.

[0142] In this embodiment, the dihedral symmetry group D is selected. M As the basis for symmetry modeling, M represents the number of equal parts to divide a full circle of 2π angles. In the preferred case, M=8, in which case D8 contains 8 rotation elements and 8 mirror elements, for a total of 16 group elements, that is, 16 attitude elements.

[0143] Specifically, it can be said that the dihedral group D M Generated by a rotation generator r and a mirror generator s, satisfying:

[0144]

[0145] Where e is the unit element, r m represents a rotation of 2πm / M around the center, and s represents a mirror operation around a fixed axis.

[0146] In this application, instead of learning a separate set of convolutional kernels for each pose, a set of "basic convolutional kernels" ψ is defined for each layer, with a size of K×K and the number of channels C. in To C out Then, for each group element / pose element g∈D M Through geometric transformation operator T g The basic kernel is transformed to obtain several corresponding transformed convolution kernels, thus obtaining a group of convolution kernels. The specific transformation formula is as follows:

[0147]

[0148] In this embodiment, geometric transformations can be achieved by rearranging the convolution kernels in spatial index, specifically including discrete rotations around the kernel center at preset angles, and mirroring operations about the horizontal and vertical axes. Using this method, only one set of basic convolution kernels ψ needs to be set in the parameter design; the convolution kernels for all other poses are obtained from this basic kernel through corresponding geometric transformations, thereby achieving kernel parameter sharing within the same symmetry group.

[0149] By using this construction method of basic convolution kernel combined with geometric transformation, when the input wafer image undergoes overall rotation or mirroring, the feature responses in each group channel can be rearranged accordingly between the channel indices. The convolutional layer does not need to set independent filtering parameters for different geometric poses, which makes it easier to control the model parameter scale while ensuring expressive power.

[0150] Specifically, the target symmetry group equivariant convolutional network submodule includes three cascaded equivariant convolutional network layers: a first equivariant convolutional network layer, a second equivariant convolutional network layer, and a third equivariant convolutional network layer.

[0151] For the first isovariant convolutional network layer, there is a corresponding first target basic convolutional kernel.

[0152] The input channels of the first isovariant convolutional network layer can be set to 1 or a small value (corresponding to a single-channel or a small number of channels in the annular image); the size of the first target basic convolutional kernel is 3×3 or 5×5, and the number of output channels is C1.

[0153] After any initial feature map is input into the first isovariant convolutional network layer, the first isovariant convolutional network layer will combine the first target basic convolutional kernel with the dihedral symmetry group D. M The principle is to generate transform convolution kernels that correspond one-to-one with the wafer orientation, thus obtaining the first convolution kernel group. Specifically, this first convolution kernel group can contain 16 transform convolution kernels, each corresponding to a wafer orientation.

[0154] Then, the C1 output channels perform convolution processing on the initial feature map based on the first group of convolutional kernels. That is, for each output channel... The network generates 16 corresponding two-dimensional feature maps. After batch normalization and activation function processing, the output features are pooled once in the spatial domain to obtain F. g (1) (x). The final output result is F. g (1) (x) can be understood as: A four-dimensional tensor composed of 16 two-dimensional feature maps has dimensions C1×16×H×W.

[0155] For the second isovariant convolutional network layer, there is a corresponding second target basic convolutional kernel.

[0156] The second isovariant convolutional network layer has C2 output channels; the output F of the previous layer can be... g (1) (x) is used as input. Similarly, F g (1) (x) After the input is fed into the second isovariant convolutional network layer, the second isovariant convolutional network layer will combine the second target basic convolutional kernel with the dihedral symmetry group D. M The principle is to generate transform convolution kernels that correspond one-to-one with the wafer orientation, thus obtaining the second convolution kernel group. Specifically, this convolution kernel group can contain 16 transform convolution kernels, each corresponding to a wafer orientation.

[0157] Then, the C2 output channels are respectively based on the second convolutional kernel group for F. g (1) (x) is convolutionally processed. That is, for each output channel... The network generates 16 corresponding two-dimensional feature maps. After batch normalization and activation function processing, the output features are pooled once in the spatial domain to obtain F. g (2) (x). The final output result is F. g (2) (x) can be understood as: A four-dimensional tensor composed of 16 two-dimensional feature maps has dimensions C2×16×H×W.

[0158] By utilizing a second isovariant convolutional network layer, appropriate pooling can be achieved to further reduce the spatial size and enhance the receptive field, resulting in F. g (2) (x).

[0159] Similarly, for the third isovariant convolutional network layer, there is a corresponding third target basic convolutional kernel.

[0160] The third isovariant convolutional network layer has C3 output channels; the output F of the previous layer can be... g (2) (x) is used as input. Similarly, F g (2) (x) After the input is fed into the third isovariant convolutional network layer, the third isovariant convolutional network layer will combine the third target basic convolutional kernel with the dihedral symmetry group D. M The principle is to generate transform convolution kernels that correspond one-to-one with the wafer orientation, thus obtaining the third convolution kernel group. Specifically, this convolution kernel group can contain 16 transform convolution kernels, each corresponding to a wafer orientation.

[0161] Then, the C3 output channels are respectively based on the third convolutional kernel group for F. g(2) (x) is convolutionally processed. That is, for each output channel... The network generates 16 corresponding two-dimensional feature maps. After batch normalization and activation function processing, the output features are pooled once in the spatial domain to obtain F. g (3) (x). The final output result is F. g (3) (x) can be understood as: A four-dimensional tensor composed of 16 two-dimensional feature maps has dimensions C3×16×H×W.

[0162] In this embodiment, based on the second isovariant convolutional network layer, the output channels are further increased to C3; the structure is similar to the first two layers, enabling the acquisition of higher-level group isovariant features F. g (3) (x) lays the foundation for subsequent feature fusion and defect determination.

[0163] Furthermore, let the input feature map of a certain layer of isovariant convolution be denoted as:

[0164]

[0165] in C represents the discrete spatial coordinate plane. in Let g be the number of input channels for this layer. For each group element / pose element g∈D M The transformed convolution kernel ψ obtained using the aforementioned geometric transformation g Define the output of the corresponding channel of the convolution kernel group as:

[0166]

[0167] Where x, y are two-dimensional spatial coordinates, ψ g Let c be the transform convolution kernel applied to the c-th input channel under the group element / pose element g. Combining the outputs of all g yields a feature tensor with group index.

[0168]

[0169] When a geometric transformation of a certain group element / pose element h is applied to the entire input image, the corresponding input feature is denoted as F(h). Under the aforementioned convolution kernel construction constraints, the output satisfies the following relationship with the original output:

[0170]

[0171] Where x′ is the spatial position of x under the transformation h. The above relationship indicates that when the input undergoes rotation or mirroring, the responses of each group channel are indexed and rearranged according to the group multiplication relationship, thus mathematically guaranteeing that the convolutional layer adheres to the dihedral symmetry group D. M Isovariability.

[0172] In implementation, this application sets up normalization and nonlinear units after group-equal convolution, which can improve training stability and enhance expressive power. Specifically, for each group element g and position x, batch normalization is first performed:

[0173]

[0174] Then, the output features are obtained through an activation function:

[0175]

[0176] Where BN is the batch normalization operation for jointly calculating statistics in the group channel and the ordinary channel, and σ(·) is a nonlinear function such as ReLU or LeakyReLU. Depending on the needs, it can also be normalized in the spatial dimension. Max pooling or average pooling is used to control the feature map size and expand the receptive field, providing a foundation for feature extraction and defect determination in subsequent layers.

[0177] In this embodiment, the aforementioned equivariant convolutional layer architecture is adopted, and some network parameters are shared or parallel branches are designed between different annular zones and different scales as needed. A simpler implementation is to extract local features for each annular zone scale through shallow equivariant convolution, and then concatenate or weighted sum these features along the channel dimension after a certain layer to form a unified group equivariant feature representation.

[0178] Throughout the feature extraction process, the network naturally handles translation of the input image through convolutional structures, while maintaining structural responses to rotation and mirroring through dihedral group isovariant convolutions. Unlike traditional methods that directly use ordinary convolutions in Cartesian coordinates, this step introduces wafer geometric symmetry into the convolutional layers in the form of "group structure + kernel transformation + group channels," thereby achieving unified modeling of wafer rotation / mirror symmetry at the network level. This provides a more stable and physically meaningful feature foundation for subsequent feature fusion and defect determination.

[0179] Step S206: Using the target fusion module in the pre-trained target detection model, feature fusion is performed on the feature maps of each target to obtain the fused global feature vector of the target.

[0180] In this step, based on the target feature maps corresponding to each initial feature map, feature fusion is performed on the group channel dimension (pose dimension) of each output channel, and combined with the annular region division, a target fused feature map F corresponding to each annular region is obtained. final (k) (r,θ); For each of the target fusion feature maps, average pooling is performed according to the angular dimension to obtain the radial feature curve corresponding to each annular region; For each of the radial feature curves, convergence processing is performed according to the radial dimension to obtain the annular feature vector corresponding to each annular region; For each of the annular feature vectors, they are concatenated in the order from the center region to the edge region to obtain the target global feature vector.

[0181] Specifically, the step of performing feature fusion on each target feature map corresponding to each initial feature map according to the output channel and the annular region to obtain a target fused feature map corresponding to each annular region includes: performing a first feature fusion on each target feature map output under the same output channel for the same initial feature map to obtain an initial fused feature map corresponding to each output channel, thereby obtaining several initial fused feature maps corresponding to each initial feature map; and performing a second feature fusion based on each initial fused feature map corresponding to each initial feature map within the same annular region to obtain a target fused feature map F corresponding to each annular region. final (k) (r,θ).

[0182] That is, the high-level features obtained after the multi-layer isovariant convolution in step S205 above are denoted as Fg. (r,θ) , where g∈D M Let (r, θ) be the index of the group element and (r, θ) be the polar coordinate position. Since the group channels have explicitly distinguished the responses under different rotation / mirror poses, convergence is needed along the group channel dimension to obtain features that are insensitive to overall pose changes. The specific process is as follows:

[0183] Step S206-1: Perform average pooling on all group channels, using the following formula:

[0184]

[0185] F inv F represents the initial fused feature map obtained after fusing the target feature maps output from the same initial feature map and under the same output channel; inv It no longer distinguishes between specific rotation or mirror orientations; when the entire wafer rotates or flips, F inv It remains largely unchanged and can be used as the main information for subsequent judgment.

[0186] Based on the reference group element g0, the orientation information of its corresponding channel is preserved to obtain the orientation residual features. The specific formula is as follows:

[0187]

[0188] in, Represents the characteristic tensor F of the high-level group. g The specific channel response extracted from the reference group element g0 (usually the unit element corresponding to the original 0° orientation) serves as a physical anchor point for orientation information. It preserves the original detailed features of the wafer under the reference view without geometric transformation and is used to restore the orientation sensitivity smoothed by average pooling during the feature fusion stage.

[0189] To avoid introducing too many redundant channels, for F dir Compression is achieved through 1×1 convolution and nonlinear transformation to obtain the directional residual features of the nonlinear compression mapping. The specific formula is as follows:

[0190]

[0191] Among them, W 1×1 σ is a 1×1 convolution kernel, b is the bias, and σ(·) is the activation function.

[0192] Finally, feature fusion can be performed using the following fusion formula to obtain the target fused feature map F corresponding to each annular region. final (k) (r,θ), the fusion formula is:

[0193]

[0194] Wherein, λ is the weight coefficient, which can be set according to the validation results or obtained through model training.

[0195] Step S206-2: Perform average pooling on the features within the annular zone in the angular dimension;

[0196] In this step, F in polar coordinate space final (k) (r, θ) correspond to the different annular regions defined in the above steps. To reflect the radial distribution variation of the wafer from the center to the edge, the features need to be aggregated according to the annular regions. Let the radius range of the k-th annular region be R. k ={r∣R k 1≤r <R k}, then the feature / target fusion feature map of the k-th ring is F final (k)(r, θ). Specifically, the target fused feature map can be processed using the average pooling formula to obtain the radial feature curve. The average pooling formula is as follows:

[0197]

[0198] Where, N θ ′ This represents the number of angular sampling points at this scale. This operation integrates information from different angles at the same radius location to obtain a radial feature curve that is only related to the radius. .

[0199] Step S206-3: Converge the radial feature curves in the radial dimension to obtain the annular feature vector;

[0200] In this step, the radial feature curves are further converged along the radial dimension. This can be achieved using global average pooling, weighted average, or pooling formulas for several radial sub-intervals, to form the annular feature vector. Specifically, the convergence formula is as follows:

[0201]

[0202] Pool r (·) denotes the convergence operator in the radial direction. Thus, v k The overall defect characteristics of the k-th annulus at the current scale are summarized.

[0203] Step S206-4: Concatenate the feature vectors of each annular zone in order from the center region to the edge region to obtain the target global feature vector. The formula is as follows:

[0204]

[0205] This vector is relatively compact in dimensions and retains the differences between different rings, making it suitable as input for wafer-level decision-making.

[0206] Step S207: Based on the target defect detection module in the pre-trained target detection model, perform chip-level defect detection and wafer-level defect detection on the global feature vector of the target to obtain the target detection result;

[0207] In the specific implementation process of this step, based on the target global feature vector, the target normalization exponential function in the target defect detection module can be used to calculate the first defect probability of the wafer object under test belonging to different defect types, thereby obtaining the wafer-level defect detection result; based on the target fusion feature map F corresponding to each annular region... final (k)(r,θ), determine the chip-level feature vector u corresponding to each chip unit. i,j Based on the feature vectors of each chip, the second defect probability of each chip unit is calculated using the target classification function in the target defect detection module to obtain the chip-level defect detection result; based on the wafer-level defect detection result and the chip-level defect detection result, the target detection result is obtained.

[0208] In other words, it specifically includes the following steps:

[0209] Step S207-1: Perform wafer-level defect detection and obtain wafer-level defect detection results;

[0210] The target global feature vector v is fed into one or two fully connected layers to output scores for each category, and then converted into probabilistic form using the target normalization exponential function / Softmax function.

[0211]

[0212] Among them, W w They represent b respectively w The weights and biases of the wafer-level classifier are obtained through model training. wafer This represents the probability vector for different defect modes. Based on the maximum probability principle or a set threshold rule, the overall defect type of the wafer can be determined.

[0213] Step S207-2: Perform chip-level defect detection and obtain chip-level defect detection results;

[0214] In this step, for chip-level determination, the wafer center (x) obtained above is used as a reference. c , y c ) and rotational deviation Based on the row and column layout information of the standard wafer layout, the center coordinates of each chip in the image coordinate system are calculated through rigid body transformation. Map it to polar coordinates:

[0215]

[0216] According to r i,j Determine the ring index k to which the chip belongs, in F final Select from (k) with (r) i,j ,θ i,j A local window centered on the chip and covering the range corresponding to the chip's physical dimensions is used to perform average pooling on the features within the window, resulting in a chip-level feature vector u. i,j .

[0217] will u i,j Input a lightweight fully connected layer and calculate the chip defect probability:

[0218]

[0219] Among them, W c They represent b respectively c The weights and biases of the chip-level classifier; σ(·) is the Sigmoid function / target classification function.

[0220] In this embodiment, a judgment threshold τ can be preset during implementation. When p i,j When the value is greater than or equal to τ, the chip unit is marked as a defective chip; otherwise, it is marked as a normal chip unit.

[0221] In wafer-level GOOD / NG determination, multiple rules can be applied by combining chip-level results. For example, if the proportion of defective chip cells exceeds a preset ratio, the entire wafer is determined to be NG; or, when the area of ​​the connected region formed by adjacent defective chip cells exceeds a set threshold, the wafer is considered to have severe concentrated defects. In practical applications, an appropriate determination strategy can be selected according to process requirements.

[0222] In this embodiment, the detection results can be presented in various forms, such as: displaying the defect probability of each chip in pseudo-color on the wafer planar diagram and marking the location of the chip determined to be defective; and compiling information such as the defect type, number of defective chips, and defect distribution rings for each wafer in the report to provide analysis basis for process engineers.

[0223] In this embodiment, the above feature fusion and determination process not only utilizes the pose robustness brought by group isovariant convolution, but also retains radial partitioning and local chip-level difference information, making the defect detection results at the wafer level and chip level more consistent and interpretable.

[0224] The key technical point of this embodiment lies in the organic combination of prior wafer geometry and convolutional network structure. On the one hand, polar coordinate transformation is performed on the aligned wafer image, and multiple concentric rings are divided in the radial direction. Then, a multi-scale feature pyramid is constructed inside each ring, so that the input features directly correspond to physical regions such as "center area - transition area - edge area" in form, distinguishing the process characteristics and defect distribution patterns of different radial positions from the source. On the other hand, dihedral symmetry group modeling is introduced in the feature extraction stage. Through a set of basic convolutional kernels and their geometric transformations, convolutional kernels of various poses are constructed to form a convolutional network structure that maintains equivariance under the action of this symmetry group. This allows the network to transmit features in a regular manner between group channels when facing overall wafer rotation, mirroring, and slight pose deviations, reducing parameter redundancy and dependence on rotation-enhanced samples.

[0225] Building upon this foundation, this application balances the invariance and directionality of isotropic features through a combination of channel pooling and directional residual information. Combined with annular-level feature convergence, it forms a compact representation that simultaneously reflects attitude robustness and radial structural differences. Through the mapping relationship between polar coordinates and layout coordinates, the network output can be used not only for wafer-level defect pattern recognition but also for chip-level defect probability assessment, generating a visualized defect distribution map and providing intuitive evidence for process analysis. These steps constitute a complete technical chain from coordinate system transformation and symmetry group modeling to feature fusion and determination, which is the core of this application that distinguishes it from existing wafer defect detection methods.

[0226] In this embodiment, the target detection model can be pre-trained. The specific model training process is as follows:

[0227] Step 1: Acquire images of several sample wafers;

[0228] Step 2: Perform image processing on each sample wafer image to obtain the processed target sample wafer image;

[0229] Step 3: Divide the target sample wafer image into annular regions and perform multi-scale feature extraction to obtain several initial sample feature maps of different scales corresponding to each annular region.

[0230] Step 4: Using the initial symmetry group equivariant convolutional network submodule in the initial detection model, extract features from each initial sample feature map corresponding to each annular region to obtain several target sample feature maps corresponding to each initial sample feature map.

[0231] Step 5: Using the initial fusion module in the initial detection model, feature fusion is performed on the feature maps of each target sample to obtain the global feature vector of the fused sample corresponding to the wafer image of each sample.

[0232] Step 6: Based on the initial defect detection module in the initial detection model, perform chip-level defect detection and wafer-level defect detection on the global feature vectors of each sample to obtain the initial detection results;

[0233] Step 7: Based on the initial detection results, calculate the initial loss, determine whether the initial loss meets the predetermined training stopping condition, and if the predetermined training stopping condition is not met, adjust the parameters in the initial symmetry group equivariant convolutional network submodule, the initial fusion module, and the initial defect detection module in the initial detection model to obtain the current detection model, and return to step 4 until the calculated current loss meets the predetermined training stopping condition, and then use the current detection model as the target detection model.

[0234] In this step, parameter optimization specifically involves optimizing the basic convolutional kernels in the initial symmetry group equivariant convolutional network submodule and the fusion weights in the initial fusion module. The classifier parameter W in the initial defect detection module w Classifier parameter b w Classifier parameters W c Classifier parameter b c Adjustments and optimizations will be made.

[0235] In this embodiment, the specific process for calculating the loss is as follows:

[0236] For chip-level binary classification tasks, cross-entropy loss with class weights can be used. Consider several wafer samples, each containing N chip unit samples, where the true label of the nth chip unit sample is y. n ∈{0,1}, the predicted defect probability is p n (Right now Then, the chip-level defect loss corresponding to each wafer sample / sample wafer image is... for:

[0237]

[0238] Here, α∈(0,1) is used to appropriately increase the weight of defective samples in the loss to mitigate the impact of class imbalance on training.

[0239] At the same time, the probability vector p corresponding to different defect modes of each wafer sample can be used as a basis. wafer Calculate wafer-level defect loss Finally, based on wafer-level defect loss and chip-level defect loss, the total loss is calculated using the total loss calculation function. The formula for calculating the total loss is as follows:

[0240]

[0241] Where β is a weighting coefficient used to adjust the contribution of wafer-level tasks to the overall optimization.

[0242] In this embodiment, after calculating the total loss corresponding to each wafer sample, the parameters in the initial detection model can be updated. Parameter updates can employ stochastic gradient descent (SGD) with momentum or the Adam optimization algorithm. The initial learning rate can be selected based on a suitable value according to the network size and the number of samples. During training, the learning rate is gradually reduced in stages or using cosine annealing based on the performance of the validation set. To suppress overfitting, weight decay (L2 regularization) can be introduced in the isovariant convolutional layers and fully connected layers, and Dropout can be added to some layers.

[0243] In this embodiment, the wafer images of each target sample can be divided to obtain a training set, a test set, and a validation set. The training set is used for model training. During training, iterative forward computation and parameter updates are performed in batches, and chip-level accuracy, recall, F1 score, and wafer-level recognition accuracy are periodically evaluated on the validation set. When the performance on the validation set no longer improves within several iterations, training can be stopped, and the model parameters with the best performance on the validation set are saved as the final model. The test set is only used for an objective evaluation after all training is completed and does not participate in model parameter adjustment.

[0244] The method in this embodiment can explicitly utilize the geometric characteristics of the wafer, which is "approximately disk-shaped and centrally symmetrically distributed," within the network structure. By generating convolutional kernel groups based on basic convolutional kernels, robustness to wafer rotation, flipping, and notch orientation changes can be improved without requiring extensive data augmentation through rotation and translation, or additional feature transformation steps. This fundamentally solves the problem of insufficient modeling of geometric symmetry in networks. Accurate defect detection can be achieved regardless of changes in wafer placement posture or imaging perspective.

[0245] In other words, by explicitly introducing dihedral symmetry group equivariance into the network structure / model, rotation and mirror transformation are modeled uniformly through the group structure. When the wafer as a whole rotates, the notch orientation changes, or there is a certain degree of alignment error, the features are rearranged according to fixed rules among the group channels, and the network output representation and judgment results remain relatively stable, thereby reducing the dependence on high-precision mechanical alignment and large-scale rotation enhancement data. Through polar coordinate mapping and radial ring pyramid construction, this application distinguishes the statistical characteristics of the wafer center region, transition region, and edge region at the feature level, so that the difference in defect distribution in different radius regions is reflected in the representation. For ring defects, edge ring defects, and defect patterns concentrated in specific radius segments, this method can highlight relevant regions while maintaining the overall field of view, which is beneficial to improving the detection rate and reducing false positives. By adopting group equivariant convolution, the same set of basic convolution kernels are shared in multiple symmetric postures through geometric transformation, avoiding the repeated configuration of independent filters for different directions and rotation postures, and controlling the parameter scale while covering multiple geometric changes. For real-world engineering scenarios with limited defect samples and severely imbalanced class distributions, this structure helps improve model convergence, reduce overfitting risk, and enhance generalization performance across different batches and machine data. The method described in this application saves computational resources. Due to the introduction of a symmetric group sharing mechanism in the convolutional kernel design, the parameter scale is more compact compared to similar deep networks, thus reducing inference computation. Depending on the actual production line's cycle time requirements, the model can be deployed on GPU servers, edge computing boxes, or high-performance CPU industrial control computers, typically meeting near real-time or near real-time online detection needs. If subsequent process conditions change significantly, new data can be collected periodically to incrementally train or retrain the model before updating it to the online inference engine, maintaining stable detection performance.

[0246] Another embodiment of this application provides a wafer defect detection device, such as... Figure 2 As shown, it includes:

[0247] Processing module 11 is used to perform image processing on the original wafer image of the wafer to be tested, and obtain the processed target wafer image;

[0248] The region segmentation module 12 is used to perform annular region segmentation and multi-scale feature extraction processing on the target wafer image to obtain several initial feature maps of different scales corresponding to each annular region.

[0249] Feature extraction module 13 is used to extract features from each initial feature map corresponding to each annular region using the target symmetry group equivariant convolutional network submodule in the pre-trained target detection model, and obtain several target feature maps corresponding to each initial feature map.

[0250] The fusion module 14 is used to perform feature fusion on each target feature map using the target fusion module in the pre-trained target detection model to obtain the fused global feature vector of the target.

[0251] Detection module 15 is used to perform chip-level defect detection and wafer-level defect detection on the global feature vector of the target based on the target defect detection module in the pre-trained target detection model, and obtain the target detection result.

[0252] In this embodiment, the processing module specifically includes a preprocessing module and a correction module. The preprocessing module is used to perform normalization, denoising, and standardization processing on the original wafer image in sequence to obtain the preprocessed wafer image. The correction module is used to perform orientation correction on the preprocessed wafer image to obtain the corrected target wafer image.

[0253] In this embodiment, the correction module is specifically used for: performing wafer outer contour detection on the preprocessed wafer image to determine the position and size of the wafer object to be tested in the wafer image; dividing the preprocessed wafer image into regions based on the position and size to obtain a narrow ring region; identifying a reference marker based on the narrow ring region to determine the angle value between the reference marker and a predetermined reference direction; and rotating the preprocessed wafer image based on the angle value to obtain the target wafer image.

[0254] In this embodiment, the target symmetry group equivariant convolutional network submodule includes: a plurality of target equivariant convolutional layers connected in sequence; the number of output channels of each target equivariant convolutional layer increases sequentially; each target equivariant convolutional layer contains a target basic convolutional kernel; when performing feature extraction, each target equivariant convolutional layer transforms the corresponding target basic convolutional kernel based on the transformation matrix corresponding to each pose element in the dihedral symmetry group to obtain a convolutional kernel group corresponding to each output channel, wherein each transformed convolutional kernel in the convolutional kernel group corresponds one-to-one with each pose element.

[0255] In this embodiment, the fusion module is specifically used for: fusing features of each target feature map corresponding to each initial feature map according to the output channel and the annular region to obtain a target fused feature map corresponding to each annular region; performing average pooling on each target fused feature map according to the angular dimension to obtain a radial feature curve corresponding to each annular region; performing convergence processing on each radial feature curve according to the radial dimension to obtain an annular feature vector corresponding to each annular region; and concatenating each annular feature vector in the order from the center region to the edge region to obtain the target global feature vector.

[0256] In this embodiment, the fusion module is specifically used to: perform a first feature fusion on each target feature map output under the same output channel for the same initial feature map, to obtain an initial fused feature map corresponding to each output channel, and to obtain a number of initial fused feature maps corresponding to each initial feature map; and perform a second feature fusion based on each initial fused feature map corresponding to each initial feature map within the same annular region, to obtain a target fused feature map corresponding to each annular region.

[0257] In this embodiment, the detection module is specifically used for: calculating the first defect probability of the wafer object to be tested belonging to different defect types based on the target global feature vector and using the target normalization exponential function in the target defect detection module, thereby obtaining wafer-level defect detection results; determining the chip-level feature vector corresponding to each chip unit based on the target fusion feature map corresponding to each annular region; calculating the second defect probability of each chip unit based on each chip-level feature vector and using the target classification function in the target defect detection module, thereby obtaining chip-level defect detection results; and obtaining the target detection result based on the wafer-level defect detection results and the chip-level defect detection results.

[0258] The device in this embodiment extracts features at different scales from the target wafer image according to different annular regions, thereby obtaining multi-scale feature / initial feature maps for each annular region. This ensures comprehensive feature extraction. Subsequently, based on the multi-scale feature / initial feature maps, the target symmetry group equivariant convolutional network submodule in the target detection model can be used to extract target feature maps of the wafer at different orientations. This allows for a stable response to changes in the overall wafer orientation without adding a large number of redundant parameters, enabling subsequent judgments to reflect the defect distribution itself rather than differences in wafer placement angle or mirror direction. Furthermore, the target global feature vector can be accurately fused based on the target feature maps. Chip-level defect detection and wafer-level defect detection can then be performed simultaneously based on the target global feature vector, further ensuring the accuracy of the detection results.

[0259] Another embodiment of this application provides a storage medium storing a computer program, which, when executed by a processor, implements the following method steps:

[0260] Step 1: Perform image processing on the original wafer image of the wafer to be tested to obtain the processed target wafer image;

[0261] Step 2: Divide the target wafer image into annular regions and perform multi-scale feature extraction to obtain several initial feature maps of different scales corresponding to each annular region;

[0262] Step 3: Using the target symmetry group equivariant convolutional network submodule in the pre-trained target detection model, extract features from each initial feature map corresponding to each annular region to obtain several target feature maps corresponding to each initial feature map.

[0263] Step 4: Using the target fusion module in the pre-trained target detection model, perform feature fusion on the feature maps of each target to obtain the fused global feature vector of the target.

[0264] Step 5: Based on the target defect detection module in the pre-trained target detection model, perform chip-level defect detection and wafer-level defect detection on the global feature vector of the target to obtain the target detection result.

[0265] The specific implementation process of the above method steps can be found in the embodiments of the above arbitrary wafer defect detection method, which will not be repeated here.

[0266] The storage medium in this application extracts features at different scales from different annular regions of the target wafer image, thereby obtaining multi-scale feature / initial feature maps for each annular region. This ensures comprehensive feature extraction. Subsequently, based on the multi-scale feature / initial feature maps, the target symmetry group equivariant convolutional network submodule in the target detection model can be used to extract target feature maps of the wafer at different orientations. This allows for a stable response to changes in the overall wafer orientation without adding a large number of redundant parameters, enabling subsequent judgments to reflect the defect distribution itself rather than differences in wafer placement angle or mirror direction. Furthermore, the target global feature vector can be accurately obtained by fusing the various target feature maps. Chip-level defect detection and wafer-level defect detection can then be performed simultaneously based on the target global feature vector, further ensuring the accuracy of the detection results.

[0267] Another embodiment of this application provides an electronic device, such as... Figure 3 As shown, it includes at least a memory 1 and a processor 2. The memory 1 stores a computer program, and the processor 2 performs the following method steps when executing the computer program in the memory 1:

[0268] Step 1: Perform image processing on the original wafer image of the wafer to be tested to obtain the processed target wafer image;

[0269] Step 2: Divide the target wafer image into annular regions and perform multi-scale feature extraction to obtain several initial feature maps of different scales corresponding to each annular region;

[0270] Step 3: Using the target symmetry group equivariant convolutional network submodule in the pre-trained target detection model, extract features from each initial feature map corresponding to each annular region to obtain several target feature maps corresponding to each initial feature map.

[0271] Step 4: Using the target fusion module in the pre-trained target detection model, perform feature fusion on the feature maps of each target to obtain the fused global feature vector of the target.

[0272] Step 5: Based on the target defect detection module in the pre-trained target detection model, perform chip-level defect detection and wafer-level defect detection on the global feature vector of the target to obtain the target detection result.

[0273] The specific implementation process of the above method steps can be found in the embodiments of the above arbitrary wafer defect detection method, which will not be repeated here.

[0274] The electronic device in this application extracts features at different scales from different annular regions of the target wafer image, thereby obtaining multi-scale feature / initial feature maps for each annular region. This ensures comprehensive feature extraction. Subsequently, based on the multi-scale feature / initial feature maps, the target symmetry group equivariant convolutional network submodule in the target detection model can be used to extract target feature maps of the wafer at different orientations. This allows for a stable response to changes in the overall wafer orientation without adding a large number of redundant parameters, enabling subsequent judgments to reflect the defect distribution itself rather than differences in wafer placement angle or mirror direction. Furthermore, the target global feature vector can be accurately fused based on the target feature maps. Chip-level defect detection and wafer-level defect detection can then be performed simultaneously based on the target global feature vector, further ensuring the accuracy of the detection results.

[0275] The above embodiments are merely exemplary embodiments of this application and are not intended to limit this application. Those skilled in the art can make various modifications or equivalent substitutions to this application within the scope and nature of this application, and such modifications or equivalent substitutions should also be considered to fall within the scope of protection of this application.

Claims

1. A method for detecting wafer defects, characterized in that, include: Image processing is performed on the original wafer image of the wafer to be tested to obtain the processed target wafer image; The target wafer image is divided into annular regions and subjected to multi-scale feature extraction processing to obtain several initial feature maps of different scales corresponding to each annular region. Using the target symmetry group equivariant convolutional network submodule in the pre-trained target detection model, feature extraction is performed on each initial feature map corresponding to each annular region to obtain several target feature maps corresponding to each initial feature map. By using the target fusion module in the pre-trained target detection model, feature fusion is performed on the feature maps of each target to obtain the fused global feature vector of the target. Based on the target defect detection module in the pre-trained target detection model, chip-level defect detection and wafer-level defect detection are performed on the global feature vector of the target to obtain the target detection result. The target symmetry group equivariant convolutional network submodule includes: a plurality of target equivariant convolutional layers connected in sequence; the number of output channels of each target equivariant convolutional layer increases sequentially. Each of the target isovariant convolutional layers contains a target basic convolutional kernel; When performing feature extraction, each target isovariant convolutional layer transforms the corresponding target base convolutional kernel based on the transformation matrix corresponding to each pose element in the dihedral symmetry group to obtain a convolutional kernel group corresponding to each output channel, wherein each transformed convolutional kernel in the convolutional kernel group corresponds one-to-one with each pose element.

2. The wafer defect detection method as described in claim 1, characterized in that, The image processing of the original wafer image of the wafer to be tested to obtain the processed target wafer image specifically includes: The original wafer image is sequentially normalized, denoised, and standardized to obtain a preprocessed wafer image; the preprocessed wafer image is then subjected to attitude correction to obtain a corrected target wafer image.

3. The wafer defect detection method as described in claim 2, characterized in that, The step of performing attitude correction on the preprocessed wafer image to obtain the corrected target wafer image specifically includes: The preprocessed wafer image is subjected to wafer outer contour detection to determine the position and size of the wafer object to be tested in the wafer image; Based on the location and size, the preprocessed wafer image is divided into regions to obtain narrow ring regions; Based on the narrow annular region, a reference marker is identified to determine the angle value between the reference marker and a predetermined reference direction. The preprocessed wafer image is rotated based on the angle value to obtain the target wafer image.

4. The wafer defect detection method as described in claim 1, characterized in that, The step of using the target fusion module in the pre-trained target detection model to fuse the feature maps of each target and obtain the fused global feature vector of the target specifically includes: For each target feature map corresponding to each initial feature map, feature fusion is performed according to the output channel and the annular region to obtain the target fused feature map corresponding to each annular region; For each of the target fusion feature maps, average pooling is performed according to the angular dimension to obtain the radial feature curves corresponding to each annular region; For each of the radial feature curves, convergence processing is performed according to the radial dimension to obtain the annular feature vector corresponding to each annular region; The target global feature vector is obtained by concatenating the feature vectors of each annular zone in order from the center region to the edge region.

5. The wafer defect detection method as described in claim 4, characterized in that, The step of fusing features of each target feature map corresponding to each initial feature map according to the output channel and the annular region to obtain a target fused feature map corresponding to each annular region specifically includes: For each target feature map output under the same initial feature map and the same output channel, the first feature fusion is performed to obtain the initial fused feature map corresponding to each output channel, so as to obtain several initial fused feature maps corresponding to each initial feature map. Based on the initial fused feature maps corresponding to each initial feature map within the same annular region, a second feature fusion is performed to obtain the target fused feature map corresponding to each annular region.

6. The wafer defect detection method as described in claim 1, characterized in that, The target defect detection module in the pre-trained target detection model performs chip-level defect detection and wafer-level defect detection on the global feature vector of the target to obtain the target detection result, specifically including: Based on the target global feature vector, the target normalization exponential function in the target defect detection module is used to calculate the first defect probability of the wafer object under test belonging to different defect types, and obtain the wafer-level defect detection result. Based on the target fusion feature map corresponding to each annular region, the chip-level feature vector corresponding to each chip unit is determined; Based on the feature vectors of each chip, the second defect probability of each chip unit is calculated using the target classification function in the target defect detection module to obtain the chip-level defect detection results. The target detection result is obtained based on the wafer-level defect detection result and the chip-level defect detection result.

7. A wafer defect detection device, characterized in that, include: The processing module is used to perform image processing on the original wafer image of the wafer to be tested, and obtain the processed target wafer image. The region segmentation module is used to perform annular region segmentation and multi-scale feature extraction processing on the target wafer image to obtain several initial feature maps of different scales corresponding to each annular region. The feature extraction module is used to extract features from each initial feature map corresponding to each annular region using the target symmetry group equivariant convolutional network submodule in the pre-trained target detection model, thereby obtaining several target feature maps corresponding to each initial feature map. The fusion module is used to fuse the feature maps of each target using the target fusion module in the pre-trained target detection model to obtain the fused global feature vector of the target. The detection module is used to perform chip-level defect detection and wafer-level defect detection on the global feature vector of the target based on the target defect detection module in the pre-trained target detection model, and obtain the target detection result; The target symmetry group equivariant convolutional network submodule includes: a plurality of target equivariant convolutional layers connected in sequence; the number of output channels of each target equivariant convolutional layer increases sequentially. Each of the target isovariant convolutional layers contains a target basic convolutional kernel; When performing feature extraction, each target isovariant convolutional layer transforms the corresponding target base convolutional kernel based on the transformation matrix corresponding to each pose element in the dihedral symmetry group to obtain a convolutional kernel group corresponding to each output channel, wherein each transformed convolutional kernel in the convolutional kernel group corresponds one-to-one with each pose element.

8. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the steps of the wafer defect detection method according to any one of claims 1-6.

9. An electronic device, characterized in that, It includes at least a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program in the memory to implement the steps of the wafer defect detection method according to any one of claims 1-6.

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