Display substrate, display panel and display device

Abstract

The embodiment of the invention provides a display substrate, a display panel and a display device. The display substrate comprises a substrate body, a first electrode and a second electrode, a plurality of grid line groups; a plurality of data lines; the plurality of data lines comprise a first type of data lines and a second type of data lines which are alternately arranged along the first direction; a plurality of transistors, the transistors in the same sub-transistor group are connected to the same grid line, the transistors in the adjacent sub-transistor groups are connected to different grid lines, and the transistors in the same sub-transistor group are connected to different data lines; the plurality of pins comprise a first type of pins and a second type of pins which are alternately arranged along the first direction; wherein every two adjacent first type data lines are connected to one first type pin, and every two adjacent second type data lines are connected to one second type pin.

Description

Display substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0002] As shown in Figure 1A, a single-gate structure corresponds to one gate line for each row of pixels, and one data line for each column of pixels. Compared to a single-gate structure, a dual-gate product, shown in Figure 1B, reduces the number of source ICs by increasing the number of gate lines and reducing the number of data lines, thereby lowering costs. For example, a product with a resolution of 1280*480 has 480 gate lines and 1280*3 = 3840 data lines. A mainstream IC has 1920 channels, requiring two source ICs to drive the entire panel. Using dual-gate technology, however, the number of gate lines is 480*2 = 960. Because gate drivers typically utilize gate-on-array (GOA) technology, increasing the number of gate lines does not increase the number of gate ICs. The number of data lines is 1280*3 / 2 = 1920, requiring only one IC.

[0003] Summary of the Invention

[0004] An embodiment of the present disclosure provides a display substrate, comprising:

[0005] substrate;

[0006] A plurality of gate line groups are located on one side of the base substrate and extend along a first direction, wherein at least one gate line group of the plurality of gate line groups includes two gate lines extending along the first direction;

[0007] a plurality of data lines, located on the same side of the base substrate as the gate lines, extending along a second direction; the plurality of data lines comprising: first-type data lines and second-type data lines alternately arranged along the first direction;

[0008] a plurality of transistors located in an area formed by the intersection of the gate line group and the data line, the plurality of transistors comprising: a sub-transistor group located between adjacent gate line groups and arranged along the first direction, the sub-transistor group comprising two transistors, the transistors in the same sub-transistor group being connected to the same gate line, the transistors in adjacent sub-transistor groups being connected to different gate lines, and the transistors in the same sub-transistor group being connected to different data lines;

[0009] A plurality of pins are located on the same side of the base substrate as the gate line, and the plurality of pins include: first-type pins and second-type pins arranged alternately along the first direction; wherein two adjacent first-type data lines are connected to a first-type pin, and two adjacent second-type data lines are connected to a second-type pin.

[0010] In a possible implementation, the gate line group includes: a first gate line and a second gate line;

[0011] The plurality of transistors include: a first transistor row and a second transistor row extending along the first direction and alternately arranged along the second direction; the sub-transistor group includes: a first sub-transistor group and a second sub-transistor group alternately arranged along the first direction;

[0012] In the first transistor row, the transistors in the first sub-transistor group are connected to the first gate line, and the transistors in the second sub-transistor are connected to the second gate line; in the second transistor row, the transistors in the first sub-transistor group are connected to the second gate line, and the transistors in the second sub-transistor are connected to the first gate line; and two adjacent transistors in the same column of transistors are connected to different data lines.

[0013] In a possible implementation, the display substrate further includes: a plurality of first leads, and a plurality of second leads;

[0014] The first lead includes: a first connecting portion and two first lead ends; one end of the first connecting portion is connected to the first type pin, and the other end is connected to the two first lead ends; the other end of the first lead end is connected to the first type data line;

[0015] The second lead includes: a second connecting portion and two second lead ends, one end of the second connecting portion is connected to the second type pin, the other end is connected to the two second lead ends, and the other end of the second lead end is connected to the second type data line.

[0016] In a possible implementation manner, an orthographic projection of one of the two first lead ends on the substrate and an orthographic projection of one of the two second lead ends on the substrate are arranged to intersect.

[0017] In a possible implementation manner, the first lead and the second lead are located in different layers.

[0018] In a possible implementation manner, the first lead and the data line are provided in the same layer; and the second lead and the gate line are provided in the same layer.

[0019] In a possible implementation, the display substrate further includes: a transfer portion;

[0020] The end of the second type data line further has a first overlapping portion, the orthographic projection of the transition portion on the base substrate covers the orthographic projection of the first overlapping portion on the base substrate, and the transition portion is electrically connected to the first overlapping portion through a first via hole;

[0021] The second lead end further has a second overlapping portion, the orthographic projection of the transition portion on the base substrate covers the orthographic projection of the second overlapping portion on the base substrate, and the transition portion is electrically connected to the second overlapping portion through a second via hole;

[0022] The first overlapping portion and the second overlapping portion are electrically connected through the transition portion.

[0023] In a possible implementation, the display substrate further includes a common electrode layer, and the transition portion and the common electrode layer are made of the same layer and material.

[0024] In a possible implementation manner, the common electrode layer is reused as a touch electrode layer; the touch electrode layer includes a plurality of touch electrode blocks spaced apart from each other;

[0025] The display substrate further includes a touch wiring layer, wherein the touch wiring layer includes touch wirings electrically connected to the touch electrode blocks in a one-to-one correspondence;

[0026] The touch traces and the data layer are located in different layers.

[0027] In a possible implementation manner, the orthographic projection of the touch trace on the base substrate covers the orthographic projection of the data line on the base substrate.

[0028] In a possible implementation, the display substrate further includes: a pixel electrode layer located on a side of the data line layer facing away from the base substrate; the common electrode layer is located on a side of the pixel electrode layer facing away from the base substrate;

[0029] The touch wiring layer is located between the pixel electrode layer and the common electrode layer.

[0030] In a possible implementation, a first passivation layer is further provided between the touch wiring layer and the common electrode layer. The first passivation layer has a third via hole exposing the touch wiring portion. The touch wiring is electrically connected to the touch electrode block through the third via hole.

[0031] In a possible implementation manner, the orthographic projection of the third via hole on the base substrate is located at a gap between two gate lines of the same gate line group.

[0032] An embodiment of the present disclosure provides a display panel, which includes the display substrate provided by the embodiment of the present disclosure.

[0033] An embodiment of the present disclosure provides a display device, which includes the display panel provided by the embodiment of the present disclosure.

[0034] An embodiment of the present disclosure provides a driving method of the display substrate provided in the embodiment of the present disclosure, wherein the driving method includes:

[0035] When displaying an image in the Nth frame, a first type of signal is applied to the first type of pin, and a second type of signal is applied to the second type of pin, wherein the polarity of the first type of signal is opposite to that of the second type of signal, and N is an integer;

[0036] When displaying an image in the (N+1)th frame, the second-type signal is loaded onto the first-type pin, and the first-type signal is loaded onto the second-type pin. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] FIG1A is a schematic diagram of a display panel with a single-gate structure;

[0038] FIG1B is a schematic diagram of a display panel with a dual-gate structure;

[0039] FIG2A is a schematic diagram of a display panel with a double-gate structure and column flipping;

[0040] FIG2B is a schematic diagram showing a double-gate structure generating head shake patterns;

[0041] FIG2C is a second schematic diagram of a dual-gate structure generating head shaking patterns;

[0042] FIG2D is a third schematic diagram of a dual-gate structure generating head shake patterns;

[0043] FIG2E is a schematic diagram of a dot-inversion display panel with a dual-gate structure;

[0044] FIG3 is a schematic diagram of a display panel with a dual-gate Z-structure;

[0045] FIG4 is a schematic diagram of a display panel according to an embodiment of the present disclosure;

[0046] FIG5 is a second schematic diagram of a display panel provided in an embodiment of the present disclosure;

[0047] FIG6 is a third schematic diagram of a display panel provided in an embodiment of the present disclosure;

[0048] FIG7A is a schematic diagram of a film layer of a display substrate provided by an embodiment of the present disclosure;

[0049] FIG7B is a schematic diagram of a single film layer of the gate line in FIG7A;

[0050] FIG7C is a schematic diagram of a single film layer of the active layer in FIG7A ;

[0051] FIG7D is a schematic diagram of a single film layer of the data line in FIG7A ;

[0052] FIG7E is a schematic diagram of a single film layer of the flat layer in FIG7A ;

[0053] FIG7F is a schematic diagram of a single film layer of the pixel electrode layer in FIG7A ;

[0054] FIG7G is a schematic diagram of a single film layer of the common electrode layer in FIG7A ;

[0055] FIG7H is a schematic diagram showing the distribution of first leads and second leads provided in an embodiment of the present disclosure;

[0056] FIG7I is a schematic diagram of a single film layer of the gate line layer in FIG7H ;

[0057] FIG7J is a schematic diagram of a single film layer of the data line layer in FIG7H ;

[0058] FIG7K is a schematic diagram of a single film layer at the overlapping portion in FIG7H ;

[0059] FIG7L is a schematic cross-sectional view taken along dotted line AA′ in FIG7H ;

[0060] FIG8A is a schematic diagram of a display substrate with touch wiring provided by an embodiment of the present disclosure;

[0061] FIG8B is a schematic diagram of a single film layer of the touch wiring in FIG8A ;

[0062] FIG9A is a schematic diagram of a display panel manufacturing process according to an embodiment of the present disclosure;

[0063] FIG9B is a second schematic diagram of a display panel manufacturing process according to an embodiment of the present disclosure;

[0064] FIG10 is a schematic diagram of a display panel manufacturing and driving method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiments of the present invention. It should be noted that the sizes and shapes of the figures in the drawings do not reflect the actual proportions, and the purpose is only to illustrate the contents of the present invention. And the same or similar numbers throughout represent the same or similar elements or elements with the same or similar functions. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0066] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the invention belongs. The words "first", "second" and similar terms used in the specification and claims of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0067] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0068] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0069] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0070] In the existing dual-gate pixel architecture, when column inversion is used, mixed color patterns and special patterns (for example, a pure green screen) result in differences in charging between different columns, resulting in vertical streak defects. Specifically, as shown in FIG2A , in a yellow pattern of red and green mixed colors, the sub-pixels corresponding to the red and green colors are bright, while the blue sub-pixel is dark. In FIG2A , columns D1, D2, D4, and D5 are bright, while columns D3 and D6 are dark. When column inversion is used, the data voltages corresponding to columns D1 and D2 are DC, resulting in stronger charging of columns D1 and D2. Since column D3 is dark and column D4 is bright, the data voltage connecting columns D3 and D4 is AC, resulting in a lower charging rate of column D4 than that of column D1. Similarly, the charging rate of column D5 is lower than that of column D2. At low temperatures, this difference is amplified, making vertical streak defects more likely to occur. Specifically, as shown in Figures 2B to 2D, for a monochrome image, such as a red image, spatially: within the same frame, the polarity of each red pixel column is +-+- periodic, and the brightness of adjacent polarities of +- can be averaged, while the brightness of adjacent polarities of ++ or - cannot be averaged, and the polarity needs to be flipped in the next frame or averaged by the brightness of two frames; temporally: during continuous observation, the polarity of each frame is reversed, and the brightness of each column between adjacent frames can be averaged by superimposing itself, but when the head moves, frames may be lost, resulting in the two columns that cannot be averaged in space losing the time averaging effect, resulting in periodic vertical stripes, called head shaking stripes. In order to alleviate the vertical stripe defect, 2-subpixel (dot) inversion is usually used, as shown in Figure 2E, but 2-dot inversion consumes very high power. In order to use column inversion, a dual gate Z architecture is proposed, as shown in Figure 3. The data line of this architecture needs to go around to the adjacent subpixels, reducing the aperture ratio of the pixel.

[0071] Therefore, it is urgently necessary for those skilled in the art to propose a dual gate pixel structure that can use column inversion, avoid charging differences between different columns, and not reduce the aperture ratio.

[0072] In view of this, referring to FIG. 4 and FIG. 7A-FIG , where FIG. 7B is a schematic diagram of a single film layer of the gate line in FIG. 7A , FIG. 7B is a schematic diagram of a single film layer of the gate line in FIG. 7A ; FIG. 7C is a schematic diagram of a single film layer of the active layer in FIG. 7A ; FIG. 7D is a schematic diagram of a single film layer of the data line in FIG. 7A ; FIG. 7E is a schematic diagram of a single film layer of the planar layer in FIG. 7A ; FIG. 7F is a schematic diagram of a single film layer of the pixel electrode layer in FIG. 7A ; and FIG. 7G is a schematic diagram of a single film layer of the common electrode layer in FIG. 7A , an embodiment of the present disclosure provides a display substrate, comprising:

[0073] Base substrate 1;

[0074] A plurality of gate line groups 20 are located on one side of the base substrate 1 and extend along a first direction X. At least one gate line group 20 of the plurality of gate line groups 20 includes two gate lines 2 extending along the first direction X.

[0075] A plurality of data lines 3 are located on the same side of the base substrate 1 as the gate lines 2 and extend along the second direction Y. The plurality of data lines 3 include: first-type data lines 31 and second-type data lines 32 alternately arranged along the first direction X.

[0076] a plurality of transistors T located in an area formed by the intersection of the gate line group 20 and the data line 3, the plurality of transistors T including: a sub-transistor group T1 located between adjacent gate line groups 20 and arranged along the first direction X, the sub-transistor group T1 including two transistors T, the transistors T in the same sub-transistor group T1 being connected to the same gate line 2, the transistors T in adjacent sub-transistor groups T1 being connected to different gate lines 2, and the transistors T in the same sub-transistor group T1 being connected to different data lines 3; that is, two adjacent transistors T connected to the same gate line 2 can be considered as one sub-transistor group T1;

[0077] Multiple pins 4 are located on the same side of the base substrate 1 as the gate lines 2. The multiple pins 4 include first-type pins 41 and second-type pins 42 arranged alternately along the first direction X. Two adjacent first-type data lines 31 are connected to a first-type pin 41, and adjacent second-type data lines 32 are connected to a second-type pin 42. Specifically, the signals loaded on the first-type pins 41 and the second-type pins 42 have opposite polarities, and column inversion is performed between adjacent frames.

[0078] Specifically, for the display substrate provided by the embodiment of the present disclosure, when a pure grayscale pattern is displayed, as shown in FIG4 , the signal loaded on the first type pin 41 is positive polarity, and the signal loaded on the second type pin 42 is negative polarity. Within one frame, the signal loaded on the first type pin 41 and the signal loaded on the second type pin 42 are both DC, and the charging degree of all pixel columns is the same, there is no charging difference between different columns, and the polarities of adjacent sub-pixels are opposite. For example, in a certain frame, the signal loaded on the first type pin 41 is positive polarity, and the signal loaded on the second type pin 42 is negative polarity. The pixel electrode of sub-pixel A is charged with a positive voltage signal, and the surrounding sub-pixels B, C, D, The negative voltage signal of the second type of pin 42 for equal charging of sub-pixel E, the pixel voltage of sub-pixel A pulls the voltage loaded on the common electrode (com) in a positive direction, and the voltages of the surrounding sub-pixels pull com in a negative direction. Since the pulling directions are opposite, the pulling on the common electrode loaded voltage is offset, which is beneficial to improving flicker and afterimage (if the pulling on the common electrode loaded voltage cannot be offset, the common electrode loaded voltage deviates from the center point after being pulled, the brightness difference between the positive and negative frames is large, and the flick is aggravated; at the same time, after the common electrode loaded voltage is pulled away from the center point, the DC bias in the display box is aggravated, resulting in an increased severity of the afterimage).

[0079] Specifically, for the display substrate provided by the embodiment of the present disclosure, when a pure color image is displayed, such as a pure green image, as shown in FIG5 , the signal loaded by the first type pin 41 is positive polarity, and the signal loaded by the second type pin 42 is negative polarity, both of which are column inversions. The voltage of the data line 3 is a DC signal within one frame, and the charging rate of all positive polarity green sub-pixels is the same, and the charging rate of all negative polarity green sub-pixels is the same. Therefore, there is no charging difference between different columns of the pure color pattern, and there is no vertical streak defect. Moreover, the polarities of adjacent green sub-pixels are opposite, and the pull of the pixel electrode (pixel) voltage on the voltage loaded on the common electrode (com) can be offset, which is beneficial to improve Flick and afterimage.

[0080] Specifically, for the display substrate provided by the embodiment of the present disclosure, when a mixed color pattern is displayed, for example, a yellow pattern of red and green mixed colors, as shown in Figure 6, the sub-pixels corresponding to the red pixel column and the green pixel column are bright, and the blue pixel column is not bright. Using the display substrate and pixel driving method provided by the embodiment of the present disclosure, the data voltages corresponding to the red and green sub-pixels in the mixed color pattern are both AC signals, and there is no difference in charging of different sub-pixels. Therefore, the vertical stripe defect existing in the existing dual gate pixels is fundamentally solved.

[0081] As described above, the display substrate and driving method provided by the embodiments of the present disclosure have no charging differences when displaying pure grayscale patterns (i.e., yellow, green, and blue sub-pixels are all bright), pure color patterns, mixed color patterns, etc., thereby improving vertical streak defects; at the same time, the use of a column inversion method greatly reduces the power consumption of the display substrate; that is, the number of data lines is reduced by increasing the number of gate lines, which has the same purpose as conventional dual gate products, and can reduce the number of ICs, thereby reducing costs, and at the same time can improve the limitation of existing dual gate pixels that cannot use column inversion, thereby greatly reducing power consumption; column inversion can be achieved using non-Z-shaped winding, and the aperture ratio is increased by 8% to 10%; in addition, the pixel voltages of adjacent sub-pixels pull the common electrode load voltage in opposite directions, and the pulls cancel each other out, which is beneficial to improving flicker and afterimage problems.

[0082] Specifically, as shown in Figures 7A to 7G , the data line 3 can be located on the side of the gate line 2 facing away from the base substrate 1. A pixel electrode layer 8 can be further provided on the side of the data line 3 facing away from the gate line 2. A common electrode layer 6 can also be provided on the side of the pixel electrode layer 8 facing away from the data line 3. Specifically, the pixel electrodes of the pixel electrode layer 8 can be block-shaped, and the common electrode layer 6 can be a comb-shaped structure with slits.

[0083] In a possible implementation, as shown in FIG4 to FIG6 , the gate line group 20 includes: a first gate line 21 and a second gate line 22 ;

[0084] The plurality of transistors T include: a first transistor row T100 and a second transistor row T200 extending along a first direction X and alternately arranged along a second direction Y; the sub-transistor group T1 includes: a first sub-transistor group T11 and a second sub-transistor group T12 alternately arranged along the first direction X;

[0085] In the first transistor row T100, the transistors T in the first sub-transistor group T11 are connected to the first gate line 21, and the transistors T in the second sub-transistor group T12 are connected to the second gate line 22. In the second transistor row T200, the transistors T in the first sub-transistor group T11 are connected to the second gate line 22, and the transistors T in the second sub-transistor group T12 are connected to the first gate line 21. Moreover, two adjacent transistors T in the same column of transistors T are connected to different data lines 3.

[0086] In one possible embodiment, referring to FIG. 7H-FIG . 7L , FIG. 7I is a schematic diagram of a single film layer of the gate line layer in FIG. 7H , FIG. 7J is a schematic diagram of a single film layer of the data line layer in FIG. 7H , FIG. 7K is a schematic diagram of a single film layer of the overlapping portion in FIG. 7H , and FIG. 7L is a schematic cross-sectional view taken along dotted line AA′ in FIG. 7H . The display substrate further includes: a plurality of first leads 51 and a plurality of second leads 52;

[0087] The first lead 51 includes a first connecting portion 511 and two first lead ends 512 ; one end of the first connecting portion 511 is connected to the first type pin 41 , and the other end is connected to the two first lead ends 512 ; the other end of the first lead end 512 is connected to the first type data line 31 ;

[0088] The second lead 52 includes a second connecting portion 521 and two second lead ends 522. One end of the second connecting portion 521 is connected to the second type pin 42, and the other end is connected to the two second lead ends 522. The other end of the second lead end 522 is connected to the second type data line 32. In this way, different data lines can be electrically connected to different pins.

[0089] In a possible embodiment, referring to FIG. 7H and FIG. 7L , the orthographic projection of one of the two first lead ends 512 on the base substrate 1 is intersected with the orthographic projection of one of the two second lead ends 522 on the base substrate 1 .

[0090] In a possible implementation, referring to FIG. 7H and FIG. 7L , the first lead 51 and the second lead 52 are located in different layers.

[0091] In a possible implementation, referring to FIG. 7H and FIG. 7L , the first lead 51 and the data line 3 are provided in the same layer; the second lead 52 and the gate line 2 are provided in the same layer.

[0092] In a possible implementation, referring to FIG. 7H to FIG. 7L , the display substrate further includes: a transfer portion 61 ;

[0093] The end of the second type data line 32 further has a first overlapping portion 320, and the orthographic projection of the transition portion 61 on the base substrate 1 covers the orthographic projection of the first overlapping portion 320 on the base substrate 1. The transition portion 61 is electrically connected to the first overlapping portion 320 through the first via K1;

[0094] The second lead end 522 further has a second overlapping portion 5220 . The orthographic projection of the transition portion 61 on the base substrate 1 covers the orthographic projection of the second overlapping portion 5220 on the base substrate 1 . The transition portion 61 is electrically connected to the second overlapping portion 5220 through the second via K2 .

[0095] The first overlapping portion 320 and the second overlapping portion 5220 are electrically connected via the transition portion 61 .

[0096] In a possible implementation, the display substrate further includes a common electrode layer 6 , and the transition portion 61 and the common electrode layer 6 are made of the same layer and material.

[0097] In one possible implementation, during the specific manufacturing process of the display substrate provided by the embodiment of the present disclosure, as shown in FIG9A , a gate line 2, an active layer 93, a gate insulating layer 95, a pixel electrode layer 8, a data line 3, a second passivation layer 92, and a common electrode layer 6 can be sequentially formed on one side of the base substrate. The gate insulating layer 95 and the second passivation layer 92 can be patterned through a one-step etching process.

[0098] In one possible embodiment, refer to Figures 8A and 8B, where Figure 8B is a single-film layer schematic diagram of the touch trace 71 in Figure 8A, and the common electrode layer 6 is reused as the touch electrode layer; the touch electrode layer includes a plurality of touch electrode blocks spaced apart from each other (not shown in the figure); the display substrate also includes a touch trace layer, and the touch trace layer includes touch traces 71 electrically connected to the touch electrode blocks in a one-to-one correspondence; the touch trace 71 and the data line 3 are located on different layers.

[0099] In one possible implementation, as shown in Figures 8A and 8B , the orthographic projection of the touch trace 71 on the base substrate 11 overlaps the orthographic projection of the data line 3 on the base substrate 1. Specifically, the touch trace 71 can be provided at the location where the data line 3 is located. Specifically, the width of the touch trace 71 in the first direction X can be greater than the width of the data line 3 in the first direction X.

[0100] In a possible embodiment, the display substrate further includes: a pixel electrode layer 8 located on the side of the data line 3 facing away from the base substrate 1; a common electrode layer 6 located on the side of the pixel electrode layer 8 facing away from the base substrate 1; and a touch line 71 located between the pixel electrode layer 8 and the common electrode layer 6.

[0101] Specifically, when the display substrate provided by the embodiment of the present disclosure has a touch line 71, during the specific manufacturing process, as shown in FIG9B , a gate line 2, an active layer 93, a gate insulating layer 95, a data line 3, a second passivation layer 92, a planar layer 94, a pixel electrode layer 8, a touch line 71, a first passivation layer 91, and a common electrode layer 6 can be sequentially formed on one side of the base substrate. The gate insulating layer 95, the second passivation layer 92, and the first passivation layer 91 can be patterned through a one-step etching process.

[0102] In a possible embodiment, as shown in Figures 8A, 8B and 9B, a first passivation layer 91 is further provided between the touch trace 71 and the common electrode layer 6. The first passivation layer 91 has a third via K1 that exposes a portion of the touch trace 71. The touch trace 71 is electrically connected to the touch electrode block through the third via K1.

[0103] In a possible implementation, referring to FIG. 8A and FIG. 8B , the orthographic projection of the third via hole K1 on the base substrate 1 is located at a gap between two gate lines 2 of the same gate line group 20 .

[0104] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the display substrate as provided in the embodiment of the present disclosure.

[0105] The display panel provided by the embodiments of the present disclosure is suitable for advanced dimension switch (ADS) liquid crystal displays, high-aperture ratio advanced dimension switch (HADS) liquid crystal displays, and twisted nematic (TN) liquid crystal displays. It is applicable not only to a-Si transistor products, but also to products using oxide transistors and low-temperature polysilicon transistors.

[0106] Based on the same inventive concept, the embodiment of the present disclosure also provides a display device, which includes a display panel as provided in the embodiment of the present disclosure. The display device can be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function. Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used as limitations on the present invention. In addition, since the principle of solving the problem by the display device is similar to the principle of solving the problem by the above-mentioned display panel, the implementation of the display device can refer to the embodiment of the above-mentioned liquid crystal display panel, and the repeated parts will not be described in detail.

[0107] Based on the same inventive concept, the embodiment of the present disclosure further provides a driving method of the display substrate provided in the embodiment of the present disclosure, as shown in FIG10 , wherein the driving method includes:

[0108] Step S100: When displaying an image in the Nth frame, a first-type signal is applied to a first-type pin, and a second-type signal is applied to a second-type pin, wherein the polarity of the first-type signal is opposite to that of the second-type signal, where N is an integer; specifically, for example, the first-type signal is a positive polarity signal and the second-type signal is a negative polarity signal;

[0109] Step S200 : When displaying an image in the N+1th frame, the second type of signal is loaded to the first type of pins, and the first type of signal is loaded to the second type of pins.

[0110] The display substrate and driving method provided by the embodiments of the present disclosure have no charging differences when displaying pure grayscale patterns (i.e., yellow, green, and blue sub-pixels are all bright), pure color patterns, mixed color patterns, etc., thereby improving vertical streak defects. Furthermore, the use of a column inversion method greatly reduces the power consumption of the display substrate. That is, the number of data lines is reduced by increasing the number of gate lines, which has the same purpose as conventional dual gate products. Both can reduce the number of ICs, thus reducing costs. It can also overcome the limitation of existing dual gate pixels that cannot use column inversion, greatly reducing power consumption. Column inversion can be achieved using non-Z-shaped windings, increasing the aperture ratio by 8% to 10%. In addition, the pixel voltages of adjacent sub-pixels pull the common electrode load voltage in opposite directions, and the pulls cancel each other out, which helps to improve flicker and afterimage problems.

[0111] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0112] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A display substrate, wherein: include: substrate substrate; A plurality of gate line groups are located on one side of the substrate and extend along a first direction, wherein at least one gate line group of the plurality of gate line groups includes two gate lines extending along the first direction; A plurality of data lines are located on the same side of the base substrate as the gate lines and extend along a second direction; the plurality of data lines include: first-type data lines and second-type data lines alternately arranged along the first direction; a plurality of transistors located in a region formed by the intersection of the gate line group and the data line, the plurality of transistors comprising: a sub-transistor group located between adjacent gate line groups and arranged along the first direction, the sub-transistor group comprising two transistors, the transistors in the same sub-transistor group being connected to the same gate line, the transistors in adjacent sub-transistor groups being connected to different gate lines, and the transistors in the same sub-transistor group being connected to different data lines; A plurality of pins are located on the same side of the substrate as the gate line, and the plurality of pins include: first-type pins and second-type pins alternately arranged along the first direction; wherein two adjacent first-type data lines are connected to a first-type pin, and two adjacent second-type data lines are connected to a second-type pin.

2. The display substrate according to claim 1, wherein: The gate line group includes: a first gate line and a second gate line; The plurality of transistors include: a first transistor row and a second transistor row extending along the first direction and arranged alternately along the second direction; the sub-transistor group includes: a first sub-transistor group and a second sub-transistor group arranged alternately along the first direction; In the first transistor row, the transistors in the first sub-transistor group are connected to the first gate line, and the transistors in the second sub-transistor group are connected to the second gate line; in the second transistor row, the transistors in the first sub-transistor group are connected to the second gate line, and the transistors in the second sub-transistor group are connected to the first gate line; and the transistors in the same column are connected to the first gate line. Two adjacent transistors in the tube are connected to different data lines.

3. The display substrate according to claim 2, wherein: The display substrate further includes: a plurality of first leads, and a plurality of second leads; The first lead includes: a first connection portion and two first lead ends; one end of the first connection portion is connected to the first type of pin, and the other end is connected to the two first lead ends; the other end of the first lead end is connected to the first type of data line; The second lead includes: a second connection portion and two second lead ends, one end of the second connection portion is connected to the second type pin, the other end is connected to the two second lead ends, and the other end of the second lead end is connected to the second type data line.

4. The display substrate according to claim 3, wherein: The orthographic projection of one of the two first lead ends on the base substrate is arranged to intersect with the orthographic projection of one of the two second lead ends on the base substrate.

5. The display substrate according to claim 3 or 4, wherein: The first lead and the second lead are located in different layers.

6. The display substrate according to claim 5, wherein: The first lead line is arranged in the same layer as the data line; and the second lead line is arranged in the same layer as the gate line.

7. The display substrate according to any one of claims 3 to 6, wherein: The display substrate further includes: a transfer portion; The end of the second type data line further has a first overlapping portion, the orthographic projection of the transition portion on the base substrate covers the orthographic projection of the first overlapping portion on the base substrate, and the transition portion is connected to the first overlapping portion through a first via hole; The second lead end further has a second overlapping portion, the orthographic projection of the transition portion on the base substrate covers the orthographic projection of the second overlapping portion on the base substrate, and the transition portion is connected to the second overlapping portion through a second via hole; The first overlapping portion and the second overlapping portion are electrically connected via the transition portion.

8. The display substrate according to claim 7, wherein: The display substrate further includes a common electrode layer, and the transition portion and the common electrode layer are formed in the same layer and made of the same material.

9. The display substrate according to any one of claims 1 to 8, wherein: The common electrode layer is reused as a touch electrode layer; the touch electrode layer includes a plurality of touch electrode blocks spaced apart from each other; The display substrate further comprises a touch wiring layer, wherein the touch wiring layer comprises touch wirings electrically connected to the touch electrode blocks in a one-to-one correspondence; The touch control wiring and the data layer are located in different layers.

10. The display substrate according to claim 9, wherein: The orthographic projection of the touch line on the base substrate covers the orthographic projection of the data line on the base substrate.

11. The display substrate according to claim 9 or 10, wherein: The display substrate further comprises: a pixel electrode layer located on a side of the data line layer away from the base substrate; the common electrode layer is located on a side of the pixel electrode layer away from the base substrate; The touch wiring layer is located between the pixel electrode layer and the common electrode layer.

12. The display substrate according to claim 11, wherein: A first passivation layer is further provided between the touch wiring layer and the common electrode layer. The first passivation layer has a third via hole exposing a portion of the touch wiring. The touch wiring is electrically connected to the touch electrode block through the third via hole.

13. The display substrate according to claim 12, wherein: The orthographic projection of the third via hole on the base substrate is located at a gap between two gate lines of the same gate line group.

14. A display panel, wherein: Comprising the display substrate as described in any one of claims 1-13.

15. A display device, wherein: Comprising the display panel as claimed in claim 14.

16. A method for driving a display substrate according to any one of claims 1 to 13, wherein: The driving method comprises: When displaying an image in the Nth frame, a first type of signal is loaded to the first type of pin, and a second type of signal is loaded to the second type of pin, wherein the polarity of the first type of signal is opposite to that of the second type of signal, and N is an integer; When displaying the picture in the N+1th frame, the second type of signal is loaded to the first type of pin, and the first type of signal is loaded to the second type of pin.

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